1 //===-- MipsastISel.cpp - Mips FastISel implementation
2 //---------------------===//
4 #include "MipsCCState.h"
5 #include "MipsInstrInfo.h"
6 #include "MipsISelLowering.h"
7 #include "MipsMachineFunction.h"
8 #include "MipsRegisterInfo.h"
9 #include "MipsSubtarget.h"
10 #include "MipsTargetMachine.h"
11 #include "llvm/Analysis/TargetLibraryInfo.h"
12 #include "llvm/CodeGen/FastISel.h"
13 #include "llvm/CodeGen/FunctionLoweringInfo.h"
14 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineRegisterInfo.h"
16 #include "llvm/IR/GetElementPtrTypeIterator.h"
17 #include "llvm/IR/GlobalAlias.h"
18 #include "llvm/IR/GlobalVariable.h"
19 #include "llvm/Target/TargetInstrInfo.h"
25 class MipsFastISel final : public FastISel {
27 // All possible address modes.
30 typedef enum { RegBase, FrameIndexBase } BaseKind;
41 const GlobalValue *GV;
44 // Innocuous defaults for our address.
45 Address() : Kind(RegBase), Offset(0), GV(0) { Base.Reg = 0; }
46 void setKind(BaseKind K) { Kind = K; }
47 BaseKind getKind() const { return Kind; }
48 bool isRegBase() const { return Kind == RegBase; }
49 bool isFIBase() const { return Kind == FrameIndexBase; }
50 void setReg(unsigned Reg) {
51 assert(isRegBase() && "Invalid base register access!");
54 unsigned getReg() const {
55 assert(isRegBase() && "Invalid base register access!");
58 void setFI(unsigned FI) {
59 assert(isFIBase() && "Invalid base frame index access!");
62 unsigned getFI() const {
63 assert(isFIBase() && "Invalid base frame index access!");
67 void setOffset(int64_t Offset_) { Offset = Offset_; }
68 int64_t getOffset() const { return Offset; }
69 void setGlobalValue(const GlobalValue *G) { GV = G; }
70 const GlobalValue *getGlobalValue() { return GV; }
73 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can
74 /// make the right decision when generating code for different targets.
75 const TargetMachine &TM;
76 const MipsSubtarget *Subtarget;
77 const TargetInstrInfo &TII;
78 const TargetLowering &TLI;
79 MipsFunctionInfo *MFI;
81 // Convenience variables to avoid some queries.
84 bool fastLowerCall(CallLoweringInfo &CLI) override;
85 bool fastLowerIntrinsicCall(const IntrinsicInst *II) override;
88 bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle
89 // floating point but not reject doing fast-isel in other
93 // Selection routines.
94 bool selectLogicalOp(const Instruction *I);
95 bool selectLoad(const Instruction *I);
96 bool selectStore(const Instruction *I);
97 bool selectBranch(const Instruction *I);
98 bool selectSelect(const Instruction *I);
99 bool selectCmp(const Instruction *I);
100 bool selectFPExt(const Instruction *I);
101 bool selectFPTrunc(const Instruction *I);
102 bool selectFPToInt(const Instruction *I, bool IsSigned);
103 bool selectRet(const Instruction *I);
104 bool selectTrunc(const Instruction *I);
105 bool selectIntExt(const Instruction *I);
106 bool selectShift(const Instruction *I);
107 bool selectDivRem(const Instruction *I, unsigned ISDOpcode);
109 // Utility helper routines.
110 bool isTypeLegal(Type *Ty, MVT &VT);
111 bool isTypeSupported(Type *Ty, MVT &VT);
112 bool isLoadTypeLegal(Type *Ty, MVT &VT);
113 bool computeAddress(const Value *Obj, Address &Addr);
114 bool computeCallAddress(const Value *V, Address &Addr);
115 void simplifyAddress(Address &Addr);
117 // Emit helper routines.
118 bool emitCmp(unsigned DestReg, const CmpInst *CI);
119 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
120 unsigned Alignment = 0);
121 bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
122 MachineMemOperand *MMO = nullptr);
123 bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,
124 unsigned Alignment = 0);
125 unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
126 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
129 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
131 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
132 bool emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
134 bool emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
137 unsigned getRegEnsuringSimpleIntegerWidening(const Value *, bool IsUnsigned);
139 unsigned emitLogicalOp(unsigned ISDOpc, MVT RetVT, const Value *LHS,
142 unsigned materializeFP(const ConstantFP *CFP, MVT VT);
143 unsigned materializeGV(const GlobalValue *GV, MVT VT);
144 unsigned materializeInt(const Constant *C, MVT VT);
145 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
146 unsigned materializeExternalCallSym(const char *SynName);
148 MachineInstrBuilder emitInst(unsigned Opc) {
149 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
151 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
152 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
155 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
156 unsigned MemReg, int64_t MemOffset) {
157 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
159 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
160 unsigned MemReg, int64_t MemOffset) {
161 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
164 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
165 const TargetRegisterClass *RC,
166 unsigned Op0, bool Op0IsKill,
167 unsigned Op1, bool Op1IsKill);
169 // for some reason, this default is not generated by tablegen
170 // so we explicitly generate it here.
172 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
173 unsigned Op0, bool Op0IsKill, uint64_t imm1,
174 uint64_t imm2, unsigned Op3, bool Op3IsKill) {
178 // Call handling routines.
180 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
181 bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
183 bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
186 // Backend specific FastISel code.
187 explicit MipsFastISel(FunctionLoweringInfo &funcInfo,
188 const TargetLibraryInfo *libInfo)
189 : FastISel(funcInfo, libInfo), TM(funcInfo.MF->getTarget()),
190 Subtarget(&funcInfo.MF->getSubtarget<MipsSubtarget>()),
191 TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) {
192 MFI = funcInfo.MF->getInfo<MipsFunctionInfo>();
193 Context = &funcInfo.Fn->getContext();
195 ((TM.getRelocationModel() == Reloc::PIC_) &&
196 ((Subtarget->hasMips32r2() || Subtarget->hasMips32()) &&
197 (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32())));
198 UnsupportedFPMode = Subtarget->isFP64bit();
201 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
202 unsigned fastMaterializeConstant(const Constant *C) override;
203 bool fastSelectInstruction(const Instruction *I) override;
205 #include "MipsGenFastISel.inc"
207 } // end anonymous namespace.
209 static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,
210 CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
211 CCState &State) LLVM_ATTRIBUTE_UNUSED;
213 static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,
214 CCValAssign::LocInfo LocInfo,
215 ISD::ArgFlagsTy ArgFlags, CCState &State) {
216 llvm_unreachable("should not be called");
219 static bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,
220 CCValAssign::LocInfo LocInfo,
221 ISD::ArgFlagsTy ArgFlags, CCState &State) {
222 llvm_unreachable("should not be called");
225 #include "MipsGenCallingConv.inc"
227 CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {
231 unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,
232 const Value *LHS, const Value *RHS) {
233 // Canonicalize immediates to the RHS first.
234 if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))
238 if (ISDOpc == ISD::AND) {
240 } else if (ISDOpc == ISD::OR) {
242 } else if (ISDOpc == ISD::XOR) {
245 llvm_unreachable("unexpected opcode");
247 unsigned LHSReg = getRegForValue(LHS);
248 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
256 if (const auto *C = dyn_cast<ConstantInt>(RHS))
257 RHSReg = materializeInt(C, MVT::i32);
259 RHSReg = getRegForValue(RHS);
264 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
268 unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
269 assert(TLI.getValueType(AI->getType(), true) == MVT::i32 &&
270 "Alloca should always return a pointer.");
272 DenseMap<const AllocaInst *, int>::iterator SI =
273 FuncInfo.StaticAllocaMap.find(AI);
275 if (SI != FuncInfo.StaticAllocaMap.end()) {
276 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
277 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
279 .addFrameIndex(SI->second)
287 unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {
288 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
290 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
291 const ConstantInt *CI = cast<ConstantInt>(C);
293 if ((VT != MVT::i1) && CI->isNegative())
294 Imm = CI->getSExtValue();
296 Imm = CI->getZExtValue();
297 return materialize32BitInt(Imm, RC);
300 unsigned MipsFastISel::materialize32BitInt(int64_t Imm,
301 const TargetRegisterClass *RC) {
302 unsigned ResultReg = createResultReg(RC);
304 if (isInt<16>(Imm)) {
305 unsigned Opc = Mips::ADDiu;
306 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
308 } else if (isUInt<16>(Imm)) {
309 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
312 unsigned Lo = Imm & 0xFFFF;
313 unsigned Hi = (Imm >> 16) & 0xFFFF;
315 // Both Lo and Hi have nonzero bits.
316 unsigned TmpReg = createResultReg(RC);
317 emitInst(Mips::LUi, TmpReg).addImm(Hi);
318 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
320 emitInst(Mips::LUi, ResultReg).addImm(Hi);
325 unsigned MipsFastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
326 if (UnsupportedFPMode)
328 int64_t Imm = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
329 if (VT == MVT::f32) {
330 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
331 unsigned DestReg = createResultReg(RC);
332 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
333 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
335 } else if (VT == MVT::f64) {
336 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
337 unsigned DestReg = createResultReg(RC);
338 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
340 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
341 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
347 unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) {
348 // For now 32-bit only.
351 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
352 unsigned DestReg = createResultReg(RC);
353 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
354 bool IsThreadLocal = GVar && GVar->isThreadLocal();
355 // TLS not supported at this time.
358 emitInst(Mips::LW, DestReg)
359 .addReg(MFI->getGlobalBaseReg())
360 .addGlobalAddress(GV, 0, MipsII::MO_GOT);
361 if ((GV->hasInternalLinkage() ||
362 (GV->hasLocalLinkage() && !isa<Function>(GV)))) {
363 unsigned TempReg = createResultReg(RC);
364 emitInst(Mips::ADDiu, TempReg)
366 .addGlobalAddress(GV, 0, MipsII::MO_ABS_LO);
372 unsigned MipsFastISel::materializeExternalCallSym(const char *SymName) {
373 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
374 unsigned DestReg = createResultReg(RC);
375 emitInst(Mips::LW, DestReg)
376 .addReg(MFI->getGlobalBaseReg())
377 .addExternalSymbol(SymName, MipsII::MO_GOT);
381 // Materialize a constant into a register, and return the register
382 // number (or zero if we failed to handle it).
383 unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) {
384 EVT CEVT = TLI.getValueType(C->getType(), true);
386 // Only handle simple types.
387 if (!CEVT.isSimple())
389 MVT VT = CEVT.getSimpleVT();
391 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
392 return (UnsupportedFPMode) ? 0 : materializeFP(CFP, VT);
393 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
394 return materializeGV(GV, VT);
395 else if (isa<ConstantInt>(C))
396 return materializeInt(C, VT);
401 bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) {
403 const User *U = nullptr;
404 unsigned Opcode = Instruction::UserOp1;
405 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
406 // Don't walk into other basic blocks unless the object is an alloca from
407 // another block, otherwise it may not have a virtual register assigned.
408 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
409 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
410 Opcode = I->getOpcode();
413 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
414 Opcode = C->getOpcode();
420 case Instruction::BitCast: {
421 // Look through bitcasts.
422 return computeAddress(U->getOperand(0), Addr);
424 case Instruction::GetElementPtr: {
425 Address SavedAddr = Addr;
426 uint64_t TmpOffset = Addr.getOffset();
427 // Iterate through the GEP folding the constants into offsets where
429 gep_type_iterator GTI = gep_type_begin(U);
430 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e;
432 const Value *Op = *i;
433 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
434 const StructLayout *SL = DL.getStructLayout(STy);
435 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
436 TmpOffset += SL->getElementOffset(Idx);
438 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
440 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
441 // Constant-offset addressing.
442 TmpOffset += CI->getSExtValue() * S;
445 if (canFoldAddIntoGEP(U, Op)) {
446 // A compatible add with a constant operand. Fold the constant.
448 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
449 TmpOffset += CI->getSExtValue() * S;
450 // Iterate on the other operand.
451 Op = cast<AddOperator>(Op)->getOperand(0);
455 goto unsupported_gep;
459 // Try to grab the base operand now.
460 Addr.setOffset(TmpOffset);
461 if (computeAddress(U->getOperand(0), Addr))
463 // We failed, restore everything and try the other options.
468 case Instruction::Alloca: {
469 const AllocaInst *AI = cast<AllocaInst>(Obj);
470 DenseMap<const AllocaInst *, int>::iterator SI =
471 FuncInfo.StaticAllocaMap.find(AI);
472 if (SI != FuncInfo.StaticAllocaMap.end()) {
473 Addr.setKind(Address::FrameIndexBase);
474 Addr.setFI(SI->second);
480 Addr.setReg(getRegForValue(Obj));
481 return Addr.getReg() != 0;
484 bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {
485 const User *U = nullptr;
486 unsigned Opcode = Instruction::UserOp1;
488 if (const auto *I = dyn_cast<Instruction>(V)) {
489 // Check if the value is defined in the same basic block. This information
490 // is crucial to know whether or not folding an operand is valid.
491 if (I->getParent() == FuncInfo.MBB->getBasicBlock()) {
492 Opcode = I->getOpcode();
495 } else if (const auto *C = dyn_cast<ConstantExpr>(V)) {
496 Opcode = C->getOpcode();
503 case Instruction::BitCast:
504 // Look past bitcasts if its operand is in the same BB.
505 return computeCallAddress(U->getOperand(0), Addr);
507 case Instruction::IntToPtr:
508 // Look past no-op inttoptrs if its operand is in the same BB.
509 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
510 return computeCallAddress(U->getOperand(0), Addr);
512 case Instruction::PtrToInt:
513 // Look past no-op ptrtoints if its operand is in the same BB.
514 if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
515 return computeCallAddress(U->getOperand(0), Addr);
519 if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
520 Addr.setGlobalValue(GV);
524 // If all else fails, try to materialize the value in a register.
525 if (!Addr.getGlobalValue()) {
526 Addr.setReg(getRegForValue(V));
527 return Addr.getReg() != 0;
533 bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {
534 EVT evt = TLI.getValueType(Ty, true);
535 // Only handle simple types.
536 if (evt == MVT::Other || !evt.isSimple())
538 VT = evt.getSimpleVT();
540 // Handle all legal types, i.e. a register that will directly hold this
542 return TLI.isTypeLegal(VT);
545 bool MipsFastISel::isTypeSupported(Type *Ty, MVT &VT) {
546 if (Ty->isVectorTy())
549 if (isTypeLegal(Ty, VT))
552 // If this is a type than can be sign or zero-extended to a basic operation
553 // go ahead and accept it now.
554 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
560 bool MipsFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
561 if (isTypeLegal(Ty, VT))
563 // We will extend this in a later patch:
564 // If this is a type than can be sign or zero-extended to a basic operation
565 // go ahead and accept it now.
566 if (VT == MVT::i8 || VT == MVT::i16)
570 // Because of how EmitCmp is called with fast-isel, you can
571 // end up with redundant "andi" instructions after the sequences emitted below.
572 // We should try and solve this issue in the future.
574 bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) {
575 const Value *Left = CI->getOperand(0), *Right = CI->getOperand(1);
576 bool IsUnsigned = CI->isUnsigned();
577 unsigned LeftReg = getRegEnsuringSimpleIntegerWidening(Left, IsUnsigned);
580 unsigned RightReg = getRegEnsuringSimpleIntegerWidening(Right, IsUnsigned);
583 CmpInst::Predicate P = CI->getPredicate();
588 case CmpInst::ICMP_EQ: {
589 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
590 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
591 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
594 case CmpInst::ICMP_NE: {
595 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
596 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
597 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
600 case CmpInst::ICMP_UGT: {
601 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
604 case CmpInst::ICMP_ULT: {
605 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
608 case CmpInst::ICMP_UGE: {
609 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
610 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
611 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
614 case CmpInst::ICMP_ULE: {
615 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
616 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
617 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
620 case CmpInst::ICMP_SGT: {
621 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
624 case CmpInst::ICMP_SLT: {
625 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
628 case CmpInst::ICMP_SGE: {
629 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
630 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
631 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
634 case CmpInst::ICMP_SLE: {
635 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
636 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
637 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
640 case CmpInst::FCMP_OEQ:
641 case CmpInst::FCMP_UNE:
642 case CmpInst::FCMP_OLT:
643 case CmpInst::FCMP_OLE:
644 case CmpInst::FCMP_OGT:
645 case CmpInst::FCMP_OGE: {
646 if (UnsupportedFPMode)
648 bool IsFloat = Left->getType()->isFloatTy();
649 bool IsDouble = Left->getType()->isDoubleTy();
650 if (!IsFloat && !IsDouble)
652 unsigned Opc, CondMovOpc;
654 case CmpInst::FCMP_OEQ:
655 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
656 CondMovOpc = Mips::MOVT_I;
658 case CmpInst::FCMP_UNE:
659 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
660 CondMovOpc = Mips::MOVF_I;
662 case CmpInst::FCMP_OLT:
663 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
664 CondMovOpc = Mips::MOVT_I;
666 case CmpInst::FCMP_OLE:
667 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
668 CondMovOpc = Mips::MOVT_I;
670 case CmpInst::FCMP_OGT:
671 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
672 CondMovOpc = Mips::MOVF_I;
674 case CmpInst::FCMP_OGE:
675 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
676 CondMovOpc = Mips::MOVF_I;
679 llvm_unreachable("Only switching of a subset of CCs.");
681 unsigned RegWithZero = createResultReg(&Mips::GPR32RegClass);
682 unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass);
683 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
684 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
685 emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(
686 Mips::FCC0, RegState::ImplicitDefine);
687 MachineInstrBuilder MI = emitInst(CondMovOpc, ResultReg)
690 .addReg(RegWithZero, RegState::Implicit);
691 MI->tieOperands(0, 3);
697 bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
698 unsigned Alignment) {
700 // more cases will be handled here in following patches.
703 switch (VT.SimpleTy) {
705 ResultReg = createResultReg(&Mips::GPR32RegClass);
710 ResultReg = createResultReg(&Mips::GPR32RegClass);
715 ResultReg = createResultReg(&Mips::GPR32RegClass);
720 if (UnsupportedFPMode)
722 ResultReg = createResultReg(&Mips::FGR32RegClass);
727 if (UnsupportedFPMode)
729 ResultReg = createResultReg(&Mips::AFGR64RegClass);
736 if (Addr.isRegBase()) {
737 simplifyAddress(Addr);
738 emitInstLoad(Opc, ResultReg, Addr.getReg(), Addr.getOffset());
741 if (Addr.isFIBase()) {
742 unsigned FI = Addr.getFI();
744 unsigned Offset = Addr.getOffset();
745 MachineFrameInfo &MFI = *MF->getFrameInfo();
746 MachineMemOperand *MMO = MF->getMachineMemOperand(
747 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
748 MFI.getObjectSize(FI), Align);
749 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
758 bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr,
759 unsigned Alignment) {
761 // more cases will be handled here in following patches.
764 switch (VT.SimpleTy) {
775 if (UnsupportedFPMode)
780 if (UnsupportedFPMode)
787 if (Addr.isRegBase()) {
788 simplifyAddress(Addr);
789 emitInstStore(Opc, SrcReg, Addr.getReg(), Addr.getOffset());
792 if (Addr.isFIBase()) {
793 unsigned FI = Addr.getFI();
795 unsigned Offset = Addr.getOffset();
796 MachineFrameInfo &MFI = *MF->getFrameInfo();
797 MachineMemOperand *MMO = MF->getMachineMemOperand(
798 MachinePointerInfo::getFixedStack(FI), MachineMemOperand::MOLoad,
799 MFI.getObjectSize(FI), Align);
800 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
810 bool MipsFastISel::selectLogicalOp(const Instruction *I) {
812 if (!isTypeSupported(I->getType(), VT))
816 switch (I->getOpcode()) {
818 llvm_unreachable("Unexpected instruction.");
819 case Instruction::And:
820 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
822 case Instruction::Or:
823 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
825 case Instruction::Xor:
826 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
833 updateValueMap(I, ResultReg);
837 bool MipsFastISel::selectLoad(const Instruction *I) {
838 // Atomic loads need special handling.
839 if (cast<LoadInst>(I)->isAtomic())
842 // Verify we have a legal type before going any further.
844 if (!isLoadTypeLegal(I->getType(), VT))
847 // See if we can handle this address.
849 if (!computeAddress(I->getOperand(0), Addr))
853 if (!emitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
855 updateValueMap(I, ResultReg);
859 bool MipsFastISel::selectStore(const Instruction *I) {
860 Value *Op0 = I->getOperand(0);
863 // Atomic stores need special handling.
864 if (cast<StoreInst>(I)->isAtomic())
867 // Verify we have a legal type before going any further.
869 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT))
872 // Get the value to be stored into a register.
873 SrcReg = getRegForValue(Op0);
877 // See if we can handle this address.
879 if (!computeAddress(I->getOperand(1), Addr))
882 if (!emitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
888 // This can cause a redundant sltiu to be generated.
889 // FIXME: try and eliminate this in a future patch.
891 bool MipsFastISel::selectBranch(const Instruction *I) {
892 const BranchInst *BI = cast<BranchInst>(I);
893 MachineBasicBlock *BrBB = FuncInfo.MBB;
895 // TBB is the basic block for the case where the comparison is true.
896 // FBB is the basic block for the case where the comparison is false.
897 // if (cond) goto TBB
901 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
902 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
904 // For now, just try the simplest case where it's fed by a compare.
905 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
906 unsigned CondReg = createResultReg(&Mips::GPR32RegClass);
907 if (!emitCmp(CondReg, CI))
909 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::BGTZ))
912 fastEmitBranch(FBB, DbgLoc);
913 FuncInfo.MBB->addSuccessor(TBB);
919 bool MipsFastISel::selectCmp(const Instruction *I) {
920 const CmpInst *CI = cast<CmpInst>(I);
921 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
922 if (!emitCmp(ResultReg, CI))
924 updateValueMap(I, ResultReg);
928 // Attempt to fast-select a floating-point extend instruction.
929 bool MipsFastISel::selectFPExt(const Instruction *I) {
930 if (UnsupportedFPMode)
932 Value *Src = I->getOperand(0);
933 EVT SrcVT = TLI.getValueType(Src->getType(), true);
934 EVT DestVT = TLI.getValueType(I->getType(), true);
936 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
940 getRegForValue(Src); // his must be a 32 bit floating point register class
941 // maybe we should handle this differently
945 unsigned DestReg = createResultReg(&Mips::AFGR64RegClass);
946 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
947 updateValueMap(I, DestReg);
951 bool MipsFastISel::selectSelect(const Instruction *I) {
952 assert(isa<SelectInst>(I) && "Expected a select instruction.");
955 if (!isTypeSupported(I->getType(), VT))
959 const TargetRegisterClass *RC;
961 if (VT.isInteger() && !VT.isVector() && VT.getSizeInBits() <= 32) {
962 CondMovOpc = Mips::MOVN_I_I;
963 RC = &Mips::GPR32RegClass;
964 } else if (VT == MVT::f32) {
965 CondMovOpc = Mips::MOVN_I_S;
966 RC = &Mips::FGR32RegClass;
967 } else if (VT == MVT::f64) {
968 CondMovOpc = Mips::MOVN_I_D32;
969 RC = &Mips::AFGR64RegClass;
973 const SelectInst *SI = cast<SelectInst>(I);
974 const Value *Cond = SI->getCondition();
975 unsigned Src1Reg = getRegForValue(SI->getTrueValue());
976 unsigned Src2Reg = getRegForValue(SI->getFalseValue());
977 unsigned CondReg = getRegForValue(Cond);
979 if (!Src1Reg || !Src2Reg || !CondReg)
982 unsigned ResultReg = createResultReg(RC);
983 unsigned TempReg = createResultReg(RC);
985 if (!ResultReg || !TempReg)
988 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
989 emitInst(CondMovOpc, ResultReg)
990 .addReg(Src1Reg).addReg(CondReg).addReg(TempReg);
991 updateValueMap(I, ResultReg);
995 // Attempt to fast-select a floating-point truncate instruction.
996 bool MipsFastISel::selectFPTrunc(const Instruction *I) {
997 if (UnsupportedFPMode)
999 Value *Src = I->getOperand(0);
1000 EVT SrcVT = TLI.getValueType(Src->getType(), true);
1001 EVT DestVT = TLI.getValueType(I->getType(), true);
1003 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
1006 unsigned SrcReg = getRegForValue(Src);
1010 unsigned DestReg = createResultReg(&Mips::FGR32RegClass);
1014 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1015 updateValueMap(I, DestReg);
1019 // Attempt to fast-select a floating-point-to-integer conversion.
1020 bool MipsFastISel::selectFPToInt(const Instruction *I, bool IsSigned) {
1021 if (UnsupportedFPMode)
1025 return false; // We don't handle this case yet. There is no native
1026 // instruction for this but it can be synthesized.
1027 Type *DstTy = I->getType();
1028 if (!isTypeLegal(DstTy, DstVT))
1031 if (DstVT != MVT::i32)
1034 Value *Src = I->getOperand(0);
1035 Type *SrcTy = Src->getType();
1036 if (!isTypeLegal(SrcTy, SrcVT))
1039 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1042 unsigned SrcReg = getRegForValue(Src);
1046 // Determine the opcode for the conversion, which takes place
1047 // entirely within FPRs.
1048 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1049 unsigned TempReg = createResultReg(&Mips::FGR32RegClass);
1052 if (SrcVT == MVT::f32)
1053 Opc = Mips::TRUNC_W_S;
1055 Opc = Mips::TRUNC_W_D32;
1057 // Generate the convert.
1058 emitInst(Opc, TempReg).addReg(SrcReg);
1060 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1062 updateValueMap(I, DestReg);
1066 bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,
1067 SmallVectorImpl<MVT> &OutVTs,
1068 unsigned &NumBytes) {
1069 CallingConv::ID CC = CLI.CallConv;
1070 SmallVector<CCValAssign, 16> ArgLocs;
1071 CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);
1072 CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));
1073 // Get a count of how many bytes are to be pushed on the stack.
1074 NumBytes = CCInfo.getNextStackOffset();
1075 // This is the minimum argument area used for A0-A3.
1079 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);
1080 // Process the args.
1082 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1083 CCValAssign &VA = ArgLocs[i];
1084 const Value *ArgVal = CLI.OutVals[VA.getValNo()];
1085 MVT ArgVT = OutVTs[VA.getValNo()];
1089 if (ArgVT == MVT::f32) {
1090 VA.convertToReg(Mips::F12);
1091 } else if (ArgVT == MVT::f64) {
1092 VA.convertToReg(Mips::D6);
1094 } else if (i == 1) {
1095 if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {
1096 if (ArgVT == MVT::f32) {
1097 VA.convertToReg(Mips::F14);
1098 } else if (ArgVT == MVT::f64) {
1099 VA.convertToReg(Mips::D7);
1103 if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32) || (ArgVT == MVT::i16) ||
1104 (ArgVT == MVT::i8)) &&
1106 switch (VA.getLocMemOffset()) {
1108 VA.convertToReg(Mips::A0);
1111 VA.convertToReg(Mips::A1);
1114 VA.convertToReg(Mips::A2);
1117 VA.convertToReg(Mips::A3);
1123 unsigned ArgReg = getRegForValue(ArgVal);
1127 // Handle arg promotion: SExt, ZExt, AExt.
1128 switch (VA.getLocInfo()) {
1129 case CCValAssign::Full:
1131 case CCValAssign::AExt:
1132 case CCValAssign::SExt: {
1133 MVT DestVT = VA.getLocVT();
1135 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
1140 case CCValAssign::ZExt: {
1141 MVT DestVT = VA.getLocVT();
1143 ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
1149 llvm_unreachable("Unknown arg promotion!");
1152 // Now copy/store arg to correct locations.
1153 if (VA.isRegLoc() && !VA.needsCustom()) {
1154 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1155 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1156 CLI.OutRegs.push_back(VA.getLocReg());
1157 } else if (VA.needsCustom()) {
1158 llvm_unreachable("Mips does not use custom args.");
1162 // FIXME: This path will currently return false. It was copied
1163 // from the AArch64 port and should be essentially fine for Mips too.
1164 // The work to finish up this path will be done in a follow-on patch.
1166 assert(VA.isMemLoc() && "Assuming store on stack.");
1167 // Don't emit stores for undef values.
1168 if (isa<UndefValue>(ArgVal))
1171 // Need to store on the stack.
1172 // FIXME: This alignment is incorrect but this path is disabled
1173 // for now (will return false). We need to determine the right alignment
1174 // based on the normal alignment for the underlying machine type.
1176 unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);
1178 unsigned BEAlign = 0;
1179 if (ArgSize < 8 && !Subtarget->isLittle())
1180 BEAlign = 8 - ArgSize;
1183 Addr.setKind(Address::RegBase);
1184 Addr.setReg(Mips::SP);
1185 Addr.setOffset(VA.getLocMemOffset() + BEAlign);
1187 unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());
1188 MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(
1189 MachinePointerInfo::getStack(Addr.getOffset()),
1190 MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
1192 // if (!emitStore(ArgVT, ArgReg, Addr, MMO))
1193 return false; // can't store on the stack yet.
1200 bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
1201 unsigned NumBytes) {
1202 CallingConv::ID CC = CLI.CallConv;
1203 emitInst(Mips::ADJCALLSTACKUP).addImm(16);
1204 if (RetVT != MVT::isVoid) {
1205 SmallVector<CCValAssign, 16> RVLocs;
1206 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1207 CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);
1209 // Only handle a single return value.
1210 if (RVLocs.size() != 1)
1212 // Copy all of the result registers out of their specified physreg.
1213 MVT CopyVT = RVLocs[0].getValVT();
1214 // Special handling for extended integers.
1215 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)
1218 unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));
1221 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1222 TII.get(TargetOpcode::COPY),
1223 ResultReg).addReg(RVLocs[0].getLocReg());
1224 CLI.InRegs.push_back(RVLocs[0].getLocReg());
1226 CLI.ResultReg = ResultReg;
1227 CLI.NumResultRegs = 1;
1232 bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1233 CallingConv::ID CC = CLI.CallConv;
1234 bool IsTailCall = CLI.IsTailCall;
1235 bool IsVarArg = CLI.IsVarArg;
1236 const Value *Callee = CLI.Callee;
1237 const char *SymName = CLI.SymName;
1239 // Allow SelectionDAG isel to handle tail calls.
1243 // Let SDISel handle vararg functions.
1247 // FIXME: Only handle *simple* calls for now.
1249 if (CLI.RetTy->isVoidTy())
1250 RetVT = MVT::isVoid;
1251 else if (!isTypeSupported(CLI.RetTy, RetVT))
1254 for (auto Flag : CLI.OutFlags)
1255 if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())
1258 // Set up the argument vectors.
1259 SmallVector<MVT, 16> OutVTs;
1260 OutVTs.reserve(CLI.OutVals.size());
1262 for (auto *Val : CLI.OutVals) {
1264 if (!isTypeLegal(Val->getType(), VT) &&
1265 !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))
1268 // We don't handle vector parameters yet.
1269 if (VT.isVector() || VT.getSizeInBits() > 64)
1272 OutVTs.push_back(VT);
1276 if (!computeCallAddress(Callee, Addr))
1279 // Handle the arguments now that we've gotten them.
1281 if (!processCallArgs(CLI, OutVTs, NumBytes))
1284 if (!Addr.getGlobalValue())
1288 unsigned DestAddress;
1290 DestAddress = materializeExternalCallSym(SymName);
1292 DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);
1293 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1294 MachineInstrBuilder MIB =
1295 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1296 Mips::RA).addReg(Mips::T9);
1298 // Add implicit physical register uses to the call.
1299 for (auto Reg : CLI.OutRegs)
1300 MIB.addReg(Reg, RegState::Implicit);
1302 // Add a register mask with the call-preserved registers.
1303 // Proper defs for return values will be added by setPhysRegsDeadExcept().
1304 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1308 // Finish off the call including any return values.
1309 return finishCall(CLI, RetVT, NumBytes);
1312 bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
1313 switch (II->getIntrinsicID()) {
1316 case Intrinsic::bswap: {
1317 Type *RetTy = II->getCalledFunction()->getReturnType();
1320 if (!isTypeSupported(RetTy, VT))
1323 unsigned SrcReg = getRegForValue(II->getOperand(0));
1326 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1329 if (VT == MVT::i16) {
1330 if (Subtarget->hasMips32r2()) {
1331 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1332 updateValueMap(II, DestReg);
1335 unsigned TempReg[3];
1336 for (int i = 0; i < 3; i++) {
1337 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1338 if (TempReg[i] == 0)
1341 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1342 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1343 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1344 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1345 updateValueMap(II, DestReg);
1348 } else if (VT == MVT::i32) {
1349 if (Subtarget->hasMips32r2()) {
1350 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1351 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1352 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1353 updateValueMap(II, DestReg);
1356 unsigned TempReg[8];
1357 for (int i = 0; i < 8; i++) {
1358 TempReg[i] = createResultReg(&Mips::GPR32RegClass);
1359 if (TempReg[i] == 0)
1363 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1364 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1365 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1366 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1368 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1369 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1371 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1372 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1373 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1374 updateValueMap(II, DestReg);
1380 case Intrinsic::memcpy:
1381 case Intrinsic::memmove: {
1382 const auto *MTI = cast<MemTransferInst>(II);
1383 // Don't handle volatile.
1384 if (MTI->isVolatile())
1386 if (!MTI->getLength()->getType()->isIntegerTy(32))
1388 const char *IntrMemName = isa<MemCpyInst>(II) ? "memcpy" : "memmove";
1389 return lowerCallTo(II, IntrMemName, II->getNumArgOperands() - 2);
1391 case Intrinsic::memset: {
1392 const MemSetInst *MSI = cast<MemSetInst>(II);
1393 // Don't handle volatile.
1394 if (MSI->isVolatile())
1396 if (!MSI->getLength()->getType()->isIntegerTy(32))
1398 return lowerCallTo(II, "memset", II->getNumArgOperands() - 2);
1404 bool MipsFastISel::selectRet(const Instruction *I) {
1405 const Function &F = *I->getParent()->getParent();
1406 const ReturnInst *Ret = cast<ReturnInst>(I);
1408 if (!FuncInfo.CanLowerReturn)
1411 // Build a list of return value registers.
1412 SmallVector<unsigned, 4> RetRegs;
1414 if (Ret->getNumOperands() > 0) {
1415 CallingConv::ID CC = F.getCallingConv();
1416 SmallVector<ISD::OutputArg, 4> Outs;
1417 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI);
1418 // Analyze operands of the call, assigning locations to each operand.
1419 SmallVector<CCValAssign, 16> ValLocs;
1420 MipsCCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs,
1422 CCAssignFn *RetCC = RetCC_Mips;
1423 CCInfo.AnalyzeReturn(Outs, RetCC);
1425 // Only handle a single return value for now.
1426 if (ValLocs.size() != 1)
1429 CCValAssign &VA = ValLocs[0];
1430 const Value *RV = Ret->getOperand(0);
1432 // Don't bother handling odd stuff for now.
1433 if ((VA.getLocInfo() != CCValAssign::Full) &&
1434 (VA.getLocInfo() != CCValAssign::BCvt))
1437 // Only handle register returns for now.
1441 unsigned Reg = getRegForValue(RV);
1445 unsigned SrcReg = Reg + VA.getValNo();
1446 unsigned DestReg = VA.getLocReg();
1447 // Avoid a cross-class copy. This is very unlikely.
1448 if (!MRI.getRegClass(SrcReg)->contains(DestReg))
1451 EVT RVEVT = TLI.getValueType(RV->getType());
1452 if (!RVEVT.isSimple())
1455 if (RVEVT.isVector())
1458 MVT RVVT = RVEVT.getSimpleVT();
1459 if (RVVT == MVT::f128)
1462 MVT DestVT = VA.getValVT();
1463 // Special handling for extended integers.
1464 if (RVVT != DestVT) {
1465 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16)
1468 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) {
1469 bool IsZExt = Outs[0].Flags.isZExt();
1470 SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
1477 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1478 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1480 // Add register to return instruction.
1481 RetRegs.push_back(VA.getLocReg());
1483 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1484 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1485 MIB.addReg(RetRegs[i], RegState::Implicit);
1489 bool MipsFastISel::selectTrunc(const Instruction *I) {
1490 // The high bits for a type smaller than the register size are assumed to be
1492 Value *Op = I->getOperand(0);
1495 SrcVT = TLI.getValueType(Op->getType(), true);
1496 DestVT = TLI.getValueType(I->getType(), true);
1498 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8)
1500 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1)
1503 unsigned SrcReg = getRegForValue(Op);
1507 // Because the high bits are undefined, a truncate doesn't generate
1509 updateValueMap(I, SrcReg);
1512 bool MipsFastISel::selectIntExt(const Instruction *I) {
1513 Type *DestTy = I->getType();
1514 Value *Src = I->getOperand(0);
1515 Type *SrcTy = Src->getType();
1517 bool isZExt = isa<ZExtInst>(I);
1518 unsigned SrcReg = getRegForValue(Src);
1522 EVT SrcEVT, DestEVT;
1523 SrcEVT = TLI.getValueType(SrcTy, true);
1524 DestEVT = TLI.getValueType(DestTy, true);
1525 if (!SrcEVT.isSimple())
1527 if (!DestEVT.isSimple())
1530 MVT SrcVT = SrcEVT.getSimpleVT();
1531 MVT DestVT = DestEVT.getSimpleVT();
1532 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1534 if (!emitIntExt(SrcVT, SrcReg, DestVT, ResultReg, isZExt))
1536 updateValueMap(I, ResultReg);
1539 bool MipsFastISel::emitIntSExt32r1(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1542 switch (SrcVT.SimpleTy) {
1552 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1553 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1554 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1558 bool MipsFastISel::emitIntSExt32r2(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1560 switch (SrcVT.SimpleTy) {
1564 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1567 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1573 bool MipsFastISel::emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1575 if ((DestVT != MVT::i32) && (DestVT != MVT::i16))
1577 if (Subtarget->hasMips32r2())
1578 return emitIntSExt32r2(SrcVT, SrcReg, DestVT, DestReg);
1579 return emitIntSExt32r1(SrcVT, SrcReg, DestVT, DestReg);
1582 bool MipsFastISel::emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1584 switch (SrcVT.SimpleTy) {
1588 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(1);
1591 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xff);
1594 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);
1600 bool MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1601 unsigned DestReg, bool IsZExt) {
1602 // FastISel does not have plumbing to deal with extensions where the SrcVT or
1603 // DestVT are odd things, so test to make sure that they are both types we can
1604 // handle (i1/i8/i16/i32 for SrcVT and i8/i16/i32/i64 for DestVT), otherwise
1605 // bail out to SelectionDAG.
1606 if (((DestVT != MVT::i8) && (DestVT != MVT::i16) && (DestVT != MVT::i32)) ||
1607 ((SrcVT != MVT::i1) && (SrcVT != MVT::i8) && (SrcVT != MVT::i16)))
1610 return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);
1611 return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);
1614 unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1616 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1617 bool Success = emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);
1618 return Success ? DestReg : 0;
1621 bool MipsFastISel::selectDivRem(const Instruction *I, unsigned ISDOpcode) {
1622 EVT DestEVT = TLI.getValueType(I->getType(), true);
1623 if (!DestEVT.isSimple())
1626 MVT DestVT = DestEVT.getSimpleVT();
1627 if (DestVT != MVT::i32)
1631 switch (ISDOpcode) {
1636 DivOpc = Mips::SDIV;
1640 DivOpc = Mips::UDIV;
1644 unsigned Src0Reg = getRegForValue(I->getOperand(0));
1645 unsigned Src1Reg = getRegForValue(I->getOperand(1));
1646 if (!Src0Reg || !Src1Reg)
1649 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1650 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1652 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1656 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
1659 emitInst(MFOpc, ResultReg);
1661 updateValueMap(I, ResultReg);
1665 bool MipsFastISel::selectShift(const Instruction *I) {
1668 if (!isTypeSupported(I->getType(), RetVT))
1671 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
1675 unsigned Opcode = I->getOpcode();
1676 const Value *Op0 = I->getOperand(0);
1677 unsigned Op0Reg = getRegForValue(Op0);
1681 // If AShr or LShr, then we need to make sure the operand0 is sign extended.
1682 if (Opcode == Instruction::AShr || Opcode == Instruction::LShr) {
1683 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1687 MVT Op0MVT = TLI.getValueType(Op0->getType(), true).getSimpleVT();
1688 bool IsZExt = Opcode == Instruction::LShr;
1689 if (!emitIntExt(Op0MVT, Op0Reg, MVT::i32, TempReg, IsZExt))
1695 if (const auto *C = dyn_cast<ConstantInt>(I->getOperand(1))) {
1696 uint64_t ShiftVal = C->getZExtValue();
1700 llvm_unreachable("Unexpected instruction.");
1701 case Instruction::Shl:
1704 case Instruction::AShr:
1707 case Instruction::LShr:
1712 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
1713 updateValueMap(I, ResultReg);
1717 unsigned Op1Reg = getRegForValue(I->getOperand(1));
1723 llvm_unreachable("Unexpected instruction.");
1724 case Instruction::Shl:
1725 Opcode = Mips::SLLV;
1727 case Instruction::AShr:
1728 Opcode = Mips::SRAV;
1730 case Instruction::LShr:
1731 Opcode = Mips::SRLV;
1735 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
1736 updateValueMap(I, ResultReg);
1740 bool MipsFastISel::fastSelectInstruction(const Instruction *I) {
1741 if (!TargetSupported)
1743 switch (I->getOpcode()) {
1746 case Instruction::Load:
1747 return selectLoad(I);
1748 case Instruction::Store:
1749 return selectStore(I);
1750 case Instruction::SDiv:
1751 if (!selectBinaryOp(I, ISD::SDIV))
1752 return selectDivRem(I, ISD::SDIV);
1754 case Instruction::UDiv:
1755 if (!selectBinaryOp(I, ISD::UDIV))
1756 return selectDivRem(I, ISD::UDIV);
1758 case Instruction::SRem:
1759 if (!selectBinaryOp(I, ISD::SREM))
1760 return selectDivRem(I, ISD::SREM);
1762 case Instruction::URem:
1763 if (!selectBinaryOp(I, ISD::UREM))
1764 return selectDivRem(I, ISD::UREM);
1766 case Instruction::Shl:
1767 case Instruction::LShr:
1768 case Instruction::AShr:
1769 return selectShift(I);
1770 case Instruction::And:
1771 case Instruction::Or:
1772 case Instruction::Xor:
1773 return selectLogicalOp(I);
1774 case Instruction::Br:
1775 return selectBranch(I);
1776 case Instruction::Ret:
1777 return selectRet(I);
1778 case Instruction::Trunc:
1779 return selectTrunc(I);
1780 case Instruction::ZExt:
1781 case Instruction::SExt:
1782 return selectIntExt(I);
1783 case Instruction::FPTrunc:
1784 return selectFPTrunc(I);
1785 case Instruction::FPExt:
1786 return selectFPExt(I);
1787 case Instruction::FPToSI:
1788 return selectFPToInt(I, /*isSigned*/ true);
1789 case Instruction::FPToUI:
1790 return selectFPToInt(I, /*isSigned*/ false);
1791 case Instruction::ICmp:
1792 case Instruction::FCmp:
1793 return selectCmp(I);
1794 case Instruction::Select:
1795 return selectSelect(I);
1800 unsigned MipsFastISel::getRegEnsuringSimpleIntegerWidening(const Value *V,
1802 unsigned VReg = getRegForValue(V);
1805 MVT VMVT = TLI.getValueType(V->getType(), true).getSimpleVT();
1806 if ((VMVT == MVT::i8) || (VMVT == MVT::i16)) {
1807 unsigned TempReg = createResultReg(&Mips::GPR32RegClass);
1808 if (!emitIntExt(VMVT, VReg, MVT::i32, TempReg, IsUnsigned))
1815 void MipsFastISel::simplifyAddress(Address &Addr) {
1816 if (!isInt<16>(Addr.getOffset())) {
1818 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
1819 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1820 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
1821 Addr.setReg(DestReg);
1826 unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
1827 const TargetRegisterClass *RC,
1828 unsigned Op0, bool Op0IsKill,
1829 unsigned Op1, bool Op1IsKill) {
1830 // We treat the MUL instruction in a special way because it clobbers
1831 // the HI0 & LO0 registers. The TableGen definition of this instruction can
1832 // mark these registers only as implicitly defined. As a result, the
1833 // register allocator runs out of registers when this instruction is
1834 // followed by another instruction that defines the same registers too.
1835 // We can fix this by explicitly marking those registers as dead.
1836 if (MachineInstOpcode == Mips::MUL) {
1837 unsigned ResultReg = createResultReg(RC);
1838 const MCInstrDesc &II = TII.get(MachineInstOpcode);
1839 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
1840 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
1841 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1842 .addReg(Op0, getKillRegState(Op0IsKill))
1843 .addReg(Op1, getKillRegState(Op1IsKill))
1844 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
1845 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
1849 return FastISel::fastEmitInst_rr(MachineInstOpcode, RC, Op0, Op0IsKill, Op1,
1854 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,
1855 const TargetLibraryInfo *libInfo) {
1856 return new MipsFastISel(funcInfo, libInfo);