1 //===- MipsISelLowering.h - Mips DAG Lowering Interface ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that Mips uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
16 #define LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H
18 #include "MCTargetDesc/MipsABIInfo.h"
19 #include "MCTargetDesc/MipsBaseInfo.h"
20 #include "MCTargetDesc/MipsMCTargetDesc.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/ISDOpcodes.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGNodes.h"
27 #include "llvm/CodeGen/TargetLowering.h"
28 #include "llvm/CodeGen/ValueTypes.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/InlineAsm.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/MachineValueType.h"
33 #include "llvm/Target/TargetMachine.h"
47 class FunctionLoweringInfo;
48 class MachineBasicBlock;
49 class MachineFrameInfo;
52 class MipsFunctionInfo;
54 class MipsTargetMachine;
55 class TargetLibraryInfo;
56 class TargetRegisterClass;
60 enum NodeType : unsigned {
61 // Start the numbering from where ISD NodeType finishes.
62 FIRST_NUMBER = ISD::BUILTIN_OP_END,
64 // Jump and link (call)
70 // Get the Highest (63-48) 16 bits from a 64-bit immediate
73 // Get the Higher (47-32) 16 bits from a 64-bit immediate
76 // Get the High 16 bits from a 32/64-bit immediate
77 // No relation with Mips Hi register
80 // Get the Lower 16 bits from a 32/64-bit immediate
81 // No relation with Mips Lo register
84 // Get the High 16 bits from a 32 bit immediate for accessing the GOT.
87 // Handle gp_rel (small data/bss sections) relocation.
93 // Vector Floating Point Multiply and Subtract
96 // Floating Point Branch Conditional
99 // Floating Point Compare
102 // Floating point select
105 // Node used to generate an MTC1 i32 to f64 instruction
108 // Floating Point Conditional Moves
112 // FP-to-int truncation node.
118 // Interrupt, exception, error trap Return
121 // Software Exception Return.
124 // Node used to extract integer from accumulator.
128 // Node used to insert integers to accumulator.
160 // EXTR.W instrinsic nodes.
170 // DPA.W intrinsic nodes.
206 // DSP setcc and select_cc nodes.
210 // Vector comparisons.
211 // These take a vector and return a boolean.
217 // These take a vector and return a vector bitmask.
224 // Vector Shuffle with mask as an operand
225 VSHF, // Generic shuffle
226 SHF, // 4-element set shuffle.
227 ILVEV, // Interleave even elements
228 ILVOD, // Interleave odd elements
229 ILVL, // Interleave left elements
230 ILVR, // Interleave right elements
231 PCKEV, // Pack even elements
232 PCKOD, // Pack odd elements
235 INSVE, // Copy element from one vector to another
237 // Combined (XOR (OR $a, $b), -1)
240 // Extended vector element extraction
244 // Load/Store Left/Right nodes.
245 LWL = ISD::FIRST_TARGET_MEMORY_OPCODE,
255 } // ene namespace MipsISD
257 //===--------------------------------------------------------------------===//
258 // TargetLowering Implementation
259 //===--------------------------------------------------------------------===//
261 class MipsTargetLowering : public TargetLowering {
265 explicit MipsTargetLowering(const MipsTargetMachine &TM,
266 const MipsSubtarget &STI);
268 static const MipsTargetLowering *create(const MipsTargetMachine &TM,
269 const MipsSubtarget &STI);
271 /// createFastISel - This method returns a target specific FastISel object,
272 /// or null if the target does not support "fast" ISel.
273 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
274 const TargetLibraryInfo *libInfo) const override;
276 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
280 bool isCheapToSpeculateCttz() const override;
281 bool isCheapToSpeculateCtlz() const override;
283 /// Return the register type for a given MVT, ensuring vectors are treated
284 /// as a series of gpr sized integers.
285 MVT getRegisterTypeForCallingConv(LLVMContext &Context,
286 EVT VT) const override;
288 /// Return the number of registers for a given MVT, ensuring vectors are
289 /// treated as a series of gpr sized integers.
290 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
291 EVT VT) const override;
293 /// Break down vectors to the correct number of gpr sized integers.
294 unsigned getVectorTypeBreakdownForCallingConv(
295 LLVMContext &Context, EVT VT, EVT &IntermediateVT,
296 unsigned &NumIntermediates, MVT &RegisterVT) const override;
298 /// Return the correct alignment for the current calling convention.
299 unsigned getABIAlignmentForCallingConv(Type *ArgTy,
300 DataLayout DL) const override {
301 if (ArgTy->isVectorTy())
302 return std::min(DL.getABITypeAlignment(ArgTy), 8U);
303 return DL.getABITypeAlignment(ArgTy);
306 ISD::NodeType getExtendForAtomicOps() const override {
307 return ISD::SIGN_EXTEND;
310 void LowerOperationWrapper(SDNode *N,
311 SmallVectorImpl<SDValue> &Results,
312 SelectionDAG &DAG) const override;
314 /// LowerOperation - Provide custom lowering hooks for some operations.
315 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
317 /// ReplaceNodeResults - Replace the results of node with an illegal result
318 /// type with new values built out of custom code.
320 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
321 SelectionDAG &DAG) const override;
323 /// getTargetNodeName - This method returns the name of a target specific
325 const char *getTargetNodeName(unsigned Opcode) const override;
327 /// getSetCCResultType - get the ISD::SETCC result ValueType
328 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
329 EVT VT) const override;
331 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
334 EmitInstrWithCustomInserter(MachineInstr &MI,
335 MachineBasicBlock *MBB) const override;
337 void HandleByVal(CCState *, unsigned &, unsigned) const override;
339 unsigned getRegisterByName(const char* RegName, EVT VT,
340 SelectionDAG &DAG) const override;
342 /// If a physical register, this returns the register that receives the
343 /// exception address on entry to an EH pad.
345 getExceptionPointerRegister(const Constant *PersonalityFn) const override {
346 return ABI.IsN64() ? Mips::A0_64 : Mips::A0;
349 /// If a physical register, this returns the register that receives the
350 /// exception typeid on entry to a landing pad.
352 getExceptionSelectorRegister(const Constant *PersonalityFn) const override {
353 return ABI.IsN64() ? Mips::A1_64 : Mips::A1;
356 /// Returns true if a cast between SrcAS and DestAS is a noop.
357 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
358 // Mips doesn't have any special address spaces so we just reserve
359 // the first 256 for software use (e.g. OpenCL) and treat casts
360 // between them as noops.
361 return SrcAS < 256 && DestAS < 256;
364 bool isJumpTableRelative() const override {
365 return getTargetMachine().isPositionIndependent();
368 CCAssignFn *CCAssignFnForCall() const;
370 CCAssignFn *CCAssignFnForReturn() const;
373 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
375 // This method creates the following nodes, which are necessary for
376 // computing a local symbol's address:
378 // (add (load (wrapper $gp, %got(sym)), %lo(sym))
379 template <class NodeTy>
380 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
381 bool IsN32OrN64) const {
382 unsigned GOTFlag = IsN32OrN64 ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT;
383 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
384 getTargetNode(N, Ty, DAG, GOTFlag));
386 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT,
387 MachinePointerInfo::getGOT(DAG.getMachineFunction()));
388 unsigned LoFlag = IsN32OrN64 ? MipsII::MO_GOT_OFST : MipsII::MO_ABS_LO;
389 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty,
390 getTargetNode(N, Ty, DAG, LoFlag));
391 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo);
394 // This method creates the following nodes, which are necessary for
395 // computing a global symbol's address:
397 // (load (wrapper $gp, %got(sym)))
398 template <class NodeTy>
399 SDValue getAddrGlobal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG,
400 unsigned Flag, SDValue Chain,
401 const MachinePointerInfo &PtrInfo) const {
402 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty),
403 getTargetNode(N, Ty, DAG, Flag));
404 return DAG.getLoad(Ty, DL, Chain, Tgt, PtrInfo);
407 // This method creates the following nodes, which are necessary for
408 // computing a global symbol's address in large-GOT mode:
410 // (load (wrapper (add %hi(sym), $gp), %lo(sym)))
411 template <class NodeTy>
412 SDValue getAddrGlobalLargeGOT(NodeTy *N, const SDLoc &DL, EVT Ty,
413 SelectionDAG &DAG, unsigned HiFlag,
414 unsigned LoFlag, SDValue Chain,
415 const MachinePointerInfo &PtrInfo) const {
416 SDValue Hi = DAG.getNode(MipsISD::GotHi, DL, Ty,
417 getTargetNode(N, Ty, DAG, HiFlag));
418 Hi = DAG.getNode(ISD::ADD, DL, Ty, Hi, getGlobalReg(DAG, Ty));
419 SDValue Wrapper = DAG.getNode(MipsISD::Wrapper, DL, Ty, Hi,
420 getTargetNode(N, Ty, DAG, LoFlag));
421 return DAG.getLoad(Ty, DL, Chain, Wrapper, PtrInfo);
424 // This method creates the following nodes, which are necessary for
425 // computing a symbol's address in non-PIC mode:
427 // (add %hi(sym), %lo(sym))
429 // This method covers O32, N32 and N64 in sym32 mode.
430 template <class NodeTy>
431 SDValue getAddrNonPIC(NodeTy *N, const SDLoc &DL, EVT Ty,
432 SelectionDAG &DAG) const {
433 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
434 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
435 return DAG.getNode(ISD::ADD, DL, Ty,
436 DAG.getNode(MipsISD::Hi, DL, Ty, Hi),
437 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
440 // This method creates the following nodes, which are necessary for
441 // computing a symbol's address in non-PIC mode for N64.
443 // (add (shl (add (shl (add %highest(sym), %higher(sim)), 16), %high(sym)),
446 // FIXME: This method is not efficent for (micro)MIPS64R6.
447 template <class NodeTy>
448 SDValue getAddrNonPICSym64(NodeTy *N, const SDLoc &DL, EVT Ty,
449 SelectionDAG &DAG) const {
450 SDValue Hi = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_HI);
451 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO);
454 DAG.getNode(MipsISD::Highest, DL, Ty,
455 getTargetNode(N, Ty, DAG, MipsII::MO_HIGHEST));
456 SDValue Higher = getTargetNode(N, Ty, DAG, MipsII::MO_HIGHER);
458 DAG.getNode(ISD::ADD, DL, Ty, Highest,
459 DAG.getNode(MipsISD::Higher, DL, Ty, Higher));
460 SDValue Cst = DAG.getConstant(16, DL, MVT::i32);
461 SDValue Shift = DAG.getNode(ISD::SHL, DL, Ty, HigherPart, Cst);
462 SDValue Add = DAG.getNode(ISD::ADD, DL, Ty, Shift,
463 DAG.getNode(MipsISD::Hi, DL, Ty, Hi));
464 SDValue Shift2 = DAG.getNode(ISD::SHL, DL, Ty, Add, Cst);
466 return DAG.getNode(ISD::ADD, DL, Ty, Shift2,
467 DAG.getNode(MipsISD::Lo, DL, Ty, Lo));
470 // This method creates the following nodes, which are necessary for
471 // computing a symbol's address using gp-relative addressing:
473 // (add $gp, %gp_rel(sym))
474 template <class NodeTy>
475 SDValue getAddrGPRel(NodeTy *N, const SDLoc &DL, EVT Ty,
476 SelectionDAG &DAG, bool IsN64) const {
477 SDValue GPRel = getTargetNode(N, Ty, DAG, MipsII::MO_GPREL);
480 DAG.getRegister(IsN64 ? Mips::GP_64 : Mips::GP, Ty),
481 DAG.getNode(MipsISD::GPRel, DL, DAG.getVTList(Ty), GPRel));
484 /// This function fills Ops, which is the list of operands that will later
485 /// be used when a function call node is created. It also generates
486 /// copyToReg nodes to set up argument registers.
488 getOpndList(SmallVectorImpl<SDValue> &Ops,
489 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
490 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
491 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
492 SDValue Chain) const;
495 SDValue lowerLOAD(SDValue Op, SelectionDAG &DAG) const;
496 SDValue lowerSTORE(SDValue Op, SelectionDAG &DAG) const;
499 const MipsSubtarget &Subtarget;
500 // Cache the ABI from the TargetMachine, we use it everywhere.
501 const MipsABIInfo &ABI;
504 // Create a TargetGlobalAddress node.
505 SDValue getTargetNode(GlobalAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
506 unsigned Flag) const;
508 // Create a TargetExternalSymbol node.
509 SDValue getTargetNode(ExternalSymbolSDNode *N, EVT Ty, SelectionDAG &DAG,
510 unsigned Flag) const;
512 // Create a TargetBlockAddress node.
513 SDValue getTargetNode(BlockAddressSDNode *N, EVT Ty, SelectionDAG &DAG,
514 unsigned Flag) const;
516 // Create a TargetJumpTable node.
517 SDValue getTargetNode(JumpTableSDNode *N, EVT Ty, SelectionDAG &DAG,
518 unsigned Flag) const;
520 // Create a TargetConstantPool node.
521 SDValue getTargetNode(ConstantPoolSDNode *N, EVT Ty, SelectionDAG &DAG,
522 unsigned Flag) const;
524 // Lower Operand helpers
525 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
526 CallingConv::ID CallConv, bool isVarArg,
527 const SmallVectorImpl<ISD::InputArg> &Ins,
528 const SDLoc &dl, SelectionDAG &DAG,
529 SmallVectorImpl<SDValue> &InVals,
530 TargetLowering::CallLoweringInfo &CLI) const;
532 // Lower Operand specifics
533 SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
534 SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
535 SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
536 SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
537 SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
538 SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
539 SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
540 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
541 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
542 SDValue lowerVAARG(SDValue Op, SelectionDAG &DAG) const;
543 SDValue lowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
544 SDValue lowerFABS(SDValue Op, SelectionDAG &DAG) const;
545 SDValue lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
546 SDValue lowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
547 SDValue lowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
548 SDValue lowerATOMIC_FENCE(SDValue Op, SelectionDAG& DAG) const;
549 SDValue lowerShiftLeftParts(SDValue Op, SelectionDAG& DAG) const;
550 SDValue lowerShiftRightParts(SDValue Op, SelectionDAG& DAG,
552 SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
553 SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
555 /// isEligibleForTailCallOptimization - Check whether the call is eligible
556 /// for tail call optimization.
558 isEligibleForTailCallOptimization(const CCState &CCInfo,
559 unsigned NextStackOffset,
560 const MipsFunctionInfo &FI) const = 0;
562 /// copyByValArg - Copy argument registers which were used to pass a byval
563 /// argument to the stack. Create a stack frame object for the byval
565 void copyByValRegs(SDValue Chain, const SDLoc &DL,
566 std::vector<SDValue> &OutChains, SelectionDAG &DAG,
567 const ISD::ArgFlagsTy &Flags,
568 SmallVectorImpl<SDValue> &InVals,
569 const Argument *FuncArg, unsigned FirstReg,
570 unsigned LastReg, const CCValAssign &VA,
571 MipsCCState &State) const;
573 /// passByValArg - Pass a byval argument in registers or on stack.
574 void passByValArg(SDValue Chain, const SDLoc &DL,
575 std::deque<std::pair<unsigned, SDValue>> &RegsToPass,
576 SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr,
577 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg,
578 unsigned FirstReg, unsigned LastReg,
579 const ISD::ArgFlagsTy &Flags, bool isLittle,
580 const CCValAssign &VA) const;
582 /// writeVarArgRegs - Write variable function arguments passed in registers
583 /// to the stack. Also create a stack frame object for the first variable
585 void writeVarArgRegs(std::vector<SDValue> &OutChains, SDValue Chain,
586 const SDLoc &DL, SelectionDAG &DAG,
587 CCState &State) const;
590 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
591 const SmallVectorImpl<ISD::InputArg> &Ins,
592 const SDLoc &dl, SelectionDAG &DAG,
593 SmallVectorImpl<SDValue> &InVals) const override;
595 SDValue passArgOnStack(SDValue StackPtr, unsigned Offset, SDValue Chain,
596 SDValue Arg, const SDLoc &DL, bool IsTailCall,
597 SelectionDAG &DAG) const;
599 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
600 SmallVectorImpl<SDValue> &InVals) const override;
602 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
604 const SmallVectorImpl<ISD::OutputArg> &Outs,
605 LLVMContext &Context) const override;
607 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
608 const SmallVectorImpl<ISD::OutputArg> &Outs,
609 const SmallVectorImpl<SDValue> &OutVals,
610 const SDLoc &dl, SelectionDAG &DAG) const override;
612 SDValue LowerInterruptReturn(SmallVectorImpl<SDValue> &RetOps,
613 const SDLoc &DL, SelectionDAG &DAG) const;
615 bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const override;
617 // Inline asm support
618 ConstraintType getConstraintType(StringRef Constraint) const override;
620 /// Examine constraint string and operand type and determine a weight value.
621 /// The operand object must already have been set up with the operand type.
622 ConstraintWeight getSingleConstraintMatchWeight(
623 AsmOperandInfo &info, const char *constraint) const override;
625 /// This function parses registers that appear in inline-asm constraints.
626 /// It returns pair (0, 0) on failure.
627 std::pair<unsigned, const TargetRegisterClass *>
628 parseRegForInlineAsmConstraint(StringRef C, MVT VT) const;
630 std::pair<unsigned, const TargetRegisterClass *>
631 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
632 StringRef Constraint, MVT VT) const override;
634 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
635 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
636 /// true it means one of the asm constraint of the inline asm instruction
637 /// being processed is 'm'.
638 void LowerAsmOperandForConstraint(SDValue Op,
639 std::string &Constraint,
640 std::vector<SDValue> &Ops,
641 SelectionDAG &DAG) const override;
644 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
645 if (ConstraintCode == "R")
646 return InlineAsm::Constraint_R;
647 else if (ConstraintCode == "ZC")
648 return InlineAsm::Constraint_ZC;
649 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
652 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
653 Type *Ty, unsigned AS,
654 Instruction *I = nullptr) const override;
656 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
658 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
660 bool IsMemset, bool ZeroMemset,
662 MachineFunction &MF) const override;
664 /// isFPImmLegal - Returns true if the target can instruction select the
665 /// specified FP immediate natively. If false, the legalizer will
666 /// materialize the FP immediate as a load from a constant pool.
667 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
669 unsigned getJumpTableEncoding() const override;
670 bool useSoftFloat() const override;
672 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
676 /// Emit a sign-extension using sll/sra, seb, or seh appropriately.
677 MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr &MI,
678 MachineBasicBlock *BB,
679 unsigned Size, unsigned DstReg,
680 unsigned SrcRec) const;
682 MachineBasicBlock *emitAtomicBinary(MachineInstr &MI,
683 MachineBasicBlock *BB) const;
684 MachineBasicBlock *emitAtomicBinaryPartword(MachineInstr &MI,
685 MachineBasicBlock *BB,
686 unsigned Size) const;
687 MachineBasicBlock *emitAtomicCmpSwap(MachineInstr &MI,
688 MachineBasicBlock *BB) const;
689 MachineBasicBlock *emitAtomicCmpSwapPartword(MachineInstr &MI,
690 MachineBasicBlock *BB,
691 unsigned Size) const;
692 MachineBasicBlock *emitSEL_D(MachineInstr &MI, MachineBasicBlock *BB) const;
693 MachineBasicBlock *emitPseudoSELECT(MachineInstr &MI, MachineBasicBlock *BB,
694 bool isFPCmp, unsigned Opc) const;
697 /// Create MipsTargetLowering objects.
698 const MipsTargetLowering *
699 createMips16TargetLowering(const MipsTargetMachine &TM,
700 const MipsSubtarget &STI);
701 const MipsTargetLowering *
702 createMipsSETargetLowering(const MipsTargetMachine &TM,
703 const MipsSubtarget &STI);
707 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
708 const TargetLibraryInfo *libInfo);
710 } // end namespace Mips
712 } // end namespace llvm
714 #endif // LLVM_LIB_TARGET_MIPS_MIPSISELLOWERING_H