lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  39                                        "PPC::DIR_E500mc", "">;
  40 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  41                                        "PPC::DIR_E5500", "">;
  42 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
  43 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
  44 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
  45 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
  46 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  47 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
  48 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  49 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
  50
  51 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  52                                         "Enable 64-bit instructions">;
  53 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  54                               "Enable 64-bit registers usage for ppc32 [beta]">;
  55 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
  56                               "Use condition-register bits individually">;
  57 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  58                                         "Enable Altivec instructions">;
  59 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  60                                         "Enable the MFOCRF instruction">;
  61 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  62                                         "Enable the fsqrt instruction">;
  63 def FeatureFCPSGN    : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
  64                                         "Enable the fcpsgn instruction">;
  65 def FeatureFRE       : SubtargetFeature<"fre", "HasFRE", "true",
  66                                         "Enable the fre instruction">;
  67 def FeatureFRES      : SubtargetFeature<"fres", "HasFRES", "true",
  68                                         "Enable the fres instruction">;
  69 def FeatureFRSQRTE   : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
  70                                         "Enable the frsqrte instruction">;
  71 def FeatureFRSQRTES  : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
  72                                         "Enable the frsqrtes instruction">;
  73 def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
  74                               "Assume higher precision reciprocal estimates">;
  75 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  76                                         "Enable the stfiwx instruction">;
  77 def FeatureLFIWAX    : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
  78                                         "Enable the lfiwax instruction">;
  79 def FeatureFPRND     : SubtargetFeature<"fprnd", "HasFPRND", "true",
  80                                         "Enable the fri[mnpz] instructions">;
  81 def FeatureFPCVT     : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
  82   "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
  83 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  84                                         "Enable the isel instruction">;
  85 def FeaturePOPCNTD   : SubtargetFeature<"popcntd","HasPOPCNTD", "true",
  86                                         "Enable the popcnt[dw] instructions">;
  87 def FeatureLDBRX     : SubtargetFeature<"ldbrx","HasLDBRX", "true",
  88                                         "Enable the ldbrx instruction">;
  89 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
  90                                         "Enable Book E instructions">;
  91 def FeatureQPX       : SubtargetFeature<"qpx","HasQPX", "true",
  92                                         "Enable QPX instructions">;
  93 def FeatureVSX       : SubtargetFeature<"vsx","HasVSX", "true",
  94                                         "Enable VSX instructions",
  95                                         [FeatureAltivec]>;
  96
  97 def DeprecatedMFTB   : SubtargetFeature<"", "DeprecatedMFTB", "true",
  98                                         "Treat mftb as deprecated">;
  99 def DeprecatedDST    : SubtargetFeature<"", "DeprecatedDST", "true",
 100   "Treat vector data stream cache control instructions as deprecated">;
 101
 102 // Note: Future features to add when support is extended to more
 103 // recent ISA levels:
 104 //
 105 // CMPB         p6, p6x, p7        cmpb
 106 // DFP          p6, p6x, p7        decimal floating-point instructions
 107 // POPCNTB      p5 through p7      popcntb and related instructions
 108 // VSX          p7                 vector-scalar instruction set
 109
 110 //===----------------------------------------------------------------------===//
 111 // Classes used for relation maps.
 112 //===----------------------------------------------------------------------===//
 113 // RecFormRel - Filter class used to relate non-record-form instructions with
 114 // their record-form variants.
 115 class RecFormRel;
 116
 117 // AltVSXFMARel - Filter class used to relate the primary addend-killing VSX
 118 // FMA instruction forms with their corresponding factor-killing forms.
 119 class AltVSXFMARel {
 120   bit IsVSXFMAAlt = 0;
 121 }
 122
 123 //===----------------------------------------------------------------------===//
 124 // Relation Map Definitions.
 125 //===----------------------------------------------------------------------===//
 126
 127 def getRecordFormOpcode : InstrMapping {
 128   let FilterClass = "RecFormRel";
 129   // Instructions with the same BaseName and Interpretation64Bit values
 130   // form a row.
 131   let RowFields = ["BaseName", "Interpretation64Bit"];
 132   // Instructions with the same RC value form a column.
 133   let ColFields = ["RC"];
 134   // The key column are the non-record-form instructions.
 135   let KeyCol = ["0"];
 136   // Value columns RC=1
 137   let ValueCols = [["1"]];
 138 }
 139
 140 def getNonRecordFormOpcode : InstrMapping {
 141   let FilterClass = "RecFormRel";
 142   // Instructions with the same BaseName and Interpretation64Bit values
 143   // form a row.
 144   let RowFields = ["BaseName", "Interpretation64Bit"];
 145   // Instructions with the same RC value form a column.
 146   let ColFields = ["RC"];
 147   // The key column are the record-form instructions.
 148   let KeyCol = ["1"];
 149   // Value columns are RC=0
 150   let ValueCols = [["0"]];
 151 }
 152
 153 def getAltVSXFMAOpcode : InstrMapping {
 154   let FilterClass = "AltVSXFMARel";
 155   // Instructions with the same BaseName and Interpretation64Bit values
 156   // form a row.
 157   let RowFields = ["BaseName"];
 158   // Instructions with the same RC value form a column.
 159   let ColFields = ["IsVSXFMAAlt"];
 160   // The key column are the (default) addend-killing instructions.
 161   let KeyCol = ["0"];
 162   // Value columns IsVSXFMAAlt=1
 163   let ValueCols = [["1"]];
 164 }
 165
 166 //===----------------------------------------------------------------------===//
 167 // Register File Description
 168 //===----------------------------------------------------------------------===//
 169
 170 include "PPCRegisterInfo.td"
 171 include "PPCSchedule.td"
 172 include "PPCInstrInfo.td"
 173
 174 //===----------------------------------------------------------------------===//
 175 // PowerPC processors supported.
 176 //
 177
 178 def : Processor<"generic", G3Itineraries, [Directive32]>;
 179 def : ProcessorModel<"440", PPC440Model, [Directive440, FeatureISEL,
 180                                           FeatureFRES, FeatureFRSQRTE,
 181                                           FeatureBookE, DeprecatedMFTB]>;
 182 def : ProcessorModel<"450", PPC440Model, [Directive440, FeatureISEL,
 183                                           FeatureFRES, FeatureFRSQRTE,
 184                                           FeatureBookE, DeprecatedMFTB]>;
 185 def : Processor<"601", G3Itineraries, [Directive601]>;
 186 def : Processor<"602", G3Itineraries, [Directive602]>;
 187 def : Processor<"603", G3Itineraries, [Directive603,
 188                                        FeatureFRES, FeatureFRSQRTE]>;
 189 def : Processor<"603e", G3Itineraries, [Directive603,
 190                                         FeatureFRES, FeatureFRSQRTE]>;
 191 def : Processor<"603ev", G3Itineraries, [Directive603,
 192                                          FeatureFRES, FeatureFRSQRTE]>;
 193 def : Processor<"604", G3Itineraries, [Directive604,
 194                                        FeatureFRES, FeatureFRSQRTE]>;
 195 def : Processor<"604e", G3Itineraries, [Directive604,
 196                                         FeatureFRES, FeatureFRSQRTE]>;
 197 def : Processor<"620", G3Itineraries, [Directive620,
 198                                        FeatureFRES, FeatureFRSQRTE]>;
 199 def : Processor<"750", G4Itineraries, [Directive750,
 200                                        FeatureFRES, FeatureFRSQRTE]>;
 201 def : Processor<"g3", G3Itineraries, [Directive750,
 202                                       FeatureFRES, FeatureFRSQRTE]>;
 203 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec,
 204                                         FeatureFRES, FeatureFRSQRTE]>;
 205 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec,
 206                                       FeatureFRES, FeatureFRSQRTE]>;
 207 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec,
 208                                             FeatureFRES, FeatureFRSQRTE]>;
 209 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec,
 210                                            FeatureFRES, FeatureFRSQRTE]>;
 211 def : ProcessorModel<"970", G5Model,
 212                   [Directive970, FeatureAltivec,
 213                    FeatureMFOCRF, FeatureFSqrt,
 214                    FeatureFRES, FeatureFRSQRTE, FeatureSTFIWX,
 215                    Feature64Bit /*, Feature64BitRegs */]>;
 216 def : ProcessorModel<"g5", G5Model,
 217                   [Directive970, FeatureAltivec,
 218                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 219                    FeatureFRES, FeatureFRSQRTE,
 220                    Feature64Bit /*, Feature64BitRegs */,
 221                    DeprecatedMFTB, DeprecatedDST]>;
 222 def : ProcessorModel<"e500mc", PPCE500mcModel,
 223                   [DirectiveE500mc, FeatureMFOCRF,
 224                    FeatureSTFIWX, FeatureBookE, FeatureISEL,
 225                    DeprecatedMFTB]>;
 226 def : ProcessorModel<"e5500", PPCE5500Model,
 227                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 228                    FeatureSTFIWX, FeatureBookE, FeatureISEL,
 229                    DeprecatedMFTB]>;
 230 def : ProcessorModel<"a2", PPCA2Model,
 231                   [DirectiveA2, FeatureBookE, FeatureMFOCRF,
 232                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 233                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 234                    FeatureSTFIWX, FeatureLFIWAX,
 235                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 236                    FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
 237                /*, Feature64BitRegs */, DeprecatedMFTB]>;
 238 def : ProcessorModel<"a2q", PPCA2Model,
 239                   [DirectiveA2, FeatureBookE, FeatureMFOCRF,
 240                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 241                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 242                    FeatureSTFIWX, FeatureLFIWAX,
 243                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 244                    FeaturePOPCNTD, FeatureLDBRX, Feature64Bit
 245                /*, Feature64BitRegs */, FeatureQPX, DeprecatedMFTB]>;
 246 def : ProcessorModel<"pwr3", G5Model,
 247                   [DirectivePwr3, FeatureAltivec,
 248                    FeatureFRES, FeatureFRSQRTE, FeatureMFOCRF,
 249                    FeatureSTFIWX, Feature64Bit]>;
 250 def : ProcessorModel<"pwr4", G5Model,
 251                   [DirectivePwr4, FeatureAltivec, FeatureMFOCRF,
 252                    FeatureFSqrt, FeatureFRES, FeatureFRSQRTE,
 253                    FeatureSTFIWX, Feature64Bit]>;
 254 def : ProcessorModel<"pwr5", G5Model,
 255                   [DirectivePwr5, FeatureAltivec, FeatureMFOCRF,
 256                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 257                    FeatureFRSQRTE, FeatureFRSQRTES,
 258                    FeatureSTFIWX, Feature64Bit,
 259                    DeprecatedMFTB, DeprecatedDST]>;
 260 def : ProcessorModel<"pwr5x", G5Model,
 261                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 262                    FeatureFSqrt, FeatureFRE, FeatureFRES,
 263                    FeatureFRSQRTE, FeatureFRSQRTES,
 264                    FeatureSTFIWX, FeatureFPRND, Feature64Bit,
 265                    DeprecatedMFTB, DeprecatedDST]>;
 266 def : ProcessorModel<"pwr6", G5Model,
 267                   [DirectivePwr6, FeatureAltivec,
 268                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 269                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 270                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 271                    FeatureFPRND, Feature64Bit /*, Feature64BitRegs */,
 272                    DeprecatedMFTB, DeprecatedDST]>;
 273 def : ProcessorModel<"pwr6x", G5Model,
 274                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
 275                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
 276                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
 277                    FeatureSTFIWX, FeatureLFIWAX,
 278                    FeatureFPRND, Feature64Bit,
 279                    DeprecatedMFTB, DeprecatedDST]>;
 280 def : ProcessorModel<"pwr7", P7Model,
 281                   [DirectivePwr7, FeatureAltivec,
 282                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 283                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 284                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 285                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 286                    FeaturePOPCNTD, FeatureLDBRX,
 287                    Feature64Bit /*, Feature64BitRegs */,
 288                    DeprecatedMFTB, DeprecatedDST]>;
 289 def : ProcessorModel<"pwr8", P7Model /* FIXME: Update to P8Model when available */,
 290                   [DirectivePwr8, FeatureAltivec,
 291                    FeatureMFOCRF, FeatureFCPSGN, FeatureFSqrt, FeatureFRE,
 292                    FeatureFRES, FeatureFRSQRTE, FeatureFRSQRTES,
 293                    FeatureRecipPrec, FeatureSTFIWX, FeatureLFIWAX,
 294                    FeatureFPRND, FeatureFPCVT, FeatureISEL,
 295                    FeaturePOPCNTD, FeatureLDBRX,
 296                    Feature64Bit /*, Feature64BitRegs */,
 297                    DeprecatedMFTB, DeprecatedDST]>;
 298 def : Processor<"ppc", G3Itineraries, [Directive32]>;
 299 def : ProcessorModel<"ppc64", G5Model,
 300                   [Directive64, FeatureAltivec,
 301                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 302                    FeatureFRSQRTE, FeatureSTFIWX,
 303                    Feature64Bit /*, Feature64BitRegs */]>;
 304 def : ProcessorModel<"ppc64le", G5Model,
 305                   [Directive64, FeatureAltivec,
 306                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
 307                    FeatureFRSQRTE, FeatureSTFIWX,
 308                    Feature64Bit /*, Feature64BitRegs */]>;
 309
 310 //===----------------------------------------------------------------------===//
 311 // Calling Conventions
 312 //===----------------------------------------------------------------------===//
 313
 314 include "PPCCallingConv.td"
 315
 316 def PPCInstrInfo : InstrInfo {
 317   let isLittleEndianEncoding = 1;
 318
 319   // FIXME: Unset this when no longer needed!
 320   let decodePositionallyEncodedOperands = 1;
 321
 322   let noNamedPositionallyEncodedOperands = 1;
 323 }
 324
 325 def PPCAsmParser : AsmParser {
 326   let ShouldEmitMatchRegisterName = 0;
 327 }
 328
 329 def PPCAsmParserVariant : AsmParserVariant {
 330   int Variant = 0;
 331
 332   // We do not use hard coded registers in asm strings.  However, some
 333   // InstAlias definitions use immediate literals.  Set RegisterPrefix
 334   // so that those are not misinterpreted as registers.
 335   string RegisterPrefix = "%";
 336 }
 337
 338 def PPC : Target {
 339   // Information about the instructions.
 340   let InstructionSet = PPCInstrInfo;
 341
 342   let AssemblyParsers = [PPCAsmParser];
 343   let AssemblyParserVariants = [PPCAsmParserVariant];
 344 }