lib/Target/PowerPC/PPC.td

   1 //===-- PPC.td - Describe the PowerPC Target Machine -------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // PowerPC Subtarget features.
  20 //
  21
  22 //===----------------------------------------------------------------------===//
  23 // CPU Directives                                                             //
  24 //===----------------------------------------------------------------------===//
  25
  26 def Directive440 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_440", "">;
  27 def Directive601 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_601", "">;
  28 def Directive602 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_602", "">;
  29 def Directive603 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  30 def Directive604 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  31 def Directive620 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_603", "">;
  32 def Directive7400: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_7400", "">;
  33 def Directive750 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_750", "">;
  34 def Directive970 : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_970", "">;
  35 def Directive32  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_32", "">;
  36 def Directive64  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_64", "">;
  37 def DirectiveA2  : SubtargetFeature<"", "DarwinDirective", "PPC::DIR_A2", "">;
  38 def DirectiveE500mc : SubtargetFeature<"", "DarwinDirective",
  39                                        "PPC::DIR_E500mc", "">;
  40 def DirectiveE5500  : SubtargetFeature<"", "DarwinDirective",
  41                                        "PPC::DIR_E5500", "">;
  42 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
  43 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
  44
  45 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
  46                                         "Enable 64-bit instructions">;
  47 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
  48                               "Enable 64-bit registers usage for ppc32 [beta]">;
  49 def FeatureAltivec   : SubtargetFeature<"altivec","HasAltivec", "true",
  50                                         "Enable Altivec instructions">;
  51 def FeatureMFOCRF    : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
  52                                         "Enable the MFOCRF instruction">;
  53 def FeatureFSqrt     : SubtargetFeature<"fsqrt","HasFSQRT", "true",
  54                                         "Enable the fsqrt instruction">;
  55 def FeatureSTFIWX    : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
  56                                         "Enable the stfiwx instruction">;
  57 def FeatureISEL      : SubtargetFeature<"isel","HasISEL", "true",
  58                                         "Enable the isel instruction">;
  59 def FeatureBookE     : SubtargetFeature<"booke", "IsBookE", "true",
  60                                         "Enable Book E instructions">;
  61
  62 //===----------------------------------------------------------------------===//
  63 // Register File Description
  64 //===----------------------------------------------------------------------===//
  65
  66 include "PPCRegisterInfo.td"
  67 include "PPCSchedule.td"
  68 include "PPCInstrInfo.td"
  69
  70 //===----------------------------------------------------------------------===//
  71 // PowerPC processors supported.
  72 //
  73
  74 def : Processor<"generic", G3Itineraries, [Directive32]>;
  75 def : Processor<"440", PPC440Itineraries, [Directive440, FeatureISEL,
  76                                            FeatureBookE]>;
  77 def : Processor<"450", PPC440Itineraries, [Directive440, FeatureISEL,
  78                                            FeatureBookE]>;
  79 def : Processor<"601", G3Itineraries, [Directive601]>;
  80 def : Processor<"602", G3Itineraries, [Directive602]>;
  81 def : Processor<"603", G3Itineraries, [Directive603]>;
  82 def : Processor<"603e", G3Itineraries, [Directive603]>;
  83 def : Processor<"603ev", G3Itineraries, [Directive603]>;
  84 def : Processor<"604", G3Itineraries, [Directive604]>;
  85 def : Processor<"604e", G3Itineraries, [Directive604]>;
  86 def : Processor<"620", G3Itineraries, [Directive620]>;
  87 def : Processor<"750", G4Itineraries, [Directive750]>;
  88 def : Processor<"g3", G3Itineraries, [Directive750]>;
  89 def : Processor<"7400", G4Itineraries, [Directive7400, FeatureAltivec]>;
  90 def : Processor<"g4", G4Itineraries, [Directive7400, FeatureAltivec]>;
  91 def : Processor<"7450", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
  92 def : Processor<"g4+", G4PlusItineraries, [Directive7400, FeatureAltivec]>;
  93 def : Processor<"970", G5Itineraries,
  94                   [Directive970, FeatureAltivec,
  95                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
  96                    Feature64Bit /*, Feature64BitRegs */]>;
  97 def : Processor<"g5", G5Itineraries,
  98                   [Directive970, FeatureAltivec,
  99                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 100                    Feature64Bit /*, Feature64BitRegs */]>;
 101 def : ProcessorModel<"e500mc", PPCE500mcModel,
 102                   [DirectiveE500mc, FeatureMFOCRF,
 103                    FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
 104 def : ProcessorModel<"e5500", PPCE5500Model,
 105                   [DirectiveE5500, FeatureMFOCRF, Feature64Bit,
 106                    FeatureSTFIWX, FeatureBookE, FeatureISEL]>;
 107 def : Processor<"a2", PPCA2Itineraries, [DirectiveA2, FeatureBookE,
 108                                          FeatureMFOCRF, FeatureFSqrt,
 109                                          FeatureSTFIWX, FeatureISEL,
 110                                          Feature64Bit
 111                                      /*, Feature64BitRegs */]>;
 112 def : Processor<"pwr6", G5Itineraries,
 113                   [DirectivePwr6, FeatureAltivec,
 114                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 115                    Feature64Bit /*, Feature64BitRegs */]>;
 116 def : Processor<"pwr7", G5Itineraries,
 117                   [DirectivePwr7, FeatureAltivec,
 118                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 119                    FeatureISEL, Feature64Bit /*, Feature64BitRegs */]>;
 120 def : Processor<"ppc", G3Itineraries, [Directive32]>;
 121 def : Processor<"ppc64", G5Itineraries,
 122                   [Directive64, FeatureAltivec,
 123                    FeatureMFOCRF, FeatureFSqrt, FeatureSTFIWX,
 124                    Feature64Bit /*, Feature64BitRegs */]>;
 125
 126
 127 //===----------------------------------------------------------------------===//
 128 // Calling Conventions
 129 //===----------------------------------------------------------------------===//
 130
 131 include "PPCCallingConv.td"
 132
 133 def PPCInstrInfo : InstrInfo {
 134   let isLittleEndianEncoding = 1;
 135 }
 136
 137 def PPCAsmWriter : AsmWriter {
 138   string AsmWriterClassName  = "InstPrinter";
 139   bit isMCAsmWriter = 1;
 140 }
 141
 142 def PPC : Target {
 143   // Information about the instructions.
 144   let InstructionSet = PPCInstrInfo;
 145
 146   let AssemblyWriters = [PPCAsmWriter];
 147 }