1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the interfaces that PPC uses to lower LLVM code into a
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
15 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
18 #include "PPCInstrInfo.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineMemOperand.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGNodes.h"
24 #include "llvm/CodeGen/TargetLowering.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/IR/Attributes.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/IR/Metadata.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/MachineValueType.h"
39 // When adding a NEW PPCISD node please add it to the correct position in
40 // the enum. The order of elements in this enum matters!
41 // Values that are added after this entry:
42 // STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE
43 // are considerd memory opcodes and are treated differently than entries
44 // that come before it. For example, ADD or MUL should be placed before
45 // the ISD::FIRST_TARGET_MEMORY_OPCODE while a LOAD or STORE should come
47 enum NodeType : unsigned {
48 // Start the numbering where the builtin ops and target ops leave off.
49 FIRST_NUMBER = ISD::BUILTIN_OP_END,
51 /// FSEL - Traditional three-operand fsel node.
55 /// FCFID - The FCFID instruction, taking an f64 operand and producing
56 /// and f64 value containing the FP representation of the integer that
57 /// was temporarily in the f64 operand.
60 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
61 /// unsigned integers and single-precision outputs.
62 FCFIDU, FCFIDS, FCFIDUS,
64 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
65 /// operand, producing an f64 value containing the integer representation
69 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
70 /// unsigned integers with round toward zero.
73 /// Floating-point-to-interger conversion instructions
74 FP_TO_UINT_IN_VSR, FP_TO_SINT_IN_VSR,
76 /// VEXTS, ByteWidth - takes an input in VSFRC and produces an output in
77 /// VSFRC that is sign-extended from ByteWidth to a 64-byte integer.
80 /// SExtVElems, takes an input vector of a smaller type and sign
81 /// extends to an output vector of a larger type.
84 /// Reciprocal estimate instructions (unary FP ops).
87 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
88 // three v4f32 operands and producing a v4f32 result.
91 /// VPERM - The PPC VPERM Instruction.
95 /// XXSPLT - The PPC VSX splat instructions
99 /// VECINSERT - The PPC vector insert instruction
103 /// XXREVERSE - The PPC VSX reverse instruction
107 /// VECSHL - The PPC vector shift left instruction
111 /// XXPERMDI - The PPC XXPERMDI instruction
115 /// The CMPB instruction (takes two operands of i32 or i64).
118 /// Hi/Lo - These represent the high and low 16-bit parts of a global
119 /// address respectively. These nodes have two operands, the first of
120 /// which must be a TargetGlobalAddress, and the second of which must be a
121 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
122 /// though these are usually folded into other nodes.
125 /// The following two target-specific nodes are used for calls through
126 /// function pointers in the 64-bit SVR4 ABI.
128 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
129 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
130 /// compute an allocation on the stack.
133 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
134 /// compute an offset from native SP to the address of the most recent
138 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
139 /// at function entry, used for PIC code.
142 /// These nodes represent PPC shifts.
144 /// For scalar types, only the last `n + 1` bits of the shift amounts
145 /// are used, where n is log2(sizeof(element) * 8). See sld/slw, etc.
146 /// for exact behaviors.
148 /// For vector types, only the last n bits are used. See vsld.
151 /// EXTSWSLI = The PPC extswsli instruction, which does an extend-sign
152 /// word and shift left immediate.
155 /// The combination of sra[wd]i and addze used to implemented signed
156 /// integer division by a power of 2. The first operand is the dividend,
157 /// and the second is the constant shift amount (representing the
161 /// CALL - A direct function call.
162 /// CALL_NOP is a call with the special NOP which follows 64-bit
166 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
167 /// MTCTR instruction.
170 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
171 /// BCTRL instruction.
174 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
175 /// instruction and the TOC reload required on SVR4 PPC64.
178 /// Return with a flag operand, matched by 'blr'
181 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
182 /// This copies the bits corresponding to the specified CRREG into the
183 /// resultant GPR. Bits corresponding to other CR regs are undefined.
186 /// Direct move from a VSX register to a GPR
189 /// Direct move from a GPR to a VSX register (algebraic)
192 /// Direct move from a GPR to a VSX register (zero)
195 /// Direct move of 2 consective GPR to a VSX register.
198 /// Extract a subvector from signed integer vector and convert to FP.
199 /// It is primarily used to convert a (widened) illegal integer vector
200 /// type to a legal floating point vector type.
201 /// For example v2i32 -> widened to v4i32 -> v2f64
204 /// Extract a subvector from unsigned integer vector and convert to FP.
205 /// As with SINT_VEC_TO_FP, used for converting illegal types.
208 // FIXME: Remove these once the ANDI glue bug is fixed:
209 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
210 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
211 /// implement truncation of i32 or i64 to i1.
212 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
214 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
215 // target (returns (Lo, Hi)). It takes a chain operand.
218 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
221 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
224 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
225 /// instructions. For lack of better number, we use the opcode number
226 /// encoding for the OPC field to identify the compare. For example, 838
230 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
231 /// altivec VCMP*o instructions. For lack of better number, we use the
232 /// opcode number encoding for the OPC field to identify the compare. For
233 /// example, 838 is VCMPGTSH.
236 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
237 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
238 /// condition register to branch on, OPC is the branch opcode to use (e.g.
239 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
240 /// an optional input flag argument.
243 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
247 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
248 /// towards zero. Used only as part of the long double-to-int
249 /// conversion sequence.
252 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
255 /// TC_RETURN - A tail call return.
257 /// operand #1 callee (register or absolute)
258 /// operand #2 stack adjustment
259 /// operand #3 optional in flag
262 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
266 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
270 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
271 /// local dynamic TLS on PPC32.
274 /// G8RC = ADDIS_GOT_TPREL_HA %x2, Symbol - Used by the initial-exec
275 /// TLS model, produces an ADDIS8 instruction that adds the GOT
276 /// base to sym\@got\@tprel\@ha.
279 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
280 /// TLS model, produces a LD instruction with base register G8RReg
281 /// and offset sym\@got\@tprel\@l. This completes the addition that
282 /// finds the offset of "sym" relative to the thread pointer.
285 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
286 /// model, produces an ADD instruction that adds the contents of
287 /// G8RReg to the thread pointer. Symbol contains a relocation
288 /// sym\@tls which is to be replaced by the thread pointer and
289 /// identifies to the linker that the instruction is part of a
293 /// G8RC = ADDIS_TLSGD_HA %x2, Symbol - For the general-dynamic TLS
294 /// model, produces an ADDIS8 instruction that adds the GOT base
295 /// register to sym\@got\@tlsgd\@ha.
298 /// %x3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
299 /// model, produces an ADDI8 instruction that adds G8RReg to
300 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
301 /// ADDIS_TLSGD_L_ADDR until after register assignment.
304 /// %x3 = GET_TLS_ADDR %x3, Symbol - For the general-dynamic TLS
305 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
306 /// ADDIS_TLSGD_L_ADDR until after register assignment.
309 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
310 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
311 /// register assignment.
314 /// G8RC = ADDIS_TLSLD_HA %x2, Symbol - For the local-dynamic TLS
315 /// model, produces an ADDIS8 instruction that adds the GOT base
316 /// register to sym\@got\@tlsld\@ha.
319 /// %x3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
320 /// model, produces an ADDI8 instruction that adds G8RReg to
321 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
322 /// ADDIS_TLSLD_L_ADDR until after register assignment.
325 /// %x3 = GET_TLSLD_ADDR %x3, Symbol - For the local-dynamic TLS
326 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
327 /// ADDIS_TLSLD_L_ADDR until after register assignment.
330 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
331 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
332 /// following register assignment.
335 /// G8RC = ADDIS_DTPREL_HA %x3, Symbol - For the local-dynamic TLS
336 /// model, produces an ADDIS8 instruction that adds X3 to
340 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
341 /// model, produces an ADDI8 instruction that adds G8RReg to
342 /// sym\@got\@dtprel\@l.
345 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
346 /// during instruction selection to optimize a BUILD_VECTOR into
347 /// operations on splats. This is necessary to avoid losing these
348 /// optimizations due to constant folding.
351 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
352 /// operand identifies the operating system entry point.
355 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
358 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
359 /// history rolling buffer entry.
362 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
365 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
366 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
367 /// or stxvd2x instruction. The chain is necessary because the
368 /// sequence replaces a load and needs to provide the same number
372 /// An SDNode for swaps that are not associated with any loads/stores
373 /// and thereby have no chain.
376 /// An SDNode for Power9 vector absolute value difference.
377 /// operand #0 vector
378 /// operand #1 vector
379 /// operand #2 constant i32 0 or 1, to indicate whether needs to patch
380 /// the most significant bit for signed i32
382 /// Power9 VABSD* instructions are designed to support unsigned integer
383 /// vectors (byte/halfword/word), if we want to make use of them for signed
384 /// integer vectors, we have to flip their sign bits first. To flip sign bit
385 /// for byte/halfword integer vector would become inefficient, but for word
386 /// integer vector, we can leverage XVNEGSP to make it efficiently. eg:
387 /// abs(sub(a,b)) => VABSDUW(a+0x80000000, b+0x80000000)
388 /// => VABSDUW((XVNEGSP a), (XVNEGSP b))
391 /// QVFPERM = This corresponds to the QPX qvfperm instruction.
394 /// QVGPCI = This corresponds to the QPX qvgpci instruction.
397 /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
400 /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
403 /// QBFLT = Access the underlying QPX floating-point boolean
407 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
408 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
409 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
411 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
413 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
414 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
415 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
419 /// STFIWX - The STFIWX instruction. The first operand is an input token
420 /// chain, then an f64 value to store, then an address to store it to.
423 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
424 /// load which sign-extends from a 32-bit integer value into the
425 /// destination 64-bit register.
428 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
429 /// load which zero-extends from a 32-bit integer value into the
430 /// destination 64-bit register.
433 /// GPRC, CHAIN = LXSIZX, CHAIN, Ptr, ByteWidth - This is a load of an
434 /// integer smaller than 64 bits into a VSR. The integer is zero-extended.
435 /// This can be used for converting loaded integers to floating point.
438 /// STXSIX - The STXSI[bh]X instruction. The first operand is an input
439 /// chain, then an f64 value to store, then an address to store it to,
440 /// followed by a byte-width for the store.
443 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
444 /// Maps directly to an lxvd2x instruction that will be followed by
448 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
449 /// Maps directly to an stxvd2x instruction that will be preceded by
453 /// Store scalar integers from VSR.
456 /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
457 /// The 4xf32 load used for v4i1 constants.
460 /// ATOMIC_CMP_SWAP - the exact same as the target-independent nodes
461 /// except they ensure that the compare input is zero-extended for
462 /// sub-word versions because the atomic loads zero-extend.
463 ATOMIC_CMP_SWAP_8, ATOMIC_CMP_SWAP_16,
465 /// GPRC = TOC_ENTRY GA, TOC
466 /// Loads the entry for GA from the TOC, where the TOC base is given by
467 /// the last operand.
471 } // end namespace PPCISD
473 /// Define some predicates that are used for node matching.
476 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
477 /// VPKUHUM instruction.
478 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
481 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
482 /// VPKUWUM instruction.
483 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
486 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
487 /// VPKUDUM instruction.
488 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
491 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
492 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
493 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
494 unsigned ShuffleKind, SelectionDAG &DAG);
496 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
497 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
498 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
499 unsigned ShuffleKind, SelectionDAG &DAG);
501 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
502 /// a VMRGEW or VMRGOW instruction
503 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
504 unsigned ShuffleKind, SelectionDAG &DAG);
505 /// isXXSLDWIShuffleMask - Return true if this is a shuffle mask suitable
506 /// for a XXSLDWI instruction.
507 bool isXXSLDWIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
508 bool &Swap, bool IsLE);
510 /// isXXBRHShuffleMask - Return true if this is a shuffle mask suitable
511 /// for a XXBRH instruction.
512 bool isXXBRHShuffleMask(ShuffleVectorSDNode *N);
514 /// isXXBRWShuffleMask - Return true if this is a shuffle mask suitable
515 /// for a XXBRW instruction.
516 bool isXXBRWShuffleMask(ShuffleVectorSDNode *N);
518 /// isXXBRDShuffleMask - Return true if this is a shuffle mask suitable
519 /// for a XXBRD instruction.
520 bool isXXBRDShuffleMask(ShuffleVectorSDNode *N);
522 /// isXXBRQShuffleMask - Return true if this is a shuffle mask suitable
523 /// for a XXBRQ instruction.
524 bool isXXBRQShuffleMask(ShuffleVectorSDNode *N);
526 /// isXXPERMDIShuffleMask - Return true if this is a shuffle mask suitable
527 /// for a XXPERMDI instruction.
528 bool isXXPERMDIShuffleMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
529 bool &Swap, bool IsLE);
531 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
532 /// shift amount, otherwise return -1.
533 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
536 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
537 /// specifies a splat of a single element that is suitable for input to
538 /// VSPLTB/VSPLTH/VSPLTW.
539 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
541 /// isXXINSERTWMask - Return true if this VECTOR_SHUFFLE can be handled by
542 /// the XXINSERTW instruction introduced in ISA 3.0. This is essentially any
543 /// shuffle of v4f32/v4i32 vectors that just inserts one element from one
544 /// vector into the other. This function will also set a couple of
545 /// output parameters for how much the source vector needs to be shifted and
546 /// what byte number needs to be specified for the instruction to put the
547 /// element in the desired location of the target vector.
548 bool isXXINSERTWMask(ShuffleVectorSDNode *N, unsigned &ShiftElts,
549 unsigned &InsertAtByte, bool &Swap, bool IsLE);
551 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
552 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
553 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
555 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
556 /// formed by using a vspltis[bhw] instruction of the specified element
557 /// size, return the constant being splatted. The ByteSize field indicates
558 /// the number of bytes of each element [124] -> [bhw].
559 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
561 /// If this is a qvaligni shuffle mask, return the shift
562 /// amount, otherwise return -1.
563 int isQVALIGNIShuffleMask(SDNode *N);
565 } // end namespace PPC
567 class PPCTargetLowering : public TargetLowering {
568 const PPCSubtarget &Subtarget;
571 explicit PPCTargetLowering(const PPCTargetMachine &TM,
572 const PPCSubtarget &STI);
574 /// getTargetNodeName() - This method returns the name of a target specific
576 const char *getTargetNodeName(unsigned Opcode) const override;
578 bool isSelectSupported(SelectSupportKind Kind) const override {
579 // PowerPC does not support scalar condition selects on vectors.
580 return (Kind != SelectSupportKind::ScalarCondVectorVal);
583 /// getPreferredVectorAction - The code we generate when vector types are
584 /// legalized by promoting the integer element type is often much worse
585 /// than code we generate if we widen the type for applicable vector types.
586 /// The issue with promoting is that the vector is scalaraized, individual
587 /// elements promoted and then the vector is rebuilt. So say we load a pair
588 /// of v4i8's and shuffle them. This will turn into a mess of 8 extending
589 /// loads, moves back into VSR's (or memory ops if we don't have moves) and
590 /// then the VPERM for the shuffle. All in all a very slow sequence.
591 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(MVT VT)
593 if (VT.getScalarSizeInBits() % 8 == 0)
594 return TypeWidenVector;
595 return TargetLoweringBase::getPreferredVectorAction(VT);
598 bool useSoftFloat() const override;
602 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
606 bool isCheapToSpeculateCttz() const override {
610 bool isCheapToSpeculateCtlz() const override {
614 bool isCtlzFast() const override {
618 bool hasAndNotCompare(SDValue) const override {
622 bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
623 return VT.isScalarInteger();
626 bool supportSplitCSR(MachineFunction *MF) const override {
628 MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
629 MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
632 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
634 void insertCopiesSplitCSR(
635 MachineBasicBlock *Entry,
636 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
638 /// getSetCCResultType - Return the ISD::SETCC ValueType
639 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
640 EVT VT) const override;
642 /// Return true if target always beneficiates from combining into FMA for a
643 /// given value type. This must typically return false on targets where FMA
644 /// takes more cycles to execute than FADD.
645 bool enableAggressiveFMAFusion(EVT VT) const override;
647 /// getPreIndexedAddressParts - returns true by value, base pointer and
648 /// offset pointer and addressing mode by reference if the node's address
649 /// can be legally represented as pre-indexed load / store address.
650 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
652 ISD::MemIndexedMode &AM,
653 SelectionDAG &DAG) const override;
655 /// SelectAddressRegReg - Given the specified addressed, check to see if it
656 /// can be represented as an indexed [r+r] operation. Returns false if it
657 /// can be more efficiently represented with [r+imm].
658 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
659 SelectionDAG &DAG) const;
661 /// SelectAddressRegImm - Returns true if the address N can be represented
662 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
663 /// is not better represented as reg+reg. If Aligned is true, only accept
664 /// displacements suitable for STD and friends, i.e. multiples of 4.
665 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
666 SelectionDAG &DAG, unsigned Alignment) const;
668 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
669 /// represented as an indexed [r+r] operation.
670 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
671 SelectionDAG &DAG) const;
673 Sched::Preference getSchedulingPreference(SDNode *N) const override;
675 /// LowerOperation - Provide custom lowering hooks for some operations.
677 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
679 /// ReplaceNodeResults - Replace the results of node with an illegal result
680 /// type with new values built out of custom code.
682 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
683 SelectionDAG &DAG) const override;
685 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
686 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
688 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
690 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
691 SmallVectorImpl<SDNode *> &Created) const override;
693 unsigned getRegisterByName(const char* RegName, EVT VT,
694 SelectionDAG &DAG) const override;
696 void computeKnownBitsForTargetNode(const SDValue Op,
698 const APInt &DemandedElts,
699 const SelectionDAG &DAG,
700 unsigned Depth = 0) const override;
702 unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
704 bool shouldInsertFencesForAtomic(const Instruction *I) const override {
708 Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
709 AtomicOrdering Ord) const override;
710 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
711 AtomicOrdering Ord) const override;
714 EmitInstrWithCustomInserter(MachineInstr &MI,
715 MachineBasicBlock *MBB) const override;
716 MachineBasicBlock *EmitAtomicBinary(MachineInstr &MI,
717 MachineBasicBlock *MBB,
720 unsigned CmpOpcode = 0,
721 unsigned CmpPred = 0) const;
722 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr &MI,
723 MachineBasicBlock *MBB,
726 unsigned CmpOpcode = 0,
727 unsigned CmpPred = 0) const;
729 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr &MI,
730 MachineBasicBlock *MBB) const;
732 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
733 MachineBasicBlock *MBB) const;
735 ConstraintType getConstraintType(StringRef Constraint) const override;
737 /// Examine constraint string and operand type and determine a weight value.
738 /// The operand object must already have been set up with the operand type.
739 ConstraintWeight getSingleConstraintMatchWeight(
740 AsmOperandInfo &info, const char *constraint) const override;
742 std::pair<unsigned, const TargetRegisterClass *>
743 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
744 StringRef Constraint, MVT VT) const override;
746 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
747 /// function arguments in the caller parameter area. This is the actual
748 /// alignment, not its logarithm.
749 unsigned getByValTypeAlignment(Type *Ty,
750 const DataLayout &DL) const override;
752 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
753 /// vector. If it is invalid, don't add anything to Ops.
754 void LowerAsmOperandForConstraint(SDValue Op,
755 std::string &Constraint,
756 std::vector<SDValue> &Ops,
757 SelectionDAG &DAG) const override;
760 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
761 if (ConstraintCode == "es")
762 return InlineAsm::Constraint_es;
763 else if (ConstraintCode == "o")
764 return InlineAsm::Constraint_o;
765 else if (ConstraintCode == "Q")
766 return InlineAsm::Constraint_Q;
767 else if (ConstraintCode == "Z")
768 return InlineAsm::Constraint_Z;
769 else if (ConstraintCode == "Zy")
770 return InlineAsm::Constraint_Zy;
771 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
774 /// isLegalAddressingMode - Return true if the addressing mode represented
775 /// by AM is legal for this target, for a load/store of the specified type.
776 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
777 Type *Ty, unsigned AS,
778 Instruction *I = nullptr) const override;
780 /// isLegalICmpImmediate - Return true if the specified immediate is legal
781 /// icmp immediate, that is the target has icmp instructions which can
782 /// compare a register against the immediate without having to materialize
783 /// the immediate into a register.
784 bool isLegalICmpImmediate(int64_t Imm) const override;
786 /// isLegalAddImmediate - Return true if the specified immediate is legal
787 /// add immediate, that is the target has add instructions which can
788 /// add a register and the immediate without having to materialize
789 /// the immediate into a register.
790 bool isLegalAddImmediate(int64_t Imm) const override;
792 /// isTruncateFree - Return true if it's free to truncate a value of
793 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
794 /// register X1 to i32 by referencing its sub-register R1.
795 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
796 bool isTruncateFree(EVT VT1, EVT VT2) const override;
798 bool isZExtFree(SDValue Val, EVT VT2) const override;
800 bool isFPExtFree(EVT DestVT, EVT SrcVT) const override;
802 /// Returns true if it is beneficial to convert a load of a constant
803 /// to just the constant itself.
804 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
805 Type *Ty) const override;
807 bool convertSelectOfConstantsToMath(EVT VT) const override {
811 // Returns true if the address of the global is stored in TOC entry.
812 bool isAccessedAsGotIndirect(SDValue N) const;
814 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
816 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
819 unsigned Intrinsic) const override;
821 /// getOptimalMemOpType - Returns the target specific optimal type for load
822 /// and store operations as a result of memset, memcpy, and memmove
823 /// lowering. If DstAlign is zero that means it's safe to destination
824 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
825 /// means there isn't a need to check it against alignment requirement,
826 /// probably because the source does not need to be loaded. If 'IsMemset' is
827 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
828 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
829 /// source is constant so it does not need to be loaded.
830 /// It returns EVT::Other if the type should be determined using generic
831 /// target-independent logic.
833 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
834 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
835 MachineFunction &MF) const override;
837 /// Is unaligned memory access allowed for the given type, and is it fast
838 /// relative to software emulation.
839 bool allowsMisalignedMemoryAccesses(EVT VT,
842 bool *Fast = nullptr) const override;
844 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
845 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
846 /// expanded to FMAs when this method returns true, otherwise fmuladd is
847 /// expanded to fmul + fadd.
848 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
850 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
852 // Should we expand the build vector with shuffles?
854 shouldExpandBuildVectorWithShuffles(EVT VT,
855 unsigned DefinedValues) const override;
857 /// createFastISel - This method returns a target-specific FastISel object,
858 /// or null if the target does not support "fast" instruction selection.
859 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
860 const TargetLibraryInfo *LibInfo) const override;
862 /// Returns true if an argument of type Ty needs to be passed in a
863 /// contiguous block of registers in calling convention CallConv.
864 bool functionArgumentNeedsConsecutiveRegisters(
865 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
866 // We support any array type as "consecutive" block in the parameter
867 // save area. The element type defines the alignment requirement and
868 // whether the argument should go in GPRs, FPRs, or VRs if available.
870 // Note that clang uses this capability both to implement the ELFv2
871 // homogeneous float/vector aggregate ABI, and to avoid having to use
872 // "byval" when passing aggregates that might fully fit in registers.
873 return Ty->isArrayTy();
876 /// If a physical register, this returns the register that receives the
877 /// exception address on entry to an EH pad.
879 getExceptionPointerRegister(const Constant *PersonalityFn) const override;
881 /// If a physical register, this returns the register that receives the
882 /// exception typeid on entry to a landing pad.
884 getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
886 /// Override to support customized stack guard loading.
887 bool useLoadStackGuardNode() const override;
888 void insertSSPDeclarations(Module &M) const override;
890 bool isFPImmLegal(const APFloat &Imm, EVT VT,
891 bool ForCodeSize) const override;
893 unsigned getJumpTableEncoding() const override;
894 bool isJumpTableRelative() const override;
895 SDValue getPICJumpTableRelocBase(SDValue Table,
896 SelectionDAG &DAG) const override;
897 const MCExpr *getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
899 MCContext &Ctx) const override;
901 unsigned getNumRegistersForCallingConv(LLVMContext &Context,
903 EVT VT) const override;
905 MVT getRegisterTypeForCallingConv(LLVMContext &Context,
907 EVT VT) const override;
910 struct ReuseLoadInfo {
914 MachinePointerInfo MPI;
915 bool IsDereferenceable = false;
916 bool IsInvariant = false;
917 unsigned Alignment = 0;
919 const MDNode *Ranges = nullptr;
921 ReuseLoadInfo() = default;
923 MachineMemOperand::Flags MMOFlags() const {
924 MachineMemOperand::Flags F = MachineMemOperand::MONone;
925 if (IsDereferenceable)
926 F |= MachineMemOperand::MODereferenceable;
928 F |= MachineMemOperand::MOInvariant;
933 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
934 // Addrspacecasts are always noops.
938 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
940 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
941 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
942 SelectionDAG &DAG) const;
944 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
945 SelectionDAG &DAG, const SDLoc &dl) const;
946 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
947 const SDLoc &dl) const;
949 bool directMoveIsProfitable(const SDValue &Op) const;
950 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
951 const SDLoc &dl) const;
953 SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
954 const SDLoc &dl) const;
956 SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const;
958 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
959 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
962 IsEligibleForTailCallOptimization(SDValue Callee,
963 CallingConv::ID CalleeCC,
965 const SmallVectorImpl<ISD::InputArg> &Ins,
966 SelectionDAG& DAG) const;
969 IsEligibleForTailCallOptimization_64SVR4(
971 CallingConv::ID CalleeCC,
972 ImmutableCallSite CS,
974 const SmallVectorImpl<ISD::OutputArg> &Outs,
975 const SmallVectorImpl<ISD::InputArg> &Ins,
976 SelectionDAG& DAG) const;
978 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG &DAG, int SPDiff,
979 SDValue Chain, SDValue &LROpOut,
981 const SDLoc &dl) const;
983 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
984 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
985 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
986 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
987 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
988 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
989 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
990 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
991 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
992 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
993 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
994 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
995 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
996 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
997 SDValue LowerGET_DYNAMIC_AREA_OFFSET(SDValue Op, SelectionDAG &DAG) const;
998 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
999 SDValue LowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
1000 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
1001 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
1002 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
1003 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
1004 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
1005 const SDLoc &dl) const;
1006 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
1007 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
1008 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1009 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
1010 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
1011 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1012 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
1013 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1014 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
1015 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
1016 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
1017 SDValue LowerREM(SDValue Op, SelectionDAG &DAG) const;
1018 SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
1019 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
1020 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
1021 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
1022 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
1023 SDValue LowerABS(SDValue Op, SelectionDAG &DAG) const;
1025 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
1026 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
1028 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
1029 CallingConv::ID CallConv, bool isVarArg,
1030 const SmallVectorImpl<ISD::InputArg> &Ins,
1031 const SDLoc &dl, SelectionDAG &DAG,
1032 SmallVectorImpl<SDValue> &InVals) const;
1033 SDValue FinishCall(CallingConv::ID CallConv, const SDLoc &dl,
1034 bool isTailCall, bool isVarArg, bool isPatchPoint,
1035 bool hasNest, SelectionDAG &DAG,
1036 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
1037 SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
1038 SDValue &Callee, int SPDiff, unsigned NumBytes,
1039 const SmallVectorImpl<ISD::InputArg> &Ins,
1040 SmallVectorImpl<SDValue> &InVals,
1041 ImmutableCallSite CS) const;
1044 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1045 const SmallVectorImpl<ISD::InputArg> &Ins,
1046 const SDLoc &dl, SelectionDAG &DAG,
1047 SmallVectorImpl<SDValue> &InVals) const override;
1049 SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
1050 SmallVectorImpl<SDValue> &InVals) const override;
1052 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1054 const SmallVectorImpl<ISD::OutputArg> &Outs,
1055 LLVMContext &Context) const override;
1057 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1058 const SmallVectorImpl<ISD::OutputArg> &Outs,
1059 const SmallVectorImpl<SDValue> &OutVals,
1060 const SDLoc &dl, SelectionDAG &DAG) const override;
1062 SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
1063 SelectionDAG &DAG, SDValue ArgVal,
1064 const SDLoc &dl) const;
1066 SDValue LowerFormalArguments_Darwin(
1067 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1068 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1069 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1070 SDValue LowerFormalArguments_64SVR4(
1071 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1072 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1073 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1074 SDValue LowerFormalArguments_32SVR4(
1075 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
1076 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
1077 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
1079 SDValue createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
1080 SDValue CallSeqStart,
1081 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
1082 const SDLoc &dl) const;
1084 SDValue LowerCall_Darwin(SDValue Chain, SDValue Callee,
1085 CallingConv::ID CallConv, bool isVarArg,
1086 bool isTailCall, bool isPatchPoint,
1087 const SmallVectorImpl<ISD::OutputArg> &Outs,
1088 const SmallVectorImpl<SDValue> &OutVals,
1089 const SmallVectorImpl<ISD::InputArg> &Ins,
1090 const SDLoc &dl, SelectionDAG &DAG,
1091 SmallVectorImpl<SDValue> &InVals,
1092 ImmutableCallSite CS) const;
1093 SDValue LowerCall_64SVR4(SDValue Chain, SDValue Callee,
1094 CallingConv::ID CallConv, bool isVarArg,
1095 bool isTailCall, bool isPatchPoint,
1096 const SmallVectorImpl<ISD::OutputArg> &Outs,
1097 const SmallVectorImpl<SDValue> &OutVals,
1098 const SmallVectorImpl<ISD::InputArg> &Ins,
1099 const SDLoc &dl, SelectionDAG &DAG,
1100 SmallVectorImpl<SDValue> &InVals,
1101 ImmutableCallSite CS) const;
1102 SDValue LowerCall_32SVR4(SDValue Chain, SDValue Callee,
1103 CallingConv::ID CallConv, bool isVarArg,
1104 bool isTailCall, bool isPatchPoint,
1105 const SmallVectorImpl<ISD::OutputArg> &Outs,
1106 const SmallVectorImpl<SDValue> &OutVals,
1107 const SmallVectorImpl<ISD::InputArg> &Ins,
1108 const SDLoc &dl, SelectionDAG &DAG,
1109 SmallVectorImpl<SDValue> &InVals,
1110 ImmutableCallSite CS) const;
1112 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
1113 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
1114 SDValue LowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
1116 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
1117 SDValue DAGCombineBuildVector(SDNode *N, DAGCombinerInfo &DCI) const;
1118 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
1119 SDValue combineStoreFPToInt(SDNode *N, DAGCombinerInfo &DCI) const;
1120 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
1121 SDValue combineSHL(SDNode *N, DAGCombinerInfo &DCI) const;
1122 SDValue combineSRA(SDNode *N, DAGCombinerInfo &DCI) const;
1123 SDValue combineSRL(SDNode *N, DAGCombinerInfo &DCI) const;
1124 SDValue combineMUL(SDNode *N, DAGCombinerInfo &DCI) const;
1125 SDValue combineADD(SDNode *N, DAGCombinerInfo &DCI) const;
1126 SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
1127 SDValue combineSetCC(SDNode *N, DAGCombinerInfo &DCI) const;
1128 SDValue combineABS(SDNode *N, DAGCombinerInfo &DCI) const;
1129 SDValue combineVSelect(SDNode *N, DAGCombinerInfo &DCI) const;
1131 /// ConvertSETCCToSubtract - looks at SETCC that compares ints. It replaces
1132 /// SETCC with integer subtraction when (1) there is a legal way of doing it
1133 /// (2) keeping the result of comparison in GPR has performance benefit.
1134 SDValue ConvertSETCCToSubtract(SDNode *N, DAGCombinerInfo &DCI) const;
1136 SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1137 int &RefinementSteps, bool &UseOneConstNR,
1138 bool Reciprocal) const override;
1139 SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
1140 int &RefinementSteps) const override;
1141 unsigned combineRepeatedFPDivisors() const override;
1144 combineElementTruncationToVectorTruncation(SDNode *N,
1145 DAGCombinerInfo &DCI) const;
1147 /// lowerToVINSERTH - Return the SDValue if this VECTOR_SHUFFLE can be
1148 /// handled by the VINSERTH instruction introduced in ISA 3.0. This is
1149 /// essentially any shuffle of v8i16 vectors that just inserts one element
1150 /// from one vector into the other.
1151 SDValue lowerToVINSERTH(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1153 /// lowerToVINSERTB - Return the SDValue if this VECTOR_SHUFFLE can be
1154 /// handled by the VINSERTB instruction introduced in ISA 3.0. This is
1155 /// essentially v16i8 vector version of VINSERTH.
1156 SDValue lowerToVINSERTB(ShuffleVectorSDNode *N, SelectionDAG &DAG) const;
1158 // Return whether the call instruction can potentially be optimized to a
1159 // tail call. This will cause the optimizers to attempt to move, or
1160 // duplicate return instructions to help enable tail call optimizations.
1161 bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
1162 bool hasBitPreservingFPLogic(EVT VT) const override;
1163 bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
1164 }; // end class PPCTargetLowering
1168 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
1169 const TargetLibraryInfo *LibInfo);
1171 } // end namespace PPC
1173 bool isIntS16Immediate(SDNode *N, int16_t &Imm);
1174 bool isIntS16Immediate(SDValue Op, int16_t &Imm);
1176 } // end namespace llvm
1178 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H