1 //===-- SparcAsmParser.cpp - Parse Sparc assembly to MCInst instructions --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SparcMCExpr.h"
11 #include "MCTargetDesc/SparcMCTargetDesc.h"
12 #include "llvm/ADT/SmallVector.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/StringRef.h"
15 #include "llvm/ADT/Triple.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCObjectFileInfo.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbol.h"
28 #include "llvm/Support/Casting.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/SMLoc.h"
31 #include "llvm/Support/raw_ostream.h"
32 #include "llvm/Support/TargetRegistry.h"
40 // The generated AsmMatcher SparcGenAsmMatcher uses "Sparc" as the target
41 // namespace. But SPARC backend uses "SP" as its namespace.
47 } // end namespace Sparc
48 } // end namespace llvm
54 class SparcAsmParser : public MCTargetAsmParser {
57 /// @name Auto-generated Match Functions
60 #define GET_ASSEMBLER_HEADER
61 #include "SparcGenAsmMatcher.inc"
65 // public interface of the MCTargetAsmParser.
66 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
67 OperandVector &Operands, MCStreamer &Out,
69 bool MatchingInlineAsm) override;
70 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
71 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
72 SMLoc NameLoc, OperandVector &Operands) override;
73 bool ParseDirective(AsmToken DirectiveID) override;
75 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
76 unsigned Kind) override;
78 // Custom parse functions for Sparc specific operands.
79 OperandMatchResultTy parseMEMOperand(OperandVector &Operands);
81 OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Name);
84 parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Operand,
87 OperandMatchResultTy parseBranchModifiers(OperandVector &Operands);
89 // Helper function for dealing with %lo / %hi in PIC mode.
90 const SparcMCExpr *adjustPICRelocation(SparcMCExpr::VariantKind VK,
91 const MCExpr *subExpr);
93 // returns true if Tok is matched to a register and returns register in RegNo.
94 bool matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
97 bool matchSparcAsmModifiers(const MCExpr *&EVal, SMLoc &EndLoc);
98 bool parseDirectiveWord(unsigned Size, SMLoc L);
100 bool is64Bit() const {
101 return getSTI().getTargetTriple().getArch() == Triple::sparcv9;
104 bool expandSET(MCInst &Inst, SMLoc IDLoc,
105 SmallVectorImpl<MCInst> &Instructions);
108 SparcAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
109 const MCInstrInfo &MII,
110 const MCTargetOptions &Options)
111 : MCTargetAsmParser(Options, sti), Parser(parser) {
112 // Initialize the set of available features.
113 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
117 } // end anonymous namespace
119 static const MCPhysReg IntRegs[32] = {
120 Sparc::G0, Sparc::G1, Sparc::G2, Sparc::G3,
121 Sparc::G4, Sparc::G5, Sparc::G6, Sparc::G7,
122 Sparc::O0, Sparc::O1, Sparc::O2, Sparc::O3,
123 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
124 Sparc::L0, Sparc::L1, Sparc::L2, Sparc::L3,
125 Sparc::L4, Sparc::L5, Sparc::L6, Sparc::L7,
126 Sparc::I0, Sparc::I1, Sparc::I2, Sparc::I3,
127 Sparc::I4, Sparc::I5, Sparc::I6, Sparc::I7 };
129 static const MCPhysReg FloatRegs[32] = {
130 Sparc::F0, Sparc::F1, Sparc::F2, Sparc::F3,
131 Sparc::F4, Sparc::F5, Sparc::F6, Sparc::F7,
132 Sparc::F8, Sparc::F9, Sparc::F10, Sparc::F11,
133 Sparc::F12, Sparc::F13, Sparc::F14, Sparc::F15,
134 Sparc::F16, Sparc::F17, Sparc::F18, Sparc::F19,
135 Sparc::F20, Sparc::F21, Sparc::F22, Sparc::F23,
136 Sparc::F24, Sparc::F25, Sparc::F26, Sparc::F27,
137 Sparc::F28, Sparc::F29, Sparc::F30, Sparc::F31 };
139 static const MCPhysReg DoubleRegs[32] = {
140 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
141 Sparc::D4, Sparc::D5, Sparc::D6, Sparc::D7,
142 Sparc::D8, Sparc::D9, Sparc::D10, Sparc::D11,
143 Sparc::D12, Sparc::D13, Sparc::D14, Sparc::D15,
144 Sparc::D16, Sparc::D17, Sparc::D18, Sparc::D19,
145 Sparc::D20, Sparc::D21, Sparc::D22, Sparc::D23,
146 Sparc::D24, Sparc::D25, Sparc::D26, Sparc::D27,
147 Sparc::D28, Sparc::D29, Sparc::D30, Sparc::D31 };
149 static const MCPhysReg QuadFPRegs[32] = {
150 Sparc::Q0, Sparc::Q1, Sparc::Q2, Sparc::Q3,
151 Sparc::Q4, Sparc::Q5, Sparc::Q6, Sparc::Q7,
152 Sparc::Q8, Sparc::Q9, Sparc::Q10, Sparc::Q11,
153 Sparc::Q12, Sparc::Q13, Sparc::Q14, Sparc::Q15 };
155 static const MCPhysReg ASRRegs[32] = {
156 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
157 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
158 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
159 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
160 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
161 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
162 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
163 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
165 static const MCPhysReg IntPairRegs[] = {
166 Sparc::G0_G1, Sparc::G2_G3, Sparc::G4_G5, Sparc::G6_G7,
167 Sparc::O0_O1, Sparc::O2_O3, Sparc::O4_O5, Sparc::O6_O7,
168 Sparc::L0_L1, Sparc::L2_L3, Sparc::L4_L5, Sparc::L6_L7,
169 Sparc::I0_I1, Sparc::I2_I3, Sparc::I4_I5, Sparc::I6_I7};
171 static const MCPhysReg CoprocRegs[32] = {
172 Sparc::C0, Sparc::C1, Sparc::C2, Sparc::C3,
173 Sparc::C4, Sparc::C5, Sparc::C6, Sparc::C7,
174 Sparc::C8, Sparc::C9, Sparc::C10, Sparc::C11,
175 Sparc::C12, Sparc::C13, Sparc::C14, Sparc::C15,
176 Sparc::C16, Sparc::C17, Sparc::C18, Sparc::C19,
177 Sparc::C20, Sparc::C21, Sparc::C22, Sparc::C23,
178 Sparc::C24, Sparc::C25, Sparc::C26, Sparc::C27,
179 Sparc::C28, Sparc::C29, Sparc::C30, Sparc::C31 };
181 static const MCPhysReg CoprocPairRegs[] = {
182 Sparc::C0_C1, Sparc::C2_C3, Sparc::C4_C5, Sparc::C6_C7,
183 Sparc::C8_C9, Sparc::C10_C11, Sparc::C12_C13, Sparc::C14_C15,
184 Sparc::C16_C17, Sparc::C18_C19, Sparc::C20_C21, Sparc::C22_C23,
185 Sparc::C24_C25, Sparc::C26_C27, Sparc::C28_C29, Sparc::C30_C31};
189 /// SparcOperand - Instances of this class represent a parsed Sparc machine
191 class SparcOperand : public MCParsedAsmOperand {
214 SMLoc StartLoc, EndLoc;
244 SparcOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
246 bool isToken() const override { return Kind == k_Token; }
247 bool isReg() const override { return Kind == k_Register; }
248 bool isImm() const override { return Kind == k_Immediate; }
249 bool isMem() const override { return isMEMrr() || isMEMri(); }
250 bool isMEMrr() const { return Kind == k_MemoryReg; }
251 bool isMEMri() const { return Kind == k_MemoryImm; }
253 bool isIntReg() const {
254 return (Kind == k_Register && Reg.Kind == rk_IntReg);
257 bool isFloatReg() const {
258 return (Kind == k_Register && Reg.Kind == rk_FloatReg);
261 bool isFloatOrDoubleReg() const {
262 return (Kind == k_Register && (Reg.Kind == rk_FloatReg
263 || Reg.Kind == rk_DoubleReg));
266 bool isCoprocReg() const {
267 return (Kind == k_Register && Reg.Kind == rk_CoprocReg);
270 StringRef getToken() const {
271 assert(Kind == k_Token && "Invalid access!");
272 return StringRef(Tok.Data, Tok.Length);
275 unsigned getReg() const override {
276 assert((Kind == k_Register) && "Invalid access!");
280 const MCExpr *getImm() const {
281 assert((Kind == k_Immediate) && "Invalid access!");
285 unsigned getMemBase() const {
286 assert((Kind == k_MemoryReg || Kind == k_MemoryImm) && "Invalid access!");
290 unsigned getMemOffsetReg() const {
291 assert((Kind == k_MemoryReg) && "Invalid access!");
292 return Mem.OffsetReg;
295 const MCExpr *getMemOff() const {
296 assert((Kind == k_MemoryImm) && "Invalid access!");
300 /// getStartLoc - Get the location of the first token of this operand.
301 SMLoc getStartLoc() const override {
304 /// getEndLoc - Get the location of the last token of this operand.
305 SMLoc getEndLoc() const override {
309 void print(raw_ostream &OS) const override {
311 case k_Token: OS << "Token: " << getToken() << "\n"; break;
312 case k_Register: OS << "Reg: #" << getReg() << "\n"; break;
313 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
314 case k_MemoryReg: OS << "Mem: " << getMemBase() << "+"
315 << getMemOffsetReg() << "\n"; break;
316 case k_MemoryImm: assert(getMemOff() != nullptr);
317 OS << "Mem: " << getMemBase()
318 << "+" << *getMemOff()
323 void addRegOperands(MCInst &Inst, unsigned N) const {
324 assert(N == 1 && "Invalid number of operands!");
325 Inst.addOperand(MCOperand::createReg(getReg()));
328 void addImmOperands(MCInst &Inst, unsigned N) const {
329 assert(N == 1 && "Invalid number of operands!");
330 const MCExpr *Expr = getImm();
334 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
335 // Add as immediate when possible. Null MCExpr = 0.
337 Inst.addOperand(MCOperand::createImm(0));
338 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
339 Inst.addOperand(MCOperand::createImm(CE->getValue()));
341 Inst.addOperand(MCOperand::createExpr(Expr));
344 void addMEMrrOperands(MCInst &Inst, unsigned N) const {
345 assert(N == 2 && "Invalid number of operands!");
347 Inst.addOperand(MCOperand::createReg(getMemBase()));
349 assert(getMemOffsetReg() != 0 && "Invalid offset");
350 Inst.addOperand(MCOperand::createReg(getMemOffsetReg()));
353 void addMEMriOperands(MCInst &Inst, unsigned N) const {
354 assert(N == 2 && "Invalid number of operands!");
356 Inst.addOperand(MCOperand::createReg(getMemBase()));
358 const MCExpr *Expr = getMemOff();
362 static std::unique_ptr<SparcOperand> CreateToken(StringRef Str, SMLoc S) {
363 auto Op = make_unique<SparcOperand>(k_Token);
364 Op->Tok.Data = Str.data();
365 Op->Tok.Length = Str.size();
371 static std::unique_ptr<SparcOperand> CreateReg(unsigned RegNum, unsigned Kind,
373 auto Op = make_unique<SparcOperand>(k_Register);
374 Op->Reg.RegNum = RegNum;
375 Op->Reg.Kind = (SparcOperand::RegisterKind)Kind;
381 static std::unique_ptr<SparcOperand> CreateImm(const MCExpr *Val, SMLoc S,
383 auto Op = make_unique<SparcOperand>(k_Immediate);
390 static bool MorphToIntPairReg(SparcOperand &Op) {
391 unsigned Reg = Op.getReg();
392 assert(Op.Reg.Kind == rk_IntReg);
393 unsigned regIdx = 32;
394 if (Reg >= Sparc::G0 && Reg <= Sparc::G7)
395 regIdx = Reg - Sparc::G0;
396 else if (Reg >= Sparc::O0 && Reg <= Sparc::O7)
397 regIdx = Reg - Sparc::O0 + 8;
398 else if (Reg >= Sparc::L0 && Reg <= Sparc::L7)
399 regIdx = Reg - Sparc::L0 + 16;
400 else if (Reg >= Sparc::I0 && Reg <= Sparc::I7)
401 regIdx = Reg - Sparc::I0 + 24;
402 if (regIdx % 2 || regIdx > 31)
404 Op.Reg.RegNum = IntPairRegs[regIdx / 2];
405 Op.Reg.Kind = rk_IntPairReg;
409 static bool MorphToDoubleReg(SparcOperand &Op) {
410 unsigned Reg = Op.getReg();
411 assert(Op.Reg.Kind == rk_FloatReg);
412 unsigned regIdx = Reg - Sparc::F0;
413 if (regIdx % 2 || regIdx > 31)
415 Op.Reg.RegNum = DoubleRegs[regIdx / 2];
416 Op.Reg.Kind = rk_DoubleReg;
420 static bool MorphToQuadReg(SparcOperand &Op) {
421 unsigned Reg = Op.getReg();
423 switch (Op.Reg.Kind) {
424 default: llvm_unreachable("Unexpected register kind!");
426 regIdx = Reg - Sparc::F0;
427 if (regIdx % 4 || regIdx > 31)
429 Reg = QuadFPRegs[regIdx / 4];
432 regIdx = Reg - Sparc::D0;
433 if (regIdx % 2 || regIdx > 31)
435 Reg = QuadFPRegs[regIdx / 2];
439 Op.Reg.Kind = rk_QuadReg;
443 static bool MorphToCoprocPairReg(SparcOperand &Op) {
444 unsigned Reg = Op.getReg();
445 assert(Op.Reg.Kind == rk_CoprocReg);
446 unsigned regIdx = 32;
447 if (Reg >= Sparc::C0 && Reg <= Sparc::C31)
448 regIdx = Reg - Sparc::C0;
449 if (regIdx % 2 || regIdx > 31)
451 Op.Reg.RegNum = CoprocPairRegs[regIdx / 2];
452 Op.Reg.Kind = rk_CoprocPairReg;
456 static std::unique_ptr<SparcOperand>
457 MorphToMEMrr(unsigned Base, std::unique_ptr<SparcOperand> Op) {
458 unsigned offsetReg = Op->getReg();
459 Op->Kind = k_MemoryReg;
461 Op->Mem.OffsetReg = offsetReg;
462 Op->Mem.Off = nullptr;
466 static std::unique_ptr<SparcOperand>
467 CreateMEMr(unsigned Base, SMLoc S, SMLoc E) {
468 auto Op = make_unique<SparcOperand>(k_MemoryReg);
470 Op->Mem.OffsetReg = Sparc::G0; // always 0
471 Op->Mem.Off = nullptr;
477 static std::unique_ptr<SparcOperand>
478 MorphToMEMri(unsigned Base, std::unique_ptr<SparcOperand> Op) {
479 const MCExpr *Imm = Op->getImm();
480 Op->Kind = k_MemoryImm;
482 Op->Mem.OffsetReg = 0;
488 } // end anonymous namespace
490 bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
491 SmallVectorImpl<MCInst> &Instructions) {
492 MCOperand MCRegOp = Inst.getOperand(0);
493 MCOperand MCValOp = Inst.getOperand(1);
494 assert(MCRegOp.isReg());
495 assert(MCValOp.isImm() || MCValOp.isExpr());
497 // the imm operand can be either an expression or an immediate.
498 bool IsImm = Inst.getOperand(1).isImm();
499 int64_t RawImmValue = IsImm ? MCValOp.getImm() : 0;
501 // Allow either a signed or unsigned 32-bit immediate.
502 if (RawImmValue < -2147483648LL || RawImmValue > 4294967295LL) {
504 "set: argument must be between -2147483648 and 4294967295");
507 // If the value was expressed as a large unsigned number, that's ok.
508 // We want to see if it "looks like" a small signed number.
509 int32_t ImmValue = RawImmValue;
510 // For 'set' you can't use 'or' with a negative operand on V9 because
511 // that would splat the sign bit across the upper half of the destination
512 // register, whereas 'set' is defined to zero the high 32 bits.
513 bool IsEffectivelyImm13 =
514 IsImm && ((is64Bit() ? 0 : -4096) <= ImmValue && ImmValue < 4096);
515 const MCExpr *ValExpr;
517 ValExpr = MCConstantExpr::create(ImmValue, getContext());
519 ValExpr = MCValOp.getExpr();
521 MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
523 // If not just a signed imm13 value, then either we use a 'sethi' with a
524 // following 'or', or a 'sethi' by itself if there are no more 1 bits.
525 // In either case, start with the 'sethi'.
526 if (!IsEffectivelyImm13) {
528 const MCExpr *Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_HI, ValExpr);
529 TmpInst.setLoc(IDLoc);
530 TmpInst.setOpcode(SP::SETHIi);
531 TmpInst.addOperand(MCRegOp);
532 TmpInst.addOperand(MCOperand::createExpr(Expr));
533 Instructions.push_back(TmpInst);
537 // The low bits require touching in 3 cases:
538 // * A non-immediate value will always require both instructions.
539 // * An effectively imm13 value needs only an 'or' instruction.
540 // * Otherwise, an immediate that is not effectively imm13 requires the
541 // 'or' only if bits remain after clearing the 22 bits that 'sethi' set.
542 // If the low bits are known zeros, there's nothing to do.
543 // In the second case, and only in that case, must we NOT clear
544 // bits of the immediate value via the %lo() assembler function.
545 // Note also, the 'or' instruction doesn't mind a large value in the case
546 // where the operand to 'set' was 0xFFFFFzzz - it does exactly what you mean.
547 if (!IsImm || IsEffectivelyImm13 || (ImmValue & 0x3ff)) {
550 if (IsEffectivelyImm13)
553 Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_LO, ValExpr);
554 TmpInst.setLoc(IDLoc);
555 TmpInst.setOpcode(SP::ORri);
556 TmpInst.addOperand(MCRegOp);
557 TmpInst.addOperand(PrevReg);
558 TmpInst.addOperand(MCOperand::createExpr(Expr));
559 Instructions.push_back(TmpInst);
564 bool SparcAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
565 OperandVector &Operands,
568 bool MatchingInlineAsm) {
570 SmallVector<MCInst, 8> Instructions;
571 unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
573 switch (MatchResult) {
574 case Match_Success: {
575 switch (Inst.getOpcode()) {
578 Instructions.push_back(Inst);
581 if (expandSET(Inst, IDLoc, Instructions))
586 for (const MCInst &I : Instructions) {
587 Out.EmitInstruction(I, getSTI());
592 case Match_MissingFeature:
594 "instruction requires a CPU feature not currently enabled");
596 case Match_InvalidOperand: {
597 SMLoc ErrorLoc = IDLoc;
598 if (ErrorInfo != ~0ULL) {
599 if (ErrorInfo >= Operands.size())
600 return Error(IDLoc, "too few operands for instruction");
602 ErrorLoc = ((SparcOperand &)*Operands[ErrorInfo]).getStartLoc();
603 if (ErrorLoc == SMLoc())
607 return Error(ErrorLoc, "invalid operand for instruction");
609 case Match_MnemonicFail:
610 return Error(IDLoc, "invalid instruction mnemonic");
612 llvm_unreachable("Implement any new match types added!");
615 bool SparcAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
617 const AsmToken &Tok = Parser.getTok();
618 StartLoc = Tok.getLoc();
619 EndLoc = Tok.getEndLoc();
621 if (getLexer().getKind() != AsmToken::Percent)
624 unsigned regKind = SparcOperand::rk_None;
625 if (matchRegisterName(Tok, RegNo, regKind)) {
630 return Error(StartLoc, "invalid register name");
633 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
636 bool SparcAsmParser::ParseInstruction(ParseInstructionInfo &Info,
637 StringRef Name, SMLoc NameLoc,
638 OperandVector &Operands) {
640 // First operand in MCInst is instruction mnemonic.
641 Operands.push_back(SparcOperand::CreateToken(Name, NameLoc));
643 // apply mnemonic aliases, if any, so that we can parse operands correctly.
644 applyMnemonicAliases(Name, getAvailableFeatures(), 0);
646 if (getLexer().isNot(AsmToken::EndOfStatement)) {
647 // Read the first operand.
648 if (getLexer().is(AsmToken::Comma)) {
649 if (parseBranchModifiers(Operands) != MatchOperand_Success) {
650 SMLoc Loc = getLexer().getLoc();
651 return Error(Loc, "unexpected token");
654 if (parseOperand(Operands, Name) != MatchOperand_Success) {
655 SMLoc Loc = getLexer().getLoc();
656 return Error(Loc, "unexpected token");
659 while (getLexer().is(AsmToken::Comma) || getLexer().is(AsmToken::Plus)) {
660 if (getLexer().is(AsmToken::Plus)) {
661 // Plus tokens are significant in software_traps (p83, sparcv8.pdf). We must capture them.
662 Operands.push_back(SparcOperand::CreateToken("+", Parser.getTok().getLoc()));
664 Parser.Lex(); // Eat the comma or plus.
665 // Parse and remember the operand.
666 if (parseOperand(Operands, Name) != MatchOperand_Success) {
667 SMLoc Loc = getLexer().getLoc();
668 return Error(Loc, "unexpected token");
672 if (getLexer().isNot(AsmToken::EndOfStatement)) {
673 SMLoc Loc = getLexer().getLoc();
674 return Error(Loc, "unexpected token");
676 Parser.Lex(); // Consume the EndOfStatement.
680 bool SparcAsmParser::
681 ParseDirective(AsmToken DirectiveID)
683 StringRef IDVal = DirectiveID.getString();
685 if (IDVal == ".byte")
686 return parseDirectiveWord(1, DirectiveID.getLoc());
688 if (IDVal == ".half")
689 return parseDirectiveWord(2, DirectiveID.getLoc());
691 if (IDVal == ".word")
692 return parseDirectiveWord(4, DirectiveID.getLoc());
694 if (IDVal == ".nword")
695 return parseDirectiveWord(is64Bit() ? 8 : 4, DirectiveID.getLoc());
697 if (is64Bit() && IDVal == ".xword")
698 return parseDirectiveWord(8, DirectiveID.getLoc());
700 if (IDVal == ".register") {
701 // For now, ignore .register directive.
702 Parser.eatToEndOfStatement();
705 if (IDVal == ".proc") {
706 // For compatibility, ignore this directive.
707 // (It's supposed to be an "optimization" in the Sun assembler)
708 Parser.eatToEndOfStatement();
712 // Let the MC layer to handle other directives.
716 bool SparcAsmParser:: parseDirectiveWord(unsigned Size, SMLoc L) {
717 if (getLexer().isNot(AsmToken::EndOfStatement)) {
720 if (getParser().parseExpression(Value))
723 getParser().getStreamer().EmitValue(Value, Size);
725 if (getLexer().is(AsmToken::EndOfStatement))
728 // FIXME: Improve diagnostic.
729 if (getLexer().isNot(AsmToken::Comma))
730 return Error(L, "unexpected token in directive");
739 SparcAsmParser::parseMEMOperand(OperandVector &Operands) {
741 unsigned BaseReg = 0;
743 if (ParseRegister(BaseReg, S, E)) {
744 return MatchOperand_NoMatch;
747 switch (getLexer().getKind()) {
748 default: return MatchOperand_NoMatch;
750 case AsmToken::Comma:
751 case AsmToken::RBrac:
752 case AsmToken::EndOfStatement:
753 Operands.push_back(SparcOperand::CreateMEMr(BaseReg, S, E));
754 return MatchOperand_Success;
756 case AsmToken:: Plus:
757 Parser.Lex(); // Eat the '+'
759 case AsmToken::Minus:
763 std::unique_ptr<SparcOperand> Offset;
764 OperandMatchResultTy ResTy = parseSparcAsmOperand(Offset);
765 if (ResTy != MatchOperand_Success || !Offset)
766 return MatchOperand_NoMatch;
769 Offset->isImm() ? SparcOperand::MorphToMEMri(BaseReg, std::move(Offset))
770 : SparcOperand::MorphToMEMrr(BaseReg, std::move(Offset)));
772 return MatchOperand_Success;
776 SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
778 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
780 // If there wasn't a custom match, try the generic matcher below. Otherwise,
781 // there was a match, but an error occurred, in which case, just return that
782 // the operand parsing failed.
783 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)
786 if (getLexer().is(AsmToken::LBrac)) {
788 Operands.push_back(SparcOperand::CreateToken("[",
789 Parser.getTok().getLoc()));
790 Parser.Lex(); // Eat the [
792 if (Mnemonic == "cas" || Mnemonic == "casx" || Mnemonic == "casa") {
793 SMLoc S = Parser.getTok().getLoc();
794 if (getLexer().getKind() != AsmToken::Percent)
795 return MatchOperand_NoMatch;
796 Parser.Lex(); // eat %
798 unsigned RegNo, RegKind;
799 if (!matchRegisterName(Parser.getTok(), RegNo, RegKind))
800 return MatchOperand_NoMatch;
802 Parser.Lex(); // Eat the identifier token.
803 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
804 Operands.push_back(SparcOperand::CreateReg(RegNo, RegKind, S, E));
805 ResTy = MatchOperand_Success;
807 ResTy = parseMEMOperand(Operands);
810 if (ResTy != MatchOperand_Success)
813 if (!getLexer().is(AsmToken::RBrac))
814 return MatchOperand_ParseFail;
816 Operands.push_back(SparcOperand::CreateToken("]",
817 Parser.getTok().getLoc()));
818 Parser.Lex(); // Eat the ]
820 // Parse an optional address-space identifier after the address.
821 if (getLexer().is(AsmToken::Integer)) {
822 std::unique_ptr<SparcOperand> Op;
823 ResTy = parseSparcAsmOperand(Op, false);
824 if (ResTy != MatchOperand_Success || !Op)
825 return MatchOperand_ParseFail;
826 Operands.push_back(std::move(Op));
828 return MatchOperand_Success;
831 std::unique_ptr<SparcOperand> Op;
833 ResTy = parseSparcAsmOperand(Op, (Mnemonic == "call"));
834 if (ResTy != MatchOperand_Success || !Op)
835 return MatchOperand_ParseFail;
837 // Push the parsed operand into the list of operands
838 Operands.push_back(std::move(Op));
840 return MatchOperand_Success;
844 SparcAsmParser::parseSparcAsmOperand(std::unique_ptr<SparcOperand> &Op,
846 SMLoc S = Parser.getTok().getLoc();
847 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
851 switch (getLexer().getKind()) {
854 case AsmToken::Percent:
855 Parser.Lex(); // Eat the '%'.
858 if (matchRegisterName(Parser.getTok(), RegNo, RegKind)) {
859 StringRef name = Parser.getTok().getString();
860 Parser.Lex(); // Eat the identifier token.
861 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
864 Op = SparcOperand::CreateReg(RegNo, RegKind, S, E);
867 Op = SparcOperand::CreateToken("%psr", S);
870 Op = SparcOperand::CreateToken("%fsr", S);
873 Op = SparcOperand::CreateToken("%fq", S);
876 Op = SparcOperand::CreateToken("%csr", S);
879 Op = SparcOperand::CreateToken("%cq", S);
882 Op = SparcOperand::CreateToken("%wim", S);
885 Op = SparcOperand::CreateToken("%tbr", S);
889 Op = SparcOperand::CreateToken("%xcc", S);
891 Op = SparcOperand::CreateToken("%icc", S);
896 if (matchSparcAsmModifiers(EVal, E)) {
897 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
898 Op = SparcOperand::CreateImm(EVal, S, E);
902 case AsmToken::Minus:
903 case AsmToken::Integer:
904 case AsmToken::LParen:
906 if (!getParser().parseExpression(EVal, E))
907 Op = SparcOperand::CreateImm(EVal, S, E);
910 case AsmToken::Identifier: {
911 StringRef Identifier;
912 if (!getParser().parseIdentifier(Identifier)) {
913 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
914 MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
916 const MCExpr *Res = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
918 if (isCall && getContext().getObjectFileInfo()->isPositionIndependent())
919 Res = SparcMCExpr::create(SparcMCExpr::VK_Sparc_WPLT30, Res,
921 Op = SparcOperand::CreateImm(Res, S, E);
926 return (Op) ? MatchOperand_Success : MatchOperand_ParseFail;
930 SparcAsmParser::parseBranchModifiers(OperandVector &Operands) {
931 // parse (,a|,pn|,pt)+
933 while (getLexer().is(AsmToken::Comma)) {
934 Parser.Lex(); // Eat the comma
936 if (!getLexer().is(AsmToken::Identifier))
937 return MatchOperand_ParseFail;
938 StringRef modName = Parser.getTok().getString();
939 if (modName == "a" || modName == "pn" || modName == "pt") {
940 Operands.push_back(SparcOperand::CreateToken(modName,
941 Parser.getTok().getLoc()));
942 Parser.Lex(); // eat the identifier.
945 return MatchOperand_Success;
948 bool SparcAsmParser::matchRegisterName(const AsmToken &Tok, unsigned &RegNo,
952 RegKind = SparcOperand::rk_None;
953 if (Tok.is(AsmToken::Identifier)) {
954 StringRef name = Tok.getString();
957 if (name.equals("fp")) {
959 RegKind = SparcOperand::rk_IntReg;
963 if (name.equals("sp")) {
965 RegKind = SparcOperand::rk_IntReg;
969 if (name.equals("y")) {
971 RegKind = SparcOperand::rk_Special;
975 if (name.substr(0, 3).equals_lower("asr")
976 && !name.substr(3).getAsInteger(10, intVal)
977 && intVal > 0 && intVal < 32) {
978 RegNo = ASRRegs[intVal];
979 RegKind = SparcOperand::rk_Special;
983 // %fprs is an alias of %asr6.
984 if (name.equals("fprs")) {
986 RegKind = SparcOperand::rk_Special;
990 if (name.equals("icc")) {
992 RegKind = SparcOperand::rk_Special;
996 if (name.equals("psr")) {
998 RegKind = SparcOperand::rk_Special;
1002 if (name.equals("fsr")) {
1004 RegKind = SparcOperand::rk_Special;
1008 if (name.equals("fq")) {
1010 RegKind = SparcOperand::rk_Special;
1014 if (name.equals("csr")) {
1015 RegNo = Sparc::CPSR;
1016 RegKind = SparcOperand::rk_Special;
1020 if (name.equals("cq")) {
1022 RegKind = SparcOperand::rk_Special;
1026 if (name.equals("wim")) {
1028 RegKind = SparcOperand::rk_Special;
1032 if (name.equals("tbr")) {
1034 RegKind = SparcOperand::rk_Special;
1038 if (name.equals("xcc")) {
1039 // FIXME:: check 64bit.
1041 RegKind = SparcOperand::rk_Special;
1046 if (name.substr(0, 3).equals_lower("fcc")
1047 && !name.substr(3).getAsInteger(10, intVal)
1049 // FIXME: check 64bit and handle %fcc1 - %fcc3
1050 RegNo = Sparc::FCC0 + intVal;
1051 RegKind = SparcOperand::rk_Special;
1056 if (name.substr(0, 1).equals_lower("g")
1057 && !name.substr(1).getAsInteger(10, intVal)
1059 RegNo = IntRegs[intVal];
1060 RegKind = SparcOperand::rk_IntReg;
1064 if (name.substr(0, 1).equals_lower("o")
1065 && !name.substr(1).getAsInteger(10, intVal)
1067 RegNo = IntRegs[8 + intVal];
1068 RegKind = SparcOperand::rk_IntReg;
1071 if (name.substr(0, 1).equals_lower("l")
1072 && !name.substr(1).getAsInteger(10, intVal)
1074 RegNo = IntRegs[16 + intVal];
1075 RegKind = SparcOperand::rk_IntReg;
1078 if (name.substr(0, 1).equals_lower("i")
1079 && !name.substr(1).getAsInteger(10, intVal)
1081 RegNo = IntRegs[24 + intVal];
1082 RegKind = SparcOperand::rk_IntReg;
1086 if (name.substr(0, 1).equals_lower("f")
1087 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 32) {
1088 RegNo = FloatRegs[intVal];
1089 RegKind = SparcOperand::rk_FloatReg;
1093 if (name.substr(0, 1).equals_lower("f")
1094 && !name.substr(1, 2).getAsInteger(10, intVal)
1095 && intVal >= 32 && intVal <= 62 && (intVal % 2 == 0)) {
1097 RegNo = DoubleRegs[intVal/2];
1098 RegKind = SparcOperand::rk_DoubleReg;
1103 if (name.substr(0, 1).equals_lower("r")
1104 && !name.substr(1, 2).getAsInteger(10, intVal) && intVal < 31) {
1105 RegNo = IntRegs[intVal];
1106 RegKind = SparcOperand::rk_IntReg;
1111 if (name.substr(0, 1).equals_lower("c")
1112 && !name.substr(1).getAsInteger(10, intVal)
1114 RegNo = CoprocRegs[intVal];
1115 RegKind = SparcOperand::rk_CoprocReg;
1119 if (name.equals("tpc")) {
1121 RegKind = SparcOperand::rk_Special;
1124 if (name.equals("tnpc")) {
1125 RegNo = Sparc::TNPC;
1126 RegKind = SparcOperand::rk_Special;
1129 if (name.equals("tstate")) {
1130 RegNo = Sparc::TSTATE;
1131 RegKind = SparcOperand::rk_Special;
1134 if (name.equals("tt")) {
1136 RegKind = SparcOperand::rk_Special;
1139 if (name.equals("tick")) {
1140 RegNo = Sparc::TICK;
1141 RegKind = SparcOperand::rk_Special;
1144 if (name.equals("tba")) {
1146 RegKind = SparcOperand::rk_Special;
1149 if (name.equals("pstate")) {
1150 RegNo = Sparc::PSTATE;
1151 RegKind = SparcOperand::rk_Special;
1154 if (name.equals("tl")) {
1156 RegKind = SparcOperand::rk_Special;
1159 if (name.equals("pil")) {
1161 RegKind = SparcOperand::rk_Special;
1164 if (name.equals("cwp")) {
1166 RegKind = SparcOperand::rk_Special;
1169 if (name.equals("cansave")) {
1170 RegNo = Sparc::CANSAVE;
1171 RegKind = SparcOperand::rk_Special;
1174 if (name.equals("canrestore")) {
1175 RegNo = Sparc::CANRESTORE;
1176 RegKind = SparcOperand::rk_Special;
1179 if (name.equals("cleanwin")) {
1180 RegNo = Sparc::CLEANWIN;
1181 RegKind = SparcOperand::rk_Special;
1184 if (name.equals("otherwin")) {
1185 RegNo = Sparc::OTHERWIN;
1186 RegKind = SparcOperand::rk_Special;
1189 if (name.equals("wstate")) {
1190 RegNo = Sparc::WSTATE;
1191 RegKind = SparcOperand::rk_Special;
1198 // Determine if an expression contains a reference to the symbol
1199 // "_GLOBAL_OFFSET_TABLE_".
1200 static bool hasGOTReference(const MCExpr *Expr) {
1201 switch (Expr->getKind()) {
1202 case MCExpr::Target:
1203 if (const SparcMCExpr *SE = dyn_cast<SparcMCExpr>(Expr))
1204 return hasGOTReference(SE->getSubExpr());
1207 case MCExpr::Constant:
1210 case MCExpr::Binary: {
1211 const MCBinaryExpr *BE = cast<MCBinaryExpr>(Expr);
1212 return hasGOTReference(BE->getLHS()) || hasGOTReference(BE->getRHS());
1215 case MCExpr::SymbolRef: {
1216 const MCSymbolRefExpr &SymRef = *cast<MCSymbolRefExpr>(Expr);
1217 return (SymRef.getSymbol().getName() == "_GLOBAL_OFFSET_TABLE_");
1221 return hasGOTReference(cast<MCUnaryExpr>(Expr)->getSubExpr());
1227 SparcAsmParser::adjustPICRelocation(SparcMCExpr::VariantKind VK,
1228 const MCExpr *subExpr) {
1229 // When in PIC mode, "%lo(...)" and "%hi(...)" behave differently.
1230 // If the expression refers contains _GLOBAL_OFFSETE_TABLE, it is
1231 // actually a %pc10 or %pc22 relocation. Otherwise, they are interpreted
1232 // as %got10 or %got22 relocation.
1234 if (getContext().getObjectFileInfo()->isPositionIndependent()) {
1237 case SparcMCExpr::VK_Sparc_LO:
1238 VK = (hasGOTReference(subExpr) ? SparcMCExpr::VK_Sparc_PC10
1239 : SparcMCExpr::VK_Sparc_GOT10);
1241 case SparcMCExpr::VK_Sparc_HI:
1242 VK = (hasGOTReference(subExpr) ? SparcMCExpr::VK_Sparc_PC22
1243 : SparcMCExpr::VK_Sparc_GOT22);
1248 return SparcMCExpr::create(VK, subExpr, getContext());
1251 bool SparcAsmParser::matchSparcAsmModifiers(const MCExpr *&EVal,
1253 AsmToken Tok = Parser.getTok();
1254 if (!Tok.is(AsmToken::Identifier))
1257 StringRef name = Tok.getString();
1259 SparcMCExpr::VariantKind VK = SparcMCExpr::parseVariantKind(name);
1261 if (VK == SparcMCExpr::VK_Sparc_None)
1264 Parser.Lex(); // Eat the identifier.
1265 if (Parser.getTok().getKind() != AsmToken::LParen)
1268 Parser.Lex(); // Eat the LParen token.
1269 const MCExpr *subExpr;
1270 if (Parser.parseParenExpression(subExpr, EndLoc))
1273 EVal = adjustPICRelocation(VK, subExpr);
1277 extern "C" void LLVMInitializeSparcAsmParser() {
1278 RegisterMCAsmParser<SparcAsmParser> A(getTheSparcTarget());
1279 RegisterMCAsmParser<SparcAsmParser> B(getTheSparcV9Target());
1280 RegisterMCAsmParser<SparcAsmParser> C(getTheSparcelTarget());
1283 #define GET_REGISTER_MATCHER
1284 #define GET_MATCHER_IMPLEMENTATION
1285 #include "SparcGenAsmMatcher.inc"
1287 unsigned SparcAsmParser::validateTargetOperandClass(MCParsedAsmOperand &GOp,
1289 SparcOperand &Op = (SparcOperand &)GOp;
1290 if (Op.isFloatOrDoubleReg()) {
1294 if (!Op.isFloatReg() || SparcOperand::MorphToDoubleReg(Op))
1295 return MCTargetAsmParser::Match_Success;
1298 if (SparcOperand::MorphToQuadReg(Op))
1299 return MCTargetAsmParser::Match_Success;
1303 if (Op.isIntReg() && Kind == MCK_IntPair) {
1304 if (SparcOperand::MorphToIntPairReg(Op))
1305 return MCTargetAsmParser::Match_Success;
1307 if (Op.isCoprocReg() && Kind == MCK_CoprocPair) {
1308 if (SparcOperand::MorphToCoprocPairReg(Op))
1309 return MCTargetAsmParser::Match_Success;
1311 return Match_InvalidOperand;