1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
37 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
38 // accesses (LARL). Operand 0 is the address.
41 // Signed integer and floating-point comparisons. The operands are the
42 // two values to compare.
45 // Likewise unsigned integer comparison.
48 // Test under mask. The first operand is ANDed with the second operand
49 // and the condition codes are set on the result.
52 // Branches if a condition is true. Operand 0 is the chain operand;
53 // operand 1 is the 4-bit condition-code mask, with bit N in
54 // big-endian order meaning "branch if CC=N"; operand 2 is the
55 // target block and operand 3 is the flag operand.
58 // Selects between operand 0 and operand 1. Operand 2 is the
59 // mask of condition-code values for which operand 0 should be
60 // chosen over operand 1; it has the same form as BR_CCMASK.
61 // Operand 3 is the flag operand.
64 // Evaluates to the gap between the stack pointer and the
65 // base of the dynamically-allocatable area.
68 // Extracts the value of a 32-bit access register. Operand 0 is
69 // the number of the register.
72 // Wrappers around the ISD opcodes of the same name. The output and
73 // first input operands are GR128s. The trailing numbers are the
74 // widths of the second operand in bits.
81 // Use a series of MVCs to copy bytes from one memory location to another.
83 // - the target address
84 // - the source address
85 // - the constant length
87 // This isn't a memory opcode because we'd need to attach two
88 // MachineMemOperands rather than one.
91 // Like MVC, but implemented as a loop that handles X*256 bytes
92 // followed by straight-line code to handle the rest (if any).
93 // The value of X is passed as an additional operand.
96 // Use CLC to compare two blocks of memory, with the same comments
97 // as for MVC and MVC_LOOP.
101 // Use an MVST-based sequence to implement stpcpy().
104 // Use a CLST-based sequence to implement strcmp(). The two input operands
105 // are the addresses of the strings to compare.
108 // Use an SRST-based sequence to search a block of memory. The first
109 // operand is the end address, the second is the start, and the third
110 // is the character to search for. CC is set to 1 on success and 2
114 // Store the CC value in bits 29 and 28 of an integer.
117 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
120 // Operand 0: the address of the containing 32-bit-aligned field
121 // Operand 1: the second operand of <op>, in the high bits of an i32
122 // for everything except ATOMIC_SWAPW
123 // Operand 2: how many bits to rotate the i32 left to bring the first
124 // operand into the high bits
125 // Operand 3: the negative of operand 2, for rotating the other way
126 // Operand 4: the width of the field in bits (8 or 16)
127 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
139 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
141 // Operand 0: the address of the containing 32-bit-aligned field
142 // Operand 1: the compare value, in the low bits of an i32
143 // Operand 2: the swap value, in the low bits of an i32
144 // Operand 3: how many bits to rotate the i32 left to bring the first
145 // operand into the high bits
146 // Operand 4: the negative of operand 2, for rotating the other way
147 // Operand 5: the width of the field in bits (8 or 16)
150 // Prefetch from the second operand using the 4-bit control code in
151 // the first operand. The code is 1 for a load prefetch and 2 for
157 class SystemZSubtarget;
158 class SystemZTargetMachine;
160 class SystemZTargetLowering : public TargetLowering {
162 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
164 // Override TargetLowering.
165 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
168 virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE {
171 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
172 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE;
173 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
175 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
177 virtual bool isTruncateFree(Type *, Type *) const LLVM_OVERRIDE;
178 virtual bool isTruncateFree(EVT, EVT) const LLVM_OVERRIDE;
179 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
180 virtual std::pair<unsigned, const TargetRegisterClass *>
181 getRegForInlineAsmConstraint(const std::string &Constraint,
182 MVT VT) const LLVM_OVERRIDE;
183 virtual TargetLowering::ConstraintType
184 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
185 virtual TargetLowering::ConstraintWeight
186 getSingleConstraintMatchWeight(AsmOperandInfo &info,
187 const char *constraint) const LLVM_OVERRIDE;
189 LowerAsmOperandForConstraint(SDValue Op,
190 std::string &Constraint,
191 std::vector<SDValue> &Ops,
192 SelectionDAG &DAG) const LLVM_OVERRIDE;
193 virtual MachineBasicBlock *
194 EmitInstrWithCustomInserter(MachineInstr *MI,
195 MachineBasicBlock *BB) const LLVM_OVERRIDE;
196 virtual SDValue LowerOperation(SDValue Op,
197 SelectionDAG &DAG) const LLVM_OVERRIDE;
198 virtual bool allowTruncateForTailCall(Type *, Type *) const LLVM_OVERRIDE;
199 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const LLVM_OVERRIDE;
201 LowerFormalArguments(SDValue Chain,
202 CallingConv::ID CallConv, bool isVarArg,
203 const SmallVectorImpl<ISD::InputArg> &Ins,
204 SDLoc DL, SelectionDAG &DAG,
205 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
207 LowerCall(CallLoweringInfo &CLI,
208 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
211 LowerReturn(SDValue Chain,
212 CallingConv::ID CallConv, bool IsVarArg,
213 const SmallVectorImpl<ISD::OutputArg> &Outs,
214 const SmallVectorImpl<SDValue> &OutVals,
215 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
218 const SystemZSubtarget &Subtarget;
219 const SystemZTargetMachine &TM;
221 // Implement LowerOperation for individual opcodes.
222 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
223 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
224 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
225 SelectionDAG &DAG) const;
226 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
227 SelectionDAG &DAG) const;
228 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
229 SelectionDAG &DAG) const;
230 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
231 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
232 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
233 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
234 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
235 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
236 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
237 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
238 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
239 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
240 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
241 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
242 unsigned Opcode) const;
243 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
244 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
245 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
246 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
248 // If the last instruction before MBBI in MBB was some form of COMPARE,
249 // try to replace it with a COMPARE AND BRANCH just before MBBI.
250 // CCMask and Target are the BRC-like operands for the branch.
251 // Return true if the change was made.
252 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
253 MachineBasicBlock::iterator MBBI,
255 MachineBasicBlock *Target) const;
257 // Implement EmitInstrWithCustomInserter for individual operation types.
258 MachineBasicBlock *emitSelect(MachineInstr *MI,
259 MachineBasicBlock *BB) const;
260 MachineBasicBlock *emitCondStore(MachineInstr *MI,
261 MachineBasicBlock *BB,
262 unsigned StoreOpcode, unsigned STOCOpcode,
264 MachineBasicBlock *emitExt128(MachineInstr *MI,
265 MachineBasicBlock *MBB,
266 bool ClearEven, unsigned SubReg) const;
267 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
268 MachineBasicBlock *BB,
269 unsigned BinOpcode, unsigned BitSize,
270 bool Invert = false) const;
271 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
272 MachineBasicBlock *MBB,
273 unsigned CompareOpcode,
274 unsigned KeepOldMask,
275 unsigned BitSize) const;
276 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
277 MachineBasicBlock *BB) const;
278 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
279 MachineBasicBlock *BB,
280 unsigned Opcode) const;
281 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
282 MachineBasicBlock *BB,
283 unsigned Opcode) const;
285 } // end namespace llvm
287 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H