1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
37 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
38 // accesses (LARL). Operand 0 is the address.
41 // Integer comparisons. There are three operands: the two values
42 // to compare, and an integer of type SystemZICMP.
45 // Floating-point comparisons. The two operands are the values to compare.
48 // Test under mask. The first operand is ANDed with the second operand
49 // and the condition codes are set on the result.
52 // Branches if a condition is true. Operand 0 is the chain operand;
53 // operand 1 is the 4-bit condition-code mask, with bit N in
54 // big-endian order meaning "branch if CC=N"; operand 2 is the
55 // target block and operand 3 is the flag operand.
58 // Selects between operand 0 and operand 1. Operand 2 is the
59 // mask of condition-code values for which operand 0 should be
60 // chosen over operand 1; it has the same form as BR_CCMASK.
61 // Operand 3 is the flag operand.
64 // Evaluates to the gap between the stack pointer and the
65 // base of the dynamically-allocatable area.
68 // Extracts the value of a 32-bit access register. Operand 0 is
69 // the number of the register.
72 // Wrappers around the ISD opcodes of the same name. The output and
73 // first input operands are GR128s. The trailing numbers are the
74 // widths of the second operand in bits.
81 // Use a series of MVCs to copy bytes from one memory location to another.
83 // - the target address
84 // - the source address
85 // - the constant length
87 // This isn't a memory opcode because we'd need to attach two
88 // MachineMemOperands rather than one.
91 // Like MVC, but implemented as a loop that handles X*256 bytes
92 // followed by straight-line code to handle the rest (if any).
93 // The value of X is passed as an additional operand.
96 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
104 // Use CLC to compare two blocks of memory, with the same comments
105 // as for MVC and MVC_LOOP.
109 // Use an MVST-based sequence to implement stpcpy().
112 // Use a CLST-based sequence to implement strcmp(). The two input operands
113 // are the addresses of the strings to compare.
116 // Use an SRST-based sequence to search a block of memory. The first
117 // operand is the end address, the second is the start, and the third
118 // is the character to search for. CC is set to 1 on success and 2
122 // Store the CC value in bits 29 and 28 of an integer.
125 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
128 // Operand 0: the address of the containing 32-bit-aligned field
129 // Operand 1: the second operand of <op>, in the high bits of an i32
130 // for everything except ATOMIC_SWAPW
131 // Operand 2: how many bits to rotate the i32 left to bring the first
132 // operand into the high bits
133 // Operand 3: the negative of operand 2, for rotating the other way
134 // Operand 4: the width of the field in bits (8 or 16)
135 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
147 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
149 // Operand 0: the address of the containing 32-bit-aligned field
150 // Operand 1: the compare value, in the low bits of an i32
151 // Operand 2: the swap value, in the low bits of an i32
152 // Operand 3: how many bits to rotate the i32 left to bring the first
153 // operand into the high bits
154 // Operand 4: the negative of operand 2, for rotating the other way
155 // Operand 5: the width of the field in bits (8 or 16)
158 // Prefetch from the second operand using the 4-bit control code in
159 // the first operand. The code is 1 for a load prefetch and 2 for
165 namespace SystemZICMP {
166 // Describes whether an integer comparison needs to be signed or unsigned,
167 // or whether either type is OK.
175 class SystemZSubtarget;
176 class SystemZTargetMachine;
178 class SystemZTargetLowering : public TargetLowering {
180 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
182 // Override TargetLowering.
183 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
186 virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE {
189 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
190 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE;
191 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
193 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
195 virtual bool isTruncateFree(Type *, Type *) const LLVM_OVERRIDE;
196 virtual bool isTruncateFree(EVT, EVT) const LLVM_OVERRIDE;
197 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
198 virtual std::pair<unsigned, const TargetRegisterClass *>
199 getRegForInlineAsmConstraint(const std::string &Constraint,
200 MVT VT) const LLVM_OVERRIDE;
201 virtual TargetLowering::ConstraintType
202 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
203 virtual TargetLowering::ConstraintWeight
204 getSingleConstraintMatchWeight(AsmOperandInfo &info,
205 const char *constraint) const LLVM_OVERRIDE;
207 LowerAsmOperandForConstraint(SDValue Op,
208 std::string &Constraint,
209 std::vector<SDValue> &Ops,
210 SelectionDAG &DAG) const LLVM_OVERRIDE;
211 virtual MachineBasicBlock *
212 EmitInstrWithCustomInserter(MachineInstr *MI,
213 MachineBasicBlock *BB) const LLVM_OVERRIDE;
214 virtual SDValue LowerOperation(SDValue Op,
215 SelectionDAG &DAG) const LLVM_OVERRIDE;
216 virtual bool allowTruncateForTailCall(Type *, Type *) const LLVM_OVERRIDE;
217 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const LLVM_OVERRIDE;
219 LowerFormalArguments(SDValue Chain,
220 CallingConv::ID CallConv, bool isVarArg,
221 const SmallVectorImpl<ISD::InputArg> &Ins,
222 SDLoc DL, SelectionDAG &DAG,
223 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
225 LowerCall(CallLoweringInfo &CLI,
226 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
229 LowerReturn(SDValue Chain,
230 CallingConv::ID CallConv, bool IsVarArg,
231 const SmallVectorImpl<ISD::OutputArg> &Outs,
232 const SmallVectorImpl<SDValue> &OutVals,
233 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
236 const SystemZSubtarget &Subtarget;
237 const SystemZTargetMachine &TM;
239 // Implement LowerOperation for individual opcodes.
240 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
241 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
242 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
243 SelectionDAG &DAG) const;
244 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
245 SelectionDAG &DAG) const;
246 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
247 SelectionDAG &DAG) const;
248 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
249 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
250 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
251 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
252 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
253 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
254 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
255 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
256 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
257 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
258 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
259 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
260 unsigned Opcode) const;
261 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
262 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
263 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
264 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
266 // If the last instruction before MBBI in MBB was some form of COMPARE,
267 // try to replace it with a COMPARE AND BRANCH just before MBBI.
268 // CCMask and Target are the BRC-like operands for the branch.
269 // Return true if the change was made.
270 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
271 MachineBasicBlock::iterator MBBI,
273 MachineBasicBlock *Target) const;
275 // Implement EmitInstrWithCustomInserter for individual operation types.
276 MachineBasicBlock *emitSelect(MachineInstr *MI,
277 MachineBasicBlock *BB) const;
278 MachineBasicBlock *emitCondStore(MachineInstr *MI,
279 MachineBasicBlock *BB,
280 unsigned StoreOpcode, unsigned STOCOpcode,
282 MachineBasicBlock *emitExt128(MachineInstr *MI,
283 MachineBasicBlock *MBB,
284 bool ClearEven, unsigned SubReg) const;
285 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
286 MachineBasicBlock *BB,
287 unsigned BinOpcode, unsigned BitSize,
288 bool Invert = false) const;
289 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
290 MachineBasicBlock *MBB,
291 unsigned CompareOpcode,
292 unsigned KeepOldMask,
293 unsigned BitSize) const;
294 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
295 MachineBasicBlock *BB) const;
296 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
297 MachineBasicBlock *BB,
298 unsigned Opcode) const;
299 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
300 MachineBasicBlock *BB,
301 unsigned Opcode) const;
303 } // end namespace llvm
305 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H