1 //===-- X86IntelInstPrinter.cpp - Intel assembly instruction printing -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file includes code for rendering MCInst instances as Intel-style
13 //===----------------------------------------------------------------------===//
15 #include "X86IntelInstPrinter.h"
16 #include "MCTargetDesc/X86BaseInfo.h"
17 #include "X86InstComments.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/Support/Casting.h"
23 #include "llvm/Support/ErrorHandling.h"
29 #define DEBUG_TYPE "asm-printer"
31 #include "X86GenAsmWriter1.inc"
33 void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
34 OS << getRegisterName(RegNo);
37 void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
39 const MCSubtargetInfo &STI) {
40 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
41 uint64_t TSFlags = Desc.TSFlags;
42 unsigned Flags = MI->getFlags();
44 if ((TSFlags & X86II::LOCK) || (Flags & X86::IP_HAS_LOCK))
47 if (Flags & X86::IP_HAS_REPEAT_NE)
49 else if (Flags & X86::IP_HAS_REPEAT)
52 if ((TSFlags & X86II::NOTRACK) || (Flags & X86::IP_HAS_NOTRACK))
55 printInstruction(MI, OS);
57 // Next always print the annotation.
58 printAnnotation(OS, Annot);
60 // If verbose assembly is enabled, we can print some informative comments.
62 EmitAnyX86InstComments(MI, *CommentStream, MII, getRegisterName);
65 void X86IntelInstPrinter::printSSEAVXCC(const MCInst *MI, unsigned Op,
67 int64_t Imm = MI->getOperand(Op).getImm();
69 default: llvm_unreachable("Invalid avxcc argument!");
70 case 0: O << "eq"; break;
71 case 1: O << "lt"; break;
72 case 2: O << "le"; break;
73 case 3: O << "unord"; break;
74 case 4: O << "neq"; break;
75 case 5: O << "nlt"; break;
76 case 6: O << "nle"; break;
77 case 7: O << "ord"; break;
78 case 8: O << "eq_uq"; break;
79 case 9: O << "nge"; break;
80 case 0xa: O << "ngt"; break;
81 case 0xb: O << "false"; break;
82 case 0xc: O << "neq_oq"; break;
83 case 0xd: O << "ge"; break;
84 case 0xe: O << "gt"; break;
85 case 0xf: O << "true"; break;
86 case 0x10: O << "eq_os"; break;
87 case 0x11: O << "lt_oq"; break;
88 case 0x12: O << "le_oq"; break;
89 case 0x13: O << "unord_s"; break;
90 case 0x14: O << "neq_us"; break;
91 case 0x15: O << "nlt_uq"; break;
92 case 0x16: O << "nle_uq"; break;
93 case 0x17: O << "ord_s"; break;
94 case 0x18: O << "eq_us"; break;
95 case 0x19: O << "nge_uq"; break;
96 case 0x1a: O << "ngt_uq"; break;
97 case 0x1b: O << "false_os"; break;
98 case 0x1c: O << "neq_os"; break;
99 case 0x1d: O << "ge_oq"; break;
100 case 0x1e: O << "gt_oq"; break;
101 case 0x1f: O << "true_us"; break;
105 void X86IntelInstPrinter::printXOPCC(const MCInst *MI, unsigned Op,
107 int64_t Imm = MI->getOperand(Op).getImm();
109 default: llvm_unreachable("Invalid xopcc argument!");
110 case 0: O << "lt"; break;
111 case 1: O << "le"; break;
112 case 2: O << "gt"; break;
113 case 3: O << "ge"; break;
114 case 4: O << "eq"; break;
115 case 5: O << "neq"; break;
116 case 6: O << "false"; break;
117 case 7: O << "true"; break;
121 void X86IntelInstPrinter::printRoundingControl(const MCInst *MI, unsigned Op,
123 int64_t Imm = MI->getOperand(Op).getImm() & 0x3;
125 case 0: O << "{rn-sae}"; break;
126 case 1: O << "{rd-sae}"; break;
127 case 2: O << "{ru-sae}"; break;
128 case 3: O << "{rz-sae}"; break;
132 /// printPCRelImm - This is used to print an immediate value that ends up
133 /// being encoded as a pc-relative value.
134 void X86IntelInstPrinter::printPCRelImm(const MCInst *MI, unsigned OpNo,
136 const MCOperand &Op = MI->getOperand(OpNo);
138 O << formatImm(Op.getImm());
140 assert(Op.isExpr() && "unknown pcrel immediate operand");
141 // If a symbolic branch target was added as a constant expression then print
142 // that address in hex.
143 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
145 if (BranchTarget && BranchTarget->evaluateAsAbsolute(Address)) {
146 O << formatHex((uint64_t)Address);
149 // Otherwise, just print the expression.
150 Op.getExpr()->print(O, &MAI);
155 void X86IntelInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
157 const MCOperand &Op = MI->getOperand(OpNo);
159 printRegName(O, Op.getReg());
160 } else if (Op.isImm()) {
161 O << formatImm((int64_t)Op.getImm());
163 assert(Op.isExpr() && "unknown operand kind in printOperand");
165 Op.getExpr()->print(O, &MAI);
169 void X86IntelInstPrinter::printMemReference(const MCInst *MI, unsigned Op,
171 const MCOperand &BaseReg = MI->getOperand(Op+X86::AddrBaseReg);
172 unsigned ScaleVal = MI->getOperand(Op+X86::AddrScaleAmt).getImm();
173 const MCOperand &IndexReg = MI->getOperand(Op+X86::AddrIndexReg);
174 const MCOperand &DispSpec = MI->getOperand(Op+X86::AddrDisp);
175 const MCOperand &SegReg = MI->getOperand(Op+X86::AddrSegmentReg);
177 // If this has a segment register, print it.
178 if (SegReg.getReg()) {
179 printOperand(MI, Op+X86::AddrSegmentReg, O);
185 bool NeedPlus = false;
186 if (BaseReg.getReg()) {
187 printOperand(MI, Op+X86::AddrBaseReg, O);
191 if (IndexReg.getReg()) {
192 if (NeedPlus) O << " + ";
194 O << ScaleVal << '*';
195 printOperand(MI, Op+X86::AddrIndexReg, O);
199 if (!DispSpec.isImm()) {
200 if (NeedPlus) O << " + ";
201 assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
202 DispSpec.getExpr()->print(O, &MAI);
204 int64_t DispVal = DispSpec.getImm();
205 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
214 O << formatImm(DispVal);
221 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
223 const MCOperand &SegReg = MI->getOperand(Op+1);
225 // If this has a segment register, print it.
226 if (SegReg.getReg()) {
227 printOperand(MI, Op+1, O);
231 printOperand(MI, Op, O);
235 void X86IntelInstPrinter::printDstIdx(const MCInst *MI, unsigned Op,
237 // DI accesses are always ES-based.
239 printOperand(MI, Op, O);
243 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
245 const MCOperand &DispSpec = MI->getOperand(Op);
246 const MCOperand &SegReg = MI->getOperand(Op+1);
248 // If this has a segment register, print it.
249 if (SegReg.getReg()) {
250 printOperand(MI, Op+1, O);
256 if (DispSpec.isImm()) {
257 O << formatImm(DispSpec.getImm());
259 assert(DispSpec.isExpr() && "non-immediate displacement?");
260 DispSpec.getExpr()->print(O, &MAI);
266 void X86IntelInstPrinter::printU8Imm(const MCInst *MI, unsigned Op,
268 if (MI->getOperand(Op).isExpr())
269 return MI->getOperand(Op).getExpr()->print(O, &MAI);
271 O << formatImm(MI->getOperand(Op).getImm() & 0xff);