1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the various pseudo instructions used by the compiler,
11 // as well as Pat patterns used during instruction selection.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Pattern Matching Support
18 def GetLo32XForm : SDNodeXForm<imm, [{
19 // Transformation function: get the low 32 bits.
20 return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N));
23 def GetLo8XForm : SDNodeXForm<imm, [{
24 // Transformation function: get the low 8 bits.
25 return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
29 //===----------------------------------------------------------------------===//
30 // Random Pseudo Instructions.
32 // PIC base construction. This expands to code that looks like this:
35 let hasSideEffects = 0, isNotDuplicable = 1, Uses = [ESP, SSP] in
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
40 // ADJCALLSTACKDOWN/UP implicitly use/def ESP because they may be expanded into
41 // a stack adjustment and the codegen must know that they may modify the stack
42 // pointer before prolog-epilog rewriting occurs.
43 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
44 // sub / add which can clobber EFLAGS.
45 let Defs = [ESP, EFLAGS, SSP], Uses = [ESP, SSP] in {
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs),
47 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
51 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
53 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
56 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
57 (ADJCALLSTACKDOWN32 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[NotLP64]>;
60 // ADJCALLSTACKDOWN/UP implicitly use/def RSP because they may be expanded into
61 // a stack adjustment and the codegen must know that they may modify the stack
62 // pointer before prolog-epilog rewriting occurs.
63 // Pessimistically assume ADJCALLSTACKDOWN / ADJCALLSTACKUP will become
64 // sub / add which can clobber EFLAGS.
65 let Defs = [RSP, EFLAGS, SSP], Uses = [RSP, SSP] in {
66 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs),
67 (ins i32imm:$amt1, i32imm:$amt2, i32imm:$amt3),
71 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
73 [(X86callseq_end timm:$amt1, timm:$amt2)]>,
76 def : Pat<(X86callseq_start timm:$amt1, timm:$amt2),
77 (ADJCALLSTACKDOWN64 i32imm:$amt1, i32imm:$amt2, 0)>, Requires<[IsLP64]>;
80 // x86-64 va_start lowering magic.
81 let usesCustomInserter = 1, Defs = [EFLAGS] in {
82 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
85 i64imm:$regsavefi, i64imm:$offset,
87 "#VASTART_SAVE_XMM_REGS $al, $regsavefi, $offset",
88 [(X86vastart_save_xmm_regs GR8:$al,
93 // The VAARG_64 pseudo-instruction takes the address of the va_list,
94 // and places the address of the next argument into a register.
95 let Defs = [EFLAGS] in
96 def VAARG_64 : I<0, Pseudo,
98 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
99 "#VAARG_64 $dst, $ap, $size, $mode, $align",
101 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
105 // When using segmented stacks these are lowered into instructions which first
106 // check if the current stacklet has enough free memory. If it does, memory is
107 // allocated by bumping the stack pointer. Otherwise memory is allocated from
110 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
111 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
112 "# variable sized alloca for segmented stacks",
114 (X86SegAlloca GR32:$size))]>,
117 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
118 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
119 "# variable sized alloca for segmented stacks",
121 (X86SegAlloca GR64:$size))]>,
122 Requires<[In64BitMode]>;
125 // Dynamic stack allocation yields a _chkstk or _alloca call for all Windows
126 // targets. These calls are needed to probe the stack when allocating more than
127 // 4k bytes in one go. Touching the stack at 4K increments is necessary to
128 // ensure that the guard pages used by the OS virtual memory manager are
129 // allocated in correct sequence.
130 // The main point of having separate instruction are extra unmodelled effects
131 // (compared to ordinary calls) like stack pointer change.
133 let Defs = [EAX, ESP, EFLAGS], Uses = [ESP] in
134 def WIN_ALLOCA_32 : I<0, Pseudo, (outs), (ins GR32:$size),
135 "# dynamic stack allocation",
136 [(X86WinAlloca GR32:$size)]>,
139 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
140 def WIN_ALLOCA_64 : I<0, Pseudo, (outs), (ins GR64:$size),
141 "# dynamic stack allocation",
142 [(X86WinAlloca GR64:$size)]>,
143 Requires<[In64BitMode]>;
145 // These instructions XOR the frame pointer into a GPR. They are used in some
146 // stack protection schemes. These are post-RA pseudos because we only know the
147 // frame register after register allocation.
148 let Constraints = "$src = $dst", isPseudo = 1 in {
149 def XOR32_FP : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src),
150 "xorl\t$$FP, $src", []>, Requires<[NotLP64]>;
151 def XOR64_FP : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src),
152 "xorq\t$$FP $src", []>, Requires<[In64BitMode]>;
155 //===----------------------------------------------------------------------===//
156 // EH Pseudo Instructions
158 let SchedRW = [WriteSystem] in {
159 let isTerminator = 1, isReturn = 1, isBarrier = 1,
160 hasCtrlDep = 1, isCodeGenOnly = 1 in {
161 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
162 "ret\t#eh_return, addr: $addr",
163 [(X86ehret GR32:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
167 let isTerminator = 1, isReturn = 1, isBarrier = 1,
168 hasCtrlDep = 1, isCodeGenOnly = 1 in {
169 def EH_RETURN64 : I<0xC3, RawFrm, (outs), (ins GR64:$addr),
170 "ret\t#eh_return, addr: $addr",
171 [(X86ehret GR64:$addr)], IIC_RET>, Sched<[WriteJumpLd]>;
175 let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,
176 isCodeGenOnly = 1, isReturn = 1 in {
177 def CLEANUPRET : I<0, Pseudo, (outs), (ins), "# CLEANUPRET", [(cleanupret)]>;
179 // CATCHRET needs a custom inserter for SEH.
180 let usesCustomInserter = 1 in
181 def CATCHRET : I<0, Pseudo, (outs), (ins brtarget32:$dst, brtarget32:$from),
183 [(catchret bb:$dst, bb:$from)]>;
186 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1,
187 usesCustomInserter = 1 in
188 def CATCHPAD : I<0, Pseudo, (outs), (ins), "# CATCHPAD", [(catchpad)]>;
190 // This instruction is responsible for re-establishing stack pointers after an
191 // exception has been caught and we are rejoining normal control flow in the
192 // parent function or funclet. It generally sets ESP and EBP, and optionally
193 // ESI. It is only needed for 32-bit WinEH, as the runtime restores CSRs for us
195 let hasSideEffects = 1, hasCtrlDep = 1, isCodeGenOnly = 1 in
196 def EH_RESTORE : I<0, Pseudo, (outs), (ins), "# EH_RESTORE", []>;
198 let hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
199 usesCustomInserter = 1 in {
200 def EH_SjLj_SetJmp32 : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$buf),
202 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
203 Requires<[Not64BitMode]>;
204 def EH_SjLj_SetJmp64 : I<0, Pseudo, (outs GR32:$dst), (ins i64mem:$buf),
206 [(set GR32:$dst, (X86eh_sjlj_setjmp addr:$buf))]>,
207 Requires<[In64BitMode]>;
208 let isTerminator = 1 in {
209 def EH_SjLj_LongJmp32 : I<0, Pseudo, (outs), (ins i32mem:$buf),
210 "#EH_SJLJ_LONGJMP32",
211 [(X86eh_sjlj_longjmp addr:$buf)]>,
212 Requires<[Not64BitMode]>;
213 def EH_SjLj_LongJmp64 : I<0, Pseudo, (outs), (ins i64mem:$buf),
214 "#EH_SJLJ_LONGJMP64",
215 [(X86eh_sjlj_longjmp addr:$buf)]>,
216 Requires<[In64BitMode]>;
221 let isBranch = 1, isTerminator = 1, isCodeGenOnly = 1 in {
222 def EH_SjLj_Setup : I<0, Pseudo, (outs), (ins brtarget:$dst),
223 "#EH_SjLj_Setup\t$dst", []>;
226 //===----------------------------------------------------------------------===//
227 // Pseudo instructions used by unwind info.
229 let isPseudo = 1 in {
230 def SEH_PushReg : I<0, Pseudo, (outs), (ins i32imm:$reg),
231 "#SEH_PushReg $reg", []>;
232 def SEH_SaveReg : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
233 "#SEH_SaveReg $reg, $dst", []>;
234 def SEH_SaveXMM : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$dst),
235 "#SEH_SaveXMM $reg, $dst", []>;
236 def SEH_StackAlloc : I<0, Pseudo, (outs), (ins i32imm:$size),
237 "#SEH_StackAlloc $size", []>;
238 def SEH_SetFrame : I<0, Pseudo, (outs), (ins i32imm:$reg, i32imm:$offset),
239 "#SEH_SetFrame $reg, $offset", []>;
240 def SEH_PushFrame : I<0, Pseudo, (outs), (ins i1imm:$mode),
241 "#SEH_PushFrame $mode", []>;
242 def SEH_EndPrologue : I<0, Pseudo, (outs), (ins),
243 "#SEH_EndPrologue", []>;
244 def SEH_Epilogue : I<0, Pseudo, (outs), (ins),
245 "#SEH_Epilogue", []>;
248 //===----------------------------------------------------------------------===//
249 // Pseudo instructions used by segmented stacks.
252 // This is lowered into a RET instruction by MCInstLower. We need
253 // this so that we don't have to have a MachineBasicBlock which ends
254 // with a RET and also has successors.
255 let isPseudo = 1 in {
256 def MORESTACK_RET: I<0, Pseudo, (outs), (ins),
259 // This instruction is lowered to a RET followed by a MOV. The two
260 // instructions are not generated on a higher level since then the
261 // verifier sees a MachineBasicBlock ending with a non-terminator.
262 def MORESTACK_RET_RESTORE_R10 : I<0, Pseudo, (outs), (ins),
266 //===----------------------------------------------------------------------===//
267 // Alias Instructions
268 //===----------------------------------------------------------------------===//
270 // Alias instruction mapping movr0 to xor.
271 // FIXME: remove when we can teach regalloc that xor reg, reg is ok.
272 let Defs = [EFLAGS], isReMaterializable = 1, isAsCheapAsAMove = 1,
273 isPseudo = 1, AddedComplexity = 10 in
274 def MOV32r0 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
275 [(set GR32:$dst, 0)], IIC_ALU_NONMEM>, Sched<[WriteZero]>;
277 // Other widths can also make use of the 32-bit xor, which may have a smaller
278 // encoding and avoid partial register updates.
279 let AddedComplexity = 10 in {
280 def : Pat<(i8 0), (EXTRACT_SUBREG (MOV32r0), sub_8bit)>;
281 def : Pat<(i16 0), (EXTRACT_SUBREG (MOV32r0), sub_16bit)>;
282 def : Pat<(i64 0), (SUBREG_TO_REG (i64 0), (MOV32r0), sub_32bit)>;
285 let Predicates = [OptForSize, Not64BitMode],
286 AddedComplexity = 10 in {
287 // Pseudo instructions for materializing 1 and -1 using XOR+INC/DEC,
288 // which only require 3 bytes compared to MOV32ri which requires 5.
289 let Defs = [EFLAGS], isReMaterializable = 1, isPseudo = 1 in {
290 def MOV32r1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
291 [(set GR32:$dst, 1)]>;
292 def MOV32r_1 : I<0, Pseudo, (outs GR32:$dst), (ins), "",
293 [(set GR32:$dst, -1)]>;
296 // MOV16ri is 4 bytes, so the instructions above are smaller.
297 def : Pat<(i16 1), (EXTRACT_SUBREG (MOV32r1), sub_16bit)>;
298 def : Pat<(i16 -1), (EXTRACT_SUBREG (MOV32r_1), sub_16bit)>;
301 let isReMaterializable = 1, isPseudo = 1, AddedComplexity = 5 in {
302 // AddedComplexity higher than MOV64ri but lower than MOV32r0 and MOV32r1.
303 // FIXME: Add itinerary class and Schedule.
304 def MOV32ImmSExti8 : I<0, Pseudo, (outs GR32:$dst), (ins i32i8imm:$src), "",
305 [(set GR32:$dst, i32immSExt8:$src)]>,
306 Requires<[OptForMinSize, NotWin64WithoutFP]>;
307 def MOV64ImmSExti8 : I<0, Pseudo, (outs GR64:$dst), (ins i64i8imm:$src), "",
308 [(set GR64:$dst, i64immSExt8:$src)]>,
309 Requires<[OptForMinSize, NotWin64WithoutFP]>;
312 // Materialize i64 constant where top 32-bits are zero. This could theoretically
313 // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however
314 // that would make it more difficult to rematerialize.
315 let isReMaterializable = 1, isAsCheapAsAMove = 1,
316 isPseudo = 1, hasSideEffects = 0 in
317 def MOV32ri64 : I<0, Pseudo, (outs GR32:$dst), (ins i64i32imm:$src), "", []>;
319 // This 64-bit pseudo-move can be used for both a 64-bit constant that is
320 // actually the zero-extension of a 32-bit constant and for labels in the
321 // x86-64 small code model.
322 def mov64imm32 : ComplexPattern<i64, 1, "selectMOV64Imm32", [imm, X86Wrapper]>;
324 let AddedComplexity = 1 in
325 def : Pat<(i64 mov64imm32:$src),
326 (SUBREG_TO_REG (i64 0), (MOV32ri64 mov64imm32:$src), sub_32bit)>;
328 // Use sbb to materialize carry bit.
329 let Uses = [EFLAGS], Defs = [EFLAGS], isPseudo = 1, SchedRW = [WriteALU] in {
330 // FIXME: These are pseudo ops that should be replaced with Pat<> patterns.
331 // However, Pat<> can't replicate the destination reg into the inputs of the
333 def SETB_C8r : I<0, Pseudo, (outs GR8:$dst), (ins), "",
334 [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
335 def SETB_C16r : I<0, Pseudo, (outs GR16:$dst), (ins), "",
336 [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
337 def SETB_C32r : I<0, Pseudo, (outs GR32:$dst), (ins), "",
338 [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
339 def SETB_C64r : I<0, Pseudo, (outs GR64:$dst), (ins), "",
340 [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>;
344 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
346 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
348 def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
351 def : Pat<(i16 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
353 def : Pat<(i32 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
355 def : Pat<(i64 (sext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
358 // We canonicalize 'setb' to "(and (sbb reg,reg), 1)" on the hope that the and
359 // will be eliminated and that the sbb can be extended up to a wider type. When
360 // this happens, it is great. However, if we are left with an 8-bit sbb and an
361 // and, we might as well just match it as a setb.
362 def : Pat<(and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1),
365 // (add OP, SETB) -> (adc OP, 0)
366 def : Pat<(add (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR8:$op),
367 (ADC8ri GR8:$op, 0)>;
368 def : Pat<(add (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR32:$op),
369 (ADC32ri8 GR32:$op, 0)>;
370 def : Pat<(add (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1), GR64:$op),
371 (ADC64ri8 GR64:$op, 0)>;
373 // (sub OP, SETB) -> (sbb OP, 0)
374 def : Pat<(sub GR8:$op, (and (i8 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
375 (SBB8ri GR8:$op, 0)>;
376 def : Pat<(sub GR32:$op, (and (i32 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
377 (SBB32ri8 GR32:$op, 0)>;
378 def : Pat<(sub GR64:$op, (and (i64 (X86setcc_c X86_COND_B, EFLAGS)), 1)),
379 (SBB64ri8 GR64:$op, 0)>;
381 // (sub OP, SETCC_CARRY) -> (adc OP, 0)
382 def : Pat<(sub GR8:$op, (i8 (X86setcc_c X86_COND_B, EFLAGS))),
383 (ADC8ri GR8:$op, 0)>;
384 def : Pat<(sub GR32:$op, (i32 (X86setcc_c X86_COND_B, EFLAGS))),
385 (ADC32ri8 GR32:$op, 0)>;
386 def : Pat<(sub GR64:$op, (i64 (X86setcc_c X86_COND_B, EFLAGS))),
387 (ADC64ri8 GR64:$op, 0)>;
389 //===----------------------------------------------------------------------===//
390 // String Pseudo Instructions
392 let SchedRW = [WriteMicrocoded] in {
393 let Defs = [ECX,EDI,ESI], Uses = [ECX,EDI,ESI], isCodeGenOnly = 1 in {
394 def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
395 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
396 Requires<[Not64BitMode]>;
397 def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
398 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
399 Requires<[Not64BitMode]>;
400 def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
401 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
402 Requires<[Not64BitMode]>;
405 let Defs = [RCX,RDI,RSI], Uses = [RCX,RDI,RSI], isCodeGenOnly = 1 in {
406 def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
407 [(X86rep_movs i8)], IIC_REP_MOVS>, REP,
408 Requires<[In64BitMode]>;
409 def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
410 [(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
411 Requires<[In64BitMode]>;
412 def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
413 [(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
414 Requires<[In64BitMode]>;
415 def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
416 [(X86rep_movs i64)], IIC_REP_MOVS>, REP,
417 Requires<[In64BitMode]>;
420 // FIXME: Should use "(X86rep_stos AL)" as the pattern.
421 let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
422 let Uses = [AL,ECX,EDI] in
423 def REP_STOSB_32 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
424 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
425 Requires<[Not64BitMode]>;
426 let Uses = [AX,ECX,EDI] in
427 def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
428 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
429 Requires<[Not64BitMode]>;
430 let Uses = [EAX,ECX,EDI] in
431 def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
432 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
433 Requires<[Not64BitMode]>;
436 let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
437 let Uses = [AL,RCX,RDI] in
438 def REP_STOSB_64 : I<0xAA, RawFrm, (outs), (ins), "{rep;stosb|rep stosb}",
439 [(X86rep_stos i8)], IIC_REP_STOS>, REP,
440 Requires<[In64BitMode]>;
441 let Uses = [AX,RCX,RDI] in
442 def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
443 [(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
444 Requires<[In64BitMode]>;
445 let Uses = [RAX,RCX,RDI] in
446 def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
447 [(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
448 Requires<[In64BitMode]>;
450 let Uses = [RAX,RCX,RDI] in
451 def REP_STOSQ_64 : RI<0xAB, RawFrm, (outs), (ins), "{rep;stosq|rep stosq}",
452 [(X86rep_stos i64)], IIC_REP_STOS>, REP,
453 Requires<[In64BitMode]>;
457 //===----------------------------------------------------------------------===//
458 // Thread Local Storage Instructions
462 // All calls clobber the non-callee saved registers. ESP is marked as
463 // a use to prevent stack-pointer assignments that appear immediately
464 // before calls from potentially appearing dead.
465 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
466 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
467 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
468 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
469 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
470 usesCustomInserter = 1, Uses = [ESP, SSP] in {
471 def TLS_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
473 [(X86tlsaddr tls32addr:$sym)]>,
474 Requires<[Not64BitMode]>;
475 def TLS_base_addr32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
477 [(X86tlsbaseaddr tls32baseaddr:$sym)]>,
478 Requires<[Not64BitMode]>;
481 // All calls clobber the non-callee saved registers. RSP is marked as
482 // a use to prevent stack-pointer assignments that appear immediately
483 // before calls from potentially appearing dead.
484 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
485 FP0, FP1, FP2, FP3, FP4, FP5, FP6, FP7,
486 ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7,
487 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
488 XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,
489 XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS],
490 usesCustomInserter = 1, Uses = [RSP, SSP] in {
491 def TLS_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
493 [(X86tlsaddr tls64addr:$sym)]>,
494 Requires<[In64BitMode]>;
495 def TLS_base_addr64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
497 [(X86tlsbaseaddr tls64baseaddr:$sym)]>,
498 Requires<[In64BitMode]>;
501 // Darwin TLS Support
502 // For i386, the address of the thunk is passed on the stack, on return the
503 // address of the variable is in %eax. %ecx is trashed during the function
504 // call. All other registers are preserved.
505 let Defs = [EAX, ECX, EFLAGS],
507 usesCustomInserter = 1 in
508 def TLSCall_32 : I<0, Pseudo, (outs), (ins i32mem:$sym),
510 [(X86TLSCall addr:$sym)]>,
511 Requires<[Not64BitMode]>;
513 // For x86_64, the address of the thunk is passed in %rdi, but the
514 // pseudo directly use the symbol, so do not add an implicit use of
515 // %rdi. The lowering will do the right thing with RDI.
516 // On return the address of the variable is in %rax. All other
517 // registers are preserved.
518 let Defs = [RAX, EFLAGS],
520 usesCustomInserter = 1 in
521 def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
523 [(X86TLSCall addr:$sym)]>,
524 Requires<[In64BitMode]>;
527 //===----------------------------------------------------------------------===//
528 // Conditional Move Pseudo Instructions
530 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
531 // instruction selection into a branch sequence.
532 multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {
533 def CMOV#NAME : I<0, Pseudo,
534 (outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),
535 "#CMOV_"#NAME#" PSEUDO!",
536 [(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond,
540 let usesCustomInserter = 1, Uses = [EFLAGS] in {
541 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
542 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
543 // however that requires promoting the operands, and can induce additional
544 // i8 register pressure.
545 defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
547 let Predicates = [NoCMov] in {
548 defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
549 defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
550 } // Predicates = [NoCMov]
552 // fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
554 let Predicates = [FPStackf32] in
555 defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;
557 let Predicates = [FPStackf64] in
558 defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;
560 defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
562 defm _FR32 : CMOVrr_PSEUDO<FR32, f32>;
563 defm _FR64 : CMOVrr_PSEUDO<FR64, f64>;
564 defm _FR128 : CMOVrr_PSEUDO<FR128, f128>;
565 defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>;
566 defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>;
567 defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>;
568 defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>;
569 defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>;
570 defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>;
571 defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
572 defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>;
573 defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>;
574 defm _V8I1 : CMOVrr_PSEUDO<VK8, v8i1>;
575 defm _V16I1 : CMOVrr_PSEUDO<VK16, v16i1>;
576 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
577 defm _V64I1 : CMOVrr_PSEUDO<VK64, v64i1>;
578 } // usesCustomInserter = 1, Uses = [EFLAGS]
580 //===----------------------------------------------------------------------===//
581 // Normal-Instructions-With-Lock-Prefix Pseudo Instructions
582 //===----------------------------------------------------------------------===//
584 // FIXME: Use normal instructions and add lock prefix dynamically.
588 // TODO: Get this to fold the constant into the instruction.
589 let isCodeGenOnly = 1, Defs = [EFLAGS] in
590 def OR32mrLocked : I<0x09, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$zero),
591 "or{l}\t{$zero, $dst|$dst, $zero}", [],
592 IIC_ALU_MEM>, Requires<[Not64BitMode]>, OpSize32, LOCK,
593 Sched<[WriteALULd, WriteRMW]>;
595 let hasSideEffects = 1 in
596 def Int_MemBarrier : I<0, Pseudo, (outs), (ins),
598 [(X86MemBarrier)]>, Sched<[WriteLoad]>;
600 // RegOpc corresponds to the mr version of the instruction
601 // ImmOpc corresponds to the mi version of the instruction
602 // ImmOpc8 corresponds to the mi8 version of the instruction
603 // ImmMod corresponds to the instruction format of the mi and mi8 versions
604 multiclass LOCK_ArithBinOp<bits<8> RegOpc, bits<8> ImmOpc, bits<8> ImmOpc8,
605 Format ImmMod, SDNode Op, string mnemonic> {
606 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
607 SchedRW = [WriteALULd, WriteRMW] in {
609 def NAME#8mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
610 RegOpc{3}, RegOpc{2}, RegOpc{1}, 0 },
611 MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src2),
612 !strconcat(mnemonic, "{b}\t",
613 "{$src2, $dst|$dst, $src2}"),
614 [(set EFLAGS, (Op addr:$dst, GR8:$src2))],
615 IIC_ALU_NONMEM>, LOCK;
617 def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
618 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
619 MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
620 !strconcat(mnemonic, "{w}\t",
621 "{$src2, $dst|$dst, $src2}"),
622 [(set EFLAGS, (Op addr:$dst, GR16:$src2))],
623 IIC_ALU_NONMEM>, OpSize16, LOCK;
625 def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
626 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
627 MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
628 !strconcat(mnemonic, "{l}\t",
629 "{$src2, $dst|$dst, $src2}"),
630 [(set EFLAGS, (Op addr:$dst, GR32:$src2))],
631 IIC_ALU_NONMEM>, OpSize32, LOCK;
633 def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
634 RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
635 MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
636 !strconcat(mnemonic, "{q}\t",
637 "{$src2, $dst|$dst, $src2}"),
638 [(set EFLAGS, (Op addr:$dst, GR64:$src2))],
639 IIC_ALU_NONMEM>, LOCK;
641 def NAME#8mi : Ii8<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
642 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 0 },
643 ImmMod, (outs), (ins i8mem :$dst, i8imm :$src2),
644 !strconcat(mnemonic, "{b}\t",
645 "{$src2, $dst|$dst, $src2}"),
646 [(set EFLAGS, (Op addr:$dst, (i8 imm:$src2)))],
649 def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
650 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
651 ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
652 !strconcat(mnemonic, "{w}\t",
653 "{$src2, $dst|$dst, $src2}"),
654 [(set EFLAGS, (Op addr:$dst, (i16 imm:$src2)))],
655 IIC_ALU_MEM>, OpSize16, LOCK;
657 def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
658 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
659 ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
660 !strconcat(mnemonic, "{l}\t",
661 "{$src2, $dst|$dst, $src2}"),
662 [(set EFLAGS, (Op addr:$dst, (i32 imm:$src2)))],
663 IIC_ALU_MEM>, OpSize32, LOCK;
665 def NAME#64mi32 : RIi32S<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
666 ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
667 ImmMod, (outs), (ins i64mem :$dst, i64i32imm :$src2),
668 !strconcat(mnemonic, "{q}\t",
669 "{$src2, $dst|$dst, $src2}"),
670 [(set EFLAGS, (Op addr:$dst, i64immSExt32:$src2))],
673 def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
674 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
675 ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
676 !strconcat(mnemonic, "{w}\t",
677 "{$src2, $dst|$dst, $src2}"),
678 [(set EFLAGS, (Op addr:$dst, i16immSExt8:$src2))],
679 IIC_ALU_MEM>, OpSize16, LOCK;
681 def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
682 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
683 ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
684 !strconcat(mnemonic, "{l}\t",
685 "{$src2, $dst|$dst, $src2}"),
686 [(set EFLAGS, (Op addr:$dst, i32immSExt8:$src2))],
687 IIC_ALU_MEM>, OpSize32, LOCK;
689 def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
690 ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
691 ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
692 !strconcat(mnemonic, "{q}\t",
693 "{$src2, $dst|$dst, $src2}"),
694 [(set EFLAGS, (Op addr:$dst, i64immSExt8:$src2))],
701 defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, X86lock_add, "add">;
702 defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, X86lock_sub, "sub">;
703 defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, X86lock_or , "or">;
704 defm LOCK_AND : LOCK_ArithBinOp<0x20, 0x80, 0x83, MRM4m, X86lock_and, "and">;
705 defm LOCK_XOR : LOCK_ArithBinOp<0x30, 0x80, 0x83, MRM6m, X86lock_xor, "xor">;
707 multiclass LOCK_ArithUnOp<bits<8> Opc8, bits<8> Opc, Format Form,
708 string frag, string mnemonic> {
709 let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1,
710 SchedRW = [WriteALULd, WriteRMW] in {
711 def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
712 !strconcat(mnemonic, "{b}\t$dst"),
713 [(set EFLAGS, (!cast<PatFrag>(frag # "_8") addr:$dst))],
714 IIC_UNARY_MEM>, LOCK;
715 def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
716 !strconcat(mnemonic, "{w}\t$dst"),
717 [(set EFLAGS, (!cast<PatFrag>(frag # "_16") addr:$dst))],
718 IIC_UNARY_MEM>, OpSize16, LOCK;
719 def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
720 !strconcat(mnemonic, "{l}\t$dst"),
721 [(set EFLAGS, (!cast<PatFrag>(frag # "_32") addr:$dst))],
722 IIC_UNARY_MEM>, OpSize32, LOCK;
723 def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
724 !strconcat(mnemonic, "{q}\t$dst"),
725 [(set EFLAGS, (!cast<PatFrag>(frag # "_64") addr:$dst))],
726 IIC_UNARY_MEM>, LOCK;
730 multiclass unary_atomic_intrin<SDNode atomic_op> {
731 def _8 : PatFrag<(ops node:$ptr),
732 (atomic_op node:$ptr), [{
733 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i8;
735 def _16 : PatFrag<(ops node:$ptr),
736 (atomic_op node:$ptr), [{
737 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i16;
739 def _32 : PatFrag<(ops node:$ptr),
740 (atomic_op node:$ptr), [{
741 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i32;
743 def _64 : PatFrag<(ops node:$ptr),
744 (atomic_op node:$ptr), [{
745 return cast<MemIntrinsicSDNode>(N)->getMemoryVT() == MVT::i64;
749 defm X86lock_inc : unary_atomic_intrin<X86lock_inc>;
750 defm X86lock_dec : unary_atomic_intrin<X86lock_dec>;
752 defm LOCK_INC : LOCK_ArithUnOp<0xFE, 0xFF, MRM0m, "X86lock_inc", "inc">;
753 defm LOCK_DEC : LOCK_ArithUnOp<0xFE, 0xFF, MRM1m, "X86lock_dec", "dec">;
755 // Atomic compare and swap.
756 multiclass LCMPXCHG_UnOp<bits<8> Opc, Format Form, string mnemonic,
757 SDPatternOperator frag, X86MemOperand x86memop,
758 InstrItinClass itin> {
759 let isCodeGenOnly = 1, usesCustomInserter = 1 in {
760 def NAME : I<Opc, Form, (outs), (ins x86memop:$ptr),
761 !strconcat(mnemonic, "\t$ptr"),
762 [(frag addr:$ptr)], itin>, TB, LOCK;
766 multiclass LCMPXCHG_BinOp<bits<8> Opc8, bits<8> Opc, Format Form,
767 string mnemonic, SDPatternOperator frag,
768 InstrItinClass itin8, InstrItinClass itin> {
769 let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
770 let Defs = [AL, EFLAGS], Uses = [AL] in
771 def NAME#8 : I<Opc8, Form, (outs), (ins i8mem:$ptr, GR8:$swap),
772 !strconcat(mnemonic, "{b}\t{$swap, $ptr|$ptr, $swap}"),
773 [(frag addr:$ptr, GR8:$swap, 1)], itin8>, TB, LOCK;
774 let Defs = [AX, EFLAGS], Uses = [AX] in
775 def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
776 !strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
777 [(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
778 let Defs = [EAX, EFLAGS], Uses = [EAX] in
779 def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
780 !strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
781 [(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
782 let Defs = [RAX, EFLAGS], Uses = [RAX] in
783 def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
784 !strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
785 [(frag addr:$ptr, GR64:$swap, 8)], itin>, TB, LOCK;
789 let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX],
790 SchedRW = [WriteALULd, WriteRMW] in {
791 defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b",
796 // This pseudo must be used when the frame uses RBX as
797 // the base pointer. Indeed, in such situation RBX is a reserved
798 // register and the register allocator will ignore any use/def of
799 // it. In other words, the register will not fix the clobbering of
800 // RBX that will happen when setting the arguments for the instrucion.
802 // Unlike the actual related instuction, we mark that this one
803 // defines EBX (instead of using EBX).
804 // The rationale is that we will define RBX during the expansion of
805 // the pseudo. The argument feeding EBX is ebx_input.
807 // The additional argument, $ebx_save, is a temporary register used to
808 // save the value of RBX across the actual instruction.
810 // To make sure the register assigned to $ebx_save does not interfere with
811 // the definition of the actual instruction, we use a definition $dst which
812 // is tied to $rbx_save. That way, the live-range of $rbx_save spans across
813 // the instruction and we are sure we will have a valid register to restore
815 let Defs = [EAX, EDX, EBX, EFLAGS], Uses = [EAX, ECX, EDX],
816 SchedRW = [WriteALULd, WriteRMW], isCodeGenOnly = 1, isPseudo = 1,
817 Constraints = "$ebx_save = $dst", usesCustomInserter = 1 in {
818 def LCMPXCHG8B_SAVE_EBX :
819 I<0, Pseudo, (outs GR32:$dst),
820 (ins i64mem:$ptr, GR32:$ebx_input, GR32:$ebx_save),
821 !strconcat("cmpxchg8b", "\t$ptr"),
822 [(set GR32:$dst, (X86cas8save_ebx addr:$ptr, GR32:$ebx_input,
828 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
829 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW] in {
830 defm LCMPXCHG16B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg16b",
832 IIC_CMPX_LOCK_16B>, REX_W;
835 // Same as LCMPXCHG8B_SAVE_RBX but for the 16 Bytes variant.
836 let Defs = [RAX, RDX, RBX, EFLAGS], Uses = [RAX, RCX, RDX],
837 Predicates = [HasCmpxchg16b], SchedRW = [WriteALULd, WriteRMW],
838 isCodeGenOnly = 1, isPseudo = 1, Constraints = "$rbx_save = $dst",
839 usesCustomInserter = 1 in {
840 def LCMPXCHG16B_SAVE_RBX :
841 I<0, Pseudo, (outs GR64:$dst),
842 (ins i128mem:$ptr, GR64:$rbx_input, GR64:$rbx_save),
843 !strconcat("cmpxchg16b", "\t$ptr"),
844 [(set GR64:$dst, (X86cas16save_rbx addr:$ptr, GR64:$rbx_input,
849 defm LCMPXCHG : LCMPXCHG_BinOp<0xB0, 0xB1, MRMDestMem, "cmpxchg",
850 X86cas, IIC_CMPX_LOCK_8, IIC_CMPX_LOCK>;
852 // Atomic exchange and add
853 multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
855 InstrItinClass itin8, InstrItinClass itin> {
856 let Constraints = "$val = $dst", Defs = [EFLAGS], isCodeGenOnly = 1,
857 SchedRW = [WriteALULd, WriteRMW] in {
858 def NAME#8 : I<opc8, MRMSrcMem, (outs GR8:$dst),
859 (ins GR8:$val, i8mem:$ptr),
860 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"),
862 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))],
864 def NAME#16 : I<opc, MRMSrcMem, (outs GR16:$dst),
865 (ins GR16:$val, i16mem:$ptr),
866 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"),
869 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
871 def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
872 (ins GR32:$val, i32mem:$ptr),
873 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
876 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
878 def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
879 (ins GR64:$val, i64mem:$ptr),
880 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
883 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))],
888 defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
889 IIC_XADD_LOCK_MEM8, IIC_XADD_LOCK_MEM>,
892 /* The following multiclass tries to make sure that in code like
893 * x.store (immediate op x.load(acquire), release)
895 * x.store (register op x.load(acquire), release)
896 * an operation directly on memory is generated instead of wasting a register.
897 * It is not automatic as atomic_store/load are only lowered to MOV instructions
898 * extremely late to prevent them from being accidentally reordered in the backend
899 * (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
901 multiclass RELEASE_BINOP_MI<SDNode op> {
902 def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
903 "#BINOP "#NAME#"8mi PSEUDO!",
904 [(atomic_store_8 addr:$dst, (op
905 (atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
906 def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src),
907 "#BINOP "#NAME#"8mr PSEUDO!",
908 [(atomic_store_8 addr:$dst, (op
909 (atomic_load_8 addr:$dst), GR8:$src))]>;
910 // NAME#16 is not generated as 16-bit arithmetic instructions are considered
911 // costly and avoided as far as possible by this backend anyway
912 def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
913 "#BINOP "#NAME#"32mi PSEUDO!",
914 [(atomic_store_32 addr:$dst, (op
915 (atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
916 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
917 "#BINOP "#NAME#"32mr PSEUDO!",
918 [(atomic_store_32 addr:$dst, (op
919 (atomic_load_32 addr:$dst), GR32:$src))]>;
920 def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
921 "#BINOP "#NAME#"64mi32 PSEUDO!",
922 [(atomic_store_64 addr:$dst, (op
923 (atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
924 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
925 "#BINOP "#NAME#"64mr PSEUDO!",
926 [(atomic_store_64 addr:$dst, (op
927 (atomic_load_64 addr:$dst), GR64:$src))]>;
929 let Defs = [EFLAGS] in {
930 defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
931 defm RELEASE_AND : RELEASE_BINOP_MI<and>;
932 defm RELEASE_OR : RELEASE_BINOP_MI<or>;
933 defm RELEASE_XOR : RELEASE_BINOP_MI<xor>;
934 // Note: we don't deal with sub, because substractions of constants are
935 // optimized into additions before this code can run.
938 // Same as above, but for floating-point.
939 // FIXME: imm version.
940 // FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
941 // FIXME: This could also handle SIMD operations with *ps and *pd instructions.
942 let usesCustomInserter = 1 in {
943 multiclass RELEASE_FP_BINOP_MI<SDNode op> {
944 def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
945 "#BINOP "#NAME#"32mr PSEUDO!",
946 [(atomic_store_32 addr:$dst,
948 (f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))),
949 FR32:$src))))]>, Requires<[HasSSE1]>;
950 def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src),
951 "#BINOP "#NAME#"64mr PSEUDO!",
952 [(atomic_store_64 addr:$dst,
954 (f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))),
955 FR64:$src))))]>, Requires<[HasSSE2]>;
957 defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>;
958 // FIXME: Add fsub, fmul, fdiv, ...
961 multiclass RELEASE_UNOP<dag dag8, dag dag16, dag dag32, dag dag64> {
962 def NAME#8m : I<0, Pseudo, (outs), (ins i8mem:$dst),
963 "#UNOP "#NAME#"8m PSEUDO!",
964 [(atomic_store_8 addr:$dst, dag8)]>;
965 def NAME#16m : I<0, Pseudo, (outs), (ins i16mem:$dst),
966 "#UNOP "#NAME#"16m PSEUDO!",
967 [(atomic_store_16 addr:$dst, dag16)]>;
968 def NAME#32m : I<0, Pseudo, (outs), (ins i32mem:$dst),
969 "#UNOP "#NAME#"32m PSEUDO!",
970 [(atomic_store_32 addr:$dst, dag32)]>;
971 def NAME#64m : I<0, Pseudo, (outs), (ins i64mem:$dst),
972 "#UNOP "#NAME#"64m PSEUDO!",
973 [(atomic_store_64 addr:$dst, dag64)]>;
976 let Defs = [EFLAGS], Predicates = [UseIncDec] in {
977 defm RELEASE_INC : RELEASE_UNOP<
978 (add (atomic_load_8 addr:$dst), (i8 1)),
979 (add (atomic_load_16 addr:$dst), (i16 1)),
980 (add (atomic_load_32 addr:$dst), (i32 1)),
981 (add (atomic_load_64 addr:$dst), (i64 1))>;
982 defm RELEASE_DEC : RELEASE_UNOP<
983 (add (atomic_load_8 addr:$dst), (i8 -1)),
984 (add (atomic_load_16 addr:$dst), (i16 -1)),
985 (add (atomic_load_32 addr:$dst), (i32 -1)),
986 (add (atomic_load_64 addr:$dst), (i64 -1))>;
989 TODO: These don't work because the type inference of TableGen fails.
990 TODO: find a way to fix it.
991 let Defs = [EFLAGS] in {
992 defm RELEASE_NEG : RELEASE_UNOP<
993 (ineg (atomic_load_8 addr:$dst)),
994 (ineg (atomic_load_16 addr:$dst)),
995 (ineg (atomic_load_32 addr:$dst)),
996 (ineg (atomic_load_64 addr:$dst))>;
998 // NOT doesn't set flags.
999 defm RELEASE_NOT : RELEASE_UNOP<
1000 (not (atomic_load_8 addr:$dst)),
1001 (not (atomic_load_16 addr:$dst)),
1002 (not (atomic_load_32 addr:$dst)),
1003 (not (atomic_load_64 addr:$dst))>;
1006 def RELEASE_MOV8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
1007 "#RELEASE_MOV8mi PSEUDO!",
1008 [(atomic_store_8 addr:$dst, (i8 imm:$src))]>;
1009 def RELEASE_MOV16mi : I<0, Pseudo, (outs), (ins i16mem:$dst, i16imm:$src),
1010 "#RELEASE_MOV16mi PSEUDO!",
1011 [(atomic_store_16 addr:$dst, (i16 imm:$src))]>;
1012 def RELEASE_MOV32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
1013 "#RELEASE_MOV32mi PSEUDO!",
1014 [(atomic_store_32 addr:$dst, (i32 imm:$src))]>;
1015 def RELEASE_MOV64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
1016 "#RELEASE_MOV64mi32 PSEUDO!",
1017 [(atomic_store_64 addr:$dst, i64immSExt32:$src)]>;
1019 def RELEASE_MOV8mr : I<0, Pseudo, (outs), (ins i8mem :$dst, GR8 :$src),
1020 "#RELEASE_MOV8mr PSEUDO!",
1021 [(atomic_store_8 addr:$dst, GR8 :$src)]>;
1022 def RELEASE_MOV16mr : I<0, Pseudo, (outs), (ins i16mem:$dst, GR16:$src),
1023 "#RELEASE_MOV16mr PSEUDO!",
1024 [(atomic_store_16 addr:$dst, GR16:$src)]>;
1025 def RELEASE_MOV32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
1026 "#RELEASE_MOV32mr PSEUDO!",
1027 [(atomic_store_32 addr:$dst, GR32:$src)]>;
1028 def RELEASE_MOV64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
1029 "#RELEASE_MOV64mr PSEUDO!",
1030 [(atomic_store_64 addr:$dst, GR64:$src)]>;
1032 def ACQUIRE_MOV8rm : I<0, Pseudo, (outs GR8 :$dst), (ins i8mem :$src),
1033 "#ACQUIRE_MOV8rm PSEUDO!",
1034 [(set GR8:$dst, (atomic_load_8 addr:$src))]>;
1035 def ACQUIRE_MOV16rm : I<0, Pseudo, (outs GR16:$dst), (ins i16mem:$src),
1036 "#ACQUIRE_MOV16rm PSEUDO!",
1037 [(set GR16:$dst, (atomic_load_16 addr:$src))]>;
1038 def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
1039 "#ACQUIRE_MOV32rm PSEUDO!",
1040 [(set GR32:$dst, (atomic_load_32 addr:$src))]>;
1041 def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
1042 "#ACQUIRE_MOV64rm PSEUDO!",
1043 [(set GR64:$dst, (atomic_load_64 addr:$src))]>;
1045 //===----------------------------------------------------------------------===//
1046 // DAG Pattern Matching Rules
1047 //===----------------------------------------------------------------------===//
1049 // Use AND/OR to store 0/-1 in memory when optimizing for minsize. This saves
1050 // binary size compared to a regular MOV, but it introduces an unnecessary
1051 // load, so is not suitable for regular or optsize functions.
1052 let Predicates = [OptForMinSize] in {
1053 def : Pat<(store (i16 0), addr:$dst), (AND16mi8 addr:$dst, 0)>;
1054 def : Pat<(store (i32 0), addr:$dst), (AND32mi8 addr:$dst, 0)>;
1055 def : Pat<(store (i64 0), addr:$dst), (AND64mi8 addr:$dst, 0)>;
1056 def : Pat<(store (i16 -1), addr:$dst), (OR16mi8 addr:$dst, -1)>;
1057 def : Pat<(store (i32 -1), addr:$dst), (OR32mi8 addr:$dst, -1)>;
1058 def : Pat<(store (i64 -1), addr:$dst), (OR64mi8 addr:$dst, -1)>;
1061 // In kernel code model, we can get the address of a label
1062 // into a register with 'movq'. FIXME: This is a hack, the 'imm' predicate of
1063 // the MOV64ri32 should accept these.
1064 def : Pat<(i64 (X86Wrapper tconstpool :$dst)),
1065 (MOV64ri32 tconstpool :$dst)>, Requires<[KernelCode]>;
1066 def : Pat<(i64 (X86Wrapper tjumptable :$dst)),
1067 (MOV64ri32 tjumptable :$dst)>, Requires<[KernelCode]>;
1068 def : Pat<(i64 (X86Wrapper tglobaladdr :$dst)),
1069 (MOV64ri32 tglobaladdr :$dst)>, Requires<[KernelCode]>;
1070 def : Pat<(i64 (X86Wrapper texternalsym:$dst)),
1071 (MOV64ri32 texternalsym:$dst)>, Requires<[KernelCode]>;
1072 def : Pat<(i64 (X86Wrapper mcsym:$dst)),
1073 (MOV64ri32 mcsym:$dst)>, Requires<[KernelCode]>;
1074 def : Pat<(i64 (X86Wrapper tblockaddress:$dst)),
1075 (MOV64ri32 tblockaddress:$dst)>, Requires<[KernelCode]>;
1077 // If we have small model and -static mode, it is safe to store global addresses
1078 // directly as immediates. FIXME: This is really a hack, the 'imm' predicate
1079 // for MOV64mi32 should handle this sort of thing.
1080 def : Pat<(store (i64 (X86Wrapper tconstpool:$src)), addr:$dst),
1081 (MOV64mi32 addr:$dst, tconstpool:$src)>,
1082 Requires<[NearData, IsNotPIC]>;
1083 def : Pat<(store (i64 (X86Wrapper tjumptable:$src)), addr:$dst),
1084 (MOV64mi32 addr:$dst, tjumptable:$src)>,
1085 Requires<[NearData, IsNotPIC]>;
1086 def : Pat<(store (i64 (X86Wrapper tglobaladdr:$src)), addr:$dst),
1087 (MOV64mi32 addr:$dst, tglobaladdr:$src)>,
1088 Requires<[NearData, IsNotPIC]>;
1089 def : Pat<(store (i64 (X86Wrapper texternalsym:$src)), addr:$dst),
1090 (MOV64mi32 addr:$dst, texternalsym:$src)>,
1091 Requires<[NearData, IsNotPIC]>;
1092 def : Pat<(store (i64 (X86Wrapper mcsym:$src)), addr:$dst),
1093 (MOV64mi32 addr:$dst, mcsym:$src)>,
1094 Requires<[NearData, IsNotPIC]>;
1095 def : Pat<(store (i64 (X86Wrapper tblockaddress:$src)), addr:$dst),
1096 (MOV64mi32 addr:$dst, tblockaddress:$src)>,
1097 Requires<[NearData, IsNotPIC]>;
1099 def : Pat<(i32 (X86RecoverFrameAlloc mcsym:$dst)), (MOV32ri mcsym:$dst)>;
1100 def : Pat<(i64 (X86RecoverFrameAlloc mcsym:$dst)), (MOV64ri mcsym:$dst)>;
1104 // tls has some funny stuff here...
1105 // This corresponds to movabs $foo@tpoff, %rax
1106 def : Pat<(i64 (X86Wrapper tglobaltlsaddr :$dst)),
1107 (MOV64ri32 tglobaltlsaddr :$dst)>;
1108 // This corresponds to add $foo@tpoff, %rax
1109 def : Pat<(add GR64:$src1, (X86Wrapper tglobaltlsaddr :$dst)),
1110 (ADD64ri32 GR64:$src1, tglobaltlsaddr :$dst)>;
1113 // Direct PC relative function call for small code model. 32-bit displacement
1114 // sign extended to 64-bit.
1115 def : Pat<(X86call (i64 tglobaladdr:$dst)),
1116 (CALL64pcrel32 tglobaladdr:$dst)>;
1117 def : Pat<(X86call (i64 texternalsym:$dst)),
1118 (CALL64pcrel32 texternalsym:$dst)>;
1120 // Tailcall stuff. The TCRETURN instructions execute after the epilog, so they
1121 // can never use callee-saved registers. That is the purpose of the GR64_TC
1122 // register classes.
1124 // The only volatile register that is never used by the calling convention is
1125 // %r11. This happens when calling a vararg function with 6 arguments.
1127 // Match an X86tcret that uses less than 7 volatile registers.
1128 def X86tcret_6regs : PatFrag<(ops node:$ptr, node:$off),
1129 (X86tcret node:$ptr, node:$off), [{
1130 // X86tcret args: (*chain, ptr, imm, regs..., glue)
1131 unsigned NumRegs = 0;
1132 for (unsigned i = 3, e = N->getNumOperands(); i != e; ++i)
1133 if (isa<RegisterSDNode>(N->getOperand(i)) && ++NumRegs > 6)
1138 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1139 (TCRETURNri ptr_rc_tailcall:$dst, imm:$off)>,
1140 Requires<[Not64BitMode]>;
1142 // FIXME: This is disabled for 32-bit PIC mode because the global base
1143 // register which is part of the address mode may be assigned a
1144 // callee-saved register.
1145 def : Pat<(X86tcret (load addr:$dst), imm:$off),
1146 (TCRETURNmi addr:$dst, imm:$off)>,
1147 Requires<[Not64BitMode, IsNotPIC]>;
1149 def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off),
1150 (TCRETURNdi tglobaladdr:$dst, imm:$off)>,
1151 Requires<[NotLP64]>;
1153 def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off),
1154 (TCRETURNdi texternalsym:$dst, imm:$off)>,
1155 Requires<[NotLP64]>;
1157 def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off),
1158 (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>,
1159 Requires<[In64BitMode]>;
1161 // Don't fold loads into X86tcret requiring more than 6 regs.
1162 // There wouldn't be enough scratch registers for base+index.
1163 def : Pat<(X86tcret_6regs (load addr:$dst), imm:$off),
1164 (TCRETURNmi64 addr:$dst, imm:$off)>,
1165 Requires<[In64BitMode]>;
1167 def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off),
1168 (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>,
1171 def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off),
1172 (TCRETURNdi64 texternalsym:$dst, imm:$off)>,
1175 // Normal calls, with various flavors of addresses.
1176 def : Pat<(X86call (i32 tglobaladdr:$dst)),
1177 (CALLpcrel32 tglobaladdr:$dst)>;
1178 def : Pat<(X86call (i32 texternalsym:$dst)),
1179 (CALLpcrel32 texternalsym:$dst)>;
1180 def : Pat<(X86call (i32 imm:$dst)),
1181 (CALLpcrel32 imm:$dst)>, Requires<[CallImmAddr]>;
1185 // TEST R,R is smaller than CMP R,0
1186 def : Pat<(X86cmp GR8:$src1, 0),
1187 (TEST8rr GR8:$src1, GR8:$src1)>;
1188 def : Pat<(X86cmp GR16:$src1, 0),
1189 (TEST16rr GR16:$src1, GR16:$src1)>;
1190 def : Pat<(X86cmp GR32:$src1, 0),
1191 (TEST32rr GR32:$src1, GR32:$src1)>;
1192 def : Pat<(X86cmp GR64:$src1, 0),
1193 (TEST64rr GR64:$src1, GR64:$src1)>;
1195 // Conditional moves with folded loads with operands swapped and conditions
1197 multiclass CMOVmr<PatLeaf InvertedCond, Instruction Inst16, Instruction Inst32,
1198 Instruction Inst64> {
1199 let Predicates = [HasCMov] in {
1200 def : Pat<(X86cmov (loadi16 addr:$src1), GR16:$src2, InvertedCond, EFLAGS),
1201 (Inst16 GR16:$src2, addr:$src1)>;
1202 def : Pat<(X86cmov (loadi32 addr:$src1), GR32:$src2, InvertedCond, EFLAGS),
1203 (Inst32 GR32:$src2, addr:$src1)>;
1204 def : Pat<(X86cmov (loadi64 addr:$src1), GR64:$src2, InvertedCond, EFLAGS),
1205 (Inst64 GR64:$src2, addr:$src1)>;
1209 defm : CMOVmr<X86_COND_B , CMOVAE16rm, CMOVAE32rm, CMOVAE64rm>;
1210 defm : CMOVmr<X86_COND_AE, CMOVB16rm , CMOVB32rm , CMOVB64rm>;
1211 defm : CMOVmr<X86_COND_E , CMOVNE16rm, CMOVNE32rm, CMOVNE64rm>;
1212 defm : CMOVmr<X86_COND_NE, CMOVE16rm , CMOVE32rm , CMOVE64rm>;
1213 defm : CMOVmr<X86_COND_BE, CMOVA16rm , CMOVA32rm , CMOVA64rm>;
1214 defm : CMOVmr<X86_COND_A , CMOVBE16rm, CMOVBE32rm, CMOVBE64rm>;
1215 defm : CMOVmr<X86_COND_L , CMOVGE16rm, CMOVGE32rm, CMOVGE64rm>;
1216 defm : CMOVmr<X86_COND_GE, CMOVL16rm , CMOVL32rm , CMOVL64rm>;
1217 defm : CMOVmr<X86_COND_LE, CMOVG16rm , CMOVG32rm , CMOVG64rm>;
1218 defm : CMOVmr<X86_COND_G , CMOVLE16rm, CMOVLE32rm, CMOVLE64rm>;
1219 defm : CMOVmr<X86_COND_P , CMOVNP16rm, CMOVNP32rm, CMOVNP64rm>;
1220 defm : CMOVmr<X86_COND_NP, CMOVP16rm , CMOVP32rm , CMOVP64rm>;
1221 defm : CMOVmr<X86_COND_S , CMOVNS16rm, CMOVNS32rm, CMOVNS64rm>;
1222 defm : CMOVmr<X86_COND_NS, CMOVS16rm , CMOVS32rm , CMOVS64rm>;
1223 defm : CMOVmr<X86_COND_O , CMOVNO16rm, CMOVNO32rm, CMOVNO64rm>;
1224 defm : CMOVmr<X86_COND_NO, CMOVO16rm , CMOVO32rm , CMOVO64rm>;
1226 // zextload bool -> zextload byte
1227 // i1 stored in one byte in zero-extended form.
1228 // Upper bits cleanup should be executed before Store.
1229 def : Pat<(zextloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1230 def : Pat<(zextloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1231 def : Pat<(zextloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1232 def : Pat<(zextloadi64i1 addr:$src),
1233 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1235 // extload bool -> extload byte
1236 // When extloading from 16-bit and smaller memory locations into 64-bit
1237 // registers, use zero-extending loads so that the entire 64-bit register is
1238 // defined, avoiding partial-register updates.
1240 def : Pat<(extloadi8i1 addr:$src), (MOV8rm addr:$src)>;
1241 def : Pat<(extloadi16i1 addr:$src), (MOVZX16rm8 addr:$src)>;
1242 def : Pat<(extloadi32i1 addr:$src), (MOVZX32rm8 addr:$src)>;
1243 def : Pat<(extloadi16i8 addr:$src), (MOVZX16rm8 addr:$src)>;
1244 def : Pat<(extloadi32i8 addr:$src), (MOVZX32rm8 addr:$src)>;
1245 def : Pat<(extloadi32i16 addr:$src), (MOVZX32rm16 addr:$src)>;
1247 // For other extloads, use subregs, since the high contents of the register are
1248 // defined after an extload.
1249 def : Pat<(extloadi64i1 addr:$src),
1250 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1251 def : Pat<(extloadi64i8 addr:$src),
1252 (SUBREG_TO_REG (i64 0), (MOVZX32rm8 addr:$src), sub_32bit)>;
1253 def : Pat<(extloadi64i16 addr:$src),
1254 (SUBREG_TO_REG (i64 0), (MOVZX32rm16 addr:$src), sub_32bit)>;
1255 def : Pat<(extloadi64i32 addr:$src),
1256 (SUBREG_TO_REG (i64 0), (MOV32rm addr:$src), sub_32bit)>;
1258 // anyext. Define these to do an explicit zero-extend to
1259 // avoid partial-register updates.
1260 def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG
1261 (MOVZX32rr8 GR8 :$src), sub_16bit)>;
1262 def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>;
1264 // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32.
1265 def : Pat<(i32 (anyext GR16:$src)),
1266 (INSERT_SUBREG (i32 (IMPLICIT_DEF)), GR16:$src, sub_16bit)>;
1268 def : Pat<(i64 (anyext GR8 :$src)),
1269 (SUBREG_TO_REG (i64 0), (MOVZX32rr8 GR8 :$src), sub_32bit)>;
1270 def : Pat<(i64 (anyext GR16:$src)),
1271 (SUBREG_TO_REG (i64 0), (MOVZX32rr16 GR16 :$src), sub_32bit)>;
1272 def : Pat<(i64 (anyext GR32:$src)),
1273 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, sub_32bit)>;
1276 // Any instruction that defines a 32-bit result leaves the high half of the
1277 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
1278 // be copying from a truncate. Any other 32-bit operation will zero-extend
1279 // up to 64 bits. AssertSext/AssertZext aren't saying anything about the upper
1280 // 32 bits, they're probably just qualifying a CopyFromReg.
1281 def def32 : PatLeaf<(i32 GR32:$src), [{
1282 return N->getOpcode() != ISD::TRUNCATE &&
1283 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
1284 N->getOpcode() != ISD::CopyFromReg &&
1285 N->getOpcode() != ISD::AssertSext &&
1286 N->getOpcode() != ISD::AssertZext;
1289 // In the case of a 32-bit def that is known to implicitly zero-extend,
1290 // we can use a SUBREG_TO_REG.
1291 def : Pat<(i64 (zext def32:$src)),
1292 (SUBREG_TO_REG (i64 0), GR32:$src, sub_32bit)>;
1294 //===----------------------------------------------------------------------===//
1295 // Pattern match OR as ADD
1296 //===----------------------------------------------------------------------===//
1298 // If safe, we prefer to pattern match OR as ADD at isel time. ADD can be
1299 // 3-addressified into an LEA instruction to avoid copies. However, we also
1300 // want to finally emit these instructions as an or at the end of the code
1301 // generator to make the generated code easier to read. To do this, we select
1302 // into "disjoint bits" pseudo ops.
1304 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
1305 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
1306 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1307 return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
1310 CurDAG->computeKnownBits(N->getOperand(0), Known0, 0);
1312 CurDAG->computeKnownBits(N->getOperand(1), Known1, 0);
1313 return (~Known0.Zero & ~Known1.Zero) == 0;
1317 // (or x1, x2) -> (add x1, x2) if two operands are known not to share bits.
1318 // Try this before the selecting to OR.
1319 let AddedComplexity = 5, SchedRW = [WriteALU] in {
1321 let isConvertibleToThreeAddress = 1,
1322 Constraints = "$src1 = $dst", Defs = [EFLAGS] in {
1323 let isCommutable = 1 in {
1324 def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
1325 "", // orw/addw REG, REG
1326 [(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
1327 def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
1328 "", // orl/addl REG, REG
1329 [(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
1330 def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
1331 "", // orq/addq REG, REG
1332 [(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
1335 // NOTE: These are order specific, we want the ri8 forms to be listed
1336 // first so that they are slightly preferred to the ri forms.
1338 def ADD16ri8_DB : I<0, Pseudo,
1339 (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
1340 "", // orw/addw REG, imm8
1341 [(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
1342 def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
1343 "", // orw/addw REG, imm
1344 [(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
1346 def ADD32ri8_DB : I<0, Pseudo,
1347 (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
1348 "", // orl/addl REG, imm8
1349 [(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
1350 def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
1351 "", // orl/addl REG, imm
1352 [(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
1355 def ADD64ri8_DB : I<0, Pseudo,
1356 (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
1357 "", // orq/addq REG, imm8
1358 [(set GR64:$dst, (or_is_add GR64:$src1,
1359 i64immSExt8:$src2))]>;
1360 def ADD64ri32_DB : I<0, Pseudo,
1361 (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
1362 "", // orq/addq REG, imm
1363 [(set GR64:$dst, (or_is_add GR64:$src1,
1364 i64immSExt32:$src2))]>;
1366 } // AddedComplexity, SchedRW
1369 //===----------------------------------------------------------------------===//
1371 //===----------------------------------------------------------------------===//
1373 // Odd encoding trick: -128 fits into an 8-bit immediate field while
1374 // +128 doesn't, so in this special case use a sub instead of an add.
1375 def : Pat<(add GR16:$src1, 128),
1376 (SUB16ri8 GR16:$src1, -128)>;
1377 def : Pat<(store (add (loadi16 addr:$dst), 128), addr:$dst),
1378 (SUB16mi8 addr:$dst, -128)>;
1380 def : Pat<(add GR32:$src1, 128),
1381 (SUB32ri8 GR32:$src1, -128)>;
1382 def : Pat<(store (add (loadi32 addr:$dst), 128), addr:$dst),
1383 (SUB32mi8 addr:$dst, -128)>;
1385 def : Pat<(add GR64:$src1, 128),
1386 (SUB64ri8 GR64:$src1, -128)>;
1387 def : Pat<(store (add (loadi64 addr:$dst), 128), addr:$dst),
1388 (SUB64mi8 addr:$dst, -128)>;
1390 // The same trick applies for 32-bit immediate fields in 64-bit
1392 def : Pat<(add GR64:$src1, 0x0000000080000000),
1393 (SUB64ri32 GR64:$src1, 0xffffffff80000000)>;
1394 def : Pat<(store (add (loadi64 addr:$dst), 0x0000000080000000), addr:$dst),
1395 (SUB64mi32 addr:$dst, 0xffffffff80000000)>;
1397 // To avoid needing to materialize an immediate in a register, use a 32-bit and
1398 // with implicit zero-extension instead of a 64-bit and if the immediate has at
1399 // least 32 bits of leading zeros. If in addition the last 32 bits can be
1400 // represented with a sign extension of a 8 bit constant, use that.
1401 // This can also reduce instruction size by eliminating the need for the REX
1404 // AddedComplexity is needed to give priority over i64immSExt8 and i64immSExt32.
1405 let AddedComplexity = 1 in {
1406 def : Pat<(and GR64:$src, i64immZExt32SExt8:$imm),
1410 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1411 (i32 (GetLo8XForm imm:$imm))),
1414 def : Pat<(and GR64:$src, i64immZExt32:$imm),
1418 (EXTRACT_SUBREG GR64:$src, sub_32bit),
1419 (i32 (GetLo32XForm imm:$imm))),
1421 } // AddedComplexity = 1
1424 // AddedComplexity is needed due to the increased complexity on the
1425 // i64immZExt32SExt8 and i64immZExt32 patterns above. Applying this to all
1426 // the MOVZX patterns keeps thems together in DAGIsel tables.
1427 let AddedComplexity = 1 in {
1428 // r & (2^16-1) ==> movz
1429 def : Pat<(and GR32:$src1, 0xffff),
1430 (MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, sub_16bit))>;
1431 // r & (2^8-1) ==> movz
1432 def : Pat<(and GR32:$src1, 0xff),
1433 (MOVZX32rr8 (EXTRACT_SUBREG GR32:$src1, sub_8bit))>;
1434 // r & (2^8-1) ==> movz
1435 def : Pat<(and GR16:$src1, 0xff),
1436 (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)),
1439 // r & (2^32-1) ==> movz
1440 def : Pat<(and GR64:$src, 0x00000000FFFFFFFF),
1441 (SUBREG_TO_REG (i64 0),
1442 (MOV32rr (EXTRACT_SUBREG GR64:$src, sub_32bit)),
1444 // r & (2^16-1) ==> movz
1445 def : Pat<(and GR64:$src, 0xffff),
1446 (SUBREG_TO_REG (i64 0),
1447 (MOVZX32rr16 (i16 (EXTRACT_SUBREG GR64:$src, sub_16bit))),
1449 // r & (2^8-1) ==> movz
1450 def : Pat<(and GR64:$src, 0xff),
1451 (SUBREG_TO_REG (i64 0),
1452 (MOVZX32rr8 (i8 (EXTRACT_SUBREG GR64:$src, sub_8bit))),
1454 } // AddedComplexity = 1
1457 // sext_inreg patterns
1458 def : Pat<(sext_inreg GR32:$src, i16),
1459 (MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, sub_16bit))>;
1460 def : Pat<(sext_inreg GR32:$src, i8),
1461 (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>;
1463 def : Pat<(sext_inreg GR16:$src, i8),
1464 (EXTRACT_SUBREG (MOVSX32rr8 (EXTRACT_SUBREG GR16:$src, sub_8bit)),
1467 def : Pat<(sext_inreg GR64:$src, i32),
1468 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, sub_32bit))>;
1469 def : Pat<(sext_inreg GR64:$src, i16),
1470 (MOVSX64rr16 (EXTRACT_SUBREG GR64:$src, sub_16bit))>;
1471 def : Pat<(sext_inreg GR64:$src, i8),
1472 (MOVSX64rr8 (EXTRACT_SUBREG GR64:$src, sub_8bit))>;
1474 // sext, sext_load, zext, zext_load
1475 def: Pat<(i16 (sext GR8:$src)),
1476 (EXTRACT_SUBREG (MOVSX32rr8 GR8:$src), sub_16bit)>;
1477 def: Pat<(sextloadi16i8 addr:$src),
1478 (EXTRACT_SUBREG (MOVSX32rm8 addr:$src), sub_16bit)>;
1479 def: Pat<(i16 (zext GR8:$src)),
1480 (EXTRACT_SUBREG (MOVZX32rr8 GR8:$src), sub_16bit)>;
1481 def: Pat<(zextloadi16i8 addr:$src),
1482 (EXTRACT_SUBREG (MOVZX32rm8 addr:$src), sub_16bit)>;
1485 def : Pat<(i16 (trunc GR32:$src)),
1486 (EXTRACT_SUBREG GR32:$src, sub_16bit)>;
1487 def : Pat<(i8 (trunc GR32:$src)),
1488 (EXTRACT_SUBREG (i32 (COPY_TO_REGCLASS GR32:$src, GR32_ABCD)),
1490 Requires<[Not64BitMode]>;
1491 def : Pat<(i8 (trunc GR16:$src)),
1492 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)),
1494 Requires<[Not64BitMode]>;
1495 def : Pat<(i32 (trunc GR64:$src)),
1496 (EXTRACT_SUBREG GR64:$src, sub_32bit)>;
1497 def : Pat<(i16 (trunc GR64:$src)),
1498 (EXTRACT_SUBREG GR64:$src, sub_16bit)>;
1499 def : Pat<(i8 (trunc GR64:$src)),
1500 (EXTRACT_SUBREG GR64:$src, sub_8bit)>;
1501 def : Pat<(i8 (trunc GR32:$src)),
1502 (EXTRACT_SUBREG GR32:$src, sub_8bit)>,
1503 Requires<[In64BitMode]>;
1504 def : Pat<(i8 (trunc GR16:$src)),
1505 (EXTRACT_SUBREG GR16:$src, sub_8bit)>,
1506 Requires<[In64BitMode]>;
1508 // h-register tricks
1509 def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
1510 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>,
1511 Requires<[Not64BitMode]>;
1512 def : Pat<(i8 (trunc (srl_su (i32 (anyext GR16:$src)), (i8 8)))),
1513 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)>,
1514 Requires<[Not64BitMode]>;
1515 def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
1516 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi)>,
1517 Requires<[Not64BitMode]>;
1518 def : Pat<(srl GR16:$src, (i8 8)),
1520 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
1522 def : Pat<(i32 (zext (srl_su GR16:$src, (i8 8)))),
1523 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>;
1524 def : Pat<(i32 (anyext (srl_su GR16:$src, (i8 8)))),
1525 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>;
1526 def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
1527 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>;
1528 def : Pat<(srl (and_su GR32:$src, 0xff00), (i8 8)),
1529 (MOVZX32_NOREXrr8 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>;
1531 // h-register tricks.
1532 // For now, be conservative on x86-64 and use an h-register extract only if the
1533 // value is immediately zero-extended or stored, which are somewhat common
1534 // cases. This uses a bunch of code to prevent a register requiring a REX prefix
1535 // from being allocated in the same instruction as the h register, as there's
1536 // currently no way to describe this requirement to the register allocator.
1538 // h-register extract and zero-extend.
1539 def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
1543 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi)),
1545 def : Pat<(i64 (zext (srl_su GR16:$src, (i8 8)))),
1549 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
1551 def : Pat<(i64 (anyext (srl_su GR16:$src, (i8 8)))),
1555 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi)),
1558 // h-register extract and store.
1559 def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
1562 (EXTRACT_SUBREG GR64:$src, sub_8bit_hi))>;
1563 def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
1566 (EXTRACT_SUBREG GR32:$src, sub_8bit_hi))>,
1567 Requires<[In64BitMode]>;
1568 def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
1571 (EXTRACT_SUBREG GR16:$src, sub_8bit_hi))>,
1572 Requires<[In64BitMode]>;
1575 // (shl x, 1) ==> (add x, x)
1576 // Note that if x is undef (immediate or otherwise), we could theoretically
1577 // end up with the two uses of x getting different values, producing a result
1578 // where the least significant bit is not 0. However, the probability of this
1579 // happening is considered low enough that this is officially not a
1581 def : Pat<(shl GR8 :$src1, (i8 1)), (ADD8rr GR8 :$src1, GR8 :$src1)>;
1582 def : Pat<(shl GR16:$src1, (i8 1)), (ADD16rr GR16:$src1, GR16:$src1)>;
1583 def : Pat<(shl GR32:$src1, (i8 1)), (ADD32rr GR32:$src1, GR32:$src1)>;
1584 def : Pat<(shl GR64:$src1, (i8 1)), (ADD64rr GR64:$src1, GR64:$src1)>;
1586 // Helper imms to check if a mask doesn't change significant shift/rotate bits.
1587 def immShift8 : ImmLeaf<i8, [{
1588 return countTrailingOnes<uint64_t>(Imm) >= 3;
1590 def immShift16 : ImmLeaf<i8, [{
1591 return countTrailingOnes<uint64_t>(Imm) >= 4;
1593 def immShift32 : ImmLeaf<i8, [{
1594 return countTrailingOnes<uint64_t>(Imm) >= 5;
1596 def immShift64 : ImmLeaf<i8, [{
1597 return countTrailingOnes<uint64_t>(Imm) >= 6;
1600 // Shift amount is implicitly masked.
1601 multiclass MaskedShiftAmountPats<SDNode frag, string name> {
1602 // (shift x (and y, 31)) ==> (shift x, y)
1603 def : Pat<(frag GR8:$src1, (and CL, immShift32)),
1604 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1605 def : Pat<(frag GR16:$src1, (and CL, immShift32)),
1606 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1607 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1608 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1609 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift32)), addr:$dst),
1610 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1611 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift32)), addr:$dst),
1612 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1613 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1614 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1616 // (shift x (and y, 63)) ==> (shift x, y)
1617 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1618 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1619 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, immShift64)), addr:$dst),
1620 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1623 defm : MaskedShiftAmountPats<shl, "SHL">;
1624 defm : MaskedShiftAmountPats<srl, "SHR">;
1625 defm : MaskedShiftAmountPats<sra, "SAR">;
1627 // ROL/ROR instructions allow a stronger mask optimization than shift for 8- and
1628 // 16-bit. We can remove a mask of any (bitwidth - 1) on the rotation amount
1629 // because over-rotating produces the same result. This is noted in the Intel
1630 // docs with: "tempCOUNT <- (COUNT & COUNTMASK) MOD SIZE". Masking the rotation
1631 // amount could affect EFLAGS results, but that does not matter because we are
1632 // not tracking flags for these nodes.
1633 multiclass MaskedRotateAmountPats<SDNode frag, string name> {
1634 // (rot x (and y, BitWidth - 1)) ==> (rot x, y)
1635 def : Pat<(frag GR8:$src1, (and CL, immShift8)),
1636 (!cast<Instruction>(name # "8rCL") GR8:$src1)>;
1637 def : Pat<(frag GR16:$src1, (and CL, immShift16)),
1638 (!cast<Instruction>(name # "16rCL") GR16:$src1)>;
1639 def : Pat<(frag GR32:$src1, (and CL, immShift32)),
1640 (!cast<Instruction>(name # "32rCL") GR32:$src1)>;
1641 def : Pat<(store (frag (loadi8 addr:$dst), (and CL, immShift8)), addr:$dst),
1642 (!cast<Instruction>(name # "8mCL") addr:$dst)>;
1643 def : Pat<(store (frag (loadi16 addr:$dst), (and CL, immShift16)), addr:$dst),
1644 (!cast<Instruction>(name # "16mCL") addr:$dst)>;
1645 def : Pat<(store (frag (loadi32 addr:$dst), (and CL, immShift32)), addr:$dst),
1646 (!cast<Instruction>(name # "32mCL") addr:$dst)>;
1648 // (rot x (and y, 63)) ==> (rot x, y)
1649 def : Pat<(frag GR64:$src1, (and CL, immShift64)),
1650 (!cast<Instruction>(name # "64rCL") GR64:$src1)>;
1651 def : Pat<(store (frag (loadi64 addr:$dst), (and CL, immShift64)), addr:$dst),
1652 (!cast<Instruction>(name # "64mCL") addr:$dst)>;
1656 defm : MaskedRotateAmountPats<rotl, "ROL">;
1657 defm : MaskedRotateAmountPats<rotr, "ROR">;
1659 // Double shift amount is implicitly masked.
1660 multiclass MaskedDoubleShiftAmountPats<SDNode frag, string name> {
1661 // (shift x (and y, 31)) ==> (shift x, y)
1662 def : Pat<(frag GR16:$src1, GR16:$src2, (and CL, immShift32)),
1663 (!cast<Instruction>(name # "16rrCL") GR16:$src1, GR16:$src2)>;
1664 def : Pat<(frag GR32:$src1, GR32:$src2, (and CL, immShift32)),
1665 (!cast<Instruction>(name # "32rrCL") GR32:$src1, GR32:$src2)>;
1667 // (shift x (and y, 63)) ==> (shift x, y)
1668 def : Pat<(frag GR64:$src1, GR64:$src2, (and CL, immShift64)),
1669 (!cast<Instruction>(name # "64rrCL") GR64:$src1, GR64:$src2)>;
1672 defm : MaskedDoubleShiftAmountPats<X86shld, "SHLD">;
1673 defm : MaskedDoubleShiftAmountPats<X86shrd, "SHRD">;
1675 let Predicates = [HasBMI2] in {
1676 let AddedComplexity = 1 in {
1677 def : Pat<(sra GR32:$src1, (and GR8:$src2, immShift32)),
1678 (SARX32rr GR32:$src1,
1680 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1681 def : Pat<(sra GR64:$src1, (and GR8:$src2, immShift64)),
1682 (SARX64rr GR64:$src1,
1684 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1686 def : Pat<(srl GR32:$src1, (and GR8:$src2, immShift32)),
1687 (SHRX32rr GR32:$src1,
1689 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1690 def : Pat<(srl GR64:$src1, (and GR8:$src2, immShift64)),
1691 (SHRX64rr GR64:$src1,
1693 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1695 def : Pat<(shl GR32:$src1, (and GR8:$src2, immShift32)),
1696 (SHLX32rr GR32:$src1,
1698 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1699 def : Pat<(shl GR64:$src1, (and GR8:$src2, immShift64)),
1700 (SHLX64rr GR64:$src1,
1702 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1705 let AddedComplexity = -20 in {
1706 def : Pat<(sra (loadi32 addr:$src1), (and GR8:$src2, immShift32)),
1707 (SARX32rm addr:$src1,
1709 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1710 def : Pat<(sra (loadi64 addr:$src1), (and GR8:$src2, immShift64)),
1711 (SARX64rm addr:$src1,
1713 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1715 def : Pat<(srl (loadi32 addr:$src1), (and GR8:$src2, immShift32)),
1716 (SHRX32rm addr:$src1,
1718 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1719 def : Pat<(srl (loadi64 addr:$src1), (and GR8:$src2, immShift64)),
1720 (SHRX64rm addr:$src1,
1722 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1724 def : Pat<(shl (loadi32 addr:$src1), (and GR8:$src2, immShift32)),
1725 (SHLX32rm addr:$src1,
1727 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1728 def : Pat<(shl (loadi64 addr:$src1), (and GR8:$src2, immShift64)),
1729 (SHLX64rm addr:$src1,
1731 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
1735 // (anyext (setcc_carry)) -> (setcc_carry)
1736 def : Pat<(i16 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1738 def : Pat<(i32 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))),
1740 def : Pat<(i32 (anyext (i16 (X86setcc_c X86_COND_B, EFLAGS)))),
1743 //===----------------------------------------------------------------------===//
1744 // EFLAGS-defining Patterns
1745 //===----------------------------------------------------------------------===//
1748 def : Pat<(add GR8 :$src1, GR8 :$src2), (ADD8rr GR8 :$src1, GR8 :$src2)>;
1749 def : Pat<(add GR16:$src1, GR16:$src2), (ADD16rr GR16:$src1, GR16:$src2)>;
1750 def : Pat<(add GR32:$src1, GR32:$src2), (ADD32rr GR32:$src1, GR32:$src2)>;
1753 def : Pat<(add GR8:$src1, (loadi8 addr:$src2)),
1754 (ADD8rm GR8:$src1, addr:$src2)>;
1755 def : Pat<(add GR16:$src1, (loadi16 addr:$src2)),
1756 (ADD16rm GR16:$src1, addr:$src2)>;
1757 def : Pat<(add GR32:$src1, (loadi32 addr:$src2)),
1758 (ADD32rm GR32:$src1, addr:$src2)>;
1761 def : Pat<(add GR8 :$src1, imm:$src2), (ADD8ri GR8:$src1 , imm:$src2)>;
1762 def : Pat<(add GR16:$src1, imm:$src2), (ADD16ri GR16:$src1, imm:$src2)>;
1763 def : Pat<(add GR32:$src1, imm:$src2), (ADD32ri GR32:$src1, imm:$src2)>;
1764 def : Pat<(add GR16:$src1, i16immSExt8:$src2),
1765 (ADD16ri8 GR16:$src1, i16immSExt8:$src2)>;
1766 def : Pat<(add GR32:$src1, i32immSExt8:$src2),
1767 (ADD32ri8 GR32:$src1, i32immSExt8:$src2)>;
1770 def : Pat<(sub GR8 :$src1, GR8 :$src2), (SUB8rr GR8 :$src1, GR8 :$src2)>;
1771 def : Pat<(sub GR16:$src1, GR16:$src2), (SUB16rr GR16:$src1, GR16:$src2)>;
1772 def : Pat<(sub GR32:$src1, GR32:$src2), (SUB32rr GR32:$src1, GR32:$src2)>;
1775 def : Pat<(sub GR8:$src1, (loadi8 addr:$src2)),
1776 (SUB8rm GR8:$src1, addr:$src2)>;
1777 def : Pat<(sub GR16:$src1, (loadi16 addr:$src2)),
1778 (SUB16rm GR16:$src1, addr:$src2)>;
1779 def : Pat<(sub GR32:$src1, (loadi32 addr:$src2)),
1780 (SUB32rm GR32:$src1, addr:$src2)>;
1783 def : Pat<(sub GR8:$src1, imm:$src2),
1784 (SUB8ri GR8:$src1, imm:$src2)>;
1785 def : Pat<(sub GR16:$src1, imm:$src2),
1786 (SUB16ri GR16:$src1, imm:$src2)>;
1787 def : Pat<(sub GR32:$src1, imm:$src2),
1788 (SUB32ri GR32:$src1, imm:$src2)>;
1789 def : Pat<(sub GR16:$src1, i16immSExt8:$src2),
1790 (SUB16ri8 GR16:$src1, i16immSExt8:$src2)>;
1791 def : Pat<(sub GR32:$src1, i32immSExt8:$src2),
1792 (SUB32ri8 GR32:$src1, i32immSExt8:$src2)>;
1795 def : Pat<(X86sub_flag 0, GR8 :$src), (NEG8r GR8 :$src)>;
1796 def : Pat<(X86sub_flag 0, GR16:$src), (NEG16r GR16:$src)>;
1797 def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;
1798 def : Pat<(X86sub_flag 0, GR64:$src), (NEG64r GR64:$src)>;
1800 // sub reg, relocImm
1801 def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt8_su:$src2),
1802 (SUB64ri8 GR64:$src1, i64relocImmSExt8_su:$src2)>;
1803 def : Pat<(X86sub_flag GR64:$src1, i64relocImmSExt32_su:$src2),
1804 (SUB64ri32 GR64:$src1, i64relocImmSExt32_su:$src2)>;
1807 def : Pat<(mul GR16:$src1, GR16:$src2),
1808 (IMUL16rr GR16:$src1, GR16:$src2)>;
1809 def : Pat<(mul GR32:$src1, GR32:$src2),
1810 (IMUL32rr GR32:$src1, GR32:$src2)>;
1813 def : Pat<(mul GR16:$src1, (loadi16 addr:$src2)),
1814 (IMUL16rm GR16:$src1, addr:$src2)>;
1815 def : Pat<(mul GR32:$src1, (loadi32 addr:$src2)),
1816 (IMUL32rm GR32:$src1, addr:$src2)>;
1819 def : Pat<(mul GR16:$src1, imm:$src2),
1820 (IMUL16rri GR16:$src1, imm:$src2)>;
1821 def : Pat<(mul GR32:$src1, imm:$src2),
1822 (IMUL32rri GR32:$src1, imm:$src2)>;
1823 def : Pat<(mul GR16:$src1, i16immSExt8:$src2),
1824 (IMUL16rri8 GR16:$src1, i16immSExt8:$src2)>;
1825 def : Pat<(mul GR32:$src1, i32immSExt8:$src2),
1826 (IMUL32rri8 GR32:$src1, i32immSExt8:$src2)>;
1828 // reg = mul mem, imm
1829 def : Pat<(mul (loadi16 addr:$src1), imm:$src2),
1830 (IMUL16rmi addr:$src1, imm:$src2)>;
1831 def : Pat<(mul (loadi32 addr:$src1), imm:$src2),
1832 (IMUL32rmi addr:$src1, imm:$src2)>;
1833 def : Pat<(mul (loadi16 addr:$src1), i16immSExt8:$src2),
1834 (IMUL16rmi8 addr:$src1, i16immSExt8:$src2)>;
1835 def : Pat<(mul (loadi32 addr:$src1), i32immSExt8:$src2),
1836 (IMUL32rmi8 addr:$src1, i32immSExt8:$src2)>;
1838 // Patterns for nodes that do not produce flags, for instructions that do.
1841 def : Pat<(add GR64:$src1, GR64:$src2),
1842 (ADD64rr GR64:$src1, GR64:$src2)>;
1843 def : Pat<(add GR64:$src1, i64immSExt8:$src2),
1844 (ADD64ri8 GR64:$src1, i64immSExt8:$src2)>;
1845 def : Pat<(add GR64:$src1, i64immSExt32:$src2),
1846 (ADD64ri32 GR64:$src1, i64immSExt32:$src2)>;
1847 def : Pat<(add GR64:$src1, (loadi64 addr:$src2)),
1848 (ADD64rm GR64:$src1, addr:$src2)>;
1851 def : Pat<(sub GR64:$src1, GR64:$src2),
1852 (SUB64rr GR64:$src1, GR64:$src2)>;
1853 def : Pat<(sub GR64:$src1, (loadi64 addr:$src2)),
1854 (SUB64rm GR64:$src1, addr:$src2)>;
1855 def : Pat<(sub GR64:$src1, i64immSExt8:$src2),
1856 (SUB64ri8 GR64:$src1, i64immSExt8:$src2)>;
1857 def : Pat<(sub GR64:$src1, i64immSExt32:$src2),
1858 (SUB64ri32 GR64:$src1, i64immSExt32:$src2)>;
1861 def : Pat<(mul GR64:$src1, GR64:$src2),
1862 (IMUL64rr GR64:$src1, GR64:$src2)>;
1863 def : Pat<(mul GR64:$src1, (loadi64 addr:$src2)),
1864 (IMUL64rm GR64:$src1, addr:$src2)>;
1865 def : Pat<(mul GR64:$src1, i64immSExt8:$src2),
1866 (IMUL64rri8 GR64:$src1, i64immSExt8:$src2)>;
1867 def : Pat<(mul GR64:$src1, i64immSExt32:$src2),
1868 (IMUL64rri32 GR64:$src1, i64immSExt32:$src2)>;
1869 def : Pat<(mul (loadi64 addr:$src1), i64immSExt8:$src2),
1870 (IMUL64rmi8 addr:$src1, i64immSExt8:$src2)>;
1871 def : Pat<(mul (loadi64 addr:$src1), i64immSExt32:$src2),
1872 (IMUL64rmi32 addr:$src1, i64immSExt32:$src2)>;
1874 // Increment/Decrement reg.
1875 // Do not make INC/DEC if it is slow
1876 let Predicates = [UseIncDec] in {
1877 def : Pat<(add GR8:$src, 1), (INC8r GR8:$src)>;
1878 def : Pat<(add GR16:$src, 1), (INC16r GR16:$src)>;
1879 def : Pat<(add GR32:$src, 1), (INC32r GR32:$src)>;
1880 def : Pat<(add GR64:$src, 1), (INC64r GR64:$src)>;
1881 def : Pat<(add GR8:$src, -1), (DEC8r GR8:$src)>;
1882 def : Pat<(add GR16:$src, -1), (DEC16r GR16:$src)>;
1883 def : Pat<(add GR32:$src, -1), (DEC32r GR32:$src)>;
1884 def : Pat<(add GR64:$src, -1), (DEC64r GR64:$src)>;
1888 def : Pat<(or GR8 :$src1, GR8 :$src2), (OR8rr GR8 :$src1, GR8 :$src2)>;
1889 def : Pat<(or GR16:$src1, GR16:$src2), (OR16rr GR16:$src1, GR16:$src2)>;
1890 def : Pat<(or GR32:$src1, GR32:$src2), (OR32rr GR32:$src1, GR32:$src2)>;
1891 def : Pat<(or GR64:$src1, GR64:$src2), (OR64rr GR64:$src1, GR64:$src2)>;
1894 def : Pat<(or GR8:$src1, (loadi8 addr:$src2)),
1895 (OR8rm GR8:$src1, addr:$src2)>;
1896 def : Pat<(or GR16:$src1, (loadi16 addr:$src2)),
1897 (OR16rm GR16:$src1, addr:$src2)>;
1898 def : Pat<(or GR32:$src1, (loadi32 addr:$src2)),
1899 (OR32rm GR32:$src1, addr:$src2)>;
1900 def : Pat<(or GR64:$src1, (loadi64 addr:$src2)),
1901 (OR64rm GR64:$src1, addr:$src2)>;
1904 def : Pat<(or GR8:$src1 , imm:$src2), (OR8ri GR8 :$src1, imm:$src2)>;
1905 def : Pat<(or GR16:$src1, imm:$src2), (OR16ri GR16:$src1, imm:$src2)>;
1906 def : Pat<(or GR32:$src1, imm:$src2), (OR32ri GR32:$src1, imm:$src2)>;
1907 def : Pat<(or GR16:$src1, i16immSExt8:$src2),
1908 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1909 def : Pat<(or GR32:$src1, i32immSExt8:$src2),
1910 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1911 def : Pat<(or GR64:$src1, i64immSExt8:$src2),
1912 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1913 def : Pat<(or GR64:$src1, i64immSExt32:$src2),
1914 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1917 def : Pat<(xor GR8 :$src1, GR8 :$src2), (XOR8rr GR8 :$src1, GR8 :$src2)>;
1918 def : Pat<(xor GR16:$src1, GR16:$src2), (XOR16rr GR16:$src1, GR16:$src2)>;
1919 def : Pat<(xor GR32:$src1, GR32:$src2), (XOR32rr GR32:$src1, GR32:$src2)>;
1920 def : Pat<(xor GR64:$src1, GR64:$src2), (XOR64rr GR64:$src1, GR64:$src2)>;
1923 def : Pat<(xor GR8:$src1, (loadi8 addr:$src2)),
1924 (XOR8rm GR8:$src1, addr:$src2)>;
1925 def : Pat<(xor GR16:$src1, (loadi16 addr:$src2)),
1926 (XOR16rm GR16:$src1, addr:$src2)>;
1927 def : Pat<(xor GR32:$src1, (loadi32 addr:$src2)),
1928 (XOR32rm GR32:$src1, addr:$src2)>;
1929 def : Pat<(xor GR64:$src1, (loadi64 addr:$src2)),
1930 (XOR64rm GR64:$src1, addr:$src2)>;
1933 def : Pat<(xor GR8:$src1, imm:$src2),
1934 (XOR8ri GR8:$src1, imm:$src2)>;
1935 def : Pat<(xor GR16:$src1, imm:$src2),
1936 (XOR16ri GR16:$src1, imm:$src2)>;
1937 def : Pat<(xor GR32:$src1, imm:$src2),
1938 (XOR32ri GR32:$src1, imm:$src2)>;
1939 def : Pat<(xor GR16:$src1, i16immSExt8:$src2),
1940 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
1941 def : Pat<(xor GR32:$src1, i32immSExt8:$src2),
1942 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
1943 def : Pat<(xor GR64:$src1, i64immSExt8:$src2),
1944 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
1945 def : Pat<(xor GR64:$src1, i64immSExt32:$src2),
1946 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
1949 def : Pat<(and GR8 :$src1, GR8 :$src2), (AND8rr GR8 :$src1, GR8 :$src2)>;
1950 def : Pat<(and GR16:$src1, GR16:$src2), (AND16rr GR16:$src1, GR16:$src2)>;
1951 def : Pat<(and GR32:$src1, GR32:$src2), (AND32rr GR32:$src1, GR32:$src2)>;
1952 def : Pat<(and GR64:$src1, GR64:$src2), (AND64rr GR64:$src1, GR64:$src2)>;
1955 def : Pat<(and GR8:$src1, (loadi8 addr:$src2)),
1956 (AND8rm GR8:$src1, addr:$src2)>;
1957 def : Pat<(and GR16:$src1, (loadi16 addr:$src2)),
1958 (AND16rm GR16:$src1, addr:$src2)>;
1959 def : Pat<(and GR32:$src1, (loadi32 addr:$src2)),
1960 (AND32rm GR32:$src1, addr:$src2)>;
1961 def : Pat<(and GR64:$src1, (loadi64 addr:$src2)),
1962 (AND64rm GR64:$src1, addr:$src2)>;
1965 def : Pat<(and GR8:$src1, imm:$src2),
1966 (AND8ri GR8:$src1, imm:$src2)>;
1967 def : Pat<(and GR16:$src1, imm:$src2),
1968 (AND16ri GR16:$src1, imm:$src2)>;
1969 def : Pat<(and GR32:$src1, imm:$src2),
1970 (AND32ri GR32:$src1, imm:$src2)>;
1971 def : Pat<(and GR16:$src1, i16immSExt8:$src2),
1972 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
1973 def : Pat<(and GR32:$src1, i32immSExt8:$src2),
1974 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
1975 def : Pat<(and GR64:$src1, i64immSExt8:$src2),
1976 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
1977 def : Pat<(and GR64:$src1, i64immSExt32:$src2),
1978 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
1980 // Bit scan instruction patterns to match explicit zero-undef behavior.
1981 def : Pat<(cttz_zero_undef GR16:$src), (BSF16rr GR16:$src)>;
1982 def : Pat<(cttz_zero_undef GR32:$src), (BSF32rr GR32:$src)>;
1983 def : Pat<(cttz_zero_undef GR64:$src), (BSF64rr GR64:$src)>;
1984 def : Pat<(cttz_zero_undef (loadi16 addr:$src)), (BSF16rm addr:$src)>;
1985 def : Pat<(cttz_zero_undef (loadi32 addr:$src)), (BSF32rm addr:$src)>;
1986 def : Pat<(cttz_zero_undef (loadi64 addr:$src)), (BSF64rm addr:$src)>;
1988 // When HasMOVBE is enabled it is possible to get a non-legalized
1989 // register-register 16 bit bswap. This maps it to a ROL instruction.
1990 let Predicates = [HasMOVBE] in {
1991 def : Pat<(bswap GR16:$src), (ROL16ri GR16:$src, (i8 8))>;