1 //===- X86RegisterInfo.cpp - X86 Register Information -----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the X86 implementation of the TargetRegisterInfo class.
11 // This file is responsible for the frame pointer elimination optimization
14 //===----------------------------------------------------------------------===//
17 #include "X86RegisterInfo.h"
18 #include "X86InstrBuilder.h"
19 #include "X86MachineFunctionInfo.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetMachine.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Type.h"
25 #include "llvm/CodeGen/ValueTypes.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineLocation.h"
31 #include "llvm/CodeGen/MachineModuleInfo.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/Target/TargetFrameInfo.h"
35 #include "llvm/Target/TargetInstrInfo.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/ADT/BitVector.h"
39 #include "llvm/ADT/STLExtras.h"
40 #include "llvm/Support/ErrorHandling.h"
43 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
44 const TargetInstrInfo &tii)
45 : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
46 X86::ADJCALLSTACKDOWN64 :
47 X86::ADJCALLSTACKDOWN32,
48 tm.getSubtarget<X86Subtarget>().is64Bit() ?
49 X86::ADJCALLSTACKUP64 :
50 X86::ADJCALLSTACKUP32),
52 // Cache some information.
53 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
54 Is64Bit = Subtarget->is64Bit();
55 IsWin64 = Subtarget->isTargetWin64();
56 StackAlign = TM.getFrameInfo()->getStackAlignment();
69 /// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
70 /// specific numbering, used in debug info and exception tables.
71 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
72 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
73 unsigned Flavour = DWARFFlavour::X86_64;
75 if (!Subtarget->is64Bit()) {
76 if (Subtarget->isTargetDarwin()) {
78 Flavour = DWARFFlavour::X86_32_DarwinEH;
80 Flavour = DWARFFlavour::X86_32_Generic;
81 } else if (Subtarget->isTargetCygMing()) {
82 // Unsupported by now, just quick fallback
83 Flavour = DWARFFlavour::X86_32_Generic;
85 Flavour = DWARFFlavour::X86_32_Generic;
89 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
92 /// getX86RegNum - This function maps LLVM register identifiers to their X86
93 /// specific numbering, which is used in various places encoding instructions.
94 unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) {
96 case X86::RAX: case X86::EAX: case X86::AX: case X86::AL: return N86::EAX;
97 case X86::RCX: case X86::ECX: case X86::CX: case X86::CL: return N86::ECX;
98 case X86::RDX: case X86::EDX: case X86::DX: case X86::DL: return N86::EDX;
99 case X86::RBX: case X86::EBX: case X86::BX: case X86::BL: return N86::EBX;
100 case X86::RSP: case X86::ESP: case X86::SP: case X86::SPL: case X86::AH:
102 case X86::RBP: case X86::EBP: case X86::BP: case X86::BPL: case X86::CH:
104 case X86::RSI: case X86::ESI: case X86::SI: case X86::SIL: case X86::DH:
106 case X86::RDI: case X86::EDI: case X86::DI: case X86::DIL: case X86::BH:
109 case X86::R8: case X86::R8D: case X86::R8W: case X86::R8B:
111 case X86::R9: case X86::R9D: case X86::R9W: case X86::R9B:
113 case X86::R10: case X86::R10D: case X86::R10W: case X86::R10B:
115 case X86::R11: case X86::R11D: case X86::R11W: case X86::R11B:
117 case X86::R12: case X86::R12D: case X86::R12W: case X86::R12B:
119 case X86::R13: case X86::R13D: case X86::R13W: case X86::R13B:
121 case X86::R14: case X86::R14D: case X86::R14W: case X86::R14B:
123 case X86::R15: case X86::R15D: case X86::R15W: case X86::R15B:
126 case X86::ST0: case X86::ST1: case X86::ST2: case X86::ST3:
127 case X86::ST4: case X86::ST5: case X86::ST6: case X86::ST7:
128 return RegNo-X86::ST0;
130 case X86::XMM0: case X86::XMM8: case X86::MM0:
132 case X86::XMM1: case X86::XMM9: case X86::MM1:
134 case X86::XMM2: case X86::XMM10: case X86::MM2:
136 case X86::XMM3: case X86::XMM11: case X86::MM3:
138 case X86::XMM4: case X86::XMM12: case X86::MM4:
140 case X86::XMM5: case X86::XMM13: case X86::MM5:
142 case X86::XMM6: case X86::XMM14: case X86::MM6:
144 case X86::XMM7: case X86::XMM15: case X86::MM7:
189 assert(isVirtualRegister(RegNo) && "Unknown physical register!");
190 llvm_unreachable("Register allocator hasn't allocated reg correctly yet!");
195 const TargetRegisterClass *
196 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
197 const TargetRegisterClass *B,
198 unsigned SubIdx) const {
202 if (B == &X86::GR8RegClass) {
203 if (A->getSize() == 2 || A->getSize() == 4 || A->getSize() == 8)
205 } else if (B == &X86::GR8_ABCD_LRegClass || B == &X86::GR8_ABCD_HRegClass) {
206 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
207 A == &X86::GR64_NOREXRegClass ||
208 A == &X86::GR64_NOSPRegClass ||
209 A == &X86::GR64_NOREX_NOSPRegClass)
210 return &X86::GR64_ABCDRegClass;
211 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
212 A == &X86::GR32_NOREXRegClass ||
213 A == &X86::GR32_NOSPRegClass)
214 return &X86::GR32_ABCDRegClass;
215 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
216 A == &X86::GR16_NOREXRegClass)
217 return &X86::GR16_ABCDRegClass;
218 } else if (B == &X86::GR8_NOREXRegClass) {
219 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
220 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
221 return &X86::GR64_NOREXRegClass;
222 else if (A == &X86::GR64_ABCDRegClass)
223 return &X86::GR64_ABCDRegClass;
224 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
225 A == &X86::GR32_NOSPRegClass)
226 return &X86::GR32_NOREXRegClass;
227 else if (A == &X86::GR32_ABCDRegClass)
228 return &X86::GR32_ABCDRegClass;
229 else if (A == &X86::GR16RegClass || A == &X86::GR16_NOREXRegClass)
230 return &X86::GR16_NOREXRegClass;
231 else if (A == &X86::GR16_ABCDRegClass)
232 return &X86::GR16_ABCDRegClass;
235 case X86::sub_8bit_hi:
236 if (B == &X86::GR8_ABCD_HRegClass) {
237 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
238 A == &X86::GR64_NOREXRegClass ||
239 A == &X86::GR64_NOSPRegClass ||
240 A == &X86::GR64_NOREX_NOSPRegClass)
241 return &X86::GR64_ABCDRegClass;
242 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
243 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
244 return &X86::GR32_ABCDRegClass;
245 else if (A == &X86::GR16RegClass || A == &X86::GR16_ABCDRegClass ||
246 A == &X86::GR16_NOREXRegClass)
247 return &X86::GR16_ABCDRegClass;
251 if (B == &X86::GR16RegClass) {
252 if (A->getSize() == 4 || A->getSize() == 8)
254 } else if (B == &X86::GR16_ABCDRegClass) {
255 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
256 A == &X86::GR64_NOREXRegClass ||
257 A == &X86::GR64_NOSPRegClass ||
258 A == &X86::GR64_NOREX_NOSPRegClass)
259 return &X86::GR64_ABCDRegClass;
260 else if (A == &X86::GR32RegClass || A == &X86::GR32_ABCDRegClass ||
261 A == &X86::GR32_NOREXRegClass || A == &X86::GR32_NOSPRegClass)
262 return &X86::GR32_ABCDRegClass;
263 } else if (B == &X86::GR16_NOREXRegClass) {
264 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
265 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
266 return &X86::GR64_NOREXRegClass;
267 else if (A == &X86::GR64_ABCDRegClass)
268 return &X86::GR64_ABCDRegClass;
269 else if (A == &X86::GR32RegClass || A == &X86::GR32_NOREXRegClass ||
270 A == &X86::GR32_NOSPRegClass)
271 return &X86::GR32_NOREXRegClass;
272 else if (A == &X86::GR32_ABCDRegClass)
273 return &X86::GR64_ABCDRegClass;
277 if (B == &X86::GR32RegClass || B == &X86::GR32_NOSPRegClass) {
278 if (A->getSize() == 8)
280 } else if (B == &X86::GR32_ABCDRegClass) {
281 if (A == &X86::GR64RegClass || A == &X86::GR64_ABCDRegClass ||
282 A == &X86::GR64_NOREXRegClass ||
283 A == &X86::GR64_NOSPRegClass ||
284 A == &X86::GR64_NOREX_NOSPRegClass)
285 return &X86::GR64_ABCDRegClass;
286 } else if (B == &X86::GR32_NOREXRegClass) {
287 if (A == &X86::GR64RegClass || A == &X86::GR64_NOREXRegClass ||
288 A == &X86::GR64_NOSPRegClass || A == &X86::GR64_NOREX_NOSPRegClass)
289 return &X86::GR64_NOREXRegClass;
290 else if (A == &X86::GR64_ABCDRegClass)
291 return &X86::GR64_ABCDRegClass;
295 if (B == &X86::FR32RegClass)
299 if (B == &X86::FR64RegClass)
303 if (B == &X86::VR128RegClass)
310 const TargetRegisterClass *
311 X86RegisterInfo::getPointerRegClass(unsigned Kind) const {
313 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
314 case 0: // Normal GPRs.
315 if (TM.getSubtarget<X86Subtarget>().is64Bit())
316 return &X86::GR64RegClass;
317 return &X86::GR32RegClass;
318 case 1: // Normal GRPs except the stack pointer (for encoding reasons).
319 if (TM.getSubtarget<X86Subtarget>().is64Bit())
320 return &X86::GR64_NOSPRegClass;
321 return &X86::GR32_NOSPRegClass;
325 const TargetRegisterClass *
326 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
327 if (RC == &X86::CCRRegClass) {
329 return &X86::GR64RegClass;
331 return &X86::GR32RegClass;
337 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
338 bool callsEHReturn = false;
339 bool ghcCall = false;
342 callsEHReturn = MF->getMMI().callsEHReturn();
343 const Function *F = MF->getFunction();
344 ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
347 static const unsigned GhcCalleeSavedRegs[] = {
351 static const unsigned CalleeSavedRegs32Bit[] = {
352 X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
355 static const unsigned CalleeSavedRegs32EHRet[] = {
356 X86::EAX, X86::EDX, X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0
359 static const unsigned CalleeSavedRegs64Bit[] = {
360 X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0
363 static const unsigned CalleeSavedRegs64EHRet[] = {
364 X86::RAX, X86::RDX, X86::RBX, X86::R12,
365 X86::R13, X86::R14, X86::R15, X86::RBP, 0
368 static const unsigned CalleeSavedRegsWin64[] = {
369 X86::RBX, X86::RBP, X86::RDI, X86::RSI,
370 X86::R12, X86::R13, X86::R14, X86::R15,
371 X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9,
372 X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13,
373 X86::XMM14, X86::XMM15, 0
377 return GhcCalleeSavedRegs;
378 } else if (Is64Bit) {
380 return CalleeSavedRegsWin64;
382 return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit);
384 return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit);
388 const TargetRegisterClass* const*
389 X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
390 bool callsEHReturn = false;
392 callsEHReturn = MF->getMMI().callsEHReturn();
394 static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = {
395 &X86::GR32RegClass, &X86::GR32RegClass,
396 &X86::GR32RegClass, &X86::GR32RegClass, 0
398 static const TargetRegisterClass * const CalleeSavedRegClasses32EHRet[] = {
399 &X86::GR32RegClass, &X86::GR32RegClass,
400 &X86::GR32RegClass, &X86::GR32RegClass,
401 &X86::GR32RegClass, &X86::GR32RegClass, 0
403 static const TargetRegisterClass * const CalleeSavedRegClasses64Bit[] = {
404 &X86::GR64RegClass, &X86::GR64RegClass,
405 &X86::GR64RegClass, &X86::GR64RegClass,
406 &X86::GR64RegClass, &X86::GR64RegClass, 0
408 static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = {
409 &X86::GR64RegClass, &X86::GR64RegClass,
410 &X86::GR64RegClass, &X86::GR64RegClass,
411 &X86::GR64RegClass, &X86::GR64RegClass,
412 &X86::GR64RegClass, &X86::GR64RegClass, 0
414 static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = {
415 &X86::GR64RegClass, &X86::GR64RegClass,
416 &X86::GR64RegClass, &X86::GR64RegClass,
417 &X86::GR64RegClass, &X86::GR64RegClass,
418 &X86::GR64RegClass, &X86::GR64RegClass,
419 &X86::VR128RegClass, &X86::VR128RegClass,
420 &X86::VR128RegClass, &X86::VR128RegClass,
421 &X86::VR128RegClass, &X86::VR128RegClass,
422 &X86::VR128RegClass, &X86::VR128RegClass,
423 &X86::VR128RegClass, &X86::VR128RegClass, 0
428 return CalleeSavedRegClassesWin64;
430 return (callsEHReturn ?
431 CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit);
433 return (callsEHReturn ?
434 CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit);
438 BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
439 BitVector Reserved(getNumRegs());
440 // Set the stack-pointer register and its aliases as reserved.
441 Reserved.set(X86::RSP);
442 Reserved.set(X86::ESP);
443 Reserved.set(X86::SP);
444 Reserved.set(X86::SPL);
446 // Set the instruction pointer register and its aliases as reserved.
447 Reserved.set(X86::RIP);
448 Reserved.set(X86::EIP);
449 Reserved.set(X86::IP);
451 // Set the frame-pointer register and its aliases as reserved if needed.
453 Reserved.set(X86::RBP);
454 Reserved.set(X86::EBP);
455 Reserved.set(X86::BP);
456 Reserved.set(X86::BPL);
459 // Mark the x87 stack registers as reserved, since they don't behave normally
460 // with respect to liveness. We don't fully model the effects of x87 stack
461 // pushes and pops after stackification.
462 Reserved.set(X86::ST0);
463 Reserved.set(X86::ST1);
464 Reserved.set(X86::ST2);
465 Reserved.set(X86::ST3);
466 Reserved.set(X86::ST4);
467 Reserved.set(X86::ST5);
468 Reserved.set(X86::ST6);
469 Reserved.set(X86::ST7);
473 //===----------------------------------------------------------------------===//
474 // Stack Frame Processing methods
475 //===----------------------------------------------------------------------===//
477 /// hasFP - Return true if the specified function should have a dedicated frame
478 /// pointer register. This is true if the function has variable sized allocas
479 /// or if frame pointer elimination is disabled.
480 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
481 const MachineFrameInfo *MFI = MF.getFrameInfo();
482 const MachineModuleInfo &MMI = MF.getMMI();
484 return (DisableFramePointerElim(MF) ||
485 needsStackRealignment(MF) ||
486 MFI->hasVarSizedObjects() ||
487 MFI->isFrameAddressTaken() ||
488 MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||
489 MMI.callsUnwindInit());
492 bool X86RegisterInfo::canRealignStack(const MachineFunction &MF) const {
493 const MachineFrameInfo *MFI = MF.getFrameInfo();
494 return (RealignStack &&
495 !MFI->hasVarSizedObjects());
498 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
499 const MachineFrameInfo *MFI = MF.getFrameInfo();
500 const Function *F = MF.getFunction();
501 bool requiresRealignment =
502 RealignStack && ((MFI->getMaxAlignment() > StackAlign) ||
503 F->hasFnAttr(Attribute::StackAlignment));
505 // FIXME: Currently we don't support stack realignment for functions with
506 // variable-sized allocas.
507 // FIXME: Temporary disable the error - it seems to be too conservative.
508 if (0 && requiresRealignment && MFI->hasVarSizedObjects())
510 "Stack realignment in presense of dynamic allocas is not supported");
512 return (requiresRealignment && !MFI->hasVarSizedObjects());
515 bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
516 return !MF.getFrameInfo()->hasVarSizedObjects();
519 bool X86RegisterInfo::hasReservedSpillSlot(MachineFunction &MF, unsigned Reg,
520 int &FrameIdx) const {
521 if (Reg == FramePtr && hasFP(MF)) {
522 FrameIdx = MF.getFrameInfo()->getObjectIndexBegin();
529 X86RegisterInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const {
530 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
531 const MachineFrameInfo *MFI = MF.getFrameInfo();
532 int Offset = MFI->getObjectOffset(FI) - TFI.getOffsetOfLocalArea();
533 uint64_t StackSize = MFI->getStackSize();
535 if (needsStackRealignment(MF)) {
537 // Skip the saved EBP.
540 unsigned Align = MFI->getObjectAlignment(FI);
541 assert((-(Offset + StackSize)) % Align == 0);
543 return Offset + StackSize;
545 // FIXME: Support tail calls
548 return Offset + StackSize;
550 // Skip the saved EBP.
553 // Skip the RETADDR move area
554 const X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
555 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
556 if (TailCallReturnAddrDelta < 0)
557 Offset -= TailCallReturnAddrDelta;
563 static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) {
566 return X86::SUB64ri8;
567 return X86::SUB64ri32;
570 return X86::SUB32ri8;
575 static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) {
578 return X86::ADD64ri8;
579 return X86::ADD64ri32;
582 return X86::ADD32ri8;
587 void X86RegisterInfo::
588 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
589 MachineBasicBlock::iterator I) const {
590 if (!hasReservedCallFrame(MF)) {
591 // If the stack pointer can be changed after prologue, turn the
592 // adjcallstackup instruction into a 'sub ESP, <amt>' and the
593 // adjcallstackdown instruction into 'add ESP, <amt>'
594 // TODO: consider using push / pop instead of sub + store / add
595 MachineInstr *Old = I;
596 uint64_t Amount = Old->getOperand(0).getImm();
598 // We need to keep the stack aligned properly. To do this, we round the
599 // amount of space needed for the outgoing arguments up to the next
600 // alignment boundary.
601 Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
603 MachineInstr *New = 0;
604 if (Old->getOpcode() == getCallFrameSetupOpcode()) {
605 New = BuildMI(MF, Old->getDebugLoc(),
606 TII.get(getSUBriOpcode(Is64Bit, Amount)),
611 assert(Old->getOpcode() == getCallFrameDestroyOpcode());
613 // Factor out the amount the callee already popped.
614 uint64_t CalleeAmt = Old->getOperand(1).getImm();
618 unsigned Opc = getADDriOpcode(Is64Bit, Amount);
619 New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr)
626 // The EFLAGS implicit def is dead.
627 New->getOperand(3).setIsDead();
629 // Replace the pseudo instruction with a new instruction.
633 } else if (I->getOpcode() == getCallFrameDestroyOpcode()) {
634 // If we are performing frame pointer elimination and if the callee pops
635 // something off the stack pointer, add it back. We do this until we have
636 // more advanced stack pointer tracking ability.
637 if (uint64_t CalleeAmt = I->getOperand(1).getImm()) {
638 unsigned Opc = getSUBriOpcode(Is64Bit, CalleeAmt);
639 MachineInstr *Old = I;
641 BuildMI(MF, Old->getDebugLoc(), TII.get(Opc),
646 // The EFLAGS implicit def is dead.
647 New->getOperand(3).setIsDead();
656 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
657 int SPAdj, FrameIndexValue *Value,
658 RegScavenger *RS) const{
659 assert(SPAdj == 0 && "Unexpected");
662 MachineInstr &MI = *II;
663 MachineFunction &MF = *MI.getParent()->getParent();
665 while (!MI.getOperand(i).isFI()) {
667 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
670 int FrameIndex = MI.getOperand(i).getIndex();
673 unsigned Opc = MI.getOpcode();
674 bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm;
675 if (needsStackRealignment(MF))
676 BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr);
680 BasePtr = (hasFP(MF) ? FramePtr : StackPtr);
682 // This must be part of a four operand memory reference. Replace the
683 // FrameIndex with base register with EBP. Add an offset to the offset.
684 MI.getOperand(i).ChangeToRegister(BasePtr, false);
686 // Now add the frame object offset to the offset from EBP.
689 // Tail call jmp happens after FP is popped.
690 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
691 const MachineFrameInfo *MFI = MF.getFrameInfo();
692 FIOffset = MFI->getObjectOffset(FrameIndex) - TFI.getOffsetOfLocalArea();
694 FIOffset = getFrameIndexOffset(MF, FrameIndex);
696 if (MI.getOperand(i+3).isImm()) {
697 // Offset is a 32-bit integer.
698 int Offset = FIOffset + (int)(MI.getOperand(i + 3).getImm());
699 MI.getOperand(i + 3).ChangeToImmediate(Offset);
701 // Offset is symbolic. This is extremely rare.
702 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
703 MI.getOperand(i+3).setOffset(Offset);
709 X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
710 RegScavenger *RS) const {
711 MachineFrameInfo *MFI = MF.getFrameInfo();
713 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
714 int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
716 if (TailCallReturnAddrDelta < 0) {
717 // create RETURNADDR area
726 MFI->CreateFixedObject(-TailCallReturnAddrDelta,
727 (-1U*SlotSize)+TailCallReturnAddrDelta,
732 assert((TailCallReturnAddrDelta <= 0) &&
733 "The Delta should always be zero or negative");
734 const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo();
736 // Create a frame entry for the EBP register that must be saved.
737 int FrameIdx = MFI->CreateFixedObject(SlotSize,
739 TFI.getOffsetOfLocalArea() +
740 TailCallReturnAddrDelta,
742 assert(FrameIdx == MFI->getObjectIndexBegin() &&
743 "Slot for EBP register must be last in order to be found!");
748 /// emitSPUpdate - Emit a series of instructions to increment / decrement the
749 /// stack pointer by a constant value.
751 void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
752 unsigned StackPtr, int64_t NumBytes, bool Is64Bit,
753 const TargetInstrInfo &TII) {
754 bool isSub = NumBytes < 0;
755 uint64_t Offset = isSub ? -NumBytes : NumBytes;
756 unsigned Opc = isSub ?
757 getSUBriOpcode(Is64Bit, Offset) :
758 getADDriOpcode(Is64Bit, Offset);
759 uint64_t Chunk = (1LL << 31) - 1;
760 DebugLoc DL = MBB.findDebugLoc(MBBI);
763 uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset;
765 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
768 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
773 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator.
775 void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
776 unsigned StackPtr, uint64_t *NumBytes = NULL) {
777 if (MBBI == MBB.begin()) return;
779 MachineBasicBlock::iterator PI = prior(MBBI);
780 unsigned Opc = PI->getOpcode();
781 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
782 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
783 PI->getOperand(0).getReg() == StackPtr) {
785 *NumBytes += PI->getOperand(2).getImm();
787 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
788 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
789 PI->getOperand(0).getReg() == StackPtr) {
791 *NumBytes -= PI->getOperand(2).getImm();
796 /// mergeSPUpdatesUp - Merge two stack-manipulating instructions lower iterator.
798 void mergeSPUpdatesDown(MachineBasicBlock &MBB,
799 MachineBasicBlock::iterator &MBBI,
800 unsigned StackPtr, uint64_t *NumBytes = NULL) {
801 // FIXME: THIS ISN'T RUN!!!
804 if (MBBI == MBB.end()) return;
806 MachineBasicBlock::iterator NI = llvm::next(MBBI);
807 if (NI == MBB.end()) return;
809 unsigned Opc = NI->getOpcode();
810 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
811 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
812 NI->getOperand(0).getReg() == StackPtr) {
814 *NumBytes -= NI->getOperand(2).getImm();
817 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
818 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
819 NI->getOperand(0).getReg() == StackPtr) {
821 *NumBytes += NI->getOperand(2).getImm();
827 /// mergeSPUpdates - Checks the instruction before/after the passed
828 /// instruction. If it is an ADD/SUB instruction it is deleted argument and the
829 /// stack adjustment is returned as a positive value for ADD and a negative for
831 static int mergeSPUpdates(MachineBasicBlock &MBB,
832 MachineBasicBlock::iterator &MBBI,
834 bool doMergeWithPrevious) {
835 if ((doMergeWithPrevious && MBBI == MBB.begin()) ||
836 (!doMergeWithPrevious && MBBI == MBB.end()))
839 MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI;
840 MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI);
841 unsigned Opc = PI->getOpcode();
844 if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 ||
845 Opc == X86::ADD32ri || Opc == X86::ADD32ri8) &&
846 PI->getOperand(0).getReg() == StackPtr){
847 Offset += PI->getOperand(2).getImm();
849 if (!doMergeWithPrevious) MBBI = NI;
850 } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 ||
851 Opc == X86::SUB32ri || Opc == X86::SUB32ri8) &&
852 PI->getOperand(0).getReg() == StackPtr) {
853 Offset -= PI->getOperand(2).getImm();
855 if (!doMergeWithPrevious) MBBI = NI;
861 void X86RegisterInfo::emitCalleeSavedFrameMoves(MachineFunction &MF,
863 unsigned FramePtr) const {
864 MachineFrameInfo *MFI = MF.getFrameInfo();
865 MachineModuleInfo &MMI = MF.getMMI();
867 // Add callee saved registers to move list.
868 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
869 if (CSI.empty()) return;
871 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
872 const TargetData *TD = MF.getTarget().getTargetData();
873 bool HasFP = hasFP(MF);
875 // Calculate amount of bytes used for return address storing.
877 (MF.getTarget().getFrameInfo()->getStackGrowthDirection() ==
878 TargetFrameInfo::StackGrowsUp ?
879 TD->getPointerSize() : -TD->getPointerSize());
881 // FIXME: This is dirty hack. The code itself is pretty mess right now.
882 // It should be rewritten from scratch and generalized sometimes.
884 // Determine maximum offset (minumum due to stack growth).
885 int64_t MaxOffset = 0;
886 for (std::vector<CalleeSavedInfo>::const_iterator
887 I = CSI.begin(), E = CSI.end(); I != E; ++I)
888 MaxOffset = std::min(MaxOffset,
889 MFI->getObjectOffset(I->getFrameIdx()));
891 // Calculate offsets.
892 int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth;
893 for (std::vector<CalleeSavedInfo>::const_iterator
894 I = CSI.begin(), E = CSI.end(); I != E; ++I) {
895 int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
896 unsigned Reg = I->getReg();
897 Offset = MaxOffset - Offset + saveAreaOffset;
899 // Don't output a new machine move if we're re-saving the frame
900 // pointer. This happens when the PrologEpilogInserter has inserted an extra
901 // "PUSH" of the frame pointer -- the "emitPrologue" method automatically
902 // generates one when frame pointers are used. If we generate a "machine
903 // move" for this extra "PUSH", the linker will lose track of the fact that
904 // the frame pointer should have the value of the first "PUSH" when it's
907 // FIXME: This looks inelegant. It's possibly correct, but it's covering up
908 // another bug. I.e., one where we generate a prolog like this:
916 // The immediate re-push of EBP is unnecessary. At the least, it's an
917 // optimization bug. EBP can be used as a scratch register in certain
918 // cases, but probably not when we have a frame pointer.
919 if (HasFP && FramePtr == Reg)
922 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
923 MachineLocation CSSrc(Reg);
924 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
928 /// emitPrologue - Push callee-saved registers onto the stack, which
929 /// automatically adjust the stack pointer. Adjust the stack pointer to allocate
930 /// space for local variables. Also emit labels used by the exception handler to
931 /// generate the exception handling frames.
932 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
933 MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB.
934 MachineBasicBlock::iterator MBBI = MBB.begin();
935 MachineFrameInfo *MFI = MF.getFrameInfo();
936 const Function *Fn = MF.getFunction();
937 const X86Subtarget *Subtarget = &MF.getTarget().getSubtarget<X86Subtarget>();
938 MachineModuleInfo &MMI = MF.getMMI();
939 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
940 bool needsFrameMoves = MMI.hasDebugInfo() ||
941 !Fn->doesNotThrow() || UnwindTablesMandatory;
942 uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment.
943 uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate.
944 bool HasFP = hasFP(MF);
947 // Add RETADDR move area to callee saved frame size.
948 int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta();
949 if (TailCallReturnAddrDelta < 0)
950 X86FI->setCalleeSavedFrameSize(
951 X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta);
953 // If this is x86-64 and the Red Zone is not disabled, if we are a leaf
954 // function, and use up to 128 bytes of stack space, don't have a frame
955 // pointer, calls, or dynamic alloca then we do not need to adjust the
956 // stack pointer (we fit in the Red Zone).
957 if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) &&
958 !needsStackRealignment(MF) &&
959 !MFI->hasVarSizedObjects() && // No dynamic alloca.
960 !MFI->adjustsStack() && // No calls.
961 !Subtarget->isTargetWin64()) { // Win64 has no Red Zone
962 uint64_t MinSize = X86FI->getCalleeSavedFrameSize();
963 if (HasFP) MinSize += SlotSize;
964 StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0);
965 MFI->setStackSize(StackSize);
966 } else if (Subtarget->isTargetWin64()) {
967 // We need to always allocate 32 bytes as register spill area.
968 // FIXME: We might reuse these 32 bytes for leaf functions.
970 MFI->setStackSize(StackSize);
973 // Insert stack pointer adjustment for later moving of return addr. Only
974 // applies to tail call optimized functions where the callee argument stack
975 // size is bigger than the callers.
976 if (TailCallReturnAddrDelta < 0) {
978 BuildMI(MBB, MBBI, DL,
979 TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)),
982 .addImm(-TailCallReturnAddrDelta);
983 MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead.
986 // Mapping for machine moves:
988 // DST: VirtualFP AND
989 // SRC: VirtualFP => DW_CFA_def_cfa_offset
990 // ELSE => DW_CFA_def_cfa
992 // SRC: VirtualFP AND
993 // DST: Register => DW_CFA_def_cfa_register
996 // OFFSET < 0 => DW_CFA_offset_extended_sf
997 // REG < 64 => DW_CFA_offset + Reg
998 // ELSE => DW_CFA_offset_extended
1000 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
1001 const TargetData *TD = MF.getTarget().getTargetData();
1002 uint64_t NumBytes = 0;
1003 int stackGrowth = -TD->getPointerSize();
1006 // Calculate required stack adjustment.
1007 uint64_t FrameSize = StackSize - SlotSize;
1008 if (needsStackRealignment(MF))
1009 FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign;
1011 NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();
1013 // Get the offset of the stack slot for the EBP register, which is
1014 // guaranteed to be the last slot by processFunctionBeforeFrameFinalized.
1015 // Update the frame offset adjustment.
1016 MFI->setOffsetAdjustment(-NumBytes);
1018 // Save EBP/RBP into the appropriate stack slot.
1019 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r))
1020 .addReg(FramePtr, RegState::Kill);
1022 if (needsFrameMoves) {
1023 // Mark the place where EBP/RBP was saved.
1024 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
1025 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
1027 // Define the current CFA rule to use the provided offset.
1029 MachineLocation SPDst(MachineLocation::VirtualFP);
1030 MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth);
1031 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
1033 // FIXME: Verify & implement for FP
1034 MachineLocation SPDst(StackPtr);
1035 MachineLocation SPSrc(StackPtr, stackGrowth);
1036 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
1039 // Change the rule for the FramePtr to be an "offset" rule.
1040 MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth);
1041 MachineLocation FPSrc(FramePtr);
1042 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1045 // Update EBP with the new base value...
1046 BuildMI(MBB, MBBI, DL,
1047 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr)
1050 if (needsFrameMoves) {
1051 // Mark effective beginning of when frame pointer becomes valid.
1052 MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol();
1053 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(FrameLabel);
1055 // Define the current CFA to use the EBP/RBP register.
1056 MachineLocation FPDst(FramePtr);
1057 MachineLocation FPSrc(MachineLocation::VirtualFP);
1058 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
1061 // Mark the FramePtr as live-in in every block except the entry.
1062 for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
1064 I->addLiveIn(FramePtr);
1067 if (needsStackRealignment(MF)) {
1069 BuildMI(MBB, MBBI, DL,
1070 TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri),
1071 StackPtr).addReg(StackPtr).addImm(-MaxAlign);
1073 // The EFLAGS implicit def is dead.
1074 MI->getOperand(3).setIsDead();
1077 NumBytes = StackSize - X86FI->getCalleeSavedFrameSize();
1080 // Skip the callee-saved push instructions.
1081 bool PushedRegs = false;
1082 int StackOffset = 2 * stackGrowth;
1084 while (MBBI != MBB.end() &&
1085 (MBBI->getOpcode() == X86::PUSH32r ||
1086 MBBI->getOpcode() == X86::PUSH64r)) {
1090 if (!HasFP && needsFrameMoves) {
1091 // Mark callee-saved push instruction.
1092 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1093 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
1095 // Define the current CFA rule to use the provided offset.
1096 unsigned Ptr = StackSize ?
1097 MachineLocation::VirtualFP : StackPtr;
1098 MachineLocation SPDst(Ptr);
1099 MachineLocation SPSrc(Ptr, StackOffset);
1100 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1101 StackOffset += stackGrowth;
1105 DL = MBB.findDebugLoc(MBBI);
1107 // Adjust stack pointer: ESP -= numbytes.
1108 if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) {
1109 // Check, whether EAX is livein for this function.
1110 bool isEAXAlive = false;
1111 for (MachineRegisterInfo::livein_iterator
1112 II = MF.getRegInfo().livein_begin(),
1113 EE = MF.getRegInfo().livein_end(); (II != EE) && !isEAXAlive; ++II) {
1114 unsigned Reg = II->first;
1115 isEAXAlive = (Reg == X86::EAX || Reg == X86::AX ||
1116 Reg == X86::AH || Reg == X86::AL);
1119 // Function prologue calls _alloca to probe the stack when allocating more
1120 // than 4k bytes in one go. Touching the stack at 4K increments is necessary
1121 // to ensure that the guard pages used by the OS virtual memory manager are
1122 // allocated in correct sequence.
1124 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1126 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1127 .addExternalSymbol("_alloca")
1128 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1131 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r))
1132 .addReg(X86::EAX, RegState::Kill);
1134 // Allocate NumBytes-4 bytes on stack. We'll also use 4 already
1135 // allocated bytes for EAX.
1136 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1137 .addImm(NumBytes - 4);
1138 BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32))
1139 .addExternalSymbol("_alloca")
1140 .addReg(StackPtr, RegState::Define | RegState::Implicit);
1143 MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm),
1145 StackPtr, false, NumBytes - 4);
1146 MBB.insert(MBBI, MI);
1148 } else if (NumBytes) {
1149 // If there is an SUB32ri of ESP immediately before this instruction, merge
1150 // the two. This can be the case when tail call elimination is enabled and
1151 // the callee has more arguments then the caller.
1152 NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true);
1154 // If there is an ADD32ri or SUB32ri of ESP immediately after this
1155 // instruction, merge the two instructions.
1156 mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes);
1159 emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII);
1162 if ((NumBytes || PushedRegs) && needsFrameMoves) {
1163 // Mark end of stack pointer adjustment.
1164 MCSymbol *Label = MMI.getContext().CreateTempSymbol();
1165 BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addSym(Label);
1167 if (!HasFP && NumBytes) {
1168 // Define the current CFA rule to use the provided offset.
1170 MachineLocation SPDst(MachineLocation::VirtualFP);
1171 MachineLocation SPSrc(MachineLocation::VirtualFP,
1172 -StackSize + stackGrowth);
1173 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1175 // FIXME: Verify & implement for FP
1176 MachineLocation SPDst(StackPtr);
1177 MachineLocation SPSrc(StackPtr, stackGrowth);
1178 Moves.push_back(MachineMove(Label, SPDst, SPSrc));
1182 // Emit DWARF info specifying the offsets of the callee-saved registers.
1184 emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr);
1188 void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
1189 MachineBasicBlock &MBB) const {
1190 const MachineFrameInfo *MFI = MF.getFrameInfo();
1191 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
1192 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1193 unsigned RetOpcode = MBBI->getOpcode();
1194 DebugLoc DL = MBBI->getDebugLoc();
1196 switch (RetOpcode) {
1198 llvm_unreachable("Can only insert epilog into returning blocks");
1201 case X86::TCRETURNdi:
1202 case X86::TCRETURNri:
1203 case X86::TCRETURNmi:
1204 case X86::TCRETURNdi64:
1205 case X86::TCRETURNri64:
1206 case X86::TCRETURNmi64:
1207 case X86::EH_RETURN:
1208 case X86::EH_RETURN64:
1209 break; // These are ok
1212 // Get the number of bytes to allocate from the FrameInfo.
1213 uint64_t StackSize = MFI->getStackSize();
1214 uint64_t MaxAlign = MFI->getMaxAlignment();
1215 unsigned CSSize = X86FI->getCalleeSavedFrameSize();
1216 uint64_t NumBytes = 0;
1219 // Calculate required stack adjustment.
1220 uint64_t FrameSize = StackSize - SlotSize;
1221 if (needsStackRealignment(MF))
1222 FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign;
1224 NumBytes = FrameSize - CSSize;
1227 BuildMI(MBB, MBBI, DL,
1228 TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr);
1230 NumBytes = StackSize - CSSize;
1233 // Skip the callee-saved pop instructions.
1234 MachineBasicBlock::iterator LastCSPop = MBBI;
1235 while (MBBI != MBB.begin()) {
1236 MachineBasicBlock::iterator PI = prior(MBBI);
1237 unsigned Opc = PI->getOpcode();
1239 if (Opc != X86::POP32r && Opc != X86::POP64r &&
1240 !PI->getDesc().isTerminator())
1246 DL = MBBI->getDebugLoc();
1248 // If there is an ADD32ri or SUB32ri of ESP immediately before this
1249 // instruction, merge the two instructions.
1250 if (NumBytes || MFI->hasVarSizedObjects())
1251 mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes);
1253 // If dynamic alloca is used, then reset esp to point to the last callee-saved
1254 // slot before popping them off! Same applies for the case, when stack was
1256 if (needsStackRealignment(MF)) {
1257 // We cannot use LEA here, because stack pointer was realigned. We need to
1258 // deallocate local frame back.
1260 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1261 MBBI = prior(LastCSPop);
1264 BuildMI(MBB, MBBI, DL,
1265 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1266 StackPtr).addReg(FramePtr);
1267 } else if (MFI->hasVarSizedObjects()) {
1269 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r;
1271 addLeaRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr),
1272 FramePtr, false, -CSSize);
1273 MBB.insert(MBBI, MI);
1275 BuildMI(MBB, MBBI, DL,
1276 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr)
1279 } else if (NumBytes) {
1280 // Adjust stack pointer back: ESP += numbytes.
1281 emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII);
1284 // We're returning from function via eh_return.
1285 if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) {
1286 MBBI = prior(MBB.end());
1287 MachineOperand &DestAddr = MBBI->getOperand(0);
1288 assert(DestAddr.isReg() && "Offset should be in register!");
1289 BuildMI(MBB, MBBI, DL,
1290 TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),
1291 StackPtr).addReg(DestAddr.getReg());
1292 } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi ||
1293 RetOpcode == X86::TCRETURNmi ||
1294 RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 ||
1295 RetOpcode == X86::TCRETURNmi64) {
1296 bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64;
1297 // Tail call return: adjust the stack pointer and jump to callee.
1298 MBBI = prior(MBB.end());
1299 MachineOperand &JumpTarget = MBBI->getOperand(0);
1300 MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1);
1301 assert(StackAdjust.isImm() && "Expecting immediate value.");
1303 // Adjust stack pointer.
1304 int StackAdj = StackAdjust.getImm();
1305 int MaxTCDelta = X86FI->getTCReturnAddrDelta();
1307 assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive");
1309 // Incoporate the retaddr area.
1310 Offset = StackAdj-MaxTCDelta;
1311 assert(Offset >= 0 && "Offset should never be negative");
1314 // Check for possible merge with preceeding ADD instruction.
1315 Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1316 emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII);
1319 // Jump to label or value in register.
1320 if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) {
1321 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi)
1322 ? X86::TAILJMPd : X86::TAILJMPd64)).
1323 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1324 JumpTarget.getTargetFlags());
1325 } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) {
1326 MachineInstrBuilder MIB =
1327 BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi)
1328 ? X86::TAILJMPm : X86::TAILJMPm64));
1329 for (unsigned i = 0; i != 5; ++i)
1330 MIB.addOperand(MBBI->getOperand(i));
1331 } else if (RetOpcode == X86::TCRETURNri64) {
1332 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg());
1334 BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg());
1337 MachineInstr *NewMI = prior(MBBI);
1338 for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
1339 NewMI->addOperand(MBBI->getOperand(i));
1341 // Delete the pseudo instruction TCRETURN.
1343 } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) &&
1344 (X86FI->getTCReturnAddrDelta() < 0)) {
1345 // Add the return addr area delta back since we are not tail calling.
1346 int delta = -1*X86FI->getTCReturnAddrDelta();
1347 MBBI = prior(MBB.end());
1349 // Check for possible merge with preceeding ADD instruction.
1350 delta += mergeSPUpdates(MBB, MBBI, StackPtr, true);
1351 emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII);
1355 unsigned X86RegisterInfo::getRARegister() const {
1356 return Is64Bit ? X86::RIP // Should have dwarf #16.
1357 : X86::EIP; // Should have dwarf #8.
1360 unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
1361 return hasFP(MF) ? FramePtr : StackPtr;
1365 X86RegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves) const {
1366 // Calculate amount of bytes used for return address storing
1367 int stackGrowth = (Is64Bit ? -8 : -4);
1369 // Initial state of the frame pointer is esp+stackGrowth.
1370 MachineLocation Dst(MachineLocation::VirtualFP);
1371 MachineLocation Src(StackPtr, stackGrowth);
1372 Moves.push_back(MachineMove(0, Dst, Src));
1374 // Add return address to move list
1375 MachineLocation CSDst(StackPtr, stackGrowth);
1376 MachineLocation CSSrc(getRARegister());
1377 Moves.push_back(MachineMove(0, CSDst, CSSrc));
1380 unsigned X86RegisterInfo::getEHExceptionRegister() const {
1381 llvm_unreachable("What is the exception register");
1385 unsigned X86RegisterInfo::getEHHandlerRegister() const {
1386 llvm_unreachable("What is the exception handler register");
1391 unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) {
1392 switch (VT.getSimpleVT().SimpleTy) {
1393 default: return Reg;
1398 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1400 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1402 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1404 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1410 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1412 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1414 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1416 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1418 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1420 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1422 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1424 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1426 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1428 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1430 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1432 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1434 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1436 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1438 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1440 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1446 default: return Reg;
1447 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1449 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1451 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1453 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1455 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1457 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1459 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1461 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1463 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1465 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1467 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1469 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1471 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1473 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1475 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1477 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1482 default: return Reg;
1483 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1485 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1487 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1489 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1491 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1493 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1495 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1497 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1499 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1501 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1503 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1505 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1507 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1509 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1511 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1513 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1518 default: return Reg;
1519 case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
1521 case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
1523 case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
1525 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
1527 case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
1529 case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
1531 case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
1533 case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
1535 case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
1537 case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
1539 case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
1541 case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
1543 case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
1545 case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
1547 case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
1549 case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
1558 #include "X86GenRegisterInfo.inc"
1561 struct MSAH : public MachineFunctionPass {
1563 MSAH() : MachineFunctionPass(&ID) {}
1565 virtual bool runOnMachineFunction(MachineFunction &MF) {
1566 const X86TargetMachine *TM =
1567 static_cast<const X86TargetMachine *>(&MF.getTarget());
1568 const X86RegisterInfo *X86RI = TM->getRegisterInfo();
1569 MachineRegisterInfo &RI = MF.getRegInfo();
1570 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
1571 unsigned StackAlignment = X86RI->getStackAlignment();
1573 // Be over-conservative: scan over all vreg defs and find whether vector
1574 // registers are used. If yes, there is a possibility that vector register
1575 // will be spilled and thus require dynamic stack realignment.
1576 for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister;
1577 RegNum < RI.getLastVirtReg(); ++RegNum)
1578 if (RI.getRegClass(RegNum)->getAlignment() > StackAlignment) {
1579 FuncInfo->setReserveFP(true);
1587 virtual const char *getPassName() const {
1588 return "X86 Maximal Stack Alignment Check";
1591 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1592 AU.setPreservesCFG();
1593 MachineFunctionPass::getAnalysisUsage(AU);
1601 llvm::createX86MaxStackAlignmentHeuristicPass() { return new MSAH(); }