lib/Target/X86/X86SchedSkylakeClient.td

   1 //=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for Skylake Client to support
  11 // instruction scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 def SkylakeClientModel : SchedMachineModel {
  16   // All x86 instructions are modeled as a single micro-op, and SKylake can
  17   // decode 6 instructions per cycle.
  18   let IssueWidth = 6;
  19   let MicroOpBufferSize = 224; // Based on the reorder buffer.
  20   let LoadLatency = 5;
  21   let MispredictPenalty = 14;
  22
  23   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  24   let LoopMicroOpBufferSize = 50;
  25
  26   // This flag is set to allow the scheduler to assign a default model to
  27   // unrecognized opcodes.
  28   let CompleteModel = 0;
  29 }
  30
  31 let SchedModel = SkylakeClientModel in {
  32
  33 // Skylake Client can issue micro-ops to 8 different ports in one cycle.
  34
  35 // Ports 0, 1, 5, and 6 handle all computation.
  36 // Port 4 gets the data half of stores. Store data can be available later than
  37 // the store address, but since we don't model the latency of stores, we can
  38 // ignore that.
  39 // Ports 2 and 3 are identical. They handle loads and the address half of
  40 // stores. Port 7 can handle address calculations.
  41 def SKLPort0 : ProcResource<1>;
  42 def SKLPort1 : ProcResource<1>;
  43 def SKLPort2 : ProcResource<1>;
  44 def SKLPort3 : ProcResource<1>;
  45 def SKLPort4 : ProcResource<1>;
  46 def SKLPort5 : ProcResource<1>;
  47 def SKLPort6 : ProcResource<1>;
  48 def SKLPort7 : ProcResource<1>;
  49
  50 // Many micro-ops are capable of issuing on multiple ports.
  51 def SKLPort01  : ProcResGroup<[SKLPort0, SKLPort1]>;
  52 def SKLPort23  : ProcResGroup<[SKLPort2, SKLPort3]>;
  53 def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
  54 def SKLPort04  : ProcResGroup<[SKLPort0, SKLPort4]>;
  55 def SKLPort05  : ProcResGroup<[SKLPort0, SKLPort5]>;
  56 def SKLPort06  : ProcResGroup<[SKLPort0, SKLPort6]>;
  57 def SKLPort15  : ProcResGroup<[SKLPort1, SKLPort5]>;
  58 def SKLPort16  : ProcResGroup<[SKLPort1, SKLPort6]>;
  59 def SKLPort56  : ProcResGroup<[SKLPort5, SKLPort6]>;
  60 def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
  61 def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
  62 def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
  63
  64 def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
  65 // FP division and sqrt on port 0.
  66 def SKLFPDivider : ProcResource<1>;
  67
  68 // 60 Entry Unified Scheduler
  69 def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
  70                               SKLPort5, SKLPort6, SKLPort7]> {
  71   let BufferSize=60;
  72 }
  73
  74 // Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  75 // cycles after the memory operand.
  76 def : ReadAdvance<ReadAfterLd, 5>;
  77
  78 // Many SchedWrites are defined in pairs with and without a folded load.
  79 // Instructions with folded loads are usually micro-fused, so they only appear
  80 // as two micro-ops when queued in the reservation station.
  81 // This multiclass defines the resource usage for variants with and without
  82 // folded loads.
  83 multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
  84                           list<ProcResourceKind> ExePorts,
  85                           int Lat, list<int> Res = [1], int UOps = 1,
  86                           int LoadLat = 5> {
  87   // Register variant is using a single cycle on ExePort.
  88   def : WriteRes<SchedRW, ExePorts> {
  89     let Latency = Lat;
  90     let ResourceCycles = Res;
  91     let NumMicroOps = UOps;
  92   }
  93
  94   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
  95   // the latency (default = 5).
  96   def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
  97     let Latency = !add(Lat, LoadLat);
  98     let ResourceCycles = !listconcat([1], Res);
  99     let NumMicroOps = !add(UOps, 1);
 100   }
 101 }
 102
 103 // A folded store needs a cycle on port 4 for the store data, and an extra port
 104 // 2/3/7 cycle to recompute the address.
 105 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
 106
 107 // Arithmetic.
 108 defm : SKLWriteResPair<WriteALU,    [SKLPort0156], 1>; // Simple integer ALU op.
 109 defm : SKLWriteResPair<WriteADC,    [SKLPort06],   1>; // Integer ALU + flags op.
 110 defm : SKLWriteResPair<WriteIMul,   [SKLPort1],    3>; // Integer multiplication.
 111 defm : SKLWriteResPair<WriteIMul64, [SKLPort1],    3>; // Integer 64-bit multiplication.
 112
 113 defm : X86WriteRes<WriteBSWAP32,    [SKLPort15], 1, [1], 1>;
 114 defm : X86WriteRes<WriteBSWAP64,    [SKLPort06, SKLPort15], 2, [1,1], 2>;
 115
 116 defm : SKLWriteResPair<WriteDiv8,   [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 117 defm : SKLWriteResPair<WriteDiv16,  [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 118 defm : SKLWriteResPair<WriteDiv32,  [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 119 defm : SKLWriteResPair<WriteDiv64,  [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 120 defm : SKLWriteResPair<WriteIDiv8,  [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 121 defm : SKLWriteResPair<WriteIDiv16, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 122 defm : SKLWriteResPair<WriteIDiv32, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 123 defm : SKLWriteResPair<WriteIDiv64, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>;
 124
 125 defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
 126
 127 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 128 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
 129
 130 defm : SKLWriteResPair<WriteCMOV,  [SKLPort06], 1, [1], 1>; // Conditional move.
 131 defm : SKLWriteResPair<WriteCMOV2, [SKLPort06], 2, [2], 2>; // Conditional (CF + ZF flag) move.
 132 defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move.
 133 def  : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
 134 def  : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
 135   let Latency = 2;
 136   let NumMicroOps = 3;
 137 }
 138 def  : WriteRes<WriteLAHFSAHF, [SKLPort06]>;
 139
 140 // Bit counts.
 141 defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;
 142 defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>;
 143 defm : SKLWriteResPair<WriteLZCNT,          [SKLPort1], 3>;
 144 defm : SKLWriteResPair<WriteTZCNT,          [SKLPort1], 3>;
 145 defm : SKLWriteResPair<WritePOPCNT,         [SKLPort1], 3>;
 146
 147 // Integer shifts and rotates.
 148 defm : SKLWriteResPair<WriteShift, [SKLPort06],  1>;
 149
 150 // SHLD/SHRD.
 151 defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;
 152 defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>;
 153 defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>;
 154 defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>;
 155
 156 // BMI1 BEXTR, BMI2 BZHI
 157 defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>;
 158 defm : SKLWriteResPair<WriteBZHI, [SKLPort15], 1>;
 159
 160 // Loads, stores, and moves, not folded with other operations.
 161 defm : X86WriteRes<WriteLoad,    [SKLPort23], 5, [1], 1>;
 162 defm : X86WriteRes<WriteStore,   [SKLPort237, SKLPort4], 1, [1,1], 1>;
 163 defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>;
 164 defm : X86WriteRes<WriteMove,    [SKLPort0156], 1, [1], 1>;
 165
 166 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 167 // These can often bypass execution ports completely.
 168 def : WriteRes<WriteZero,  []>;
 169
 170 // Branches don't produce values, so they have no latency, but they still
 171 // consume resources. Indirect branches can fold loads.
 172 defm : SKLWriteResPair<WriteJump,  [SKLPort06],   1>;
 173
 174 // Floating point. This covers both scalar and vector operations.
 175 defm : X86WriteRes<WriteFLD0,          [SKLPort05], 1, [1], 1>;
 176 defm : X86WriteRes<WriteFLD1,          [SKLPort05], 1, [2], 2>;
 177 defm : X86WriteRes<WriteFLDC,          [SKLPort05], 1, [2], 2>;
 178 defm : X86WriteRes<WriteFLoad,         [SKLPort23], 5, [1], 1>;
 179 defm : X86WriteRes<WriteFLoadX,        [SKLPort23], 6, [1], 1>;
 180 defm : X86WriteRes<WriteFLoadY,        [SKLPort23], 7, [1], 1>;
 181 defm : X86WriteRes<WriteFMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 182 defm : X86WriteRes<WriteFMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 183 defm : X86WriteRes<WriteFStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 184 defm : X86WriteRes<WriteFStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 185 defm : X86WriteRes<WriteFStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 186 defm : X86WriteRes<WriteFStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 187 defm : X86WriteRes<WriteFStoreNTX,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 188 defm : X86WriteRes<WriteFStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 189 defm : X86WriteRes<WriteFMaskedStore,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
 190 defm : X86WriteRes<WriteFMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>;
 191 defm : X86WriteRes<WriteFMove,         [SKLPort015], 1, [1], 1>;
 192 defm : X86WriteRes<WriteFMoveX,        [SKLPort015], 1, [1], 1>;
 193 defm : X86WriteRes<WriteFMoveY,        [SKLPort015], 1, [1], 1>;
 194 defm : X86WriteRes<WriteEMMS,          [SKLPort05,SKLPort0156], 10, [9,1], 10>;
 195
 196 defm : SKLWriteResPair<WriteFAdd,     [SKLPort01],  4, [1], 1, 5>; // Floating point add/sub.
 197 defm : SKLWriteResPair<WriteFAddX,    [SKLPort01],  4, [1], 1, 6>;
 198 defm : SKLWriteResPair<WriteFAddY,    [SKLPort01],  4, [1], 1, 7>;
 199 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 200 defm : SKLWriteResPair<WriteFAdd64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double add/sub.
 201 defm : SKLWriteResPair<WriteFAdd64X,  [SKLPort01],  4, [1], 1, 6>;
 202 defm : SKLWriteResPair<WriteFAdd64Y,  [SKLPort01],  4, [1], 1, 7>;
 203 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 204
 205 defm : SKLWriteResPair<WriteFCmp,     [SKLPort01],  4, [1], 1, 5>; // Floating point compare.
 206 defm : SKLWriteResPair<WriteFCmpX,    [SKLPort01],  4, [1], 1, 6>;
 207 defm : SKLWriteResPair<WriteFCmpY,    [SKLPort01],  4, [1], 1, 7>;
 208 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 209 defm : SKLWriteResPair<WriteFCmp64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double compare.
 210 defm : SKLWriteResPair<WriteFCmp64X,  [SKLPort01],  4, [1], 1, 6>;
 211 defm : SKLWriteResPair<WriteFCmp64Y,  [SKLPort01],  4, [1], 1, 7>;
 212 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 213
 214 defm : SKLWriteResPair<WriteFCom,      [SKLPort0],  2>; // Floating point compare to flags.
 215
 216 defm : SKLWriteResPair<WriteFMul,     [SKLPort01],  4, [1], 1, 5>; // Floating point multiplication.
 217 defm : SKLWriteResPair<WriteFMulX,    [SKLPort01],  4, [1], 1, 6>;
 218 defm : SKLWriteResPair<WriteFMulY,    [SKLPort01],  4, [1], 1, 7>;
 219 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 220 defm : SKLWriteResPair<WriteFMul64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double multiplication.
 221 defm : SKLWriteResPair<WriteFMul64X,  [SKLPort01],  4, [1], 1, 6>;
 222 defm : SKLWriteResPair<WriteFMul64Y,  [SKLPort01],  4, [1], 1, 7>;
 223 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 224
 225 defm : SKLWriteResPair<WriteFDiv,     [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division.
 226 //defm : SKLWriteResPair<WriteFDivX,    [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>;
 227 defm : SKLWriteResPair<WriteFDivY,    [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>;
 228 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 229 //defm : SKLWriteResPair<WriteFDiv64,   [SKLPort0,SKLFPDivider], 14, [1,3], 1, 5>; // Floating point double division.
 230 //defm : SKLWriteResPair<WriteFDiv64X,  [SKLPort0,SKLFPDivider], 14, [1,3], 1, 6>;
 231 //defm : SKLWriteResPair<WriteFDiv64Y,  [SKLPort0,SKLFPDivider], 14, [1,5], 1, 7>;
 232 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 233
 234 defm : SKLWriteResPair<WriteFSqrt,    [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
 235 defm : SKLWriteResPair<WriteFSqrtX,   [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>;
 236 defm : SKLWriteResPair<WriteFSqrtY,   [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>;
 237 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 238 defm : SKLWriteResPair<WriteFSqrt64,  [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
 239 defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>;
 240 defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>;
 241 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 242 defm : SKLWriteResPair<WriteFSqrt80,  [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root.
 243
 244 defm : SKLWriteResPair<WriteFRcp,   [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
 245 defm : SKLWriteResPair<WriteFRcpX,  [SKLPort0], 4, [1], 1, 6>;
 246 defm : SKLWriteResPair<WriteFRcpY,  [SKLPort0], 4, [1], 1, 7>;
 247 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 248
 249 defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
 250 defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>;
 251 defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>;
 252 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 253
 254 defm : SKLWriteResPair<WriteFMA,    [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add.
 255 defm : SKLWriteResPair<WriteFMAX,   [SKLPort01], 4, [1], 1, 6>;
 256 defm : SKLWriteResPair<WriteFMAY,   [SKLPort01], 4, [1], 1, 7>;
 257 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 258 defm : SKLWriteResPair<WriteDPPD,   [SKLPort5,SKLPort01],  9, [1,2], 3, 6>; // Floating point double dot product.
 259 defm : SKLWriteResPair<WriteDPPS,   [SKLPort5,SKLPort01], 13, [1,3], 4, 6>;
 260 defm : SKLWriteResPair<WriteDPPSY,  [SKLPort5,SKLPort01], 13, [1,3], 4, 7>;
 261 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
 262 defm : SKLWriteResPair<WriteFSign,   [SKLPort0], 1>; // Floating point fabs/fchs.
 263 defm : SKLWriteResPair<WriteFRnd,     [SKLPort01], 8, [2], 2, 6>; // Floating point rounding.
 264 defm : SKLWriteResPair<WriteFRndY,    [SKLPort01], 8, [2], 2, 7>;
 265 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 266 defm : SKLWriteResPair<WriteFLogic,  [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
 267 defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>;
 268 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 269 defm : SKLWriteResPair<WriteFTest,   [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
 270 defm : SKLWriteResPair<WriteFTestY,  [SKLPort0], 2, [1], 1, 7>;
 271 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 272 defm : SKLWriteResPair<WriteFShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 273 defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>;
 274 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 275 defm : SKLWriteResPair<WriteFVarShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 276 defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 277 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 278 defm : SKLWriteResPair<WriteFBlend,  [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends.
 279 defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>;
 280 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 281 defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends.
 282 defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>;
 283 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 284
 285 // FMA Scheduling helper class.
 286 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 287
 288 // Vector integer operations.
 289 defm : X86WriteRes<WriteVecLoad,         [SKLPort23], 5, [1], 1>;
 290 defm : X86WriteRes<WriteVecLoadX,        [SKLPort23], 6, [1], 1>;
 291 defm : X86WriteRes<WriteVecLoadY,        [SKLPort23], 7, [1], 1>;
 292 defm : X86WriteRes<WriteVecLoadNT,       [SKLPort23], 6, [1], 1>;
 293 defm : X86WriteRes<WriteVecLoadNTY,      [SKLPort23], 7, [1], 1>;
 294 defm : X86WriteRes<WriteVecMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
 295 defm : X86WriteRes<WriteVecMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
 296 defm : X86WriteRes<WriteVecStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
 297 defm : X86WriteRes<WriteVecStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 298 defm : X86WriteRes<WriteVecStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
 299 defm : X86WriteRes<WriteVecStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
 300 defm : X86WriteRes<WriteVecStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
 301 defm : X86WriteRes<WriteVecMaskedStore,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
 302 defm : X86WriteRes<WriteVecMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>;
 303 defm : X86WriteRes<WriteVecMove,         [SKLPort05],  1, [1], 1>;
 304 defm : X86WriteRes<WriteVecMoveX,        [SKLPort015], 1, [1], 1>;
 305 defm : X86WriteRes<WriteVecMoveY,        [SKLPort015], 1, [1], 1>;
 306 defm : X86WriteRes<WriteVecMoveToGpr,    [SKLPort0], 2, [1], 1>;
 307 defm : X86WriteRes<WriteVecMoveFromGpr,  [SKLPort5], 1, [1], 1>;
 308
 309 defm : SKLWriteResPair<WriteVecALU,   [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 310 defm : SKLWriteResPair<WriteVecALUX,  [SKLPort01], 1, [1], 1, 6>;
 311 defm : SKLWriteResPair<WriteVecALUY,  [SKLPort01], 1, [1], 1, 7>;
 312 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 313 defm : SKLWriteResPair<WriteVecLogic, [SKLPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
 314 defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>;
 315 defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>;
 316 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 317 defm : SKLWriteResPair<WriteVecTest,  [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
 318 defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>;
 319 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 320 defm : SKLWriteResPair<WriteVecIMul,  [SKLPort0] ,  4, [1], 1, 5>; // Vector integer multiply.
 321 defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01],  4, [1], 1, 6>;
 322 defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01],  4, [1], 1, 7>;
 323 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 324 defm : SKLWriteResPair<WritePMULLD,   [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD.
 325 defm : SKLWriteResPair<WritePMULLDY,  [SKLPort01], 10, [2], 2, 7>;
 326 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 327 defm : SKLWriteResPair<WriteShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
 328 defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>;
 329 defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>;
 330 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 331 defm : SKLWriteResPair<WriteVarShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
 332 defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>;
 333 defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
 334 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 335 defm : SKLWriteResPair<WriteBlend,  [SKLPort5], 1, [1], 1, 6>; // Vector blends.
 336 defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>;
 337 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 338 defm : SKLWriteResPair<WriteVarBlend,  [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.
 339 defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>;
 340 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 341 defm : SKLWriteResPair<WriteMPSAD,  [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.
 342 defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>;
 343 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
 344 defm : SKLWriteResPair<WritePSADBW,  [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW.
 345 defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>;
 346 defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>;
 347 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 348 defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS.
 349
 350 // Vector integer shifts.
 351 defm : SKLWriteResPair<WriteVecShift,     [SKLPort0], 1, [1], 1, 5>;
 352 defm : X86WriteRes<WriteVecShiftX,        [SKLPort5,SKLPort01],  2, [1,1], 2>;
 353 defm : X86WriteRes<WriteVecShiftY,        [SKLPort5,SKLPort01],  4, [1,1], 2>;
 354 defm : X86WriteRes<WriteVecShiftXLd,      [SKLPort01,SKLPort23], 7, [1,1], 2>;
 355 defm : X86WriteRes<WriteVecShiftYLd,      [SKLPort01,SKLPort23], 8, [1,1], 2>;
 356 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 357
 358 defm : SKLWriteResPair<WriteVecShiftImm,  [SKLPort0],  1, [1], 1, 5>; // Vector integer immediate shifts.
 359 defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>;
 360 defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>;
 361 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 362 defm : SKLWriteResPair<WriteVarVecShift,  [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts.
 363 defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>;
 364 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 365
 366 // Vector insert/extract operations.
 367 def : WriteRes<WriteVecInsert, [SKLPort5]> {
 368   let Latency = 2;
 369   let NumMicroOps = 2;
 370   let ResourceCycles = [2];
 371 }
 372 def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
 373   let Latency = 6;
 374   let NumMicroOps = 2;
 375 }
 376 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 377
 378 def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> {
 379   let Latency = 3;
 380   let NumMicroOps = 2;
 381 }
 382 def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> {
 383   let Latency = 2;
 384   let NumMicroOps = 3;
 385 }
 386
 387 // Conversion between integer and float.
 388 defm : SKLWriteResPair<WriteCvtSS2I,   [SKLPort1], 3>;
 389 defm : SKLWriteResPair<WriteCvtPS2I,   [SKLPort1], 3>;
 390 defm : SKLWriteResPair<WriteCvtPS2IY,  [SKLPort1], 3>;
 391 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 392 defm : SKLWriteResPair<WriteCvtSD2I,   [SKLPort1], 3>;
 393 defm : SKLWriteResPair<WriteCvtPD2I,   [SKLPort1], 3>;
 394 defm : SKLWriteResPair<WriteCvtPD2IY,  [SKLPort1], 3>;
 395 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 396
 397 defm : SKLWriteResPair<WriteCvtI2SS,   [SKLPort1], 4>;
 398 defm : SKLWriteResPair<WriteCvtI2PS,   [SKLPort1], 4>;
 399 defm : SKLWriteResPair<WriteCvtI2PSY,  [SKLPort1], 4>;
 400 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 401 defm : SKLWriteResPair<WriteCvtI2SD,   [SKLPort1], 4>;
 402 defm : SKLWriteResPair<WriteCvtI2PD,   [SKLPort1], 4>;
 403 defm : SKLWriteResPair<WriteCvtI2PDY,  [SKLPort1], 4>;
 404 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 405
 406 defm : SKLWriteResPair<WriteCvtSS2SD,  [SKLPort1], 3>;
 407 defm : SKLWriteResPair<WriteCvtPS2PD,  [SKLPort1], 3>;
 408 defm : SKLWriteResPair<WriteCvtPS2PDY, [SKLPort1], 3>;
 409 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
 410 defm : SKLWriteResPair<WriteCvtSD2SS,  [SKLPort1], 3>;
 411 defm : SKLWriteResPair<WriteCvtPD2PS,  [SKLPort1], 3>;
 412 defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort1], 3>;
 413 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
 414
 415 defm : X86WriteRes<WriteCvtPH2PS,    [SKLPort5,SKLPort015],  5, [1,1], 2>;
 416 defm : X86WriteRes<WriteCvtPH2PSY,    [SKLPort5,SKLPort01],  7, [1,1], 2>;
 417 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
 418 defm : X86WriteRes<WriteCvtPH2PSLd,  [SKLPort23,SKLPort01],  9, [1,1], 2>;
 419 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;
 420 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
 421
 422 defm : X86WriteRes<WriteCvtPS2PH,                       [SKLPort5,SKLPort015], 5, [1,1], 2>;
 423 defm : X86WriteRes<WriteCvtPS2PHY,                       [SKLPort5,SKLPort01], 7, [1,1], 2>;
 424 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
 425 defm : X86WriteRes<WriteCvtPS2PHSt,  [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>;
 426 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>;
 427 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 428
 429 // Strings instructions.
 430
 431 // Packed Compare Implicit Length Strings, Return Mask
 432 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
 433   let Latency = 10;
 434   let NumMicroOps = 3;
 435   let ResourceCycles = [3];
 436 }
 437 def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
 438   let Latency = 16;
 439   let NumMicroOps = 4;
 440   let ResourceCycles = [3,1];
 441 }
 442
 443 // Packed Compare Explicit Length Strings, Return Mask
 444 def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
 445   let Latency = 19;
 446   let NumMicroOps = 9;
 447   let ResourceCycles = [4,3,1,1];
 448 }
 449 def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
 450   let Latency = 25;
 451   let NumMicroOps = 10;
 452   let ResourceCycles = [4,3,1,1,1];
 453 }
 454
 455 // Packed Compare Implicit Length Strings, Return Index
 456 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
 457   let Latency = 10;
 458   let NumMicroOps = 3;
 459   let ResourceCycles = [3];
 460 }
 461 def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
 462   let Latency = 16;
 463   let NumMicroOps = 4;
 464   let ResourceCycles = [3,1];
 465 }
 466
 467 // Packed Compare Explicit Length Strings, Return Index
 468 def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
 469   let Latency = 18;
 470   let NumMicroOps = 8;
 471   let ResourceCycles = [4,3,1];
 472 }
 473 def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
 474   let Latency = 24;
 475   let NumMicroOps = 9;
 476   let ResourceCycles = [4,3,1,1];
 477 }
 478
 479 // MOVMSK Instructions.
 480 def : WriteRes<WriteFMOVMSK,    [SKLPort0]> { let Latency = 2; }
 481 def : WriteRes<WriteVecMOVMSK,  [SKLPort0]> { let Latency = 2; }
 482 def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; }
 483 def : WriteRes<WriteMMXMOVMSK,  [SKLPort0]> { let Latency = 2; }
 484
 485 // AES instructions.
 486 def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
 487   let Latency = 4;
 488   let NumMicroOps = 1;
 489   let ResourceCycles = [1];
 490 }
 491 def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
 492   let Latency = 10;
 493   let NumMicroOps = 2;
 494   let ResourceCycles = [1,1];
 495 }
 496
 497 def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
 498   let Latency = 8;
 499   let NumMicroOps = 2;
 500   let ResourceCycles = [2];
 501 }
 502 def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
 503   let Latency = 14;
 504   let NumMicroOps = 3;
 505   let ResourceCycles = [2,1];
 506 }
 507
 508 def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
 509   let Latency = 20;
 510   let NumMicroOps = 11;
 511   let ResourceCycles = [3,6,2];
 512 }
 513 def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
 514   let Latency = 25;
 515   let NumMicroOps = 11;
 516   let ResourceCycles = [3,6,1,1];
 517 }
 518
 519 // Carry-less multiplication instructions.
 520 def : WriteRes<WriteCLMul, [SKLPort5]> {
 521   let Latency = 6;
 522   let NumMicroOps = 1;
 523   let ResourceCycles = [1];
 524 }
 525 def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
 526   let Latency = 12;
 527   let NumMicroOps = 2;
 528   let ResourceCycles = [1,1];
 529 }
 530
 531 // Catch-all for expensive system instructions.
 532 def : WriteRes<WriteSystem,     [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 533
 534 // AVX2.
 535 defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 536 defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 537 defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 538 defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 539
 540 // Old microcoded instructions that nobody use.
 541 def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 542
 543 // Fence instructions.
 544 def : WriteRes<WriteFence,  [SKLPort23, SKLPort4]>;
 545
 546 // Load/store MXCSR.
 547 def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 548 def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 549
 550 // Nop, not very useful expect it provides a model for nops!
 551 def : WriteRes<WriteNop, []>;
 552
 553 ////////////////////////////////////////////////////////////////////////////////
 554 // Horizontal add/sub  instructions.
 555 ////////////////////////////////////////////////////////////////////////////////
 556
 557 defm : SKLWriteResPair<WriteFHAdd,  [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;
 558 defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>;
 559 defm : SKLWriteResPair<WritePHAdd,  [SKLPort5,SKLPort05],  3, [2,1], 3, 5>;
 560 defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>;
 561 defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;
 562
 563 // Remaining instrs.
 564
 565 def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
 566   let Latency = 1;
 567   let NumMicroOps = 1;
 568   let ResourceCycles = [1];
 569 }
 570 def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr",
 571                                             "MMX_PADDUS(B|W)irr",
 572                                             "MMX_PAVG(B|W)irr",
 573                                             "MMX_PCMPEQ(B|D|W)irr",
 574                                             "MMX_PCMPGT(B|D|W)irr",
 575                                             "MMX_P(MAX|MIN)SWirr",
 576                                             "MMX_P(MAX|MIN)UBirr",
 577                                             "MMX_PSUBS(B|W)irr",
 578                                             "MMX_PSUBUS(B|W)irr")>;
 579
 580 def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
 581   let Latency = 1;
 582   let NumMicroOps = 1;
 583   let ResourceCycles = [1];
 584 }
 585 def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
 586                                             "UCOM_F(P?)r")>;
 587
 588 def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
 589   let Latency = 1;
 590   let NumMicroOps = 1;
 591   let ResourceCycles = [1];
 592 }
 593 def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 594
 595 def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
 596   let Latency = 1;
 597   let NumMicroOps = 1;
 598   let ResourceCycles = [1];
 599 }
 600 def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
 601
 602 def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
 603   let Latency = 1;
 604   let NumMicroOps = 1;
 605   let ResourceCycles = [1];
 606 }
 607 def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 608 def: InstRW<[SKLWriteResGroup7], (instregex "BT(16|32|64)ri8",
 609                                             "BT(16|32|64)rr",
 610                                             "BTC(16|32|64)ri8",
 611                                             "BTC(16|32|64)rr",
 612                                             "BTR(16|32|64)ri8",
 613                                             "BTR(16|32|64)rr",
 614                                             "BTS(16|32|64)ri8",
 615                                             "BTS(16|32|64)rr")>;
 616
 617 def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
 618   let Latency = 1;
 619   let NumMicroOps = 1;
 620   let ResourceCycles = [1];
 621 }
 622 def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr",
 623                                             "BLSI(32|64)rr",
 624                                             "BLSMSK(32|64)rr",
 625                                             "BLSR(32|64)rr")>;
 626
 627 def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
 628   let Latency = 1;
 629   let NumMicroOps = 1;
 630   let ResourceCycles = [1];
 631 }
 632 def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
 633                                             "VPBLENDD(Y?)rri",
 634                                             "(V?)PSUB(B|D|Q|W)(Y?)rr")>;
 635
 636 def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
 637   let Latency = 1;
 638   let NumMicroOps = 1;
 639   let ResourceCycles = [1];
 640 }
 641 def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE,
 642                                           CMC, STC)>;
 643 def: InstRW<[SKLWriteResGroup10], (instregex "SGDT64m",
 644                                              "SIDT64m",
 645                                              "SMSW16m",
 646                                              "STRm",
 647                                              "SYSCALL")>;
 648
 649 def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
 650   let Latency = 1;
 651   let NumMicroOps = 2;
 652   let ResourceCycles = [1,1];
 653 }
 654 def: InstRW<[SKLWriteResGroup11], (instregex "FBSTPm",
 655                                              "ST_FP(32|64|80)m",
 656                                              "VMPTRSTm")>;
 657
 658 def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
 659   let Latency = 2;
 660   let NumMicroOps = 2;
 661   let ResourceCycles = [2];
 662 }
 663 def: InstRW<[SKLWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>;
 664
 665 def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
 666   let Latency = 2;
 667   let NumMicroOps = 2;
 668   let ResourceCycles = [2];
 669 }
 670 def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP)>;
 671 def: InstRW<[SKLWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>;
 672
 673 def SKLWriteResGroup15 : SchedWriteRes<[SKLPort06]> {
 674   let Latency = 2;
 675   let NumMicroOps = 2;
 676   let ResourceCycles = [2];
 677 }
 678 def: InstRW<[SKLWriteResGroup15], (instregex "ROL(8|16|32|64)r1",
 679                                              "ROL(8|16|32|64)ri",
 680                                              "ROR(8|16|32|64)r1",
 681                                              "ROR(8|16|32|64)ri",
 682                                              "SET(A|BE)r")>;
 683
 684 def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
 685   let Latency = 2;
 686   let NumMicroOps = 2;
 687   let ResourceCycles = [2];
 688 }
 689 def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
 690                                           WAIT,
 691                                           XGETBV)>;
 692
 693 def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 694   let Latency = 2;
 695   let NumMicroOps = 2;
 696   let ResourceCycles = [1,1];
 697 }
 698 def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
 699
 700 def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
 701   let Latency = 2;
 702   let NumMicroOps = 2;
 703   let ResourceCycles = [1,1];
 704 }
 705 def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
 706
 707 def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 708   let Latency = 2;
 709   let NumMicroOps = 2;
 710   let ResourceCycles = [1,1];
 711 }
 712 def: InstRW<[SKLWriteResGroup23], (instrs CWD)>;
 713 def: InstRW<[SKLWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>;
 714 def: InstRW<[SKLWriteResGroup23], (instregex "ADC8i8",
 715                                              "ADC8ri",
 716                                              "SBB8i8",
 717                                              "SBB8ri")>;
 718
 719 def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
 720   let Latency = 2;
 721   let NumMicroOps = 3;
 722   let ResourceCycles = [1,1,1];
 723 }
 724 def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
 725
 726 def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
 727   let Latency = 2;
 728   let NumMicroOps = 3;
 729   let ResourceCycles = [1,1,1];
 730 }
 731 def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 732
 733 def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
 734   let Latency = 2;
 735   let NumMicroOps = 3;
 736   let ResourceCycles = [1,1,1];
 737 }
 738 def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r,
 739                                           STOSB, STOSL, STOSQ, STOSW)>;
 740 def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr",
 741                                              "PUSH64i8")>;
 742
 743 def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
 744   let Latency = 3;
 745   let NumMicroOps = 1;
 746   let ResourceCycles = [1];
 747 }
 748 def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
 749                                              "PEXT(32|64)rr")>;
 750
 751 def SKLWriteResGroup29_16i : SchedWriteRes<[SKLPort1, SKLPort0156]> {
 752   let Latency = 4;
 753   let NumMicroOps = 2;
 754   let ResourceCycles = [1,1];
 755 }
 756 def: InstRW<[SKLWriteResGroup29_16i], (instrs IMUL16rri, IMUL16rri8)>;
 757
 758 def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
 759   let Latency = 3;
 760   let NumMicroOps = 1;
 761   let ResourceCycles = [1];
 762 }
 763 def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
 764                                              "VPBROADCASTBrr",
 765                                              "VPBROADCASTWrr",
 766                                              "(V?)PCMPGTQ(Y?)rr")>;
 767
 768 def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
 769   let Latency = 3;
 770   let NumMicroOps = 2;
 771   let ResourceCycles = [1,1];
 772 }
 773 def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;
 774
 775 def SKLWriteResGroup33 : SchedWriteRes<[SKLPort06]> {
 776   let Latency = 3;
 777   let NumMicroOps = 3;
 778   let ResourceCycles = [3];
 779 }
 780 def: InstRW<[SKLWriteResGroup33], (instregex "ROL(8|16|32|64)rCL",
 781                                              "ROR(8|16|32|64)rCL",
 782                                              "SAR(8|16|32|64)rCL",
 783                                              "SHL(8|16|32|64)rCL",
 784                                              "SHR(8|16|32|64)rCL")>;
 785
 786 def SKLWriteResGroup34 : SchedWriteRes<[SKLPort0156]> {
 787   let Latency = 2;
 788   let NumMicroOps = 3;
 789   let ResourceCycles = [3];
 790 }
 791 def: InstRW<[SKLWriteResGroup34], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr,
 792                                           XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr,
 793                                           XCHG16ar, XCHG32ar, XCHG64ar)>;
 794
 795 def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
 796   let Latency = 3;
 797   let NumMicroOps = 3;
 798   let ResourceCycles = [1,2];
 799 }
 800 def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 801
 802 def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
 803   let Latency = 3;
 804   let NumMicroOps = 3;
 805   let ResourceCycles = [2,1];
 806 }
 807 def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
 808                                              "(V?)PHSUBSW(Y?)rr")>;
 809
 810 def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
 811   let Latency = 3;
 812   let NumMicroOps = 3;
 813   let ResourceCycles = [2,1];
 814 }
 815 def: InstRW<[SKLWriteResGroup39], (instregex "MMX_PACKSSDWirr",
 816                                              "MMX_PACKSSWBirr",
 817                                              "MMX_PACKUSWBirr")>;
 818
 819 def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 820   let Latency = 3;
 821   let NumMicroOps = 3;
 822   let ResourceCycles = [1,2];
 823 }
 824 def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
 825
 826 def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
 827   let Latency = 3;
 828   let NumMicroOps = 3;
 829   let ResourceCycles = [1,2];
 830 }
 831 def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
 832
 833 def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 834   let Latency = 3;
 835   let NumMicroOps = 3;
 836   let ResourceCycles = [1,2];
 837 }
 838 def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r1",
 839                                              "RCL(8|16|32|64)ri",
 840                                              "RCR(8|16|32|64)r1",
 841                                              "RCR(8|16|32|64)ri")>;
 842
 843 def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
 844   let Latency = 3;
 845   let NumMicroOps = 3;
 846   let ResourceCycles = [1,1,1];
 847 }
 848 def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
 849
 850 def SKLWriteResGroup44 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
 851   let Latency = 3;
 852   let NumMicroOps = 4;
 853   let ResourceCycles = [1,1,2];
 854 }
 855 def: InstRW<[SKLWriteResGroup44], (instregex "SET(A|BE)m")>;
 856
 857 def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
 858   let Latency = 3;
 859   let NumMicroOps = 4;
 860   let ResourceCycles = [1,1,1,1];
 861 }
 862 def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
 863
 864 def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
 865   let Latency = 3;
 866   let NumMicroOps = 4;
 867   let ResourceCycles = [1,1,1,1];
 868 }
 869 def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;
 870
 871 def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
 872   let Latency = 4;
 873   let NumMicroOps = 1;
 874   let ResourceCycles = [1];
 875 }
 876 def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 877
 878 def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
 879   let Latency = 4;
 880   let NumMicroOps = 1;
 881   let ResourceCycles = [1];
 882 }
 883 def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr",
 884                                              "(V?)CVT(T?)PS2DQ(Y?)rr")>;
 885
 886 def SKLWriteResGroup51 : SchedWriteRes<[SKLPort1,SKLPort5]> {
 887   let Latency = 4;
 888   let NumMicroOps = 2;
 889   let ResourceCycles = [1,1];
 890 }
 891 def: InstRW<[SKLWriteResGroup51], (instrs IMUL64r, MUL64r, MULX64rr)>;
 892
 893 def SKLWriteResGroup51_16 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
 894   let Latency = 4;
 895   let NumMicroOps = 4;
 896   let ResourceCycles = [1,1,2];
 897 }
 898 def: InstRW<[SKLWriteResGroup51_16], (instrs IMUL16r, MUL16r)>;
 899
 900 def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
 901   let Latency = 4;
 902   let NumMicroOps = 3;
 903   let ResourceCycles = [1,1,1];
 904 }
 905 def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
 906                                              "IST_F(16|32)m")>;
 907
 908 def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
 909   let Latency = 4;
 910   let NumMicroOps = 4;
 911   let ResourceCycles = [4];
 912 }
 913 def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
 914
 915 def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
 916   let Latency = 4;
 917   let NumMicroOps = 4;
 918   let ResourceCycles = [1,3];
 919 }
 920 def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
 921
 922 def SKLWriteResGroup56 : SchedWriteRes<[SKLPort015,SKLPort0156]> {
 923   let Latency = 4;
 924   let NumMicroOps = 4;
 925   let ResourceCycles = [1,3];
 926 }
 927 def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;
 928
 929 def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
 930   let Latency = 4;
 931   let NumMicroOps = 4;
 932   let ResourceCycles = [1,1,2];
 933 }
 934 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
 935
 936 def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
 937   let Latency = 5;
 938   let NumMicroOps = 1;
 939   let ResourceCycles = [1];
 940 }
 941 def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm16",
 942                                              "MOVSX(16|32|64)rm32",
 943                                              "MOVSX(16|32|64)rm8",
 944                                              "MOVZX(16|32|64)rm16",
 945                                              "MOVZX(16|32|64)rm8",
 946                                              "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67?
 947
 948 def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
 949   let Latency = 5;
 950   let NumMicroOps = 2;
 951   let ResourceCycles = [1,1];
 952 }
 953 def: InstRW<[SKLWriteResGroup59], (instregex "MMX_CVTPI2PDirr",
 954                                              "(V?)CVTDQ2PDrr")>;
 955
 956 def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
 957   let Latency = 5;
 958   let NumMicroOps = 2;
 959   let ResourceCycles = [1,1];
 960 }
 961 def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr",
 962                                              "MMX_CVT(T?)PS2PIirr",
 963                                              "(V?)CVT(T?)PD2DQrr",
 964                                              "(V?)CVTPD2PSrr",
 965                                              "(V?)CVTPS2PDrr",
 966                                              "(V?)CVTSD2SSrr",
 967                                              "(V?)CVTSI642SDrr",
 968                                              "(V?)CVTSI2SDrr",
 969                                              "(V?)CVTSI2SSrr",
 970                                              "(V?)CVTSS2SDrr")>;
 971
 972 def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
 973   let Latency = 5;
 974   let NumMicroOps = 3;
 975   let ResourceCycles = [1,1,1];
 976 }
 977 def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
 978
 979 def SKLWriteResGroup62 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
 980   let Latency = 4;
 981   let NumMicroOps = 3;
 982   let ResourceCycles = [1,1,1];
 983 }
 984 def: InstRW<[SKLWriteResGroup62], (instrs IMUL32r, MUL32r, MULX32rr)>;
 985
 986 def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 987   let Latency = 5;
 988   let NumMicroOps = 5;
 989   let ResourceCycles = [1,4];
 990 }
 991 def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
 992
 993 def SKLWriteResGroup64 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
 994   let Latency = 5;
 995   let NumMicroOps = 5;
 996   let ResourceCycles = [2,3];
 997 }
 998 def: InstRW<[SKLWriteResGroup64], (instregex "CMPXCHG(8|16|32|64)rr")>;
 999
1000 def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
1001   let Latency = 5;
1002   let NumMicroOps = 6;
1003   let ResourceCycles = [1,1,4];
1004 }
1005 def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;
1006
1007 def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
1008   let Latency = 6;
1009   let NumMicroOps = 1;
1010   let ResourceCycles = [1];
1011 }
1012 def: InstRW<[SKLWriteResGroup67], (instregex "VBROADCASTSSrm",
1013                                              "(V?)MOVSHDUPrm",
1014                                              "(V?)MOVSLDUPrm",
1015                                              "VPBROADCASTDrm",
1016                                              "VPBROADCASTQrm")>;
1017
1018 def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
1019   let Latency = 6;
1020   let NumMicroOps = 2;
1021   let ResourceCycles = [2];
1022 }
1023 def: InstRW<[SKLWriteResGroup68], (instregex "MMX_CVTPI2PSirr")>;
1024
1025 def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1026   let Latency = 6;
1027   let NumMicroOps = 2;
1028   let ResourceCycles = [1,1];
1029 }
1030 def: InstRW<[SKLWriteResGroup69], (instregex "MMX_PADDSBirm",
1031                                              "MMX_PADDSWirm",
1032                                              "MMX_PADDUSBirm",
1033                                              "MMX_PADDUSWirm",
1034                                              "MMX_PAVGBirm",
1035                                              "MMX_PAVGWirm",
1036                                              "MMX_PCMPEQBirm",
1037                                              "MMX_PCMPEQDirm",
1038                                              "MMX_PCMPEQWirm",
1039                                              "MMX_PCMPGTBirm",
1040                                              "MMX_PCMPGTDirm",
1041                                              "MMX_PCMPGTWirm",
1042                                              "MMX_PMAXSWirm",
1043                                              "MMX_PMAXUBirm",
1044                                              "MMX_PMINSWirm",
1045                                              "MMX_PMINUBirm",
1046                                              "MMX_PSUBSBirm",
1047                                              "MMX_PSUBSWirm",
1048                                              "MMX_PSUBUSBirm",
1049                                              "MMX_PSUBUSWirm")>;
1050
1051 def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> {
1052   let Latency = 6;
1053   let NumMicroOps = 2;
1054   let ResourceCycles = [1,1];
1055 }
1056 def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr",
1057                                              "(V?)CVT(T?)SD2SI(64)?rr")>;
1058
1059 def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
1060   let Latency = 6;
1061   let NumMicroOps = 2;
1062   let ResourceCycles = [1,1];
1063 }
1064 def: InstRW<[SKLWriteResGroup72], (instregex "FARJMP64",
1065                                              "JMP(16|32|64)m")>;
1066
1067 def SKLWriteResGroup74 : SchedWriteRes<[SKLPort23,SKLPort06]> {
1068   let Latency = 6;
1069   let NumMicroOps = 2;
1070   let ResourceCycles = [1,1];
1071 }
1072 def: InstRW<[SKLWriteResGroup74], (instregex "BT(16|32|64)mi8")>;
1073
1074 def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
1075   let Latency = 6;
1076   let NumMicroOps = 2;
1077   let ResourceCycles = [1,1];
1078 }
1079 def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
1080                                              "BLSI(32|64)rm",
1081                                              "BLSMSK(32|64)rm",
1082                                              "BLSR(32|64)rm",
1083                                              "MOVBE(16|32|64)rm")>;
1084
1085 def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1086   let Latency = 6;
1087   let NumMicroOps = 2;
1088   let ResourceCycles = [1,1];
1089 }
1090 def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
1091 def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
1092
1093 def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1094   let Latency = 6;
1095   let NumMicroOps = 3;
1096   let ResourceCycles = [2,1];
1097 }
1098 def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
1099
1100 def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
1101   let Latency = 6;
1102   let NumMicroOps = 4;
1103   let ResourceCycles = [1,1,1,1];
1104 }
1105 def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
1106
1107 def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1108   let Latency = 6;
1109   let NumMicroOps = 4;
1110   let ResourceCycles = [1,1,1,1];
1111 }
1112 def: InstRW<[SKLWriteResGroup82], (instregex "BTC(16|32|64)mi8",
1113                                              "BTR(16|32|64)mi8",
1114                                              "BTS(16|32|64)mi8",
1115                                              "SAR(8|16|32|64)m1",
1116                                              "SAR(8|16|32|64)mi",
1117                                              "SHL(8|16|32|64)m1",
1118                                              "SHL(8|16|32|64)mi",
1119                                              "SHR(8|16|32|64)m1",
1120                                              "SHR(8|16|32|64)mi")>;
1121
1122 def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1123   let Latency = 6;
1124   let NumMicroOps = 4;
1125   let ResourceCycles = [1,1,1,1];
1126 }
1127 def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
1128                                              "PUSH(16|32|64)rmm")>;
1129
1130 def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
1131   let Latency = 6;
1132   let NumMicroOps = 6;
1133   let ResourceCycles = [1,5];
1134 }
1135 def: InstRW<[SKLWriteResGroup84], (instrs STD)>;
1136
1137 def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
1138   let Latency = 7;
1139   let NumMicroOps = 1;
1140   let ResourceCycles = [1];
1141 }
1142 def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m",
1143                                              "VBROADCASTF128",
1144                                              "VBROADCASTI128",
1145                                              "VBROADCASTSDYrm",
1146                                              "VBROADCASTSSYrm",
1147                                              "VMOVDDUPYrm",
1148                                              "VMOVSHDUPYrm",
1149                                              "VMOVSLDUPYrm",
1150                                              "VPBROADCASTDYrm",
1151                                              "VPBROADCASTQYrm")>;
1152
1153 def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {
1154   let Latency = 7;
1155   let NumMicroOps = 2;
1156   let ResourceCycles = [1,1];
1157 }
1158 def: InstRW<[SKLWriteResGroup86], (instregex "VCVTDQ2PDYrr")>;
1159
1160 def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1161   let Latency = 6;
1162   let NumMicroOps = 2;
1163   let ResourceCycles = [1,1];
1164 }
1165 def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
1166                                              "(V?)PMOV(SX|ZX)BQrm",
1167                                              "(V?)PMOV(SX|ZX)BWrm",
1168                                              "(V?)PMOV(SX|ZX)DQrm",
1169                                              "(V?)PMOV(SX|ZX)WDrm",
1170                                              "(V?)PMOV(SX|ZX)WQrm")>;
1171
1172 def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1173   let Latency = 7;
1174   let NumMicroOps = 2;
1175   let ResourceCycles = [1,1];
1176 }
1177 def: InstRW<[SKLWriteResGroup89], (instregex "VCVTPD2PSYrr",
1178                                              "VCVTPS2PDYrr",
1179                                              "VCVT(T?)PD2DQYrr")>;
1180
1181 def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1182   let Latency = 7;
1183   let NumMicroOps = 2;
1184   let ResourceCycles = [1,1];
1185 }
1186 def: InstRW<[SKLWriteResGroup91], (instregex "(V?)INSERTF128rm",
1187                                              "(V?)INSERTI128rm",
1188                                              "(V?)PADD(B|D|Q|W)rm",
1189                                              "(V?)PBLENDDrmi",
1190                                              "(V?)PSUB(B|D|Q|W)rm")>;
1191
1192 def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1193   let Latency = 7;
1194   let NumMicroOps = 3;
1195   let ResourceCycles = [2,1];
1196 }
1197 def: InstRW<[SKLWriteResGroup92], (instregex "MMX_PACKSSDWirm",
1198                                              "MMX_PACKSSWBirm",
1199                                              "MMX_PACKUSWBirm")>;
1200
1201 def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1202   let Latency = 7;
1203   let NumMicroOps = 3;
1204   let ResourceCycles = [1,2];
1205 }
1206 def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
1207                                           SCASB, SCASL, SCASQ, SCASW)>;
1208
1209 def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
1210   let Latency = 7;
1211   let NumMicroOps = 3;
1212   let ResourceCycles = [1,1,1];
1213 }
1214 def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>;
1215
1216 def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
1217   let Latency = 7;
1218   let NumMicroOps = 3;
1219   let ResourceCycles = [1,1,1];
1220 }
1221 def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
1222
1223 def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
1224   let Latency = 7;
1225   let NumMicroOps = 3;
1226   let ResourceCycles = [1,1,1];
1227 }
1228 def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>;
1229
1230 def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1231   let Latency = 7;
1232   let NumMicroOps = 5;
1233   let ResourceCycles = [1,1,1,2];
1234 }
1235 def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m1",
1236                                               "ROL(8|16|32|64)mi",
1237                                               "ROR(8|16|32|64)m1",
1238                                               "ROR(8|16|32|64)mi")>;
1239
1240 def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1241   let Latency = 7;
1242   let NumMicroOps = 5;
1243   let ResourceCycles = [1,1,1,2];
1244 }
1245 def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
1246
1247 def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1248   let Latency = 7;
1249   let NumMicroOps = 5;
1250   let ResourceCycles = [1,1,1,1,1];
1251 }
1252 def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m",
1253                                               "FARCALL64")>;
1254
1255 def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
1256   let Latency = 7;
1257   let NumMicroOps = 7;
1258   let ResourceCycles = [1,3,1,2];
1259 }
1260 def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
1261
1262 def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
1263   let Latency = 8;
1264   let NumMicroOps = 2;
1265   let ResourceCycles = [1,1];
1266 }
1267 def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
1268                                               "PEXT(32|64)rm")>;
1269
1270 def SKLWriteResGroup107_16 : SchedWriteRes<[SKLPort1, SKLPort0156, SKLPort23]> {
1271   let Latency = 8;
1272   let NumMicroOps = 3;
1273   let ResourceCycles = [1,1,1];
1274 }
1275 def: InstRW<[SKLWriteResGroup107_16], (instrs IMUL16rmi, IMUL16rmi8)>;
1276
1277 def SKLWriteResGroup107_16_2 : SchedWriteRes<[SKLPort1, SKLPort06, SKLPort0156, SKLPort23]> {
1278   let Latency = 9;
1279   let NumMicroOps = 5;
1280   let ResourceCycles = [1,1,2,1];
1281 }
1282 def: InstRW<[SKLWriteResGroup107_16_2], (instrs IMUL16m, MUL16m)>;
1283
1284 def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1285   let Latency = 8;
1286   let NumMicroOps = 2;
1287   let ResourceCycles = [1,1];
1288 }
1289 def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m",
1290                                               "VPBROADCASTBYrm",
1291                                               "VPBROADCASTWYrm",
1292                                               "VPMOVSXBDYrm",
1293                                               "VPMOVSXBQYrm",
1294                                               "VPMOVSXWQYrm")>;
1295
1296 def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1297   let Latency = 8;
1298   let NumMicroOps = 2;
1299   let ResourceCycles = [1,1];
1300 }
1301 def: InstRW<[SKLWriteResGroup110], (instregex "VPADD(B|D|Q|W)Yrm",
1302                                               "VPBLENDDYrmi",
1303                                               "VPSUB(B|D|Q|W)Yrm")>;
1304
1305 def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1306   let Latency = 8;
1307   let NumMicroOps = 4;
1308   let ResourceCycles = [1,2,1];
1309 }
1310 def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1311
1312 def SKLWriteResGroup115 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06]> {
1313   let Latency = 8;
1314   let NumMicroOps = 5;
1315   let ResourceCycles = [1,1,3];
1316 }
1317 def: InstRW<[SKLWriteResGroup115], (instregex "ROR(8|16|32|64)mCL")>;
1318
1319 def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1320   let Latency = 8;
1321   let NumMicroOps = 5;
1322   let ResourceCycles = [1,1,1,2];
1323 }
1324 def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m1",
1325                                               "RCL(8|16|32|64)mi",
1326                                               "RCR(8|16|32|64)m1",
1327                                               "RCR(8|16|32|64)mi")>;
1328
1329 def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1330   let Latency = 8;
1331   let NumMicroOps = 6;
1332   let ResourceCycles = [1,1,1,3];
1333 }
1334 def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
1335                                               "SAR(8|16|32|64)mCL",
1336                                               "SHL(8|16|32|64)mCL",
1337                                               "SHR(8|16|32|64)mCL")>;
1338
1339 def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1340   let Latency = 8;
1341   let NumMicroOps = 6;
1342   let ResourceCycles = [1,1,1,2,1];
1343 }
1344 def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
1345 def: InstRW<[SKLWriteResGroup119], (instregex "CMPXCHG(8|16|32|64)rm")>;
1346
1347 def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1348   let Latency = 9;
1349   let NumMicroOps = 2;
1350   let ResourceCycles = [1,1];
1351 }
1352 def: InstRW<[SKLWriteResGroup120], (instregex "MMX_CVTPI2PSirm")>;
1353
1354 def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1355   let Latency = 9;
1356   let NumMicroOps = 2;
1357   let ResourceCycles = [1,1];
1358 }
1359 def: InstRW<[SKLWriteResGroup121], (instregex "(V?)PCMPGTQrm",
1360                                               "VPMOVSXBWYrm",
1361                                               "VPMOVSXDQYrm",
1362                                               "VPMOVSXWDYrm",
1363                                               "VPMOVZXWDYrm")>;
1364
1365 def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
1366   let Latency = 9;
1367   let NumMicroOps = 2;
1368   let ResourceCycles = [1,1];
1369 }
1370 def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm",
1371                                               "(V?)CVTPS2PDrm")>;
1372
1373 def SKLWriteResGroup127 : SchedWriteRes<[SKLPort1,SKLPort5,SKLPort23]> {
1374   let Latency = 9;
1375   let NumMicroOps = 3;
1376   let ResourceCycles = [1,1,1];
1377 }
1378 def: InstRW<[SKLWriteResGroup127], (instrs IMUL64m, MUL64m, MULX64rm)>;
1379
1380 def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1381   let Latency = 9;
1382   let NumMicroOps = 4;
1383   let ResourceCycles = [2,1,1];
1384 }
1385 def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
1386                                               "(V?)PHSUBSWrm")>;
1387
1388 def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1389   let Latency = 9;
1390   let NumMicroOps = 5;
1391   let ResourceCycles = [1,2,1,1];
1392 }
1393 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
1394                                               "LSL(16|32|64)rm")>;
1395
1396 def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1397   let Latency = 10;
1398   let NumMicroOps = 2;
1399   let ResourceCycles = [1,1];
1400 }
1401 def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1402                                               "ILD_F(16|32|64)m",
1403                                               "VPCMPGTQYrm")>;
1404
1405 def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1406   let Latency = 10;
1407   let NumMicroOps = 2;
1408   let ResourceCycles = [1,1];
1409 }
1410 def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm",
1411                                               "(V?)CVTPS2DQrm",
1412                                               "(V?)CVTSS2SDrm",
1413                                               "(V?)CVTTPS2DQrm")>;
1414
1415 def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1416   let Latency = 10;
1417   let NumMicroOps = 3;
1418   let ResourceCycles = [1,1,1];
1419 }
1420 def: InstRW<[SKLWriteResGroup138], (instregex "MMX_CVTPI2PDirm")>;
1421
1422 def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1423   let Latency = 10;
1424   let NumMicroOps = 3;
1425   let ResourceCycles = [1,1,1];
1426 }
1427 def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>;
1428
1429 def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1430   let Latency = 10;
1431   let NumMicroOps = 4;
1432   let ResourceCycles = [2,1,1];
1433 }
1434 def: InstRW<[SKLWriteResGroup140], (instregex "VPHADDSWYrm",
1435                                               "VPHSUBSWYrm")>;
1436
1437 def SKLWriteResGroup142 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort06,SKLPort0156]> {
1438   let Latency = 9;
1439   let NumMicroOps = 4;
1440   let ResourceCycles = [1,1,1,1];
1441 }
1442 def: InstRW<[SKLWriteResGroup142], (instrs IMUL32m, MUL32m, MULX32rm)>;
1443
1444 def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1445   let Latency = 10;
1446   let NumMicroOps = 8;
1447   let ResourceCycles = [1,1,1,1,1,3];
1448 }
1449 def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
1450
1451 def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1452   let Latency = 11;
1453   let NumMicroOps = 1;
1454   let ResourceCycles = [1,3];
1455 }
1456 def : SchedAlias<WriteFDivX, SKLWriteResGroup145>; // TODO - convert to ZnWriteResFpuPair
1457
1458 def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1459   let Latency = 11;
1460   let NumMicroOps = 2;
1461   let ResourceCycles = [1,1];
1462 }
1463 def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;
1464
1465 def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1466   let Latency = 11;
1467   let NumMicroOps = 2;
1468   let ResourceCycles = [1,1];
1469 }
1470 def: InstRW<[SKLWriteResGroup147], (instregex "VCVTDQ2PSYrm",
1471                                               "VCVTPS2PDYrm",
1472                                               "VCVT(T?)PS2DQYrm")>;
1473
1474 def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1475   let Latency = 11;
1476   let NumMicroOps = 3;
1477   let ResourceCycles = [2,1];
1478 }
1479 def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
1480
1481 def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1482   let Latency = 11;
1483   let NumMicroOps = 3;
1484   let ResourceCycles = [1,1,1];
1485 }
1486 def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;
1487
1488 def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
1489   let Latency = 11;
1490   let NumMicroOps = 3;
1491   let ResourceCycles = [1,1,1];
1492 }
1493 def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm",
1494                                               "(V?)CVT(T?)SD2SI(64)?rm",
1495                                               "VCVTTSS2SI64rm",
1496                                               "(V?)CVT(T?)SS2SIrm")>;
1497
1498 def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1499   let Latency = 11;
1500   let NumMicroOps = 3;
1501   let ResourceCycles = [1,1,1];
1502 }
1503 def: InstRW<[SKLWriteResGroup152], (instregex "CVTPD2PSrm",
1504                                               "CVT(T?)PD2DQrm",
1505                                               "MMX_CVT(T?)PD2PIirm")>;
1506
1507 def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
1508   let Latency = 11;
1509   let NumMicroOps = 7;
1510   let ResourceCycles = [2,3,2];
1511 }
1512 def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
1513                                               "RCR(16|32|64)rCL")>;
1514
1515 def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1516   let Latency = 11;
1517   let NumMicroOps = 9;
1518   let ResourceCycles = [1,5,1,2];
1519 }
1520 def: InstRW<[SKLWriteResGroup155], (instregex "RCL8rCL")>;
1521
1522 def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
1523   let Latency = 11;
1524   let NumMicroOps = 11;
1525   let ResourceCycles = [2,9];
1526 }
1527 def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
1528
1529 def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> {
1530   let Latency = 12;
1531   let NumMicroOps = 4;
1532   let ResourceCycles = [1,1,1,1];
1533 }
1534 def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
1535
1536 def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1537   let Latency = 13;
1538   let NumMicroOps = 3;
1539   let ResourceCycles = [2,1];
1540 }
1541 def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1542
1543 def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1544   let Latency = 13;
1545   let NumMicroOps = 3;
1546   let ResourceCycles = [1,1,1];
1547 }
1548 def: InstRW<[SKLWriteResGroup163], (instregex "VCVTDQ2PDYrm")>;
1549
1550 def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1551   let Latency = 14;
1552   let NumMicroOps = 1;
1553   let ResourceCycles = [1,3];
1554 }
1555 def : SchedAlias<WriteFDiv64,  SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1556 def : SchedAlias<WriteFDiv64X, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1557
1558 def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1559   let Latency = 14;
1560   let NumMicroOps = 1;
1561   let ResourceCycles = [1,5];
1562 }
1563 def : SchedAlias<WriteFDiv64Y, SKLWriteResGroup166_1>; // TODO - convert to ZnWriteResFpuPair
1564
1565 def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1566   let Latency = 14;
1567   let NumMicroOps = 3;
1568   let ResourceCycles = [1,1,1];
1569 }
1570 def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
1571
1572 def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1573   let Latency = 14;
1574   let NumMicroOps = 10;
1575   let ResourceCycles = [2,4,1,3];
1576 }
1577 def: InstRW<[SKLWriteResGroup170], (instregex "RCR8rCL")>;
1578
1579 def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
1580   let Latency = 15;
1581   let NumMicroOps = 1;
1582   let ResourceCycles = [1];
1583 }
1584 def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1585
1586 def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1587   let Latency = 15;
1588   let NumMicroOps = 10;
1589   let ResourceCycles = [1,1,1,5,1,1];
1590 }
1591 def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
1592
1593 def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1594   let Latency = 16;
1595   let NumMicroOps = 14;
1596   let ResourceCycles = [1,1,1,4,2,5];
1597 }
1598 def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;
1599
1600 def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
1601   let Latency = 16;
1602   let NumMicroOps = 16;
1603   let ResourceCycles = [16];
1604 }
1605 def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;
1606
1607 def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1608   let Latency = 17;
1609   let NumMicroOps = 2;
1610   let ResourceCycles = [1,1,5];
1611 }
1612 def : SchedAlias<WriteFDivXLd, SKLWriteResGroup179>; // TODO - convert to ZnWriteResFpuPair
1613
1614 def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1615   let Latency = 17;
1616   let NumMicroOps = 15;
1617   let ResourceCycles = [2,1,2,4,2,4];
1618 }
1619 def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;
1620
1621 def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1622   let Latency = 18;
1623   let NumMicroOps = 8;
1624   let ResourceCycles = [1,1,1,5];
1625 }
1626 def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
1627
1628 def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1629   let Latency = 18;
1630   let NumMicroOps = 11;
1631   let ResourceCycles = [2,1,1,4,1,2];
1632 }
1633 def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
1634
1635 def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1636   let Latency = 19;
1637   let NumMicroOps = 2;
1638   let ResourceCycles = [1,1,4];
1639 }
1640 def : SchedAlias<WriteFDiv64Ld,  SKLWriteResGroup186>; // TODO - convert to ZnWriteResFpuPair
1641
1642 def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
1643   let Latency = 20;
1644   let NumMicroOps = 1;
1645   let ResourceCycles = [1];
1646 }
1647 def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1648
1649 def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1650   let Latency = 20;
1651   let NumMicroOps = 2;
1652   let ResourceCycles = [1,1,4];
1653 }
1654 def : SchedAlias<WriteFDiv64XLd, SKLWriteResGroup190>; // TODO - convert to ZnWriteResFpuPair
1655
1656 def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1657   let Latency = 20;
1658   let NumMicroOps = 8;
1659   let ResourceCycles = [1,1,1,1,1,1,2];
1660 }
1661 def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;
1662
1663 def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
1664   let Latency = 20;
1665   let NumMicroOps = 10;
1666   let ResourceCycles = [1,2,7];
1667 }
1668 def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;
1669
1670 def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1671   let Latency = 21;
1672   let NumMicroOps = 2;
1673   let ResourceCycles = [1,1,8];
1674 }
1675 def : SchedAlias<WriteFDiv64YLd, SKLWriteResGroup195>; // TODO - convert to ZnWriteResFpuPair
1676
1677 def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1678   let Latency = 22;
1679   let NumMicroOps = 2;
1680   let ResourceCycles = [1,1];
1681 }
1682 def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
1683
1684 def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1685   let Latency = 22;
1686   let NumMicroOps = 5;
1687   let ResourceCycles = [1,2,1,1];
1688 }
1689 def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm,
1690                                              VGATHERDPDrm,
1691                                              VGATHERQPDrm,
1692                                              VGATHERQPSrm,
1693                                              VPGATHERDDrm,
1694                                              VPGATHERDQrm,
1695                                              VPGATHERQDrm,
1696                                              VPGATHERQQrm)>;
1697
1698 def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1699   let Latency = 25;
1700   let NumMicroOps = 5;
1701   let ResourceCycles = [1,2,1,1];
1702 }
1703 def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm,
1704                                              VGATHERQPDYrm,
1705                                              VGATHERQPSYrm,
1706                                              VPGATHERDDYrm,
1707                                              VPGATHERDQYrm,
1708                                              VPGATHERQDYrm,
1709                                              VPGATHERQQYrm,
1710                                              VGATHERDPDYrm)>;
1711
1712 def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1713   let Latency = 23;
1714   let NumMicroOps = 19;
1715   let ResourceCycles = [2,1,4,1,1,4,6];
1716 }
1717 def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;
1718
1719 def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1720   let Latency = 25;
1721   let NumMicroOps = 3;
1722   let ResourceCycles = [1,1,1];
1723 }
1724 def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
1725
1726 def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1727   let Latency = 27;
1728   let NumMicroOps = 2;
1729   let ResourceCycles = [1,1];
1730 }
1731 def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
1732
1733 def SKLWriteResGroup207 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort0156]> {
1734   let Latency = 28;
1735   let NumMicroOps = 8;
1736   let ResourceCycles = [2,4,1,1];
1737 }
1738 def: InstRW<[SKLWriteResGroup207], (instregex "IDIV(8|16|32|64)m")>;
1739
1740 def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1741   let Latency = 30;
1742   let NumMicroOps = 3;
1743   let ResourceCycles = [1,1,1];
1744 }
1745 def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
1746
1747 def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
1748   let Latency = 35;
1749   let NumMicroOps = 23;
1750   let ResourceCycles = [1,5,3,4,10];
1751 }
1752 def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
1753                                               "IN(8|16|32)rr")>;
1754
1755 def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1756   let Latency = 35;
1757   let NumMicroOps = 23;
1758   let ResourceCycles = [1,5,2,1,4,10];
1759 }
1760 def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
1761                                               "OUT(8|16|32)rr")>;
1762
1763 def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1764   let Latency = 37;
1765   let NumMicroOps = 31;
1766   let ResourceCycles = [1,8,1,21];
1767 }
1768 def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
1769
1770 def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
1771   let Latency = 40;
1772   let NumMicroOps = 18;
1773   let ResourceCycles = [1,1,2,3,1,1,1,8];
1774 }
1775 def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;
1776
1777 def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1778   let Latency = 41;
1779   let NumMicroOps = 39;
1780   let ResourceCycles = [1,10,1,1,26];
1781 }
1782 def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;
1783
1784 def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
1785   let Latency = 42;
1786   let NumMicroOps = 22;
1787   let ResourceCycles = [2,20];
1788 }
1789 def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
1790
1791 def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1792   let Latency = 42;
1793   let NumMicroOps = 40;
1794   let ResourceCycles = [1,11,1,1,26];
1795 }
1796 def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;
1797 def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
1798
1799 def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1800   let Latency = 46;
1801   let NumMicroOps = 44;
1802   let ResourceCycles = [1,11,1,1,30];
1803 }
1804 def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
1805
1806 def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
1807   let Latency = 62;
1808   let NumMicroOps = 64;
1809   let ResourceCycles = [2,8,5,10,39];
1810 }
1811 def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;
1812
1813 def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1814   let Latency = 63;
1815   let NumMicroOps = 88;
1816   let ResourceCycles = [4,4,31,1,2,1,45];
1817 }
1818 def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
1819
1820 def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1821   let Latency = 63;
1822   let NumMicroOps = 90;
1823   let ResourceCycles = [4,2,33,1,2,1,47];
1824 }
1825 def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
1826
1827 def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
1828   let Latency = 75;
1829   let NumMicroOps = 15;
1830   let ResourceCycles = [6,3,6];
1831 }
1832 def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
1833
1834 def SKLWriteResGroup221 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1835   let Latency = 76;
1836   let NumMicroOps = 32;
1837   let ResourceCycles = [7,2,8,3,1,11];
1838 }
1839 def: InstRW<[SKLWriteResGroup221], (instregex "DIV(16|32|64)r")>;
1840
1841 def SKLWriteResGroup222 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1842   let Latency = 102;
1843   let NumMicroOps = 66;
1844   let ResourceCycles = [4,2,4,8,14,34];
1845 }
1846 def: InstRW<[SKLWriteResGroup222], (instregex "IDIV(16|32|64)r")>;
1847
1848 def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
1849   let Latency = 106;
1850   let NumMicroOps = 100;
1851   let ResourceCycles = [9,1,11,16,1,11,21,30];
1852 }
1853 def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
1854
1855 def: InstRW<[WriteZero], (instrs CLC)>;
1856
1857 } // SchedModel