lib/Target/X86/X86SchedSkylakeServer.td

   1 //=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the machine model for Skylake Server to support
  11 // instruction scheduling and other instruction cost heuristics.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 def SkylakeServerModel : SchedMachineModel {
  16   // All x86 instructions are modeled as a single micro-op, and SKylake can
  17   // decode 6 instructions per cycle.
  18   let IssueWidth = 6;
  19   let MicroOpBufferSize = 224; // Based on the reorder buffer.
  20   let LoadLatency = 5;
  21   let MispredictPenalty = 14;
  22
  23   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  24   let LoopMicroOpBufferSize = 50;
  25
  26   // This flag is set to allow the scheduler to assign a default model to
  27   // unrecognized opcodes.
  28   let CompleteModel = 0;
  29 }
  30
  31 let SchedModel = SkylakeServerModel in {
  32
  33 // Skylake Server can issue micro-ops to 8 different ports in one cycle.
  34
  35 // Ports 0, 1, 5, and 6 handle all computation.
  36 // Port 4 gets the data half of stores. Store data can be available later than
  37 // the store address, but since we don't model the latency of stores, we can
  38 // ignore that.
  39 // Ports 2 and 3 are identical. They handle loads and the address half of
  40 // stores. Port 7 can handle address calculations.
  41 def SKXPort0 : ProcResource<1>;
  42 def SKXPort1 : ProcResource<1>;
  43 def SKXPort2 : ProcResource<1>;
  44 def SKXPort3 : ProcResource<1>;
  45 def SKXPort4 : ProcResource<1>;
  46 def SKXPort5 : ProcResource<1>;
  47 def SKXPort6 : ProcResource<1>;
  48 def SKXPort7 : ProcResource<1>;
  49
  50 // Many micro-ops are capable of issuing on multiple ports.
  51 def SKXPort01  : ProcResGroup<[SKXPort0, SKXPort1]>;
  52 def SKXPort23  : ProcResGroup<[SKXPort2, SKXPort3]>;
  53 def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>;
  54 def SKXPort04  : ProcResGroup<[SKXPort0, SKXPort4]>;
  55 def SKXPort05  : ProcResGroup<[SKXPort0, SKXPort5]>;
  56 def SKXPort06  : ProcResGroup<[SKXPort0, SKXPort6]>;
  57 def SKXPort15  : ProcResGroup<[SKXPort1, SKXPort5]>;
  58 def SKXPort16  : ProcResGroup<[SKXPort1, SKXPort6]>;
  59 def SKXPort56  : ProcResGroup<[SKXPort5, SKXPort6]>;
  60 def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>;
  61 def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>;
  62 def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>;
  63
  64 def SKXDivider : ProcResource<1>; // Integer division issued on port 0.
  65 // FP division and sqrt on port 0.
  66 def SKXFPDivider : ProcResource<1>;
  67
  68 // 60 Entry Unified Scheduler
  69 def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4,
  70                               SKXPort5, SKXPort6, SKXPort7]> {
  71   let BufferSize=60;
  72 }
  73
  74 // Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  75 // cycles after the memory operand.
  76 def : ReadAdvance<ReadAfterLd, 5>;
  77
  78 // Many SchedWrites are defined in pairs with and without a folded load.
  79 // Instructions with folded loads are usually micro-fused, so they only appear
  80 // as two micro-ops when queued in the reservation station.
  81 // This multiclass defines the resource usage for variants with and without
  82 // folded loads.
  83 multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW,
  84                           list<ProcResourceKind> ExePorts,
  85                           int Lat, list<int> Res = [1], int UOps = 1,
  86                           int LoadLat = 5> {
  87   // Register variant is using a single cycle on ExePort.
  88   def : WriteRes<SchedRW, ExePorts> {
  89     let Latency = Lat;
  90     let ResourceCycles = Res;
  91     let NumMicroOps = UOps;
  92   }
  93
  94   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
  95   // the latency (default = 5).
  96   def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> {
  97     let Latency = !add(Lat, LoadLat);
  98     let ResourceCycles = !listconcat([1], Res);
  99     let NumMicroOps = !add(UOps, 1);
 100   }
 101 }
 102
 103 // A folded store needs a cycle on port 4 for the store data, and an extra port
 104 // 2/3/7 cycle to recompute the address.
 105 def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>;
 106
 107 // Arithmetic.
 108 defm : SKXWriteResPair<WriteALU,    [SKXPort0156], 1>; // Simple integer ALU op.
 109 defm : SKXWriteResPair<WriteADC,    [SKXPort06],   1>; // Integer ALU + flags op.
 110 defm : SKXWriteResPair<WriteIMul,   [SKXPort1],    3>; // Integer multiplication.
 111 defm : SKXWriteResPair<WriteIMul64, [SKXPort1],    3>; // Integer 64-bit multiplication.
 112
 113 defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>;
 114 defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>;
 115
 116 defm : SKXWriteResPair<WriteDiv8,   [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 117 defm : SKXWriteResPair<WriteDiv16,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 118 defm : SKXWriteResPair<WriteDiv32,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 119 defm : SKXWriteResPair<WriteDiv64,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 120 defm : SKXWriteResPair<WriteIDiv8,  [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 121 defm : SKXWriteResPair<WriteIDiv16, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 122 defm : SKXWriteResPair<WriteIDiv32, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 123 defm : SKXWriteResPair<WriteIDiv64, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>;
 124
 125 defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
 126
 127 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 128 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
 129
 130 defm : SKXWriteResPair<WriteCMOV,  [SKXPort06], 1, [1], 1>; // Conditional move.
 131 defm : SKXWriteResPair<WriteCMOV2, [SKXPort06], 2, [2], 2>; // Conditional (CF + ZF flag) move.
 132 defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move.
 133 def  : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc.
 134 def  : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
 135   let Latency = 2;
 136   let NumMicroOps = 3;
 137 }
 138 def  : WriteRes<WriteLAHFSAHF, [SKXPort06]>;
 139
 140 // Integer shifts and rotates.
 141 defm : SKXWriteResPair<WriteShift, [SKXPort06],  1>;
 142
 143 // SHLD/SHRD.
 144 defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>;
 145 defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>;
 146 defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>;
 147 defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>;
 148
 149 // Bit counts.
 150 defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>;
 151 defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>;
 152 defm : SKXWriteResPair<WriteLZCNT,          [SKXPort1], 3>;
 153 defm : SKXWriteResPair<WriteTZCNT,          [SKXPort1], 3>;
 154 defm : SKXWriteResPair<WritePOPCNT,         [SKXPort1], 3>;
 155
 156 // BMI1 BEXTR, BMI2 BZHI
 157 defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>;
 158 defm : SKXWriteResPair<WriteBZHI, [SKXPort15], 1>;
 159
 160 // Loads, stores, and moves, not folded with other operations.
 161 defm : X86WriteRes<WriteLoad,    [SKXPort23], 5, [1], 1>;
 162 defm : X86WriteRes<WriteStore,   [SKXPort237, SKXPort4], 1, [1,1], 1>;
 163 defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>;
 164 defm : X86WriteRes<WriteMove,    [SKXPort0156], 1, [1], 1>;
 165
 166 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 167 // These can often bypass execution ports completely.
 168 def : WriteRes<WriteZero,  []>;
 169
 170 // Branches don't produce values, so they have no latency, but they still
 171 // consume resources. Indirect branches can fold loads.
 172 defm : SKXWriteResPair<WriteJump,  [SKXPort06],   1>;
 173
 174 // Floating point. This covers both scalar and vector operations.
 175 defm : X86WriteRes<WriteFLD0,          [SKXPort05], 1, [1], 1>;
 176 defm : X86WriteRes<WriteFLD1,          [SKXPort05], 1, [2], 2>;
 177 defm : X86WriteRes<WriteFLDC,          [SKXPort05], 1, [2], 2>;
 178 defm : X86WriteRes<WriteFLoad,         [SKXPort23], 5, [1], 1>;
 179 defm : X86WriteRes<WriteFLoadX,        [SKXPort23], 6, [1], 1>;
 180 defm : X86WriteRes<WriteFLoadY,        [SKXPort23], 7, [1], 1>;
 181 defm : X86WriteRes<WriteFMaskedLoad,   [SKXPort23,SKXPort015], 7, [1,1], 2>;
 182 defm : X86WriteRes<WriteFMaskedLoadY,  [SKXPort23,SKXPort015], 8, [1,1], 2>;
 183 defm : X86WriteRes<WriteFStore,        [SKXPort237,SKXPort4], 1, [1,1], 2>;
 184 defm : X86WriteRes<WriteFStoreX,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 185 defm : X86WriteRes<WriteFStoreY,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 186 defm : X86WriteRes<WriteFStoreNT,      [SKXPort237,SKXPort4], 1, [1,1], 2>;
 187 defm : X86WriteRes<WriteFStoreNTX,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 188 defm : X86WriteRes<WriteFStoreNTY,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 189 defm : X86WriteRes<WriteFMaskedStore,  [SKXPort237,SKXPort0], 2, [1,1], 2>;
 190 defm : X86WriteRes<WriteFMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>;
 191 defm : X86WriteRes<WriteFMove,         [SKXPort015], 1, [1], 1>;
 192 defm : X86WriteRes<WriteFMoveX,        [SKXPort015], 1, [1], 1>;
 193 defm : X86WriteRes<WriteFMoveY,        [SKXPort015], 1, [1], 1>;
 194 defm : X86WriteRes<WriteEMMS,          [SKXPort05,SKXPort0156], 10, [9,1], 10>;
 195
 196 defm : SKXWriteResPair<WriteFAdd,      [SKXPort01],  4, [1], 1, 5>; // Floating point add/sub.
 197 defm : SKXWriteResPair<WriteFAddX,     [SKXPort01],  4, [1], 1, 6>;
 198 defm : SKXWriteResPair<WriteFAddY,     [SKXPort01],  4, [1], 1, 7>;
 199 defm : SKXWriteResPair<WriteFAddZ,     [SKXPort05],  4, [1], 1, 7>;
 200 defm : SKXWriteResPair<WriteFAdd64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double add/sub.
 201 defm : SKXWriteResPair<WriteFAdd64X,   [SKXPort01],  4, [1], 1, 6>;
 202 defm : SKXWriteResPair<WriteFAdd64Y,   [SKXPort01],  4, [1], 1, 7>;
 203 defm : SKXWriteResPair<WriteFAdd64Z,   [SKXPort05],  4, [1], 1, 7>;
 204
 205 defm : SKXWriteResPair<WriteFCmp,      [SKXPort01],  4, [1], 1, 5>; // Floating point compare.
 206 defm : SKXWriteResPair<WriteFCmpX,     [SKXPort01],  4, [1], 1, 6>;
 207 defm : SKXWriteResPair<WriteFCmpY,     [SKXPort01],  4, [1], 1, 7>;
 208 defm : SKXWriteResPair<WriteFCmpZ,     [SKXPort05],  4, [1], 1, 7>;
 209 defm : SKXWriteResPair<WriteFCmp64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double compare.
 210 defm : SKXWriteResPair<WriteFCmp64X,   [SKXPort01],  4, [1], 1, 6>;
 211 defm : SKXWriteResPair<WriteFCmp64Y,   [SKXPort01],  4, [1], 1, 7>;
 212 defm : SKXWriteResPair<WriteFCmp64Z,   [SKXPort05],  4, [1], 1, 7>;
 213
 214 defm : SKXWriteResPair<WriteFCom,       [SKXPort0],  2>; // Floating point compare to flags.
 215
 216 defm : SKXWriteResPair<WriteFMul,      [SKXPort01],  4, [1], 1, 5>; // Floating point multiplication.
 217 defm : SKXWriteResPair<WriteFMulX,     [SKXPort01],  4, [1], 1, 6>;
 218 defm : SKXWriteResPair<WriteFMulY,     [SKXPort01],  4, [1], 1, 7>;
 219 defm : SKXWriteResPair<WriteFMulZ,     [SKXPort05],  4, [1], 1, 7>;
 220 defm : SKXWriteResPair<WriteFMul64,    [SKXPort01],  4, [1], 1, 5>; // Floating point double multiplication.
 221 defm : SKXWriteResPair<WriteFMul64X,   [SKXPort01],  4, [1], 1, 6>;
 222 defm : SKXWriteResPair<WriteFMul64Y,   [SKXPort01],  4, [1], 1, 7>;
 223 defm : SKXWriteResPair<WriteFMul64Z,   [SKXPort05],  4, [1], 1, 7>;
 224
 225 defm : SKXWriteResPair<WriteFDiv,     [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
 226 //defm : SKXWriteResPair<WriteFDivX,    [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles.
 227 defm : SKXWriteResPair<WriteFDivY,    [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles.
 228 defm : SKXWriteResPair<WriteFDivZ,    [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles.
 229 //defm : SKXWriteResPair<WriteFDiv64,   [SKXPort0,SKXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division.
 230 //defm : SKXWriteResPair<WriteFDiv64X,  [SKXPort0,SKXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles.
 231 //defm : SKXWriteResPair<WriteFDiv64Y,  [SKXPort0,SKXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles.
 232 defm : SKXWriteResPair<WriteFDiv64Z,  [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles.
 233
 234 defm : SKXWriteResPair<WriteFSqrt,    [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
 235 defm : SKXWriteResPair<WriteFSqrtX,   [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>;
 236 defm : SKXWriteResPair<WriteFSqrtY,   [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>;
 237 defm : SKXWriteResPair<WriteFSqrtZ,   [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>;
 238 defm : SKXWriteResPair<WriteFSqrt64,  [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
 239 defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>;
 240 defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>;
 241 defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>;
 242 defm : SKXWriteResPair<WriteFSqrt80,  [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root.
 243
 244 defm : SKXWriteResPair<WriteFRcp,   [SKXPort0],  4, [1], 1, 5>; // Floating point reciprocal estimate.
 245 defm : SKXWriteResPair<WriteFRcpX,  [SKXPort0],  4, [1], 1, 6>;
 246 defm : SKXWriteResPair<WriteFRcpY,  [SKXPort0],  4, [1], 1, 7>;
 247 defm : SKXWriteResPair<WriteFRcpZ,  [SKXPort0,SKXPort5],  4, [2,1], 3, 7>;
 248
 249 defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0],  4, [1], 1, 5>; // Floating point reciprocal square root estimate.
 250 defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0],  4, [1], 1, 6>;
 251 defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0],  4, [1], 1, 7>;
 252 defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5],  9, [2,1], 3, 7>;
 253
 254 defm : SKXWriteResPair<WriteFMA,  [SKXPort01],  4, [1], 1, 5>; // Fused Multiply Add.
 255 defm : SKXWriteResPair<WriteFMAX, [SKXPort01],  4, [1], 1, 6>;
 256 defm : SKXWriteResPair<WriteFMAY, [SKXPort01],  4, [1], 1, 7>;
 257 defm : SKXWriteResPair<WriteFMAZ, [SKXPort05],  4, [1], 1, 7>;
 258 defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015],  9, [1,2], 3, 6>; // Floating point double dot product.
 259 defm : SKXWriteResPair<WriteDPPS, [SKXPort5,SKXPort015], 13, [1,3], 4, 6>;
 260 defm : SKXWriteResPair<WriteDPPSY,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
 261 defm : SKXWriteResPair<WriteDPPSZ,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>;
 262 defm : SKXWriteResPair<WriteFSign,  [SKXPort0],  1>; // Floating point fabs/fchs.
 263 defm : SKXWriteResPair<WriteFRnd,   [SKXPort01], 8, [2], 2, 6>; // Floating point rounding.
 264 defm : SKXWriteResPair<WriteFRndY,  [SKXPort01], 8, [2], 2, 7>;
 265 defm : SKXWriteResPair<WriteFRndZ,  [SKXPort05], 8, [2], 2, 7>;
 266 defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
 267 defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>;
 268 defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>;
 269 defm : SKXWriteResPair<WriteFTest,  [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
 270 defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>;
 271 defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>;
 272 defm : SKXWriteResPair<WriteFShuffle,  [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
 273 defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>;
 274 defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 275 defm : SKXWriteResPair<WriteFVarShuffle,  [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
 276 defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
 277 defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 278 defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends.
 279 defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>;
 280 defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>;
 281 defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends.
 282 defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>;
 283 defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>;
 284
 285 // FMA Scheduling helper class.
 286 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 287
 288 // Vector integer operations.
 289 defm : X86WriteRes<WriteVecLoad,         [SKXPort23], 5, [1], 1>;
 290 defm : X86WriteRes<WriteVecLoadX,        [SKXPort23], 6, [1], 1>;
 291 defm : X86WriteRes<WriteVecLoadY,        [SKXPort23], 7, [1], 1>;
 292 defm : X86WriteRes<WriteVecLoadNT,       [SKXPort23], 6, [1], 1>;
 293 defm : X86WriteRes<WriteVecLoadNTY,      [SKXPort23], 7, [1], 1>;
 294 defm : X86WriteRes<WriteVecMaskedLoad,   [SKXPort23,SKXPort015], 7, [1,1], 2>;
 295 defm : X86WriteRes<WriteVecMaskedLoadY,  [SKXPort23,SKXPort015], 8, [1,1], 2>;
 296 defm : X86WriteRes<WriteVecStore,        [SKXPort237,SKXPort4], 1, [1,1], 2>;
 297 defm : X86WriteRes<WriteVecStoreX,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 298 defm : X86WriteRes<WriteVecStoreY,       [SKXPort237,SKXPort4], 1, [1,1], 2>;
 299 defm : X86WriteRes<WriteVecStoreNT,      [SKXPort237,SKXPort4], 1, [1,1], 2>;
 300 defm : X86WriteRes<WriteVecStoreNTY,     [SKXPort237,SKXPort4], 1, [1,1], 2>;
 301 defm : X86WriteRes<WriteVecMaskedStore,  [SKXPort237,SKXPort0], 2, [1,1], 2>;
 302 defm : X86WriteRes<WriteVecMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>;
 303 defm : X86WriteRes<WriteVecMove,         [SKXPort05],  1, [1], 1>;
 304 defm : X86WriteRes<WriteVecMoveX,        [SKXPort015], 1, [1], 1>;
 305 defm : X86WriteRes<WriteVecMoveY,        [SKXPort015], 1, [1], 1>;
 306 defm : X86WriteRes<WriteVecMoveToGpr,    [SKXPort0], 2, [1], 1>;
 307 defm : X86WriteRes<WriteVecMoveFromGpr,  [SKXPort5], 1, [1], 1>;
 308
 309 defm : SKXWriteResPair<WriteVecALU,   [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 310 defm : SKXWriteResPair<WriteVecALUX,  [SKXPort01], 1, [1], 1, 6>;
 311 defm : SKXWriteResPair<WriteVecALUY,  [SKXPort01], 1, [1], 1, 7>;
 312 defm : SKXWriteResPair<WriteVecALUZ,  [SKXPort0], 1, [1], 1, 7>;
 313 defm : SKXWriteResPair<WriteVecLogic, [SKXPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
 314 defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>;
 315 defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>;
 316 defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>;
 317 defm : SKXWriteResPair<WriteVecTest,  [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
 318 defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
 319 defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>;
 320 defm : SKXWriteResPair<WriteVecIMul,  [SKXPort0],    4, [1], 1, 5>; // Vector integer multiply.
 321 defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01],  4, [1], 1, 6>;
 322 defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01],  4, [1], 1, 7>;
 323 defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05],  4, [1], 1, 7>;
 324 defm : SKXWriteResPair<WritePMULLD,   [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD.
 325 defm : SKXWriteResPair<WritePMULLDY,  [SKXPort01], 10, [2], 2, 7>;
 326 defm : SKXWriteResPair<WritePMULLDZ,  [SKXPort05], 10, [2], 2, 7>;
 327 defm : SKXWriteResPair<WriteShuffle,  [SKXPort5], 1, [1], 1, 5>; // Vector shuffles.
 328 defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>;
 329 defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>;
 330 defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 331 defm : SKXWriteResPair<WriteVarShuffle,  [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 332 defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>;
 333 defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>;
 334 defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>;
 335 defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends.
 336 defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>;
 337 defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>;
 338 defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends.
 339 defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>;
 340 defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05],  2, [1], 1, 6>;
 341 defm : SKXWriteResPair<WriteMPSAD,   [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD.
 342 defm : SKXWriteResPair<WriteMPSADY,  [SKXPort5], 4, [2], 2, 7>;
 343 defm : SKXWriteResPair<WriteMPSADZ,  [SKXPort5], 4, [2], 2, 7>;
 344 defm : SKXWriteResPair<WritePSADBW,  [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW.
 345 defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>;
 346 defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>;
 347 defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>;
 348 defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS.
 349
 350 // Vector integer shifts.
 351 defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>;
 352 defm : X86WriteRes<WriteVecShiftX,    [SKXPort5,SKXPort01],  2, [1,1], 2>;
 353 defm : X86WriteRes<WriteVecShiftY,    [SKXPort5,SKXPort01],  4, [1,1], 2>;
 354 defm : X86WriteRes<WriteVecShiftZ,    [SKXPort5,SKXPort0],   4, [1,1], 2>;
 355 defm : X86WriteRes<WriteVecShiftXLd,  [SKXPort01,SKXPort23], 7, [1,1], 2>;
 356 defm : X86WriteRes<WriteVecShiftYLd,  [SKXPort01,SKXPort23], 8, [1,1], 2>;
 357 defm : X86WriteRes<WriteVecShiftZLd,  [SKXPort0,SKXPort23],  8, [1,1], 2>;
 358
 359 defm : SKXWriteResPair<WriteVecShiftImm,  [SKXPort0],  1, [1], 1, 5>;
 360 defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts.
 361 defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>;
 362 defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>;
 363 defm : SKXWriteResPair<WriteVarVecShift,  [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts.
 364 defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>;
 365 defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>;
 366
 367 // Vector insert/extract operations.
 368 def : WriteRes<WriteVecInsert, [SKXPort5]> {
 369   let Latency = 2;
 370   let NumMicroOps = 2;
 371   let ResourceCycles = [2];
 372 }
 373 def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> {
 374   let Latency = 6;
 375   let NumMicroOps = 2;
 376 }
 377 def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
 378
 379 def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> {
 380   let Latency = 3;
 381   let NumMicroOps = 2;
 382 }
 383 def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> {
 384   let Latency = 2;
 385   let NumMicroOps = 3;
 386 }
 387
 388 // Conversion between integer and float.
 389 defm : SKXWriteResPair<WriteCvtSS2I,   [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ.
 390 defm : SKXWriteResPair<WriteCvtPS2I,   [SKXPort01], 3>;
 391 defm : SKXWriteResPair<WriteCvtPS2IY,  [SKXPort01], 3>;
 392 defm : SKXWriteResPair<WriteCvtPS2IZ,  [SKXPort05], 3>;
 393 defm : SKXWriteResPair<WriteCvtSD2I,   [SKXPort01], 6, [2], 2>;
 394 defm : SKXWriteResPair<WriteCvtPD2I,   [SKXPort01], 3>;
 395 defm : SKXWriteResPair<WriteCvtPD2IY,  [SKXPort01], 3>;
 396 defm : SKXWriteResPair<WriteCvtPD2IZ,  [SKXPort05], 3>;
 397
 398 defm : SKXWriteResPair<WriteCvtI2SS,   [SKXPort1], 4>;
 399 defm : SKXWriteResPair<WriteCvtI2PS,   [SKXPort01], 4>;
 400 defm : SKXWriteResPair<WriteCvtI2PSY,  [SKXPort01], 4>;
 401 defm : SKXWriteResPair<WriteCvtI2PSZ,  [SKXPort05], 4>;  // Needs more work: DD vs DQ.
 402 defm : SKXWriteResPair<WriteCvtI2SD,   [SKXPort1], 4>;
 403 defm : SKXWriteResPair<WriteCvtI2PD,   [SKXPort01], 4>;
 404 defm : SKXWriteResPair<WriteCvtI2PDY,  [SKXPort01], 4>;
 405 defm : SKXWriteResPair<WriteCvtI2PDZ,  [SKXPort05], 4>;
 406
 407 defm : SKXWriteResPair<WriteCvtSS2SD,  [SKXPort1], 3>;
 408 defm : SKXWriteResPair<WriteCvtPS2PD,  [SKXPort1], 3>;
 409 defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
 410 defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>;
 411 defm : SKXWriteResPair<WriteCvtSD2SS,  [SKXPort1], 3>;
 412 defm : SKXWriteResPair<WriteCvtPD2PS,  [SKXPort1], 3>;
 413 defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 3, [1,1], 2>;
 414 defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort05], 3, [2], 2>;
 415
 416 defm : X86WriteRes<WriteCvtPH2PS,     [SKXPort5,SKXPort01],  5, [1,1], 2>;
 417 defm : X86WriteRes<WriteCvtPH2PSY,    [SKXPort5,SKXPort01],  7, [1,1], 2>;
 418 defm : X86WriteRes<WriteCvtPH2PSZ,    [SKXPort5,SKXPort0],   7, [1,1], 2>;
 419 defm : X86WriteRes<WriteCvtPH2PSLd,  [SKXPort23,SKXPort01],  9, [1,1], 2>;
 420 defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>;
 421 defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>;
 422
 423 defm : X86WriteRes<WriteCvtPS2PH,    [SKXPort5,SKXPort01], 5, [1,1], 2>;
 424 defm : X86WriteRes<WriteCvtPS2PHY,   [SKXPort5,SKXPort01], 7, [1,1], 2>;
 425 defm : X86WriteRes<WriteCvtPS2PHZ,   [SKXPort5,SKXPort05], 7, [1,1], 2>;
 426 defm : X86WriteRes<WriteCvtPS2PHSt,  [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>;
 427 defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>;
 428 defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>;
 429
 430 // Strings instructions.
 431
 432 // Packed Compare Implicit Length Strings, Return Mask
 433 def : WriteRes<WritePCmpIStrM, [SKXPort0]> {
 434   let Latency = 10;
 435   let NumMicroOps = 3;
 436   let ResourceCycles = [3];
 437 }
 438 def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> {
 439   let Latency = 16;
 440   let NumMicroOps = 4;
 441   let ResourceCycles = [3,1];
 442 }
 443
 444 // Packed Compare Explicit Length Strings, Return Mask
 445 def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> {
 446   let Latency = 19;
 447   let NumMicroOps = 9;
 448   let ResourceCycles = [4,3,1,1];
 449 }
 450 def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> {
 451   let Latency = 25;
 452   let NumMicroOps = 10;
 453   let ResourceCycles = [4,3,1,1,1];
 454 }
 455
 456 // Packed Compare Implicit Length Strings, Return Index
 457 def : WriteRes<WritePCmpIStrI, [SKXPort0]> {
 458   let Latency = 10;
 459   let NumMicroOps = 3;
 460   let ResourceCycles = [3];
 461 }
 462 def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> {
 463   let Latency = 16;
 464   let NumMicroOps = 4;
 465   let ResourceCycles = [3,1];
 466 }
 467
 468 // Packed Compare Explicit Length Strings, Return Index
 469 def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
 470   let Latency = 18;
 471   let NumMicroOps = 8;
 472   let ResourceCycles = [4,3,1];
 473 }
 474 def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
 475   let Latency = 24;
 476   let NumMicroOps = 9;
 477   let ResourceCycles = [4,3,1,1];
 478 }
 479
 480 // MOVMSK Instructions.
 481 def : WriteRes<WriteFMOVMSK,    [SKXPort0]> { let Latency = 2; }
 482 def : WriteRes<WriteVecMOVMSK,  [SKXPort0]> { let Latency = 2; }
 483 def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; }
 484 def : WriteRes<WriteMMXMOVMSK,  [SKXPort0]> { let Latency = 2; }
 485
 486 // AES instructions.
 487 def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
 488   let Latency = 4;
 489   let NumMicroOps = 1;
 490   let ResourceCycles = [1];
 491 }
 492 def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
 493   let Latency = 10;
 494   let NumMicroOps = 2;
 495   let ResourceCycles = [1,1];
 496 }
 497
 498 def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn.
 499   let Latency = 8;
 500   let NumMicroOps = 2;
 501   let ResourceCycles = [2];
 502 }
 503 def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> {
 504   let Latency = 14;
 505   let NumMicroOps = 3;
 506   let ResourceCycles = [2,1];
 507 }
 508
 509 def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation.
 510   let Latency = 20;
 511   let NumMicroOps = 11;
 512   let ResourceCycles = [3,6,2];
 513 }
 514 def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
 515   let Latency = 25;
 516   let NumMicroOps = 11;
 517   let ResourceCycles = [3,6,1,1];
 518 }
 519
 520 // Carry-less multiplication instructions.
 521 def : WriteRes<WriteCLMul, [SKXPort5]> {
 522   let Latency = 6;
 523   let NumMicroOps = 1;
 524   let ResourceCycles = [1];
 525 }
 526 def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> {
 527   let Latency = 12;
 528   let NumMicroOps = 2;
 529   let ResourceCycles = [1,1];
 530 }
 531
 532 // Catch-all for expensive system instructions.
 533 def : WriteRes<WriteSystem,     [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 534
 535 // AVX2.
 536 defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
 537 defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
 538 defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
 539 defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
 540
 541 // Old microcoded instructions that nobody use.
 542 def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 543
 544 // Fence instructions.
 545 def : WriteRes<WriteFence,  [SKXPort23, SKXPort4]>;
 546
 547 // Load/store MXCSR.
 548 def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 549 def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 550
 551 // Nop, not very useful expect it provides a model for nops!
 552 def : WriteRes<WriteNop, []>;
 553
 554 ////////////////////////////////////////////////////////////////////////////////
 555 // Horizontal add/sub  instructions.
 556 ////////////////////////////////////////////////////////////////////////////////
 557
 558 defm : SKXWriteResPair<WriteFHAdd,  [SKXPort5,SKXPort015], 6, [2,1], 3, 6>;
 559 defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>;
 560 defm : SKXWriteResPair<WritePHAdd,  [SKXPort5,SKXPort05],  3, [2,1], 3, 5>;
 561 defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>;
 562 defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>;
 563
 564 // Remaining instrs.
 565
 566 def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> {
 567   let Latency = 1;
 568   let NumMicroOps = 1;
 569   let ResourceCycles = [1];
 570 }
 571 def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr",
 572                                             "KANDN(B|D|Q|W)rr",
 573                                             "KMOV(B|D|Q|W)kk",
 574                                             "KNOT(B|D|Q|W)rr",
 575                                             "KOR(B|D|Q|W)rr",
 576                                             "KXNOR(B|D|Q|W)rr",
 577                                             "KXOR(B|D|Q|W)rr",
 578                                             "MMX_PADDS(B|W)irr",
 579                                             "MMX_PADDUS(B|W)irr",
 580                                             "MMX_PAVG(B|W)irr",
 581                                             "MMX_PCMPEQ(B|D|W)irr",
 582                                             "MMX_PCMPGT(B|D|W)irr",
 583                                             "MMX_P(MAX|MIN)SWirr",
 584                                             "MMX_P(MAX|MIN)UBirr",
 585                                             "MMX_PSUBS(B|W)irr",
 586                                             "MMX_PSUBUS(B|W)irr",
 587                                             "VPMOVB2M(Z|Z128|Z256)rr",
 588                                             "VPMOVD2M(Z|Z128|Z256)rr",
 589                                             "VPMOVQ2M(Z|Z128|Z256)rr",
 590                                             "VPMOVW2M(Z|Z128|Z256)rr")>;
 591
 592 def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> {
 593   let Latency = 1;
 594   let NumMicroOps = 1;
 595   let ResourceCycles = [1];
 596 }
 597 def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r",
 598                                             "KMOV(B|D|Q|W)kr",
 599                                             "UCOM_F(P?)r")>;
 600
 601 def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> {
 602   let Latency = 1;
 603   let NumMicroOps = 1;
 604   let ResourceCycles = [1];
 605 }
 606 def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 607
 608 def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> {
 609   let Latency = 1;
 610   let NumMicroOps = 1;
 611   let ResourceCycles = [1];
 612 }
 613 def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>;
 614
 615 def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> {
 616   let Latency = 1;
 617   let NumMicroOps = 1;
 618   let ResourceCycles = [1];
 619 }
 620 def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
 621 def: InstRW<[SKXWriteResGroup7], (instregex "BT(16|32|64)ri8",
 622                                             "BT(16|32|64)rr",
 623                                             "BTC(16|32|64)ri8",
 624                                             "BTC(16|32|64)rr",
 625                                             "BTR(16|32|64)ri8",
 626                                             "BTR(16|32|64)rr",
 627                                             "BTS(16|32|64)ri8",
 628                                             "BTS(16|32|64)rr")>;
 629
 630 def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> {
 631   let Latency = 1;
 632   let NumMicroOps = 1;
 633   let ResourceCycles = [1];
 634 }
 635 def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr",
 636                                             "BLSI(32|64)rr",
 637                                             "BLSMSK(32|64)rr",
 638                                             "BLSR(32|64)rr")>;
 639
 640 def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> {
 641   let Latency = 1;
 642   let NumMicroOps = 1;
 643   let ResourceCycles = [1];
 644 }
 645 def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr",
 646                                             "VBLENDMPS(Z128|Z256)rr",
 647                                             "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr",
 648                                             "(V?)PADD(B|D|Q|W)rr",
 649                                             "VPBLENDD(Y?)rri",
 650                                             "VPBLENDMB(Z128|Z256)rr",
 651                                             "VPBLENDMD(Z128|Z256)rr",
 652                                             "VPBLENDMQ(Z128|Z256)rr",
 653                                             "VPBLENDMW(Z128|Z256)rr",
 654                                             "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rr",
 655                                             "(V?)PSUB(B|D|Q|W)rr",
 656                                             "VPTERNLOGD(Z|Z128|Z256)rri",
 657                                             "VPTERNLOGQ(Z|Z128|Z256)rri")>;
 658
 659 def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> {
 660   let Latency = 1;
 661   let NumMicroOps = 1;
 662   let ResourceCycles = [1];
 663 }
 664 def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE,
 665                                           CMC, STC)>;
 666 def: InstRW<[SKXWriteResGroup10], (instregex "SGDT64m",
 667                                              "SIDT64m",
 668                                              "SMSW16m",
 669                                              "STRm",
 670                                              "SYSCALL")>;
 671
 672 def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> {
 673   let Latency = 1;
 674   let NumMicroOps = 2;
 675   let ResourceCycles = [1,1];
 676 }
 677 def: InstRW<[SKXWriteResGroup11], (instregex "FBSTPm",
 678                                              "KMOV(B|D|Q|W)mk",
 679                                              "ST_FP(32|64|80)m",
 680                                              "VMPTRSTm")>;
 681
 682 def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> {
 683   let Latency = 2;
 684   let NumMicroOps = 2;
 685   let ResourceCycles = [2];
 686 }
 687 def: InstRW<[SKXWriteResGroup13], (instregex "MMX_MOVQ2DQrr")>;
 688
 689 def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> {
 690   let Latency = 2;
 691   let NumMicroOps = 2;
 692   let ResourceCycles = [2];
 693 }
 694 def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP)>;
 695 def: InstRW<[SKXWriteResGroup14], (instregex "MMX_MOVDQ2Qrr")>;
 696
 697 def SKXWriteResGroup15 : SchedWriteRes<[SKXPort06]> {
 698   let Latency = 2;
 699   let NumMicroOps = 2;
 700   let ResourceCycles = [2];
 701 }
 702 def: InstRW<[SKXWriteResGroup15], (instregex "ROL(8|16|32|64)r1",
 703                                              "ROL(8|16|32|64)ri",
 704                                              "ROR(8|16|32|64)r1",
 705                                              "ROR(8|16|32|64)ri",
 706                                              "SET(A|BE)r")>;
 707
 708 def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> {
 709   let Latency = 2;
 710   let NumMicroOps = 2;
 711   let ResourceCycles = [2];
 712 }
 713 def: InstRW<[SKXWriteResGroup17], (instrs LFENCE,
 714                                           WAIT,
 715                                           XGETBV)>;
 716
 717 def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
 718   let Latency = 2;
 719   let NumMicroOps = 2;
 720   let ResourceCycles = [1,1];
 721 }
 722 def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>;
 723
 724 def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
 725   let Latency = 2;
 726   let NumMicroOps = 2;
 727   let ResourceCycles = [1,1];
 728 }
 729 def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>;
 730
 731 def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
 732   let Latency = 2;
 733   let NumMicroOps = 2;
 734   let ResourceCycles = [1,1];
 735 }
 736 def: InstRW<[SKXWriteResGroup23], (instrs CWD)>;
 737 def: InstRW<[SKXWriteResGroup23], (instrs JCXZ, JECXZ, JRCXZ)>;
 738 def: InstRW<[SKXWriteResGroup23], (instregex "ADC8i8",
 739                                              "ADC8ri",
 740                                              "SBB8i8",
 741                                              "SBB8ri")>;
 742
 743 def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> {
 744   let Latency = 2;
 745   let NumMicroOps = 3;
 746   let ResourceCycles = [1,1,1];
 747 }
 748 def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>;
 749
 750 def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
 751   let Latency = 2;
 752   let NumMicroOps = 3;
 753   let ResourceCycles = [1,1,1];
 754 }
 755 def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
 756
 757 def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
 758   let Latency = 2;
 759   let NumMicroOps = 3;
 760   let ResourceCycles = [1,1,1];
 761 }
 762 def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r,
 763                                           STOSB, STOSL, STOSQ, STOSW)>;
 764 def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr",
 765                                              "PUSH64i8")>;
 766
 767 def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> {
 768   let Latency = 2;
 769   let NumMicroOps = 5;
 770   let ResourceCycles = [2,2,1];
 771 }
 772 def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>;
 773
 774 def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> {
 775   let Latency = 3;
 776   let NumMicroOps = 1;
 777   let ResourceCycles = [1];
 778 }
 779 def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk",
 780                                              "KORTEST(B|D|Q|W)rr",
 781                                              "KTEST(B|D|Q|W)rr")>;
 782
 783 def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> {
 784   let Latency = 3;
 785   let NumMicroOps = 1;
 786   let ResourceCycles = [1];
 787 }
 788 def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr",
 789                                              "PEXT(32|64)rr")>;
 790
 791 def SKXWriteResGroup31_16i : SchedWriteRes<[SKXPort1, SKXPort0156]> {
 792   let Latency = 4;
 793   let NumMicroOps = 2;
 794   let ResourceCycles = [1,1];
 795 }
 796 def: InstRW<[SKXWriteResGroup31_16i], (instrs IMUL16rri, IMUL16rri8)>;
 797
 798
 799 def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> {
 800   let Latency = 3;
 801   let NumMicroOps = 1;
 802   let ResourceCycles = [1];
 803 }
 804 def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
 805                                              "KADD(B|D|Q|W)rr",
 806                                              "KSHIFTL(B|D|Q|W)ri",
 807                                              "KSHIFTR(B|D|Q|W)ri",
 808                                              "KUNPCKBWrr",
 809                                              "KUNPCKDQrr",
 810                                              "KUNPCKWDrr",
 811                                              "VALIGND(Z|Z128|Z256)rri",
 812                                              "VALIGNQ(Z|Z128|Z256)rri",
 813                                              "VCMPPD(Z|Z128|Z256)rri",
 814                                              "VCMPPS(Z|Z128|Z256)rri",
 815                                              "VCMPSDZrr",
 816                                              "VCMPSSZrr",
 817                                              "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined.
 818                                              "VFPCLASSPD(Z|Z128|Z256)rr",
 819                                              "VFPCLASSPS(Z|Z128|Z256)rr",
 820                                              "VFPCLASSSDZrr",
 821                                              "VFPCLASSSSZrr",
 822                                              "VPBROADCASTBrr",
 823                                              "VPBROADCASTWrr",
 824                                              "VPCMPB(Z|Z128|Z256)rri",
 825                                              "VPCMPD(Z|Z128|Z256)rri",
 826                                              "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr",
 827                                              "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr",
 828                                              "(V?)PCMPGTQ(Y?)rr",
 829                                              "VPCMPQ(Z|Z128|Z256)rri",
 830                                              "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri",
 831                                              "VPCMPW(Z|Z128|Z256)rri",
 832                                              "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr",
 833                                              "VPSADBWZrr", // TODO: 512-bit ops require ports 0/1 to be joined.
 834                                              "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>;
 835
 836 def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> {
 837   let Latency = 3;
 838   let NumMicroOps = 2;
 839   let ResourceCycles = [1,1];
 840 }
 841 def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>;
 842
 843 def SKXWriteResGroup35 : SchedWriteRes<[SKXPort06]> {
 844   let Latency = 3;
 845   let NumMicroOps = 3;
 846   let ResourceCycles = [3];
 847 }
 848 def: InstRW<[SKXWriteResGroup35], (instregex "ROL(8|16|32|64)rCL",
 849                                              "ROR(8|16|32|64)rCL",
 850                                              "SAR(8|16|32|64)rCL",
 851                                              "SHL(8|16|32|64)rCL",
 852                                              "SHR(8|16|32|64)rCL")>;
 853
 854 def SKXWriteResGroup36 : SchedWriteRes<[SKXPort0156]> {
 855   let Latency = 2;
 856   let NumMicroOps = 3;
 857   let ResourceCycles = [3];
 858 }
 859 def: InstRW<[SKXWriteResGroup36], (instrs XADD8rr, XADD16rr, XADD32rr, XADD64rr,
 860                                           XCHG8rr, XCHG16rr, XCHG32rr, XCHG64rr,
 861                                           XCHG16ar, XCHG32ar, XCHG64ar)>;
 862
 863 def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> {
 864   let Latency = 3;
 865   let NumMicroOps = 3;
 866   let ResourceCycles = [1,2];
 867 }
 868 def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>;
 869
 870 def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> {
 871   let Latency = 3;
 872   let NumMicroOps = 3;
 873   let ResourceCycles = [2,1];
 874 }
 875 def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>;
 876
 877 def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
 878   let Latency = 3;
 879   let NumMicroOps = 3;
 880   let ResourceCycles = [2,1];
 881 }
 882 def: InstRW<[SKXWriteResGroup41], (instregex "MMX_PACKSSDWirr",
 883                                              "MMX_PACKSSWBirr",
 884                                              "MMX_PACKUSWBirr")>;
 885
 886 def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
 887   let Latency = 3;
 888   let NumMicroOps = 3;
 889   let ResourceCycles = [1,2];
 890 }
 891 def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>;
 892
 893 def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> {
 894   let Latency = 3;
 895   let NumMicroOps = 3;
 896   let ResourceCycles = [1,2];
 897 }
 898 def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>;
 899
 900 def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
 901   let Latency = 3;
 902   let NumMicroOps = 3;
 903   let ResourceCycles = [1,2];
 904 }
 905 def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r1",
 906                                              "RCL(8|16|32|64)ri",
 907                                              "RCR(8|16|32|64)r1",
 908                                              "RCR(8|16|32|64)ri")>;
 909
 910 def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> {
 911   let Latency = 3;
 912   let NumMicroOps = 3;
 913   let ResourceCycles = [1,1,1];
 914 }
 915 def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>;
 916
 917 def SKXWriteResGroup46 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> {
 918   let Latency = 3;
 919   let NumMicroOps = 4;
 920   let ResourceCycles = [1,1,2];
 921 }
 922 def: InstRW<[SKXWriteResGroup46], (instregex "SET(A|BE)m")>;
 923
 924 def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> {
 925   let Latency = 3;
 926   let NumMicroOps = 4;
 927   let ResourceCycles = [1,1,1,1];
 928 }
 929 def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>;
 930
 931 def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> {
 932   let Latency = 3;
 933   let NumMicroOps = 4;
 934   let ResourceCycles = [1,1,1,1];
 935 }
 936 def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>;
 937
 938 def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> {
 939   let Latency = 4;
 940   let NumMicroOps = 1;
 941   let ResourceCycles = [1];
 942 }
 943 def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 944
 945 def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> {
 946   let Latency = 4;
 947   let NumMicroOps = 1;
 948   let ResourceCycles = [1];
 949 }
 950 def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr",
 951                                              "(V?)CVTDQ2PSrr",
 952                                              "VCVTPD2QQ(Z128|Z256)rr",
 953                                              "VCVTPD2UQQ(Z128|Z256)rr",
 954                                              "VCVTPS2DQ(Y|Z128|Z256)rr",
 955                                              "(V?)CVTPS2DQrr",
 956                                              "VCVTPS2UDQ(Z128|Z256)rr",
 957                                              "VCVTQQ2PD(Z128|Z256)rr",
 958                                              "VCVTTPD2QQ(Z128|Z256)rr",
 959                                              "VCVTTPD2UQQ(Z128|Z256)rr",
 960                                              "VCVTTPS2DQ(Z128|Z256)rr",
 961                                              "(V?)CVTTPS2DQrr",
 962                                              "VCVTTPS2UDQ(Z128|Z256)rr",
 963                                              "VCVTUDQ2PS(Z128|Z256)rr",
 964                                              "VCVTUQQ2PD(Z128|Z256)rr")>;
 965
 966 def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> {
 967   let Latency = 4;
 968   let NumMicroOps = 1;
 969   let ResourceCycles = [1];
 970 }
 971 def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr,
 972                                            VCVTPD2QQZrr,
 973                                            VCVTPD2UQQZrr,
 974                                            VCVTPS2DQZrr,
 975                                            VCVTPS2UDQZrr,
 976                                            VCVTQQ2PDZrr,
 977                                            VCVTTPD2QQZrr,
 978                                            VCVTTPD2UQQZrr,
 979                                            VCVTTPS2DQZrr,
 980                                            VCVTTPS2UDQZrr,
 981                                            VCVTUDQ2PSZrr,
 982                                            VCVTUQQ2PDZrr)>;
 983
 984 def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> {
 985   let Latency = 4;
 986   let NumMicroOps = 2;
 987   let ResourceCycles = [2];
 988 }
 989 def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr",
 990                                              "VEXPANDPS(Z|Z128|Z256)rr",
 991                                              "VPEXPANDD(Z|Z128|Z256)rr",
 992                                              "VPEXPANDQ(Z|Z128|Z256)rr",
 993                                              "VPMOVDB(Z|Z128|Z256)rr",
 994                                              "VPMOVDW(Z|Z128|Z256)rr",
 995                                              "VPMOVQB(Z|Z128|Z256)rr",
 996                                              "VPMOVQW(Z|Z128|Z256)rr",
 997                                              "VPMOVSDB(Z|Z128|Z256)rr",
 998                                              "VPMOVSDW(Z|Z128|Z256)rr",
 999                                              "VPMOVSQB(Z|Z128|Z256)rr",
1000                                              "VPMOVSQD(Z|Z128|Z256)rr",
1001                                              "VPMOVSQW(Z|Z128|Z256)rr",
1002                                              "VPMOVSWB(Z|Z128|Z256)rr",
1003                                              "VPMOVUSDB(Z|Z128|Z256)rr",
1004                                              "VPMOVUSDW(Z|Z128|Z256)rr",
1005                                              "VPMOVUSQB(Z|Z128|Z256)rr",
1006                                              "VPMOVUSQD(Z|Z128|Z256)rr",
1007                                              "VPMOVUSWB(Z|Z128|Z256)rr",
1008                                              "VPMOVWB(Z|Z128|Z256)rr")>;
1009
1010 def SKXWriteResGroup52 : SchedWriteRes<[SKXPort1,SKXPort5]> {
1011   let Latency = 4;
1012   let NumMicroOps = 2;
1013   let ResourceCycles = [1,1];
1014 }
1015 def: InstRW<[SKXWriteResGroup52], (instrs IMUL64r, MUL64r, MULX64rr)>;
1016
1017 def SKXWriteResGroup52_16 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1018   let Latency = 4;
1019   let NumMicroOps = 4;
1020   let ResourceCycles = [1,1,2];
1021 }
1022 def: InstRW<[SKXWriteResGroup52_16], (instrs IMUL16r, MUL16r)>;
1023
1024 def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1025   let Latency = 4;
1026   let NumMicroOps = 3;
1027   let ResourceCycles = [1,1,1];
1028 }
1029 def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m",
1030                                              "IST_F(16|32)m",
1031                                              "VPMOVQD(Z|Z128|Z256)mr(b?)")>;
1032
1033 def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> {
1034   let Latency = 4;
1035   let NumMicroOps = 4;
1036   let ResourceCycles = [4];
1037 }
1038 def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>;
1039
1040 def SKXWriteResGroup56 : SchedWriteRes<[SKXPort015,SKXPort0156]> {
1041   let Latency = 4;
1042   let NumMicroOps = 4;
1043   let ResourceCycles = [1,3];
1044 }
1045 def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>;
1046
1047 def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> {
1048   let Latency = 4;
1049   let NumMicroOps = 4;
1050   let ResourceCycles = [1,1,2];
1051 }
1052 def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1053
1054 def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> {
1055   let Latency = 5;
1056   let NumMicroOps = 1;
1057   let ResourceCycles = [1];
1058 }
1059 def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm16",
1060                                              "MOVSX(16|32|64)rm32",
1061                                              "MOVSX(16|32|64)rm8",
1062                                              "MOVZX(16|32|64)rm16",
1063                                              "MOVZX(16|32|64)rm8",
1064                                              "(V?)MOVDDUPrm")>;  // TODO: Should this be SKXWriteResGroup71?
1065
1066 def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1067   let Latency = 5;
1068   let NumMicroOps = 2;
1069   let ResourceCycles = [1,1];
1070 }
1071 def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr",
1072                                              "MMX_CVT(T?)PS2PIirr",
1073                                              "VCVTDQ2PDZ128rr",
1074                                              "VCVTPD2DQZ128rr",
1075                                              "(V?)CVT(T?)PD2DQrr",
1076                                              "VCVTPD2PSZ128rr",
1077                                              "(V?)CVTPD2PSrr",
1078                                              "VCVTPD2UDQZ128rr",
1079                                              "VCVTPS2PDZ128rr",
1080                                              "(V?)CVTPS2PDrr",
1081                                              "VCVTPS2QQZ128rr",
1082                                              "VCVTPS2UQQZ128rr",
1083                                              "VCVTQQ2PSZ128rr",
1084                                              "(V?)CVTSD2SS(Z?)rr",
1085                                              "(V?)CVTSI(64)?2SDrr",
1086                                              "VCVTSI2SSZrr",
1087                                              "(V?)CVTSI2SSrr",
1088                                              "VCVTSI(64)?2SDZrr",
1089                                              "VCVTSS2SDZrr",
1090                                              "(V?)CVTSS2SDrr",
1091                                              "VCVTTPD2DQZ128rr",
1092                                              "VCVTTPD2UDQZ128rr",
1093                                              "VCVTTPS2QQZ128rr",
1094                                              "VCVTTPS2UQQZ128rr",
1095                                              "VCVTUDQ2PDZ128rr",
1096                                              "VCVTUQQ2PSZ128rr",
1097                                              "VCVTUSI2SSZrr",
1098                                              "VCVTUSI(64)?2SDZrr")>;
1099
1100 def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1101   let Latency = 5;
1102   let NumMicroOps = 3;
1103   let ResourceCycles = [2,1];
1104 }
1105 def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>;
1106
1107 def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> {
1108   let Latency = 5;
1109   let NumMicroOps = 3;
1110   let ResourceCycles = [1,1,1];
1111 }
1112 def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>;
1113
1114 def SKXWriteResGroup64 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
1115   let Latency = 4;
1116   let NumMicroOps = 3;
1117   let ResourceCycles = [1,1,1];
1118 }
1119 def: InstRW<[SKXWriteResGroup64], (instrs IMUL32r, MUL32r, MULX32rr)>;
1120
1121 def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> {
1122   let Latency = 5;
1123   let NumMicroOps = 3;
1124   let ResourceCycles = [1,1,1];
1125 }
1126 def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)",
1127                                              "VCVTPS2PHZ256mr(b?)",
1128                                              "VCVTPS2PHZmr(b?)")>;
1129
1130 def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1131   let Latency = 5;
1132   let NumMicroOps = 4;
1133   let ResourceCycles = [1,2,1];
1134 }
1135 def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)",
1136                                              "VPMOVDW(Z|Z128|Z256)mr(b?)",
1137                                              "VPMOVQB(Z|Z128|Z256)mr(b?)",
1138                                              "VPMOVQW(Z|Z128|Z256)mr(b?)",
1139                                              "VPMOVSDB(Z|Z128|Z256)mr(b?)",
1140                                              "VPMOVSDW(Z|Z128|Z256)mr(b?)",
1141                                              "VPMOVSQB(Z|Z128|Z256)mr(b?)",
1142                                              "VPMOVSQD(Z|Z128|Z256)mr(b?)",
1143                                              "VPMOVSQW(Z|Z128|Z256)mr(b?)",
1144                                              "VPMOVSWB(Z|Z128|Z256)mr(b?)",
1145                                              "VPMOVUSDB(Z|Z128|Z256)mr(b?)",
1146                                              "VPMOVUSDW(Z|Z128|Z256)mr(b?)",
1147                                              "VPMOVUSQB(Z|Z128|Z256)mr(b?)",
1148                                              "VPMOVUSQD(Z|Z128|Z256)mr(b?)",
1149                                              "VPMOVUSQW(Z|Z128|Z256)mr(b?)",
1150                                              "VPMOVUSWB(Z|Z128|Z256)mr(b?)",
1151                                              "VPMOVWB(Z|Z128|Z256)mr(b?)")>;
1152
1153 def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1154   let Latency = 5;
1155   let NumMicroOps = 5;
1156   let ResourceCycles = [1,4];
1157 }
1158 def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>;
1159
1160 def SKXWriteResGroup68 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
1161   let Latency = 5;
1162   let NumMicroOps = 5;
1163   let ResourceCycles = [2,3];
1164 }
1165 def: InstRW<[SKXWriteResGroup68], (instregex "CMPXCHG(8|16|32|64)rr")>;
1166
1167 def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> {
1168   let Latency = 5;
1169   let NumMicroOps = 6;
1170   let ResourceCycles = [1,1,4];
1171 }
1172 def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>;
1173
1174 def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> {
1175   let Latency = 6;
1176   let NumMicroOps = 1;
1177   let ResourceCycles = [1];
1178 }
1179 def: InstRW<[SKXWriteResGroup71], (instregex "VBROADCASTSSrm",
1180                                              "(V?)MOVSHDUPrm",
1181                                              "(V?)MOVSLDUPrm",
1182                                              "VPBROADCASTDrm",
1183                                              "VPBROADCASTQrm")>;
1184
1185 def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> {
1186   let Latency = 6;
1187   let NumMicroOps = 2;
1188   let ResourceCycles = [2];
1189 }
1190 def: InstRW<[SKXWriteResGroup72], (instregex "MMX_CVTPI2PSirr",
1191                                              "VCOMPRESSPD(Z|Z128|Z256)rr",
1192                                              "VCOMPRESSPS(Z|Z128|Z256)rr",
1193                                              "VPCOMPRESSD(Z|Z128|Z256)rr",
1194                                              "VPCOMPRESSQ(Z|Z128|Z256)rr",
1195                                              "VPERMW(Z|Z128|Z256)rr")>;
1196
1197 def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1198   let Latency = 6;
1199   let NumMicroOps = 2;
1200   let ResourceCycles = [1,1];
1201 }
1202 def: InstRW<[SKXWriteResGroup73], (instregex "MMX_PADDSBirm",
1203                                              "MMX_PADDSWirm",
1204                                              "MMX_PADDUSBirm",
1205                                              "MMX_PADDUSWirm",
1206                                              "MMX_PAVGBirm",
1207                                              "MMX_PAVGWirm",
1208                                              "MMX_PCMPEQBirm",
1209                                              "MMX_PCMPEQDirm",
1210                                              "MMX_PCMPEQWirm",
1211                                              "MMX_PCMPGTBirm",
1212                                              "MMX_PCMPGTDirm",
1213                                              "MMX_PCMPGTWirm",
1214                                              "MMX_PMAXSWirm",
1215                                              "MMX_PMAXUBirm",
1216                                              "MMX_PMINSWirm",
1217                                              "MMX_PMINUBirm",
1218                                              "MMX_PSUBSBirm",
1219                                              "MMX_PSUBSWirm",
1220                                              "MMX_PSUBUSBirm",
1221                                              "MMX_PSUBUSWirm")>;
1222
1223 def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> {
1224   let Latency = 6;
1225   let NumMicroOps = 2;
1226   let ResourceCycles = [1,1];
1227 }
1228 def: InstRW<[SKXWriteResGroup76], (instregex "FARJMP64",
1229                                              "JMP(16|32|64)m")>;
1230
1231 def SKXWriteResGroup78 : SchedWriteRes<[SKXPort23,SKXPort06]> {
1232   let Latency = 6;
1233   let NumMicroOps = 2;
1234   let ResourceCycles = [1,1];
1235 }
1236 def: InstRW<[SKXWriteResGroup78], (instregex "BT(16|32|64)mi8")>;
1237
1238 def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> {
1239   let Latency = 6;
1240   let NumMicroOps = 2;
1241   let ResourceCycles = [1,1];
1242 }
1243 def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm",
1244                                              "BLSI(32|64)rm",
1245                                              "BLSMSK(32|64)rm",
1246                                              "BLSR(32|64)rm",
1247                                              "MOVBE(16|32|64)rm")>;
1248
1249 def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1250   let Latency = 6;
1251   let NumMicroOps = 2;
1252   let ResourceCycles = [1,1];
1253 }
1254 def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)",
1255                                              "VMOVDI2PDIZrm(b?)")>;
1256
1257 def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1258   let Latency = 6;
1259   let NumMicroOps = 2;
1260   let ResourceCycles = [1,1];
1261 }
1262 def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>;
1263 def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>;
1264
1265 def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1266   let Latency = 6;
1267   let NumMicroOps = 3;
1268   let ResourceCycles = [2,1];
1269 }
1270 def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr",
1271                                              "VCVTSI642SSZrr",
1272                                              "VCVTUSI642SSZrr")>;
1273
1274 def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> {
1275   let Latency = 6;
1276   let NumMicroOps = 4;
1277   let ResourceCycles = [1,1,1,1];
1278 }
1279 def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>;
1280
1281 def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1282   let Latency = 6;
1283   let NumMicroOps = 4;
1284   let ResourceCycles = [1,1,1,1];
1285 }
1286 def: InstRW<[SKXWriteResGroup86], (instregex "BTC(16|32|64)mi8",
1287                                              "BTR(16|32|64)mi8",
1288                                              "BTS(16|32|64)mi8",
1289                                              "SAR(8|16|32|64)m1",
1290                                              "SAR(8|16|32|64)mi",
1291                                              "SHL(8|16|32|64)m1",
1292                                              "SHL(8|16|32|64)mi",
1293                                              "SHR(8|16|32|64)m1",
1294                                              "SHR(8|16|32|64)mi")>;
1295
1296 def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1297   let Latency = 6;
1298   let NumMicroOps = 4;
1299   let ResourceCycles = [1,1,1,1];
1300 }
1301 def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm",
1302                                              "PUSH(16|32|64)rmm")>;
1303
1304 def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
1305   let Latency = 6;
1306   let NumMicroOps = 6;
1307   let ResourceCycles = [1,5];
1308 }
1309 def: InstRW<[SKXWriteResGroup88], (instrs STD)>;
1310
1311 def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> {
1312   let Latency = 7;
1313   let NumMicroOps = 1;
1314   let ResourceCycles = [1];
1315 }
1316 def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m",
1317                                              "VBROADCASTF128",
1318                                              "VBROADCASTI128",
1319                                              "VBROADCASTSDYrm",
1320                                              "VBROADCASTSSYrm",
1321                                              "VMOVDDUPYrm",
1322                                              "VMOVSHDUPYrm",
1323                                              "VMOVSLDUPYrm",
1324                                              "VPBROADCASTDYrm",
1325                                              "VPBROADCASTQYrm")>;
1326
1327 def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> {
1328   let Latency = 7;
1329   let NumMicroOps = 2;
1330   let ResourceCycles = [1,1];
1331 }
1332 def: InstRW<[SKXWriteResGroup90], (instregex "VCVTDQ2PDYrr")>;
1333
1334 def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1335   let Latency = 7;
1336   let NumMicroOps = 2;
1337   let ResourceCycles = [1,1];
1338 }
1339 def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)",
1340                                              "VMOVSSZrm(b?)")>;
1341
1342 def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> {
1343   let Latency = 6;
1344   let NumMicroOps = 2;
1345   let ResourceCycles = [1,1];
1346 }
1347 def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm",
1348                                               "(V?)PMOV(SX|ZX)BQrm",
1349                                               "(V?)PMOV(SX|ZX)BWrm",
1350                                               "(V?)PMOV(SX|ZX)DQrm",
1351                                               "(V?)PMOV(SX|ZX)WDrm",
1352                                               "(V?)PMOV(SX|ZX)WQrm")>;
1353
1354 def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1355   let Latency = 7;
1356   let NumMicroOps = 2;
1357   let ResourceCycles = [1,1];
1358 }
1359 def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr",
1360                                              "VCVTPD2DQ(Y|Z256)rr",
1361                                              "VCVTPD2PS(Y|Z256)rr",
1362                                              "VCVTPD2UDQZ256rr",
1363                                              "VCVTPS2PD(Y|Z256)rr",
1364                                              "VCVTPS2QQZ256rr",
1365                                              "VCVTPS2UQQZ256rr",
1366                                              "VCVTQQ2PSZ256rr",
1367                                              "VCVTTPD2DQ(Y|Z256)rr",
1368                                              "VCVTTPD2UDQZ256rr",
1369                                              "VCVTTPS2QQZ256rr",
1370                                              "VCVTTPS2UQQZ256rr",
1371                                              "VCVTUDQ2PDZ256rr",
1372                                              "VCVTUQQ2PSZ256rr")>;
1373
1374 def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> {
1375   let Latency = 7;
1376   let NumMicroOps = 2;
1377   let ResourceCycles = [1,1];
1378 }
1379 def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr,
1380                                            VCVTPD2DQZrr,
1381                                            VCVTPD2PSZrr,
1382                                            VCVTPD2UDQZrr,
1383                                            VCVTPS2PDZrr,
1384                                            VCVTPS2QQZrr,
1385                                            VCVTPS2UQQZrr,
1386                                            VCVTQQ2PSZrr,
1387                                            VCVTTPD2DQZrr,
1388                                            VCVTTPD2UDQZrr,
1389                                            VCVTTPS2QQZrr,
1390                                            VCVTTPS2UQQZrr,
1391                                            VCVTUDQ2PDZrr,
1392                                            VCVTUQQ2PSZrr)>;
1393
1394 def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1395   let Latency = 7;
1396   let NumMicroOps = 2;
1397   let ResourceCycles = [1,1];
1398 }
1399 def: InstRW<[SKXWriteResGroup95], (instregex "VBLENDMPDZ128rm(b?)",
1400                                              "VBLENDMPSZ128rm(b?)",
1401                                              "VBROADCASTI32X2Z128m(b?)",
1402                                              "VBROADCASTSSZ128m(b?)",
1403                                              "VINSERTF128rm",
1404                                              "VINSERTI128rm",
1405                                              "VMOVAPDZ128rm(b?)",
1406                                              "VMOVAPSZ128rm(b?)",
1407                                              "VMOVDDUPZ128rm(b?)",
1408                                              "VMOVDQA32Z128rm(b?)",
1409                                              "VMOVDQA64Z128rm(b?)",
1410                                              "VMOVDQU16Z128rm(b?)",
1411                                              "VMOVDQU32Z128rm(b?)",
1412                                              "VMOVDQU64Z128rm(b?)",
1413                                              "VMOVDQU8Z128rm(b?)",
1414                                              "VMOVNTDQAZ128rm(b?)",
1415                                              "VMOVSHDUPZ128rm(b?)",
1416                                              "VMOVSLDUPZ128rm(b?)",
1417                                              "VMOVUPDZ128rm(b?)",
1418                                              "VMOVUPSZ128rm(b?)",
1419                                              "VPADD(B|D|Q|W)Z128rm(b?)",
1420                                              "(V?)PADD(B|D|Q|W)rm",
1421                                              "VPBLENDDrmi",
1422                                              "VPBLENDM(B|D|Q|W)Z128rm(b?)",
1423                                              "VPBROADCASTDZ128m(b?)",
1424                                              "VPBROADCASTQZ128m(b?)",
1425                                              "VPSUB(B|D|Q|W)Z128rm(b?)",
1426                                              "(V?)PSUB(B|D|Q|W)rm",
1427                                              "VPTERNLOGDZ128rm(b?)i",
1428                                              "VPTERNLOGQZ128rm(b?)i")>;
1429
1430 def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1431   let Latency = 7;
1432   let NumMicroOps = 3;
1433   let ResourceCycles = [2,1];
1434 }
1435 def: InstRW<[SKXWriteResGroup96], (instregex "MMX_PACKSSDWirm",
1436                                              "MMX_PACKSSWBirm",
1437                                              "MMX_PACKUSWBirm")>;
1438
1439 def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> {
1440   let Latency = 7;
1441   let NumMicroOps = 3;
1442   let ResourceCycles = [2,1];
1443 }
1444 def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr",
1445                                              "VPERMI2W256rr",
1446                                              "VPERMI2Wrr",
1447                                              "VPERMT2W128rr",
1448                                              "VPERMT2W256rr",
1449                                              "VPERMT2Wrr")>;
1450
1451 def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> {
1452   let Latency = 7;
1453   let NumMicroOps = 3;
1454   let ResourceCycles = [1,2];
1455 }
1456 def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64,
1457                                           SCASB, SCASL, SCASQ, SCASW)>;
1458
1459 def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> {
1460   let Latency = 7;
1461   let NumMicroOps = 3;
1462   let ResourceCycles = [1,1,1];
1463 }
1464 def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr",
1465                                               "(V?)CVTSS2SI64(Z?)rr",
1466                                               "(V?)CVTTSS2SI64(Z?)rr",
1467                                               "VCVTTSS2USI64Zrr")>;
1468
1469 def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> {
1470   let Latency = 7;
1471   let NumMicroOps = 3;
1472   let ResourceCycles = [1,1,1];
1473 }
1474 def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>;
1475
1476 def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> {
1477   let Latency = 7;
1478   let NumMicroOps = 3;
1479   let ResourceCycles = [1,1,1];
1480 }
1481 def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>;
1482
1483 def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> {
1484   let Latency = 7;
1485   let NumMicroOps = 3;
1486   let ResourceCycles = [1,1,1];
1487 }
1488 def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>;
1489
1490 def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> {
1491   let Latency = 7;
1492   let NumMicroOps = 4;
1493   let ResourceCycles = [1,2,1];
1494 }
1495 def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)",
1496                                               "VCOMPRESSPS(Z|Z128|Z256)mr(b?)",
1497                                               "VPCOMPRESSD(Z|Z128|Z256)mr(b?)",
1498                                               "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>;
1499
1500 def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1501   let Latency = 7;
1502   let NumMicroOps = 5;
1503   let ResourceCycles = [1,1,1,2];
1504 }
1505 def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m1",
1506                                               "ROL(8|16|32|64)mi",
1507                                               "ROR(8|16|32|64)m1",
1508                                               "ROR(8|16|32|64)mi")>;
1509
1510 def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> {
1511   let Latency = 7;
1512   let NumMicroOps = 5;
1513   let ResourceCycles = [1,1,1,2];
1514 }
1515 def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>;
1516
1517 def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
1518   let Latency = 7;
1519   let NumMicroOps = 5;
1520   let ResourceCycles = [1,1,1,1,1];
1521 }
1522 def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m",
1523                                               "FARCALL64")>;
1524
1525 def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1526   let Latency = 7;
1527   let NumMicroOps = 7;
1528   let ResourceCycles = [1,2,2,2];
1529 }
1530 def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr,
1531                                            VPSCATTERQQZ128mr,
1532                                            VSCATTERDPDZ128mr,
1533                                            VSCATTERQPDZ128mr)>;
1534
1535 def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> {
1536   let Latency = 7;
1537   let NumMicroOps = 7;
1538   let ResourceCycles = [1,3,1,2];
1539 }
1540 def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>;
1541
1542 def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1543   let Latency = 7;
1544   let NumMicroOps = 11;
1545   let ResourceCycles = [1,4,4,2];
1546 }
1547 def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr,
1548                                            VPSCATTERQQZ256mr,
1549                                            VSCATTERDPDZ256mr,
1550                                            VSCATTERQPDZ256mr)>;
1551
1552 def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> {
1553   let Latency = 7;
1554   let NumMicroOps = 19;
1555   let ResourceCycles = [1,8,8,2];
1556 }
1557 def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr,
1558                                            VPSCATTERQQZmr,
1559                                            VSCATTERDPDZmr,
1560                                            VSCATTERQPDZmr)>;
1561
1562 def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1563   let Latency = 7;
1564   let NumMicroOps = 36;
1565   let ResourceCycles = [1,16,1,16,2];
1566 }
1567 def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>;
1568
1569 def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> {
1570   let Latency = 8;
1571   let NumMicroOps = 2;
1572   let ResourceCycles = [1,1];
1573 }
1574 def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm",
1575                                               "PEXT(32|64)rm")>;
1576
1577 def SKXWriteResGroup118_16_1 : SchedWriteRes<[SKXPort1, SKXPort0156, SKXPort23]> {
1578   let Latency = 8;
1579   let NumMicroOps = 3;
1580   let ResourceCycles = [1,1,1];
1581 }
1582 def: InstRW<[SKXWriteResGroup118_16_1], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
1583
1584 def SKXWriteResGroup118_16_2 : SchedWriteRes<[SKXPort1, SKXPort06, SKXPort0156, SKXPort23]> {
1585   let Latency = 9;
1586   let NumMicroOps = 5;
1587   let ResourceCycles = [1,1,2,1];
1588 }
1589 def: InstRW<[SKXWriteResGroup118_16_2], (instrs IMUL16m, MUL16m)>;
1590
1591 def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1592   let Latency = 8;
1593   let NumMicroOps = 2;
1594   let ResourceCycles = [1,1];
1595 }
1596 def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m",
1597                                               "VFPCLASSSDZrm(b?)",
1598                                               "VPBROADCASTBYrm",
1599                                               "VPBROADCASTB(Z|Z256)m(b?)",
1600                                               "VPBROADCASTWYrm",
1601                                               "VPBROADCASTW(Z|Z256)m(b?)",
1602                                               "VPMOVSXBDYrm",
1603                                               "VPMOVSXBQYrm",
1604                                               "VPMOVSXWQYrm")>;
1605
1606 def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1607   let Latency = 8;
1608   let NumMicroOps = 2;
1609   let ResourceCycles = [1,1];
1610 }
1611 def: InstRW<[SKXWriteResGroup121], (instregex "VBLENDMPD(Z|Z256)rm(b?)",
1612                                               "VBLENDMPS(Z|Z256)rm(b?)",
1613                                               "VBROADCASTF32X2Z256m(b?)",
1614                                               "VBROADCASTF32X2Zm(b?)",
1615                                               "VBROADCASTF32X4Z256rm(b?)",
1616                                               "VBROADCASTF32X4rm(b?)",
1617                                               "VBROADCASTF32X8rm(b?)",
1618                                               "VBROADCASTF64X2Z128rm(b?)",
1619                                               "VBROADCASTF64X2rm(b?)",
1620                                               "VBROADCASTF64X4rm(b?)",
1621                                               "VBROADCASTI32X2Z256m(b?)",
1622                                               "VBROADCASTI32X2Zm(b?)",
1623                                               "VBROADCASTI32X4Z256rm(b?)",
1624                                               "VBROADCASTI32X4rm(b?)",
1625                                               "VBROADCASTI32X8rm(b?)",
1626                                               "VBROADCASTI64X2Z128rm(b?)",
1627                                               "VBROADCASTI64X2rm(b?)",
1628                                               "VBROADCASTI64X4rm(b?)",
1629                                               "VBROADCASTSD(Z|Z256)m(b?)",
1630                                               "VBROADCASTSS(Z|Z256)m(b?)",
1631                                               "VINSERTF32x4(Z|Z256)rm(b?)",
1632                                               "VINSERTF32x8Zrm(b?)",
1633                                               "VINSERTF64x2(Z|Z256)rm(b?)",
1634                                               "VINSERTF64x4Zrm(b?)",
1635                                               "VINSERTI32x4(Z|Z256)rm(b?)",
1636                                               "VINSERTI32x8Zrm(b?)",
1637                                               "VINSERTI64x2(Z|Z256)rm(b?)",
1638                                               "VINSERTI64x4Zrm(b?)",
1639                                               "VMOVAPD(Z|Z256)rm(b?)",
1640                                               "VMOVAPS(Z|Z256)rm(b?)",
1641                                               "VMOVDDUP(Z|Z256)rm(b?)",
1642                                               "VMOVDQA32(Z|Z256)rm(b?)",
1643                                               "VMOVDQA64(Z|Z256)rm(b?)",
1644                                               "VMOVDQU16(Z|Z256)rm(b?)",
1645                                               "VMOVDQU32(Z|Z256)rm(b?)",
1646                                               "VMOVDQU64(Z|Z256)rm(b?)",
1647                                               "VMOVDQU8(Z|Z256)rm(b?)",
1648                                               "VMOVNTDQAZ256rm(b?)",
1649                                               "VMOVSHDUP(Z|Z256)rm(b?)",
1650                                               "VMOVSLDUP(Z|Z256)rm(b?)",
1651                                               "VMOVUPD(Z|Z256)rm(b?)",
1652                                               "VMOVUPS(Z|Z256)rm(b?)",
1653                                               "VPADD(B|D|Q|W)Yrm",
1654                                               "VPADD(B|D|Q|W)(Z|Z256)rm(b?)",
1655                                               "VPBLENDDYrmi",
1656                                               "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)",
1657                                               "VPBROADCASTD(Z|Z256)m(b?)",
1658                                               "VPBROADCASTQ(Z|Z256)m(b?)",
1659                                               "VPSUB(B|D|Q|W)Yrm",
1660                                               "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)",
1661                                               "VPTERNLOGD(Z|Z256)rm(b?)i",
1662                                               "VPTERNLOGQ(Z|Z256)rm(b?)i")>;
1663
1664 def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1665   let Latency = 8;
1666   let NumMicroOps = 4;
1667   let ResourceCycles = [1,2,1];
1668 }
1669 def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1670
1671 def SKXWriteResGroup126 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06]> {
1672   let Latency = 8;
1673   let NumMicroOps = 5;
1674   let ResourceCycles = [1,1,3];
1675 }
1676 def: InstRW<[SKXWriteResGroup126], (instregex "ROR(8|16|32|64)mCL")>;
1677
1678 def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1679   let Latency = 8;
1680   let NumMicroOps = 5;
1681   let ResourceCycles = [1,1,1,2];
1682 }
1683 def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m1",
1684                                               "RCL(8|16|32|64)mi",
1685                                               "RCR(8|16|32|64)m1",
1686                                               "RCR(8|16|32|64)mi")>;
1687
1688 def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> {
1689   let Latency = 8;
1690   let NumMicroOps = 6;
1691   let ResourceCycles = [1,1,1,3];
1692 }
1693 def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL",
1694                                               "SAR(8|16|32|64)mCL",
1695                                               "SHL(8|16|32|64)mCL",
1696                                               "SHR(8|16|32|64)mCL")>;
1697
1698 def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1699   let Latency = 8;
1700   let NumMicroOps = 6;
1701   let ResourceCycles = [1,1,1,2,1];
1702 }
1703 def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>;
1704 def: InstRW<[SKXWriteResGroup130], (instregex "CMPXCHG(8|16|32|64)rm")>;
1705
1706 def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1707   let Latency = 8;
1708   let NumMicroOps = 8;
1709   let ResourceCycles = [1,2,1,2,2];
1710 }
1711 def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr,
1712                                            VPSCATTERQDZ256mr,
1713                                            VSCATTERQPSZ128mr,
1714                                            VSCATTERQPSZ256mr)>;
1715
1716 def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1717   let Latency = 8;
1718   let NumMicroOps = 12;
1719   let ResourceCycles = [1,4,1,4,2];
1720 }
1721 def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr,
1722                                            VSCATTERDPSZ128mr)>;
1723
1724 def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1725   let Latency = 8;
1726   let NumMicroOps = 20;
1727   let ResourceCycles = [1,8,1,8,2];
1728 }
1729 def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr,
1730                                            VSCATTERDPSZ256mr)>;
1731
1732 def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> {
1733   let Latency = 8;
1734   let NumMicroOps = 36;
1735   let ResourceCycles = [1,16,1,16,2];
1736 }
1737 def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>;
1738
1739 def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1740   let Latency = 9;
1741   let NumMicroOps = 2;
1742   let ResourceCycles = [1,1];
1743 }
1744 def: InstRW<[SKXWriteResGroup135], (instregex "MMX_CVTPI2PSirm")>;
1745
1746 def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1747   let Latency = 9;
1748   let NumMicroOps = 2;
1749   let ResourceCycles = [1,1];
1750 }
1751 def: InstRW<[SKXWriteResGroup136], (instregex "VALIGNDZ128rm(b?)i",
1752                                               "VALIGNQZ128rm(b?)i",
1753                                               "VCMPPDZ128rm(b?)i",
1754                                               "VCMPPSZ128rm(b?)i",
1755                                               "VCMPSDZrm",
1756                                               "VCMPSSZrm",
1757                                               "VFPCLASSSSZrm(b?)",
1758                                               "VPCMPBZ128rmi(b?)",
1759                                               "VPCMPDZ128rmi(b?)",
1760                                               "VPCMPEQ(B|D|Q|W)Z128rm(b?)",
1761                                               "VPCMPGT(B|D|Q|W)Z128rm(b?)",
1762                                               "(V?)PCMPGTQrm",
1763                                               "VPCMPQZ128rmi(b?)",
1764                                               "VPCMPU(B|D|Q|W)Z128rmi(b?)",
1765                                               "VPCMPWZ128rmi(b?)",
1766                                               "VPERMI2D128rm(b?)",
1767                                               "VPERMI2PD128rm(b?)",
1768                                               "VPERMI2PS128rm(b?)",
1769                                               "VPERMI2Q128rm(b?)",
1770                                               "VPERMT2D128rm(b?)",
1771                                               "VPERMT2PD128rm(b?)",
1772                                               "VPERMT2PS128rm(b?)",
1773                                               "VPERMT2Q128rm(b?)",
1774                                               "VPMAXSQZ128rm(b?)",
1775                                               "VPMAXUQZ128rm(b?)",
1776                                               "VPMINSQZ128rm(b?)",
1777                                               "VPMINUQZ128rm(b?)",
1778                                               "VPMOVSXBDZ128rm(b?)",
1779                                               "VPMOVSXBQZ128rm(b?)",
1780                                               "VPMOVSXBWYrm",
1781                                               "VPMOVSXBWZ128rm(b?)",
1782                                               "VPMOVSXDQYrm",
1783                                               "VPMOVSXDQZ128rm(b?)",
1784                                               "VPMOVSXWDYrm",
1785                                               "VPMOVSXWDZ128rm(b?)",
1786                                               "VPMOVSXWQZ128rm(b?)",
1787                                               "VPMOVZXBDZ128rm(b?)",
1788                                               "VPMOVZXBQZ128rm(b?)",
1789                                               "VPMOVZXBWZ128rm(b?)",
1790                                               "VPMOVZXDQZ128rm(b?)",
1791                                               "VPMOVZXWDYrm",
1792                                               "VPMOVZXWDZ128rm(b?)",
1793                                               "VPMOVZXWQZ128rm(b?)",
1794                                               "VPTESTMBZ128rm(b?)",
1795                                               "VPTESTMDZ128rm(b?)",
1796                                               "VPTESTMQZ128rm(b?)",
1797                                               "VPTESTMWZ128rm(b?)",
1798                                               "VPTESTNMBZ128rm(b?)",
1799                                               "VPTESTNMDZ128rm(b?)",
1800                                               "VPTESTNMQZ128rm(b?)",
1801                                               "VPTESTNMWZ128rm(b?)")>;
1802
1803 def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1804   let Latency = 9;
1805   let NumMicroOps = 2;
1806   let ResourceCycles = [1,1];
1807 }
1808 def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm",
1809                                               "(V?)CVTPS2PDrm")>;
1810
1811 def SKXWriteResGroup142 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort23]> {
1812   let Latency = 9;
1813   let NumMicroOps = 3;
1814   let ResourceCycles = [1,1,1];
1815 }
1816 def: InstRW<[SKXWriteResGroup142], (instrs IMUL64m, MUL64m, MULX64rm)>;
1817
1818 def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1819   let Latency = 9;
1820   let NumMicroOps = 4;
1821   let ResourceCycles = [2,1,1];
1822 }
1823 def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm",
1824                                               "(V?)PHSUBSWrm")>;
1825
1826 def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
1827   let Latency = 9;
1828   let NumMicroOps = 5;
1829   let ResourceCycles = [1,2,1,1];
1830 }
1831 def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm",
1832                                               "LSL(16|32|64)rm")>;
1833
1834 def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1835   let Latency = 10;
1836   let NumMicroOps = 2;
1837   let ResourceCycles = [1,1];
1838 }
1839 def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1840                                               "ILD_F(16|32|64)m",
1841                                               "VALIGND(Z|Z256)rm(b?)i",
1842                                               "VALIGNQ(Z|Z256)rm(b?)i",
1843                                               "VCMPPD(Z|Z256)rm(b?)i",
1844                                               "VCMPPS(Z|Z256)rm(b?)i",
1845                                               "VPCMPB(Z|Z256)rmi(b?)",
1846                                               "VPCMPD(Z|Z256)rmi(b?)",
1847                                               "VPCMPEQB(Z|Z256)rm(b?)",
1848                                               "VPCMPEQD(Z|Z256)rm(b?)",
1849                                               "VPCMPEQQ(Z|Z256)rm(b?)",
1850                                               "VPCMPEQW(Z|Z256)rm(b?)",
1851                                               "VPCMPGTB(Z|Z256)rm(b?)",
1852                                               "VPCMPGTD(Z|Z256)rm(b?)",
1853                                               "VPCMPGTQYrm",
1854                                               "VPCMPGTQ(Z|Z256)rm(b?)",
1855                                               "VPCMPGTW(Z|Z256)rm(b?)",
1856                                               "VPCMPQ(Z|Z256)rmi(b?)",
1857                                               "VPCMPU(B|D|Q|W)Z256rmi(b?)",
1858                                               "VPCMPU(B|D|Q|W)Zrmi(b?)",
1859                                               "VPCMPW(Z|Z256)rmi(b?)",
1860                                               "VPMAXSQ(Z|Z256)rm(b?)",
1861                                               "VPMAXUQ(Z|Z256)rm(b?)",
1862                                               "VPMINSQ(Z|Z256)rm(b?)",
1863                                               "VPMINUQ(Z|Z256)rm(b?)",
1864                                               "VPTESTM(B|D|Q|W)Z256rm(b?)",
1865                                               "VPTESTM(B|D|Q|W)Zrm(b?)",
1866                                               "VPTESTNM(B|D|Q|W)Z256rm(b?)",
1867                                               "VPTESTNM(B|D|Q|W)Zrm(b?)")>;
1868
1869 def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1870   let Latency = 10;
1871   let NumMicroOps = 2;
1872   let ResourceCycles = [1,1];
1873 }
1874 def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)",
1875                                               "VCVTDQ2PSZ128rm(b?)",
1876                                               "(V?)CVTDQ2PSrm",
1877                                               "VCVTPD2QQZ128rm(b?)",
1878                                               "VCVTPD2UQQZ128rm(b?)",
1879                                               "VCVTPH2PSZ128rm(b?)",
1880                                               "VCVTPS2DQZ128rm(b?)",
1881                                               "(V?)CVTPS2DQrm",
1882                                               "VCVTPS2PDZ128rm(b?)",
1883                                               "VCVTPS2QQZ128rm(b?)",
1884                                               "VCVTPS2UDQZ128rm(b?)",
1885                                               "VCVTPS2UQQZ128rm(b?)",
1886                                               "VCVTQQ2PDZ128rm(b?)",
1887                                               "VCVTQQ2PSZ128rm(b?)",
1888                                               "VCVTSS2SDZrm",
1889                                               "(V?)CVTSS2SDrm",
1890                                               "VCVTTPD2QQZ128rm(b?)",
1891                                               "VCVTTPD2UQQZ128rm(b?)",
1892                                               "VCVTTPS2DQZ128rm(b?)",
1893                                               "(V?)CVTTPS2DQrm",
1894                                               "VCVTTPS2QQZ128rm(b?)",
1895                                               "VCVTTPS2UDQZ128rm(b?)",
1896                                               "VCVTTPS2UQQZ128rm(b?)",
1897                                               "VCVTUDQ2PDZ128rm(b?)",
1898                                               "VCVTUDQ2PSZ128rm(b?)",
1899                                               "VCVTUQQ2PDZ128rm(b?)",
1900                                               "VCVTUQQ2PSZ128rm(b?)")>;
1901
1902 def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1903   let Latency = 10;
1904   let NumMicroOps = 3;
1905   let ResourceCycles = [2,1];
1906 }
1907 def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)",
1908                                               "VEXPANDPSZ128rm(b?)",
1909                                               "VPEXPANDDZ128rm(b?)",
1910                                               "VPEXPANDQZ128rm(b?)")>;
1911
1912 def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
1913   let Latency = 10;
1914   let NumMicroOps = 3;
1915   let ResourceCycles = [1,1,1];
1916 }
1917 def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>;
1918
1919 def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> {
1920   let Latency = 10;
1921   let NumMicroOps = 4;
1922   let ResourceCycles = [2,1,1];
1923 }
1924 def: InstRW<[SKXWriteResGroup154], (instregex "VPHADDSWYrm",
1925                                               "VPHSUBSWYrm")>;
1926
1927 def SKXWriteResGroup156 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort06,SKXPort0156]> {
1928   let Latency = 9;
1929   let NumMicroOps = 4;
1930   let ResourceCycles = [1,1,1,1];
1931 }
1932 def: InstRW<[SKXWriteResGroup156], (instrs IMUL32m, MUL32m, MULX32rm)>;
1933
1934 def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
1935   let Latency = 10;
1936   let NumMicroOps = 8;
1937   let ResourceCycles = [1,1,1,1,1,3];
1938 }
1939 def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>;
1940
1941 def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
1942   let Latency = 11;
1943   let NumMicroOps = 1;
1944   let ResourceCycles = [1,3];
1945 }
1946 def : SchedAlias<WriteFDivX,  SKXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair
1947
1948 def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> {
1949   let Latency = 11;
1950   let NumMicroOps = 2;
1951   let ResourceCycles = [1,1];
1952 }
1953 def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>;
1954
1955 def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1956   let Latency = 11;
1957   let NumMicroOps = 2;
1958   let ResourceCycles = [1,1];
1959 }
1960 def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2PD(Z|Z256)rm(b?)",
1961                                               "VCVTDQ2PSYrm",
1962                                               "VCVTDQ2PS(Z|Z256)rm(b?)",
1963                                               "VCVTPH2PS(Z|Z256)rm(b?)",
1964                                               "VCVTPS2PDYrm",
1965                                               "VCVTPS2PD(Z|Z256)rm(b?)",
1966                                               "VCVTQQ2PD(Z|Z256)rm(b?)",
1967                                               "VCVTQQ2PSZ256rm(b?)",
1968                                               "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1969                                               "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1970                                               "VCVT(T?)PS2DQYrm",
1971                                               "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1972                                               "VCVT(T?)PS2QQZ256rm(b?)",
1973                                               "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1974                                               "VCVT(T?)PS2UQQZ256rm(b?)",
1975                                               "VCVTUDQ2PD(Z|Z256)rm(b?)",
1976                                               "VCVTUDQ2PS(Z|Z256)rm(b?)",
1977                                               "VCVTUQQ2PD(Z|Z256)rm(b?)",
1978                                               "VCVTUQQ2PSZ256rm(b?)")>;
1979
1980 def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> {
1981   let Latency = 11;
1982   let NumMicroOps = 3;
1983   let ResourceCycles = [2,1];
1984 }
1985 def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m",
1986                                               "VEXPANDPD(Z|Z256)rm(b?)",
1987                                               "VEXPANDPS(Z|Z256)rm(b?)",
1988                                               "VPEXPANDD(Z|Z256)rm(b?)",
1989                                               "VPEXPANDQ(Z|Z256)rm(b?)")>;
1990
1991 def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> {
1992   let Latency = 11;
1993   let NumMicroOps = 3;
1994   let ResourceCycles = [1,2];
1995 }
1996 def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>;
1997
1998 def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
1999   let Latency = 11;
2000   let NumMicroOps = 3;
2001   let ResourceCycles = [1,1,1];
2002 }
2003 def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>;
2004
2005 def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2006   let Latency = 11;
2007   let NumMicroOps = 3;
2008   let ResourceCycles = [1,1,1];
2009 }
2010 def: InstRW<[SKXWriteResGroup166], (instregex "CVTPD2PSrm",
2011                                               "CVT(T?)PD2DQrm",
2012                                               "MMX_CVT(T?)PD2PIirm")>;
2013
2014 def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2015   let Latency = 11;
2016   let NumMicroOps = 4;
2017   let ResourceCycles = [2,1,1];
2018 }
2019 def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>;
2020
2021 def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> {
2022   let Latency = 11;
2023   let NumMicroOps = 7;
2024   let ResourceCycles = [2,3,2];
2025 }
2026 def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL",
2027                                               "RCR(16|32|64)rCL")>;
2028
2029 def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
2030   let Latency = 11;
2031   let NumMicroOps = 9;
2032   let ResourceCycles = [1,5,1,2];
2033 }
2034 def: InstRW<[SKXWriteResGroup170], (instregex "RCL8rCL")>;
2035
2036 def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> {
2037   let Latency = 11;
2038   let NumMicroOps = 11;
2039   let ResourceCycles = [2,9];
2040 }
2041 def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>;
2042
2043 def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> {
2044   let Latency = 12;
2045   let NumMicroOps = 3;
2046   let ResourceCycles = [3];
2047 }
2048 def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>;
2049
2050 def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> {
2051   let Latency = 12;
2052   let NumMicroOps = 3;
2053   let ResourceCycles = [3];
2054 }
2055 def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>;
2056
2057 def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> {
2058   let Latency = 12;
2059   let NumMicroOps = 3;
2060   let ResourceCycles = [2,1];
2061 }
2062 def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>;
2063
2064 def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> {
2065   let Latency = 12;
2066   let NumMicroOps = 3;
2067   let ResourceCycles = [1,1,1];
2068 }
2069 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
2070                                               "VCVT(T?)SS2USI64Zrm(b?)")>;
2071
2072 def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2073   let Latency = 12;
2074   let NumMicroOps = 3;
2075   let ResourceCycles = [1,1,1];
2076 }
2077 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
2078                                               "VCVT(T?)PS2UQQZrm(b?)")>;
2079
2080 def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> {
2081   let Latency = 12;
2082   let NumMicroOps = 4;
2083   let ResourceCycles = [1,1,1,1];
2084 }
2085 def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>;
2086
2087 def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> {
2088   let Latency = 13;
2089   let NumMicroOps = 3;
2090   let ResourceCycles = [2,1];
2091 }
2092 def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m",
2093                                               "VPERMWZ256rm(b?)",
2094                                               "VPERMWZrm(b?)")>;
2095
2096 def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2097   let Latency = 13;
2098   let NumMicroOps = 3;
2099   let ResourceCycles = [1,1,1];
2100 }
2101 def: InstRW<[SKXWriteResGroup181], (instregex "VCVTDQ2PDYrm")>;
2102
2103 def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2104   let Latency = 13;
2105   let NumMicroOps = 4;
2106   let ResourceCycles = [2,1,1];
2107 }
2108 def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)",
2109                                               "VPERMT2W128rm(b?)")>;
2110
2111 def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2112   let Latency = 14;
2113   let NumMicroOps = 1;
2114   let ResourceCycles = [1,3];
2115 }
2116 def : SchedAlias<WriteFDiv64,  SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2117 def : SchedAlias<WriteFDiv64X, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair
2118
2119 def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> {
2120   let Latency = 14;
2121   let NumMicroOps = 1;
2122   let ResourceCycles = [1,5];
2123 }
2124 def : SchedAlias<WriteFDiv64Y, SKXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair
2125
2126 def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2127   let Latency = 14;
2128   let NumMicroOps = 3;
2129   let ResourceCycles = [1,1,1];
2130 }
2131 def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>;
2132
2133 def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2134   let Latency = 14;
2135   let NumMicroOps = 3;
2136   let ResourceCycles = [1,1,1];
2137 }
2138 def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)",
2139                                               "VCVTPD2PSZrm(b?)",
2140                                               "VCVTPD2UDQZrm(b?)",
2141                                               "VCVTQQ2PSZrm(b?)",
2142                                               "VCVTTPD2DQZrm(b?)",
2143                                               "VCVTTPD2UDQZrm(b?)",
2144                                               "VCVTUQQ2PSZrm(b?)")>;
2145
2146 def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> {
2147   let Latency = 14;
2148   let NumMicroOps = 4;
2149   let ResourceCycles = [2,1,1];
2150 }
2151 def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)",
2152                                               "VPERMI2Wrm(b?)",
2153                                               "VPERMT2W256rm(b?)",
2154                                               "VPERMT2Wrm(b?)")>;
2155
2156 def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> {
2157   let Latency = 14;
2158   let NumMicroOps = 10;
2159   let ResourceCycles = [2,4,1,3];
2160 }
2161 def: InstRW<[SKXWriteResGroup190], (instregex "RCR8rCL")>;
2162
2163 def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> {
2164   let Latency = 15;
2165   let NumMicroOps = 1;
2166   let ResourceCycles = [1];
2167 }
2168 def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
2169
2170 def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2171   let Latency = 15;
2172   let NumMicroOps = 8;
2173   let ResourceCycles = [1,2,2,1,2];
2174 }
2175 def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>;
2176
2177 def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2178   let Latency = 15;
2179   let NumMicroOps = 10;
2180   let ResourceCycles = [1,1,1,5,1,1];
2181 }
2182 def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>;
2183
2184 def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2185   let Latency = 16;
2186   let NumMicroOps = 14;
2187   let ResourceCycles = [1,1,1,4,2,5];
2188 }
2189 def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>;
2190
2191 def SKXWriteResGroup200 : SchedWriteRes<[SKXPort0156]> {
2192   let Latency = 16;
2193   let NumMicroOps = 16;
2194   let ResourceCycles = [16];
2195 }
2196 def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>;
2197
2198 def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2199   let Latency = 17;
2200   let NumMicroOps = 2;
2201   let ResourceCycles = [1,1,5];
2202 }
2203 def : SchedAlias<WriteFDivXLd, SKXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair
2204
2205 def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2206   let Latency = 17;
2207   let NumMicroOps = 15;
2208   let ResourceCycles = [2,1,2,4,2,4];
2209 }
2210 def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>;
2211
2212 def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2213   let Latency = 18;
2214   let NumMicroOps = 4;
2215   let ResourceCycles = [1,3];
2216 }
2217 def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>;
2218
2219 def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2220   let Latency = 18;
2221   let NumMicroOps = 8;
2222   let ResourceCycles = [1,1,1,5];
2223 }
2224 def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>;
2225
2226 def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> {
2227   let Latency = 18;
2228   let NumMicroOps = 11;
2229   let ResourceCycles = [2,1,1,4,1,2];
2230 }
2231 def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>;
2232
2233 def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2234   let Latency = 19;
2235   let NumMicroOps = 2;
2236   let ResourceCycles = [1,1,4];
2237 }
2238 def : SchedAlias<WriteFDiv64Ld,  SKXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair
2239
2240 def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort015]> {
2241   let Latency = 19;
2242   let NumMicroOps = 4;
2243   let ResourceCycles = [1,3];
2244 }
2245 def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)",
2246                                               "VPMULLQZrm(b?)")>;
2247
2248 def SKXWriteResGroup214 : SchedWriteRes<[]> {
2249   let Latency = 20;
2250   let NumMicroOps = 0;
2251 }
2252 def: InstRW<[SKXWriteResGroup214], (instrs VGATHERDPSZ128rm,
2253                                            VGATHERQPSZrm,
2254                                            VPGATHERDDZ128rm)>;
2255
2256 def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> {
2257   let Latency = 20;
2258   let NumMicroOps = 1;
2259   let ResourceCycles = [1];
2260 }
2261 def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
2262
2263 def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2264   let Latency = 20;
2265   let NumMicroOps = 2;
2266   let ResourceCycles = [1,1,4];
2267 }
2268 def : SchedAlias<WriteFDiv64XLd, SKXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair
2269
2270 def SKXWriteResGroup218 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2271   let Latency = 20;
2272   let NumMicroOps = 5;
2273   let ResourceCycles = [1,2,1,1];
2274 }
2275 def: InstRW<[SKXWriteResGroup218], (instrs VGATHERQPSZ128rm,
2276                                            VGATHERQPSZ256rm,
2277                                            VPGATHERQDZ128rm,
2278                                            VPGATHERQDZ256rm)>;
2279
2280 def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2281   let Latency = 20;
2282   let NumMicroOps = 8;
2283   let ResourceCycles = [1,1,1,1,1,1,2];
2284 }
2285 def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>;
2286
2287 def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> {
2288   let Latency = 20;
2289   let NumMicroOps = 10;
2290   let ResourceCycles = [1,2,7];
2291 }
2292 def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>;
2293
2294 def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> {
2295   let Latency = 21;
2296   let NumMicroOps = 2;
2297   let ResourceCycles = [1,1,8];
2298 }
2299 def : SchedAlias<WriteFDiv64YLd, SKXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair
2300
2301 def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2302   let Latency = 22;
2303   let NumMicroOps = 2;
2304   let ResourceCycles = [1,1];
2305 }
2306 def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>;
2307
2308 def SKXWriteResGroup224 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2309   let Latency = 22;
2310   let NumMicroOps = 5;
2311   let ResourceCycles = [1,2,1,1];
2312 }
2313 def: InstRW<[SKXWriteResGroup224], (instrs VGATHERDPDZ128rm,
2314                                            VGATHERQPDZ128rm,
2315                                            VPGATHERDQZ128rm,
2316                                            VPGATHERQQZ128rm)>;
2317
2318 def SKXWriteResGroup224_2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2319   let Latency = 22;
2320   let NumMicroOps = 5;
2321   let ResourceCycles = [1,2,1,1];
2322 }
2323 def: InstRW<[SKXWriteResGroup224_2], (instrs VGATHERDPSrm,
2324                                              VGATHERDPDrm,
2325                                              VGATHERQPDrm,
2326                                              VGATHERQPSrm,
2327                                              VPGATHERDDrm,
2328                                              VPGATHERDQrm,
2329                                              VPGATHERQDrm,
2330                                              VPGATHERQQrm,
2331                                              VPGATHERDDrm,
2332                                              VPGATHERQDrm,
2333                                              VPGATHERDQrm,
2334                                              VPGATHERQQrm,
2335                                              VGATHERDPSrm,
2336                                              VGATHERQPSrm,
2337                                              VGATHERDPDrm,
2338                                              VGATHERQPDrm)>;
2339
2340 def SKXWriteResGroup224_3 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> {
2341   let Latency = 25;
2342   let NumMicroOps = 5;
2343   let ResourceCycles = [1,2,1,1];
2344 }
2345 def: InstRW<[SKXWriteResGroup224_3], (instrs VGATHERDPSYrm,
2346                                              VGATHERQPDYrm,
2347                                              VGATHERQPSYrm,
2348                                              VPGATHERDDYrm,
2349                                              VPGATHERDQYrm,
2350                                              VPGATHERQDYrm,
2351                                              VPGATHERQQYrm,
2352                                              VPGATHERDDYrm,
2353                                              VPGATHERQDYrm,
2354                                              VPGATHERDQYrm,
2355                                              VPGATHERQQYrm,
2356                                              VGATHERDPSYrm,
2357                                              VGATHERQPSYrm,
2358                                              VGATHERDPDYrm)>;
2359
2360 def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2361   let Latency = 22;
2362   let NumMicroOps = 14;
2363   let ResourceCycles = [5,5,4];
2364 }
2365 def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr",
2366                                               "VPCONFLICTQZ256rr")>;
2367
2368 def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2369   let Latency = 23;
2370   let NumMicroOps = 19;
2371   let ResourceCycles = [2,1,4,1,1,4,6];
2372 }
2373 def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>;
2374
2375 def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2376   let Latency = 25;
2377   let NumMicroOps = 3;
2378   let ResourceCycles = [1,1,1];
2379 }
2380 def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>;
2381
2382 def SKXWriteResGroup234 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2383   let Latency = 25;
2384   let NumMicroOps = 5;
2385   let ResourceCycles = [1,2,1,1];
2386 }
2387 def: InstRW<[SKXWriteResGroup234], (instrs VGATHERDPDZ256rm,
2388                                            VGATHERQPDZ256rm,
2389                                            VPGATHERDQZ256rm,
2390                                            VPGATHERQDZrm,
2391                                            VPGATHERQQZ256rm)>;
2392
2393 def SKXWriteResGroup238 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2394   let Latency = 26;
2395   let NumMicroOps = 5;
2396   let ResourceCycles = [1,2,1,1];
2397 }
2398 def: InstRW<[SKXWriteResGroup238], (instrs VGATHERDPDZrm,
2399                                            VGATHERQPDZrm,
2400                                            VPGATHERDQZrm,
2401                                            VPGATHERQQZrm)>;
2402
2403 def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> {
2404   let Latency = 27;
2405   let NumMicroOps = 2;
2406   let ResourceCycles = [1,1];
2407 }
2408 def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>;
2409
2410 def SKXWriteResGroup240 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2411   let Latency = 27;
2412   let NumMicroOps = 5;
2413   let ResourceCycles = [1,2,1,1];
2414 }
2415 def: InstRW<[SKXWriteResGroup240], (instrs VGATHERDPSZ256rm,
2416                                            VPGATHERDDZ256rm)>;
2417
2418 def SKXWriteResGroup241 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort0156]> {
2419   let Latency = 28;
2420   let NumMicroOps = 8;
2421   let ResourceCycles = [2,4,1,1];
2422 }
2423 def: InstRW<[SKXWriteResGroup241], (instregex "IDIV(8|16|32|64)m")>;
2424
2425 def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2426   let Latency = 29;
2427   let NumMicroOps = 15;
2428   let ResourceCycles = [5,5,1,4];
2429 }
2430 def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>;
2431
2432 def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> {
2433   let Latency = 30;
2434   let NumMicroOps = 3;
2435   let ResourceCycles = [1,1,1];
2436 }
2437 def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>;
2438
2439 def SKXWriteResGroup245 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> {
2440   let Latency = 30;
2441   let NumMicroOps = 5;
2442   let ResourceCycles = [1,2,1,1];
2443 }
2444 def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm,
2445                                            VPGATHERDDZrm)>;
2446
2447 def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> {
2448   let Latency = 35;
2449   let NumMicroOps = 23;
2450   let ResourceCycles = [1,5,3,4,10];
2451 }
2452 def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri",
2453                                               "IN(8|16|32)rr")>;
2454
2455 def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> {
2456   let Latency = 35;
2457   let NumMicroOps = 23;
2458   let ResourceCycles = [1,5,2,1,4,10];
2459 }
2460 def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir",
2461                                               "OUT(8|16|32)rr")>;
2462
2463 def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2464   let Latency = 37;
2465   let NumMicroOps = 21;
2466   let ResourceCycles = [9,7,5];
2467 }
2468 def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr",
2469                                               "VPCONFLICTQZrr")>;
2470
2471 def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> {
2472   let Latency = 37;
2473   let NumMicroOps = 31;
2474   let ResourceCycles = [1,8,1,21];
2475 }
2476 def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>;
2477
2478 def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> {
2479   let Latency = 40;
2480   let NumMicroOps = 18;
2481   let ResourceCycles = [1,1,2,3,1,1,1,8];
2482 }
2483 def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>;
2484
2485 def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2486   let Latency = 41;
2487   let NumMicroOps = 39;
2488   let ResourceCycles = [1,10,1,1,26];
2489 }
2490 def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>;
2491
2492 def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> {
2493   let Latency = 42;
2494   let NumMicroOps = 22;
2495   let ResourceCycles = [2,20];
2496 }
2497 def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>;
2498
2499 def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> {
2500   let Latency = 42;
2501   let NumMicroOps = 40;
2502   let ResourceCycles = [1,11,1,1,26];
2503 }
2504 def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>;
2505 def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
2506
2507 def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2508   let Latency = 44;
2509   let NumMicroOps = 22;
2510   let ResourceCycles = [9,7,1,5];
2511 }
2512 def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)",
2513                                               "VPCONFLICTQZrm(b?)")>;
2514
2515 def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> {
2516   let Latency = 62;
2517   let NumMicroOps = 64;
2518   let ResourceCycles = [2,8,5,10,39];
2519 }
2520 def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>;
2521
2522 def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2523   let Latency = 63;
2524   let NumMicroOps = 88;
2525   let ResourceCycles = [4,4,31,1,2,1,45];
2526 }
2527 def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>;
2528
2529 def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> {
2530   let Latency = 63;
2531   let NumMicroOps = 90;
2532   let ResourceCycles = [4,2,33,1,2,1,47];
2533 }
2534 def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>;
2535
2536 def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> {
2537   let Latency = 67;
2538   let NumMicroOps = 35;
2539   let ResourceCycles = [17,11,7];
2540 }
2541 def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>;
2542
2543 def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> {
2544   let Latency = 74;
2545   let NumMicroOps = 36;
2546   let ResourceCycles = [17,11,1,7];
2547 }
2548 def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>;
2549
2550 def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> {
2551   let Latency = 75;
2552   let NumMicroOps = 15;
2553   let ResourceCycles = [6,3,6];
2554 }
2555 def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>;
2556
2557 def SKXWriteResGroup264 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> {
2558   let Latency = 76;
2559   let NumMicroOps = 32;
2560   let ResourceCycles = [7,2,8,3,1,11];
2561 }
2562 def: InstRW<[SKXWriteResGroup264], (instregex "DIV(16|32|64)r")>;
2563
2564 def SKXWriteResGroup265 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> {
2565   let Latency = 102;
2566   let NumMicroOps = 66;
2567   let ResourceCycles = [4,2,4,8,14,34];
2568 }
2569 def: InstRW<[SKXWriteResGroup265], (instregex "IDIV(16|32|64)r")>;
2570
2571 def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> {
2572   let Latency = 106;
2573   let NumMicroOps = 100;
2574   let ResourceCycles = [9,1,11,16,1,11,21,30];
2575 }
2576 def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>;
2577
2578 def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> {
2579   let Latency = 140;
2580   let NumMicroOps = 4;
2581   let ResourceCycles = [1,3];
2582 }
2583 def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>;
2584
2585 def: InstRW<[WriteZero], (instrs CLC)>;
2586
2587 } // SchedModel