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29 /* Assumes neon instructions and a cache line size of 32 bytes. */
31 #include <machine/cpu-features.h>
32 #include <machine/asm.h>
33 #include "libc_events.h"
36 * This code assumes it is running on a processor that supports all arm v7
37 * instructions, that supports neon instructions, and that has a 32 byte
41 #define CACHE_LINE_SIZE 32
48 bgt fortify_check_failed
50 // Fall through to memcpy...
55 /* start preloading as early as possible */
56 pld [r1, #(CACHE_LINE_SIZE*4)]
59 /* do we have at least 16-bytes to copy (needed for alignment below) */
63 /* align destination to cache-line for the write-buffer */
68 /* copy up to 15-bytes (count in r3) */
79 // copies 4 bytes, destination 32-bits aligned
80 vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]!
81 vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0, :32]!
83 // copies 8 bytes, destination 64-bits aligned
85 vst1.8 {d0}, [r0, :64]!
87 2: /* make sure we have at least 64 bytes to copy */
91 1: /* The main loop copies 64 bytes at a time */
92 vld1.8 {d0 - d3}, [r1]!
93 vld1.8 {d4 - d7}, [r1]!
94 pld [r1, #(CACHE_LINE_SIZE*2)]
96 vst1.8 {d0 - d3}, [r0, :128]!
97 vst1.8 {d4 - d7}, [r0, :128]!
100 2: /* fix-up the remaining count and make sure we have >= 32 bytes left */
104 /* Copy 32 bytes. These cache lines were already preloaded */
105 vld1.8 {d0 - d3}, [r1]!
107 vst1.8 {d0 - d3}, [r0, :128]!
109 4: /* less than 32 left */
113 // copies 16 bytes, 128-bits aligned
114 vld1.8 {d0, d1}, [r1]!
115 vst1.8 {d0, d1}, [r0, :128]!
117 5: /* copy up to 15-bytes (count in r2) */
123 vld4.8 {d0[0], d1[0], d2[0], d3[0]}, [r1]!
124 vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]!
125 2: movs ip, r2, lsl #31
136 // Only reached when the __memcpy_chk check fails.
137 fortify_check_failed:
138 ldr r0, error_message
142 bl __fortify_chk_fail
144 .word BIONIC_EVENT_MEMCPY_BUFFER_OVERFLOW
146 .word error_string-(1b+8)
151 .string "memcpy buffer overflow"