1 /* Copyright (C) 1997, 1998, 1999, 2004, 2006 Free Software Foundation, Inc.
2 This file is part of the GNU C Library.
4 The GNU C Library is free software; you can redistribute it and/or
5 modify it under the terms of the GNU Lesser General Public
6 License as published by the Free Software Foundation; either
7 version 2.1 of the License, or (at your option) any later version.
9 The GNU C Library is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 Lesser General Public License for more details.
14 You should have received a copy of the GNU Lesser General Public
15 License along with the GNU C Library; if not, write to the Free
16 Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 # error "Never use <bits/fenv.h> directly; include <fenv.h> instead."
25 #ifdef __CONFIG_E500__
27 /* Define bits representing the exception. We use the bit positions of
28 the appropriate bits in the SPEFSCR... */
31 FE_INEXACT = 1 << (63 - 42),
32 #define FE_INEXACT FE_INEXACT
33 FE_INVALID = 1 << (63 - 43),
34 #define FE_INVALID FE_INVALID
35 FE_DIVBYZERO = 1 << (63 - 44),
36 #define FE_DIVBYZERO FE_DIVBYZERO
37 FE_UNDERFLOW = 1 << (63 - 45),
38 #define FE_UNDERFLOW FE_UNDERFLOW
39 FE_OVERFLOW = 1 << (63 - 46)
40 #define FE_OVERFLOW FE_OVERFLOW
43 #else /* PowerPC 6xx floating-point. */
45 /* Define bits representing the exception. We use the bit positions of
46 the appropriate bits in the FPSCR... */
49 FE_INEXACT = 1 << (31 - 6),
50 #define FE_INEXACT FE_INEXACT
51 FE_DIVBYZERO = 1 << (31 - 5),
52 #define FE_DIVBYZERO FE_DIVBYZERO
53 FE_UNDERFLOW = 1 << (31 - 4),
54 #define FE_UNDERFLOW FE_UNDERFLOW
55 FE_OVERFLOW = 1 << (31 - 3),
56 #define FE_OVERFLOW FE_OVERFLOW
58 /* ... except for FE_INVALID, for which we use bit 31. FE_INVALID
59 actually corresponds to bits 7 through 12 and 21 through 23
60 in the FPSCR, but we can't use that because the current draft
61 says that it must be a power of 2. Instead we use bit 2 which
62 is the summary bit for all the FE_INVALID exceptions, which
63 kind of makes sense. */
64 FE_INVALID = 1 << (31 - 2),
65 #define FE_INVALID FE_INVALID
68 /* Breakdown of the FE_INVALID bits. Setting FE_INVALID on an
69 input to a routine is equivalent to setting all of these bits;
70 FE_INVALID will be set on output from a routine iff one of
71 these bits is set. Note, though, that you can't disable or
72 enable these exceptions individually. */
74 /* Operation with SNaN. */
75 FE_INVALID_SNAN = 1 << (31 - 7),
76 # define FE_INVALID_SNAN FE_INVALID_SNAN
79 FE_INVALID_ISI = 1 << (31 - 8),
80 # define FE_INVALID_ISI FE_INVALID_ISI
83 FE_INVALID_IDI = 1 << (31 - 9),
84 # define FE_INVALID_IDI FE_INVALID_IDI
87 FE_INVALID_ZDZ = 1 << (31 - 10),
88 # define FE_INVALID_ZDZ FE_INVALID_ZDZ
91 FE_INVALID_IMZ = 1 << (31 - 11),
92 # define FE_INVALID_IMZ FE_INVALID_IMZ
94 /* Comparison with NaN or SNaN. */
95 FE_INVALID_COMPARE = 1 << (31 - 12),
96 # define FE_INVALID_COMPARE FE_INVALID_COMPARE
98 /* Invalid operation flag for software (not set by hardware). */
99 /* Note that some chips don't have this implemented, presumably
100 because no-one expected anyone to write software for them %-). */
101 FE_INVALID_SOFTWARE = 1 << (31 - 21),
102 # define FE_INVALID_SOFTWARE FE_INVALID_SOFTWARE
104 /* Square root of negative number (including -Inf). */
105 /* Note that some chips don't have this implemented. */
106 FE_INVALID_SQRT = 1 << (31 - 22),
107 # define FE_INVALID_SQRT FE_INVALID_SQRT
109 /* Conversion-to-integer of a NaN or a number too large or too small. */
110 FE_INVALID_INTEGER_CONVERSION = 1 << (31 - 23)
111 # define FE_INVALID_INTEGER_CONVERSION FE_INVALID_INTEGER_CONVERSION
113 # define FE_ALL_INVALID \
114 (FE_INVALID_SNAN | FE_INVALID_ISI | FE_INVALID_IDI | FE_INVALID_ZDZ \
115 | FE_INVALID_IMZ | FE_INVALID_COMPARE | FE_INVALID_SOFTWARE \
116 | FE_INVALID_SQRT | FE_INVALID_INTEGER_CONVERSION)
117 #endif /* __USE_GNU */
120 #endif /* __CONFIG_E500__ */
122 #define FE_ALL_EXCEPT \
123 (FE_INEXACT | FE_DIVBYZERO | FE_UNDERFLOW | FE_OVERFLOW | FE_INVALID)
125 /* PowerPC chips support all of the four defined rounding modes. We
126 use the bit pattern in the FPSCR as the values for the
127 appropriate macros. */
131 #define FE_TONEAREST FE_TONEAREST
133 #define FE_TOWARDZERO FE_TOWARDZERO
135 #define FE_UPWARD FE_UPWARD
137 #define FE_DOWNWARD FE_DOWNWARD
140 /* Type representing exception flags. */
141 typedef unsigned int fexcept_t;
143 /* Type representing floating-point environment. We leave it as 'double'
144 for efficiency reasons (rather than writing it to a 32-bit integer). */
145 typedef double fenv_t;
147 /* If the default argument is used we use this value. */
148 extern const fenv_t __fe_dfl_env;
149 #define FE_DFL_ENV (&__fe_dfl_env)
152 /* Floating-point environment where all exceptions are enabled. Note that
153 this is not sufficient to give you SIGFPE. */
154 extern const fenv_t __fe_enabled_env;
155 # define FE_ENABLED_ENV (&__fe_enabled_env)
157 /* Floating-point environment with (processor-dependent) non-IEEE floating
159 extern const fenv_t __fe_nonieee_env;
160 # define FE_NONIEEE_ENV (&__fe_nonieee_env)
162 /* Floating-point environment with all exceptions enabled. Note that
163 just evaluating this value will set the processor into 'FPU
164 exceptions imprecise recoverable' mode, which may cause a significant
165 performance penalty (but have no other visible effect). */
166 extern const fenv_t *__fe_nomask_env (void);
167 # define FE_NOMASK_ENV (__fe_nomask_env ())
168 #endif /* __USE_GNU */