1 /**************************************************************************
3 * Copyright © 2007 Red Hat Inc.
4 * Copyright © 2007 Intel Corporation
5 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * The above copyright notice and this permission notice (including the
25 * next paragraph) shall be included in all copies or substantial portions
29 **************************************************************************/
31 * Authors: Thomas Hellström <thomas-at-tungstengraphics-dot-com>
32 * Keith Whitwell <keithw-at-tungstengraphics-dot-com>
33 * Eric Anholt <eric@anholt.net>
34 * Dave Airlie <airlied@linux.ie>
49 #include <sys/ioctl.h>
52 #include <sys/types.h>
55 #include "libdrm_lists.h"
56 #include "intel_bufmgr.h"
57 #include "intel_bufmgr_priv.h"
58 #include "intel_chipset.h"
63 #define DBG(...) do { \
64 if (bufmgr_gem->bufmgr.debug) \
65 fprintf(stderr, __VA_ARGS__); \
68 typedef struct _drm_intel_bo_gem drm_intel_bo_gem;
70 struct drm_intel_gem_bo_bucket {
74 * Limit on the number of entries in this bucket.
76 * 0 means that this caching at this bucket size is disabled.
77 * -1 means that there is no limit to caching at this size.
83 /* Arbitrarily chosen, 16 means that the maximum size we'll cache for reuse
84 * is 1 << 16 pages, or 256MB.
86 #define DRM_INTEL_GEM_BO_BUCKETS 16
87 typedef struct _drm_intel_bufmgr_gem {
88 drm_intel_bufmgr bufmgr;
96 struct drm_i915_gem_exec_object *exec_objects;
97 drm_intel_bo **exec_bos;
101 /** Array of lists of cached gem objects of power-of-two sizes */
102 struct drm_intel_gem_bo_bucket cache_bucket[DRM_INTEL_GEM_BO_BUCKETS];
105 int available_fences;
107 } drm_intel_bufmgr_gem;
109 struct _drm_intel_bo_gem {
113 /** Boolean whether the mmap ioctl has been called for this buffer yet. */
118 * Kenel-assigned global name for this object
120 unsigned int global_name;
123 * Index of the buffer within the validation list while preparing a
124 * batchbuffer execution.
129 * Boolean whether we've started swrast
130 * Set when the buffer has been mapped
131 * Cleared when the buffer is unmapped
136 * Current tiling mode
138 uint32_t tiling_mode;
139 uint32_t swizzle_mode;
141 /** Array passed to the DRM containing relocation information. */
142 struct drm_i915_gem_relocation_entry *relocs;
143 /** Array of bos corresponding to relocs[i].target_handle */
144 drm_intel_bo **reloc_target_bo;
145 /** Number of entries in relocs */
147 /** Mapped address for the buffer, saved across map/unmap cycles */
149 /** GTT virtual address for the buffer, saved across map/unmap cycles */
156 * Boolean of whether this BO and its children have been included in
157 * the current drm_intel_bufmgr_check_aperture_space() total.
159 char included_in_check_aperture;
162 * Boolean of whether this buffer has been used as a relocation
163 * target and had its size accounted for, and thus can't have any
164 * further relocations added to it.
166 char used_as_reloc_target;
169 * Boolean of whether this buffer can be re-used
174 * Size in bytes of this buffer and its relocation descendents.
176 * Used to avoid costly tree walking in drm_intel_bufmgr_check_aperture in
181 * Number of potential fence registers required by this buffer and its
184 int reloc_tree_fences;
187 static void drm_intel_gem_bo_reference_locked(drm_intel_bo *bo);
190 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count);
193 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count);
196 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
197 uint32_t *swizzle_mode);
200 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
204 drm_intel_gem_bo_unreference(drm_intel_bo *bo);
220 static struct drm_intel_gem_bo_bucket *
221 drm_intel_gem_bo_bucket_for_size(drm_intel_bufmgr_gem *bufmgr_gem,
226 /* We only do buckets in power of two increments */
227 if ((size & (size - 1)) != 0)
230 /* We should only see sizes rounded to pages. */
231 assert((size % 4096) == 0);
233 /* We always allocate in units of pages */
234 i = ffs(size / 4096) - 1;
235 if (i >= DRM_INTEL_GEM_BO_BUCKETS)
238 return &bufmgr_gem->cache_bucket[i];
242 static void drm_intel_gem_dump_validation_list(drm_intel_bufmgr_gem *bufmgr_gem)
246 for (i = 0; i < bufmgr_gem->exec_count; i++) {
247 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
248 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
250 if (bo_gem->relocs == NULL) {
251 DBG("%2d: %d (%s)\n", i, bo_gem->gem_handle, bo_gem->name);
255 for (j = 0; j < bo_gem->reloc_count; j++) {
256 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[j];
257 drm_intel_bo_gem *target_gem = (drm_intel_bo_gem *)target_bo;
259 DBG("%2d: %d (%s)@0x%08llx -> %d (%s)@0x%08lx + 0x%08x\n",
261 bo_gem->gem_handle, bo_gem->name,
262 (unsigned long long)bo_gem->relocs[j].offset,
263 target_gem->gem_handle, target_gem->name, target_bo->offset,
264 bo_gem->relocs[j].delta);
270 * Adds the given buffer to the list of buffers to be validated (moved into the
271 * appropriate memory type) with the next batch submission.
273 * If a buffer is validated multiple times in a batch submission, it ends up
274 * with the intersection of the memory type flags and the union of the
278 drm_intel_add_validate_buffer(drm_intel_bo *bo)
280 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
281 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
284 if (bo_gem->validate_index != -1)
287 /* Extend the array of validation entries as necessary. */
288 if (bufmgr_gem->exec_count == bufmgr_gem->exec_size) {
289 int new_size = bufmgr_gem->exec_size * 2;
294 bufmgr_gem->exec_objects =
295 realloc(bufmgr_gem->exec_objects,
296 sizeof(*bufmgr_gem->exec_objects) * new_size);
297 bufmgr_gem->exec_bos =
298 realloc(bufmgr_gem->exec_bos,
299 sizeof(*bufmgr_gem->exec_bos) * new_size);
300 bufmgr_gem->exec_size = new_size;
303 index = bufmgr_gem->exec_count;
304 bo_gem->validate_index = index;
305 /* Fill in array entry */
306 bufmgr_gem->exec_objects[index].handle = bo_gem->gem_handle;
307 bufmgr_gem->exec_objects[index].relocation_count = bo_gem->reloc_count;
308 bufmgr_gem->exec_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs;
309 bufmgr_gem->exec_objects[index].alignment = 0;
310 bufmgr_gem->exec_objects[index].offset = 0;
311 bufmgr_gem->exec_bos[index] = bo;
312 drm_intel_gem_bo_reference_locked(bo);
313 bufmgr_gem->exec_count++;
317 #define RELOC_BUF_SIZE(x) ((I915_RELOC_HEADER + x * I915_RELOC0_STRIDE) * \
321 drm_intel_setup_reloc_list(drm_intel_bo *bo)
323 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
324 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
326 bo_gem->relocs = malloc(bufmgr_gem->max_relocs *
327 sizeof(struct drm_i915_gem_relocation_entry));
328 bo_gem->reloc_target_bo = malloc(bufmgr_gem->max_relocs *
329 sizeof(drm_intel_bo *));
334 static drm_intel_bo *
335 drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, const char *name,
336 unsigned long size, unsigned int alignment,
339 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
340 drm_intel_bo_gem *bo_gem;
341 unsigned int page_size = getpagesize();
343 struct drm_intel_gem_bo_bucket *bucket;
344 int alloc_from_cache = 0;
345 unsigned long bo_size;
347 /* Round the allocated size up to a power of two number of pages. */
348 bo_size = 1 << logbase2(size);
349 if (bo_size < page_size)
351 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo_size);
353 /* If we don't have caching at this size, don't actually round the
356 if (bucket == NULL || bucket->max_entries == 0) {
358 if (bo_size < page_size)
362 pthread_mutex_lock(&bufmgr_gem->lock);
363 /* Get a buffer out of the cache if available */
364 if (bucket != NULL && bucket->num_entries > 0) {
365 struct drm_i915_gem_busy busy;
368 /* Allocate new render-target BOs from the tail (MRU)
369 * of the list, as it will likely be hot in the GPU cache
370 * and in the aperture for us.
372 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.prev, head);
373 DRMLISTDEL(&bo_gem->head);
374 bucket->num_entries--;
375 alloc_from_cache = 1;
377 /* For non-render-target BOs (where we're probably going to map it
378 * first thing in order to fill it with data), check if the
379 * last BO in the cache is unbusy, and only reuse in that case.
380 * Otherwise, allocating a new buffer is probably faster than
381 * waiting for the GPU to finish.
383 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head);
385 memset(&busy, 0, sizeof(busy));
386 busy.handle = bo_gem->gem_handle;
388 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_BUSY, &busy);
389 alloc_from_cache = (ret == 0 && busy.busy == 0);
391 if (alloc_from_cache) {
392 DRMLISTDEL(&bo_gem->head);
393 bucket->num_entries--;
397 pthread_mutex_unlock(&bufmgr_gem->lock);
399 if (!alloc_from_cache) {
400 struct drm_i915_gem_create create;
402 bo_gem = calloc(1, sizeof(*bo_gem));
406 bo_gem->bo.size = bo_size;
407 memset(&create, 0, sizeof(create));
408 create.size = bo_size;
410 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_CREATE, &create);
411 bo_gem->gem_handle = create.handle;
412 bo_gem->bo.handle = bo_gem->gem_handle;
417 bo_gem->bo.bufmgr = bufmgr;
421 bo_gem->refcount = 1;
422 bo_gem->validate_index = -1;
423 bo_gem->reloc_tree_size = bo_gem->bo.size;
424 bo_gem->reloc_tree_fences = 0;
425 bo_gem->used_as_reloc_target = 0;
426 bo_gem->tiling_mode = I915_TILING_NONE;
427 bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
428 bo_gem->reusable = 1;
430 DBG("bo_create: buf %d (%s) %ldb\n",
431 bo_gem->gem_handle, bo_gem->name, size);
436 static drm_intel_bo *
437 drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, const char *name,
438 unsigned long size, unsigned int alignment)
440 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, alignment, 1);
443 static drm_intel_bo *
444 drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, const char *name,
445 unsigned long size, unsigned int alignment)
447 return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, alignment, 0);
451 * Returns a drm_intel_bo wrapping the given buffer object handle.
453 * This can be used when one application needs to pass a buffer object
457 drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, const char *name,
460 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
461 drm_intel_bo_gem *bo_gem;
463 struct drm_gem_open open_arg;
464 struct drm_i915_gem_get_tiling get_tiling;
466 bo_gem = calloc(1, sizeof(*bo_gem));
470 memset(&open_arg, 0, sizeof(open_arg));
471 open_arg.name = handle;
472 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
474 fprintf(stderr, "Couldn't reference %s handle 0x%08x: %s\n",
475 name, handle, strerror(errno));
479 bo_gem->bo.size = open_arg.size;
480 bo_gem->bo.offset = 0;
481 bo_gem->bo.virtual = NULL;
482 bo_gem->bo.bufmgr = bufmgr;
484 bo_gem->refcount = 1;
485 bo_gem->validate_index = -1;
486 bo_gem->gem_handle = open_arg.handle;
487 bo_gem->global_name = handle;
488 bo_gem->reusable = 0;
490 memset(&get_tiling, 0, sizeof(get_tiling));
491 get_tiling.handle = bo_gem->gem_handle;
492 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_TILING, &get_tiling);
494 drm_intel_gem_bo_unreference(&bo_gem->bo);
497 bo_gem->tiling_mode = get_tiling.tiling_mode;
498 bo_gem->swizzle_mode = get_tiling.swizzle_mode;
499 if (bo_gem->tiling_mode == I915_TILING_NONE)
500 bo_gem->reloc_tree_fences = 0;
502 bo_gem->reloc_tree_fences = 1;
504 DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name);
510 drm_intel_gem_bo_reference(drm_intel_bo *bo)
512 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
513 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
515 assert(bo_gem->refcount > 0);
516 pthread_mutex_lock(&bufmgr_gem->lock);
518 pthread_mutex_unlock(&bufmgr_gem->lock);
522 drm_intel_gem_bo_reference_locked(drm_intel_bo *bo)
524 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
526 assert(bo_gem->refcount > 0);
531 drm_intel_gem_bo_free(drm_intel_bo *bo)
533 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
534 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
535 struct drm_gem_close close;
538 if (bo_gem->mem_virtual)
539 munmap (bo_gem->mem_virtual, bo_gem->bo.size);
540 if (bo_gem->gtt_virtual)
541 munmap (bo_gem->gtt_virtual, bo_gem->bo.size);
543 /* Close this object */
544 memset(&close, 0, sizeof(close));
545 close.handle = bo_gem->gem_handle;
546 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_CLOSE, &close);
549 "DRM_IOCTL_GEM_CLOSE %d failed (%s): %s\n",
550 bo_gem->gem_handle, bo_gem->name, strerror(errno));
556 drm_intel_gem_bo_unreference_locked(drm_intel_bo *bo)
558 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
559 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
561 assert(bo_gem->refcount > 0);
562 if (--bo_gem->refcount == 0) {
563 struct drm_intel_gem_bo_bucket *bucket;
564 uint32_t tiling_mode;
566 if (bo_gem->relocs != NULL) {
569 /* Unreference all the target buffers */
570 for (i = 0; i < bo_gem->reloc_count; i++)
571 drm_intel_gem_bo_unreference_locked(bo_gem->reloc_target_bo[i]);
572 free(bo_gem->reloc_target_bo);
573 free(bo_gem->relocs);
576 DBG("bo_unreference final: %d (%s)\n",
577 bo_gem->gem_handle, bo_gem->name);
579 bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size);
580 /* Put the buffer into our internal cache for reuse if we can. */
581 tiling_mode = I915_TILING_NONE;
582 if (bo_gem->reusable &&
584 (bucket->max_entries == -1 ||
585 (bucket->max_entries > 0 &&
586 bucket->num_entries < bucket->max_entries)) &&
587 drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0)
590 bo_gem->validate_index = -1;
591 bo_gem->relocs = NULL;
592 bo_gem->reloc_target_bo = NULL;
593 bo_gem->reloc_count = 0;
595 DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
596 bucket->num_entries++;
598 drm_intel_gem_bo_free(bo);
604 drm_intel_gem_bo_unreference(drm_intel_bo *bo)
606 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
608 pthread_mutex_lock(&bufmgr_gem->lock);
609 drm_intel_gem_bo_unreference_locked(bo);
610 pthread_mutex_unlock(&bufmgr_gem->lock);
614 drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable)
616 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
617 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
618 struct drm_i915_gem_set_domain set_domain;
621 pthread_mutex_lock(&bufmgr_gem->lock);
623 /* Allow recursive mapping. Mesa may recursively map buffers with
624 * nested display loops.
626 if (!bo_gem->mem_virtual) {
627 struct drm_i915_gem_mmap mmap_arg;
629 DBG("bo_map: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
631 memset(&mmap_arg, 0, sizeof(mmap_arg));
632 mmap_arg.handle = bo_gem->gem_handle;
634 mmap_arg.size = bo->size;
635 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MMAP, &mmap_arg);
637 fprintf(stderr, "%s:%d: Error mapping buffer %d (%s): %s .\n",
639 bo_gem->gem_handle, bo_gem->name, strerror(errno));
640 pthread_mutex_unlock(&bufmgr_gem->lock);
643 bo_gem->mem_virtual = (void *)(uintptr_t)mmap_arg.addr_ptr;
646 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
647 bo_gem->mem_virtual);
648 bo->virtual = bo_gem->mem_virtual;
650 if (bo_gem->global_name != 0 || !bo_gem->swrast) {
651 set_domain.handle = bo_gem->gem_handle;
652 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
654 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
656 set_domain.write_domain = 0;
658 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
660 } while (ret == -1 && errno == EINTR);
662 fprintf (stderr, "%s:%d: Error setting swrast %d: %s\n",
663 __FILE__, __LINE__, bo_gem->gem_handle, strerror (errno));
664 pthread_mutex_unlock(&bufmgr_gem->lock);
670 pthread_mutex_unlock(&bufmgr_gem->lock);
676 drm_intel_gem_bo_map_gtt(drm_intel_bo *bo)
678 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
679 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
680 struct drm_i915_gem_set_domain set_domain;
683 pthread_mutex_lock(&bufmgr_gem->lock);
685 /* Get a mapping of the buffer if we haven't before. */
686 if (bo_gem->gtt_virtual == NULL) {
687 struct drm_i915_gem_mmap_gtt mmap_arg;
689 DBG("bo_map_gtt: %d (%s)\n", bo_gem->gem_handle, bo_gem->name);
691 memset(&mmap_arg, 0, sizeof(mmap_arg));
692 mmap_arg.handle = bo_gem->gem_handle;
694 /* Get the fake offset back... */
695 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &mmap_arg);
698 "%s:%d: Error preparing buffer map %d (%s): %s .\n",
700 bo_gem->gem_handle, bo_gem->name,
702 pthread_mutex_unlock(&bufmgr_gem->lock);
707 bo_gem->gtt_virtual = mmap(0, bo->size, PROT_READ | PROT_WRITE,
708 MAP_SHARED, bufmgr_gem->fd,
710 if (bo_gem->gtt_virtual == MAP_FAILED) {
712 "%s:%d: Error mapping buffer %d (%s): %s .\n",
714 bo_gem->gem_handle, bo_gem->name,
716 pthread_mutex_unlock(&bufmgr_gem->lock);
721 bo->virtual = bo_gem->gtt_virtual;
723 DBG("bo_map: %d (%s) -> %p\n", bo_gem->gem_handle, bo_gem->name,
724 bo_gem->gtt_virtual);
726 /* Now move it to the GTT domain so that the CPU caches are flushed */
727 set_domain.handle = bo_gem->gem_handle;
728 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
729 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
731 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN,
733 } while (ret == -1 && errno == EINTR);
736 fprintf (stderr, "%s:%d: Error setting domain %d: %s\n",
737 __FILE__, __LINE__, bo_gem->gem_handle, strerror (errno));
740 pthread_mutex_unlock(&bufmgr_gem->lock);
746 drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo)
748 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
749 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
750 struct drm_i915_gem_sw_finish sw_finish;
756 assert(bo_gem->gtt_virtual != NULL);
758 pthread_mutex_lock(&bufmgr_gem->lock);
760 pthread_mutex_unlock(&bufmgr_gem->lock);
766 drm_intel_gem_bo_unmap(drm_intel_bo *bo)
768 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
769 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
770 struct drm_i915_gem_sw_finish sw_finish;
776 assert(bo_gem->mem_virtual != NULL);
778 pthread_mutex_lock(&bufmgr_gem->lock);
779 if (bo_gem->swrast) {
780 sw_finish.handle = bo_gem->gem_handle;
782 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SW_FINISH,
784 } while (ret == -1 && errno == EINTR);
788 pthread_mutex_unlock(&bufmgr_gem->lock);
793 drm_intel_gem_bo_subdata (drm_intel_bo *bo, unsigned long offset,
794 unsigned long size, const void *data)
796 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
797 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
798 struct drm_i915_gem_pwrite pwrite;
801 memset (&pwrite, 0, sizeof (pwrite));
802 pwrite.handle = bo_gem->gem_handle;
803 pwrite.offset = offset;
805 pwrite.data_ptr = (uint64_t) (uintptr_t) data;
807 ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite);
808 } while (ret == -1 && errno == EINTR);
810 fprintf (stderr, "%s:%d: Error writing data to buffer %d: (%d %d) %s .\n",
812 bo_gem->gem_handle, (int) offset, (int) size,
819 drm_intel_gem_get_pipe_from_crtc_id (drm_intel_bufmgr *bufmgr, int crtc_id)
821 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr;
822 struct drm_i915_get_pipe_from_crtc_id get_pipe_from_crtc_id;
825 get_pipe_from_crtc_id.crtc_id = crtc_id;
826 ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID,
827 &get_pipe_from_crtc_id);
829 /* We return -1 here to signal that we don't
830 * know which pipe is associated with this crtc.
831 * This lets the caller know that this information
832 * isn't available; using the wrong pipe for
833 * vblank waiting can cause the chipset to lock up
838 return get_pipe_from_crtc_id.pipe;
842 drm_intel_gem_bo_get_subdata (drm_intel_bo *bo, unsigned long offset,
843 unsigned long size, void *data)
845 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
846 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
847 struct drm_i915_gem_pread pread;
850 memset (&pread, 0, sizeof (pread));
851 pread.handle = bo_gem->gem_handle;
852 pread.offset = offset;
854 pread.data_ptr = (uint64_t) (uintptr_t) data;
856 ret = ioctl (bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PREAD, &pread);
857 } while (ret == -1 && errno == EINTR);
859 fprintf (stderr, "%s:%d: Error reading data from buffer %d: (%d %d) %s .\n",
861 bo_gem->gem_handle, (int) offset, (int) size,
867 /** Waits for all GPU rendering to the object to have completed. */
869 drm_intel_gem_bo_wait_rendering(drm_intel_bo *bo)
871 return drm_intel_gem_bo_start_gtt_access(bo, 0);
875 * Sets the object to the GTT read and possibly write domain, used by the X
876 * 2D driver in the absence of kernel support to do drm_intel_gem_bo_map_gtt().
878 * In combination with drm_intel_gem_bo_pin() and manual fence management, we
879 * can do tiled pixmaps this way.
882 drm_intel_gem_bo_start_gtt_access(drm_intel_bo *bo, int write_enable)
884 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
885 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
886 struct drm_i915_gem_set_domain set_domain;
889 set_domain.handle = bo_gem->gem_handle;
890 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
891 set_domain.write_domain = write_enable ? I915_GEM_DOMAIN_GTT : 0;
893 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
894 } while (ret == -1 && errno == EINTR);
896 fprintf (stderr, "%s:%d: Error setting memory domains %d (%08x %08x): %s .\n",
898 bo_gem->gem_handle, set_domain.read_domains, set_domain.write_domain,
904 drm_intel_bufmgr_gem_destroy(drm_intel_bufmgr *bufmgr)
906 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
909 free(bufmgr_gem->exec_objects);
910 free(bufmgr_gem->exec_bos);
912 pthread_mutex_destroy(&bufmgr_gem->lock);
914 /* Free any cached buffer objects we were going to reuse */
915 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
916 struct drm_intel_gem_bo_bucket *bucket = &bufmgr_gem->cache_bucket[i];
917 drm_intel_bo_gem *bo_gem;
919 while (!DRMLISTEMPTY(&bucket->head)) {
920 bo_gem = DRMLISTENTRY(drm_intel_bo_gem, bucket->head.next, head);
921 DRMLISTDEL(&bo_gem->head);
922 bucket->num_entries--;
924 drm_intel_gem_bo_free(&bo_gem->bo);
932 * Adds the target buffer to the validation list and adds the relocation
933 * to the reloc_buffer's relocation list.
935 * The relocation entry at the given offset must already contain the
936 * precomputed relocation value, because the kernel will optimize out
937 * the relocation entry write when the buffer hasn't moved from the
938 * last known offset in target_bo.
941 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset,
942 drm_intel_bo *target_bo, uint32_t target_offset,
943 uint32_t read_domains, uint32_t write_domain)
945 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
946 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
947 drm_intel_bo_gem *target_bo_gem = (drm_intel_bo_gem *)target_bo;
949 pthread_mutex_lock(&bufmgr_gem->lock);
951 /* Create a new relocation list if needed */
952 if (bo_gem->relocs == NULL)
953 drm_intel_setup_reloc_list(bo);
956 assert(bo_gem->reloc_count < bufmgr_gem->max_relocs);
959 assert (offset <= bo->size - 4);
960 assert ((write_domain & (write_domain-1)) == 0);
962 /* Make sure that we're not adding a reloc to something whose size has
963 * already been accounted for.
965 assert(!bo_gem->used_as_reloc_target);
966 bo_gem->reloc_tree_size += target_bo_gem->reloc_tree_size;
967 bo_gem->reloc_tree_fences += target_bo_gem->reloc_tree_fences;
969 /* Flag the target to disallow further relocations in it. */
970 target_bo_gem->used_as_reloc_target = 1;
972 bo_gem->relocs[bo_gem->reloc_count].offset = offset;
973 bo_gem->relocs[bo_gem->reloc_count].delta = target_offset;
974 bo_gem->relocs[bo_gem->reloc_count].target_handle =
975 target_bo_gem->gem_handle;
976 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains;
977 bo_gem->relocs[bo_gem->reloc_count].write_domain = write_domain;
978 bo_gem->relocs[bo_gem->reloc_count].presumed_offset = target_bo->offset;
980 bo_gem->reloc_target_bo[bo_gem->reloc_count] = target_bo;
981 drm_intel_gem_bo_reference_locked(target_bo);
983 bo_gem->reloc_count++;
985 pthread_mutex_unlock(&bufmgr_gem->lock);
991 * Walk the tree of relocations rooted at BO and accumulate the list of
992 * validations to be performed and update the relocation buffers with
993 * index values into the validation list.
996 drm_intel_gem_bo_process_reloc(drm_intel_bo *bo)
998 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1001 if (bo_gem->relocs == NULL)
1004 for (i = 0; i < bo_gem->reloc_count; i++) {
1005 drm_intel_bo *target_bo = bo_gem->reloc_target_bo[i];
1007 /* Continue walking the tree depth-first. */
1008 drm_intel_gem_bo_process_reloc(target_bo);
1010 /* Add the target to the validate list */
1011 drm_intel_add_validate_buffer(target_bo);
1016 drm_intel_update_buffer_offsets (drm_intel_bufmgr_gem *bufmgr_gem)
1020 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1021 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1022 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1024 /* Update the buffer offset */
1025 if (bufmgr_gem->exec_objects[i].offset != bo->offset) {
1026 DBG("BO %d (%s) migrated: 0x%08lx -> 0x%08llx\n",
1027 bo_gem->gem_handle, bo_gem->name, bo->offset,
1028 (unsigned long long)bufmgr_gem->exec_objects[i].offset);
1029 bo->offset = bufmgr_gem->exec_objects[i].offset;
1035 drm_intel_gem_bo_exec(drm_intel_bo *bo, int used,
1036 drm_clip_rect_t *cliprects, int num_cliprects,
1039 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1040 struct drm_i915_gem_execbuffer execbuf;
1043 pthread_mutex_lock(&bufmgr_gem->lock);
1044 /* Update indices and set up the validate list. */
1045 drm_intel_gem_bo_process_reloc(bo);
1047 /* Add the batch buffer to the validation list. There are no relocations
1050 drm_intel_add_validate_buffer(bo);
1052 execbuf.buffers_ptr = (uintptr_t)bufmgr_gem->exec_objects;
1053 execbuf.buffer_count = bufmgr_gem->exec_count;
1054 execbuf.batch_start_offset = 0;
1055 execbuf.batch_len = used;
1056 execbuf.cliprects_ptr = (uintptr_t)cliprects;
1057 execbuf.num_cliprects = num_cliprects;
1062 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_EXECBUFFER, &execbuf);
1063 } while (ret != 0 && errno == EAGAIN);
1065 if (ret != 0 && errno == ENOMEM) {
1066 fprintf(stderr, "Execbuffer fails to pin. Estimate: %u. Actual: %u. Available: %u\n",
1067 drm_intel_gem_estimate_batch_space(bufmgr_gem->exec_bos,
1068 bufmgr_gem->exec_count),
1069 drm_intel_gem_compute_batch_space(bufmgr_gem->exec_bos,
1070 bufmgr_gem->exec_count),
1071 (unsigned int) bufmgr_gem->gtt_size);
1073 drm_intel_update_buffer_offsets (bufmgr_gem);
1075 if (bufmgr_gem->bufmgr.debug)
1076 drm_intel_gem_dump_validation_list(bufmgr_gem);
1078 for (i = 0; i < bufmgr_gem->exec_count; i++) {
1079 drm_intel_bo *bo = bufmgr_gem->exec_bos[i];
1080 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1082 /* Need to call swrast on next bo_map */
1085 /* Disconnect the buffer from the validate list */
1086 bo_gem->validate_index = -1;
1087 drm_intel_gem_bo_unreference_locked(bo);
1088 bufmgr_gem->exec_bos[i] = NULL;
1090 bufmgr_gem->exec_count = 0;
1091 pthread_mutex_unlock(&bufmgr_gem->lock);
1097 drm_intel_gem_bo_pin(drm_intel_bo *bo, uint32_t alignment)
1099 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1100 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1101 struct drm_i915_gem_pin pin;
1104 memset(&pin, 0, sizeof(pin));
1105 pin.handle = bo_gem->gem_handle;
1106 pin.alignment = alignment;
1109 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_PIN, &pin);
1110 } while (ret == -1 && errno == EINTR);
1115 bo->offset = pin.offset;
1120 drm_intel_gem_bo_unpin(drm_intel_bo *bo)
1122 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1123 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1124 struct drm_i915_gem_unpin unpin;
1127 memset(&unpin, 0, sizeof(unpin));
1128 unpin.handle = bo_gem->gem_handle;
1130 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
1138 drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
1141 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1142 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1143 struct drm_i915_gem_set_tiling set_tiling;
1146 if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode)
1149 /* If we're going from non-tiling to tiling, bump fence count */
1150 if (bo_gem->tiling_mode == I915_TILING_NONE)
1151 bo_gem->reloc_tree_fences++;
1153 memset(&set_tiling, 0, sizeof(set_tiling));
1154 set_tiling.handle = bo_gem->gem_handle;
1155 set_tiling.tiling_mode = *tiling_mode;
1156 set_tiling.stride = stride;
1158 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_SET_TILING, &set_tiling);
1160 *tiling_mode = bo_gem->tiling_mode;
1163 bo_gem->tiling_mode = set_tiling.tiling_mode;
1164 bo_gem->swizzle_mode = set_tiling.swizzle_mode;
1166 /* If we're going from tiling to non-tiling, drop fence count */
1167 if (bo_gem->tiling_mode == I915_TILING_NONE)
1168 bo_gem->reloc_tree_fences--;
1170 *tiling_mode = bo_gem->tiling_mode;
1175 drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t *tiling_mode,
1176 uint32_t *swizzle_mode)
1178 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1180 *tiling_mode = bo_gem->tiling_mode;
1181 *swizzle_mode = bo_gem->swizzle_mode;
1186 drm_intel_gem_bo_flink(drm_intel_bo *bo, uint32_t *name)
1188 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo->bufmgr;
1189 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1190 struct drm_gem_flink flink;
1193 if (!bo_gem->global_name) {
1194 memset(&flink, 0, sizeof(flink));
1195 flink.handle = bo_gem->gem_handle;
1197 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_GEM_FLINK, &flink);
1200 bo_gem->global_name = flink.name;
1201 bo_gem->reusable = 0;
1204 *name = bo_gem->global_name;
1209 * Enables unlimited caching of buffer objects for reuse.
1211 * This is potentially very memory expensive, as the cache at each bucket
1212 * size is only bounded by how many buffers of that size we've managed to have
1213 * in flight at once.
1216 drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr)
1218 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr;
1221 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++) {
1222 bufmgr_gem->cache_bucket[i].max_entries = -1;
1227 * Return the additional aperture space required by the tree of buffer objects
1231 drm_intel_gem_bo_get_aperture_space(drm_intel_bo *bo)
1233 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1237 if (bo == NULL || bo_gem->included_in_check_aperture)
1241 bo_gem->included_in_check_aperture = 1;
1243 for (i = 0; i < bo_gem->reloc_count; i++)
1244 total += drm_intel_gem_bo_get_aperture_space(bo_gem->reloc_target_bo[i]);
1250 * Count the number of buffers in this list that need a fence reg
1252 * If the count is greater than the number of available regs, we'll have
1253 * to ask the caller to resubmit a batch with fewer tiled buffers.
1255 * This function over-counts if the same buffer is used multiple times.
1258 drm_intel_gem_total_fences(drm_intel_bo **bo_array, int count)
1261 unsigned int total = 0;
1263 for (i = 0; i < count; i++) {
1264 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo_array[i];
1269 total += bo_gem->reloc_tree_fences;
1275 * Clear the flag set by drm_intel_gem_bo_get_aperture_space() so we're ready
1276 * for the next drm_intel_bufmgr_check_aperture_space() call.
1279 drm_intel_gem_bo_clear_aperture_space_flag(drm_intel_bo *bo)
1281 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1284 if (bo == NULL || !bo_gem->included_in_check_aperture)
1287 bo_gem->included_in_check_aperture = 0;
1289 for (i = 0; i < bo_gem->reloc_count; i++)
1290 drm_intel_gem_bo_clear_aperture_space_flag(bo_gem->reloc_target_bo[i]);
1294 * Return a conservative estimate for the amount of aperture required
1295 * for a collection of buffers. This may double-count some buffers.
1298 drm_intel_gem_estimate_batch_space(drm_intel_bo **bo_array, int count)
1301 unsigned int total = 0;
1303 for (i = 0; i < count; i++) {
1304 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo_array[i];
1306 total += bo_gem->reloc_tree_size;
1312 * Return the amount of aperture needed for a collection of buffers.
1313 * This avoids double counting any buffers, at the cost of looking
1314 * at every buffer in the set.
1317 drm_intel_gem_compute_batch_space(drm_intel_bo **bo_array, int count)
1320 unsigned int total = 0;
1322 for (i = 0; i < count; i++) {
1323 total += drm_intel_gem_bo_get_aperture_space(bo_array[i]);
1324 /* For the first buffer object in the array, we get an accurate count
1325 * back for its reloc_tree size (since nothing had been flagged as
1326 * being counted yet). We can save that value out as a more
1327 * conservative reloc_tree_size that avoids double-counting target
1328 * buffers. Since the first buffer happens to usually be the batch
1329 * buffer in our callers, this can pull us back from doing the tree
1330 * walk on every new batch emit.
1333 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo_array[i];
1334 bo_gem->reloc_tree_size = total;
1338 for (i = 0; i < count; i++)
1339 drm_intel_gem_bo_clear_aperture_space_flag(bo_array[i]);
1344 * Return -1 if the batchbuffer should be flushed before attempting to
1345 * emit rendering referencing the buffers pointed to by bo_array.
1347 * This is required because if we try to emit a batchbuffer with relocations
1348 * to a tree of buffers that won't simultaneously fit in the aperture,
1349 * the rendering will return an error at a point where the software is not
1350 * prepared to recover from it.
1352 * However, we also want to emit the batchbuffer significantly before we reach
1353 * the limit, as a series of batchbuffers each of which references buffers
1354 * covering almost all of the aperture means that at each emit we end up
1355 * waiting to evict a buffer from the last rendering, and we get synchronous
1356 * performance. By emitting smaller batchbuffers, we eat some CPU overhead to
1357 * get better parallelism.
1360 drm_intel_gem_check_aperture_space(drm_intel_bo **bo_array, int count)
1362 drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bo_array[0]->bufmgr;
1363 unsigned int total = 0;
1364 unsigned int threshold = bufmgr_gem->gtt_size * 3 / 4;
1367 /* Check for fence reg constraints if necessary */
1368 if (bufmgr_gem->available_fences) {
1369 total_fences = drm_intel_gem_total_fences(bo_array, count);
1370 if (total_fences > bufmgr_gem->available_fences)
1374 total = drm_intel_gem_estimate_batch_space(bo_array, count);
1376 if (total > threshold)
1377 total = drm_intel_gem_compute_batch_space(bo_array, count);
1379 if (total > threshold) {
1380 DBG("check_space: overflowed available aperture, %dkb vs %dkb\n",
1381 total / 1024, (int)bufmgr_gem->gtt_size / 1024);
1384 DBG("drm_check_space: total %dkb vs bufgr %dkb\n", total / 1024 ,
1385 (int)bufmgr_gem->gtt_size / 1024);
1391 * Disable buffer reuse for objects which are shared with the kernel
1392 * as scanout buffers
1395 drm_intel_gem_bo_disable_reuse(drm_intel_bo *bo)
1397 drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *)bo;
1399 bo_gem->reusable = 0;
1404 * Initializes the GEM buffer manager, which uses the kernel to allocate, map,
1405 * and manage map buffer objections.
1407 * \param fd File descriptor of the opened DRM device.
1410 drm_intel_bufmgr_gem_init(int fd, int batch_size)
1412 drm_intel_bufmgr_gem *bufmgr_gem;
1413 struct drm_i915_gem_get_aperture aperture;
1414 drm_i915_getparam_t gp;
1417 bufmgr_gem = calloc(1, sizeof(*bufmgr_gem));
1418 bufmgr_gem->fd = fd;
1420 if (pthread_mutex_init(&bufmgr_gem->lock, NULL) != 0) {
1425 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
1428 bufmgr_gem->gtt_size = aperture.aper_available_size;
1430 fprintf(stderr, "DRM_IOCTL_I915_GEM_APERTURE failed: %s\n",
1432 bufmgr_gem->gtt_size = 128 * 1024 * 1024;
1433 fprintf(stderr, "Assuming %dkB available aperture size.\n"
1434 "May lead to reduced performance or incorrect rendering.\n",
1435 (int)bufmgr_gem->gtt_size / 1024);
1438 gp.param = I915_PARAM_CHIPSET_ID;
1439 gp.value = &bufmgr_gem->pci_device;
1440 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1442 fprintf(stderr, "get chip id failed: %d\n", ret);
1443 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1446 if (!IS_I965G(bufmgr_gem)) {
1447 gp.param = I915_PARAM_NUM_FENCES_AVAIL;
1448 gp.value = &bufmgr_gem->available_fences;
1449 ret = ioctl(bufmgr_gem->fd, DRM_IOCTL_I915_GETPARAM, &gp);
1451 fprintf(stderr, "get fences failed: %d\n", ret);
1452 fprintf(stderr, "param: %d, val: %d\n", gp.param, *gp.value);
1453 bufmgr_gem->available_fences = 0;
1457 /* Let's go with one relocation per every 2 dwords (but round down a bit
1458 * since a power of two will mean an extra page allocation for the reloc
1461 * Every 4 was too few for the blender benchmark.
1463 bufmgr_gem->max_relocs = batch_size / sizeof(uint32_t) / 2 - 2;
1465 bufmgr_gem->bufmgr.bo_alloc = drm_intel_gem_bo_alloc;
1466 bufmgr_gem->bufmgr.bo_alloc_for_render = drm_intel_gem_bo_alloc_for_render;
1467 bufmgr_gem->bufmgr.bo_reference = drm_intel_gem_bo_reference;
1468 bufmgr_gem->bufmgr.bo_unreference = drm_intel_gem_bo_unreference;
1469 bufmgr_gem->bufmgr.bo_map = drm_intel_gem_bo_map;
1470 bufmgr_gem->bufmgr.bo_unmap = drm_intel_gem_bo_unmap;
1471 bufmgr_gem->bufmgr.bo_subdata = drm_intel_gem_bo_subdata;
1472 bufmgr_gem->bufmgr.bo_get_subdata = drm_intel_gem_bo_get_subdata;
1473 bufmgr_gem->bufmgr.bo_wait_rendering = drm_intel_gem_bo_wait_rendering;
1474 bufmgr_gem->bufmgr.bo_emit_reloc = drm_intel_gem_bo_emit_reloc;
1475 bufmgr_gem->bufmgr.bo_pin = drm_intel_gem_bo_pin;
1476 bufmgr_gem->bufmgr.bo_unpin = drm_intel_gem_bo_unpin;
1477 bufmgr_gem->bufmgr.bo_get_tiling = drm_intel_gem_bo_get_tiling;
1478 bufmgr_gem->bufmgr.bo_set_tiling = drm_intel_gem_bo_set_tiling;
1479 bufmgr_gem->bufmgr.bo_flink = drm_intel_gem_bo_flink;
1480 bufmgr_gem->bufmgr.bo_exec = drm_intel_gem_bo_exec;
1481 bufmgr_gem->bufmgr.destroy = drm_intel_bufmgr_gem_destroy;
1482 bufmgr_gem->bufmgr.debug = 0;
1483 bufmgr_gem->bufmgr.check_aperture_space = drm_intel_gem_check_aperture_space;
1484 bufmgr_gem->bufmgr.bo_disable_reuse = drm_intel_gem_bo_disable_reuse;
1485 bufmgr_gem->bufmgr.get_pipe_from_crtc_id = drm_intel_gem_get_pipe_from_crtc_id;
1486 /* Initialize the linked lists for BO reuse cache. */
1487 for (i = 0; i < DRM_INTEL_GEM_BO_BUCKETS; i++)
1488 DRMINITLISTHEAD(&bufmgr_gem->cache_bucket[i].head);
1490 return &bufmgr_gem->bufmgr;