2 * Copyright © 2008 Dave Airlie
3 * Copyright © 2008 Jérôme Glisse
6 * Permission is hereby granted, free of charge, to any person obtaining
7 * a copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
16 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
17 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
18 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 * The above copyright notice and this permission notice (including the
24 * next paragraph) shall be included in all copies or substantial portions
30 * Jérôme Glisse <glisse@freedesktop.org>
40 #include <sys/ioctl.h>
44 #include "radeon_drm.h"
45 #include "radeon_bo.h"
46 #include "radeon_bo_gem.h"
48 struct radeon_bo_gem {
49 struct radeon_bo base;
55 struct bo_manager_gem {
56 struct radeon_bo_manager base;
59 static int bo_wait(struct radeon_bo *bo);
61 static struct radeon_bo *bo_open(struct radeon_bo_manager *bom,
68 struct radeon_bo_gem *bo;
71 bo = (struct radeon_bo_gem*)calloc(1, sizeof(struct radeon_bo_gem));
79 bo->base.alignment = alignment;
80 bo->base.domains = domains;
81 bo->base.flags = flags;
85 struct drm_gem_open open_arg;
87 memset(&open_arg, 0, sizeof(open_arg));
88 open_arg.name = handle;
89 r = ioctl(bom->fd, DRM_IOCTL_GEM_OPEN, &open_arg);
94 bo->base.handle = open_arg.handle;
95 bo->base.size = open_arg.size;
98 struct drm_radeon_gem_create args;
101 args.alignment = alignment;
102 args.initial_domain = bo->base.domains;
105 r = drmCommandWriteRead(bom->fd, DRM_RADEON_GEM_CREATE,
106 &args, sizeof(args));
107 bo->base.handle = args.handle;
109 fprintf(stderr, "Failed to allocate :\n");
110 fprintf(stderr, " size : %d bytes\n", size);
111 fprintf(stderr, " alignment : %d bytes\n", alignment);
112 fprintf(stderr, " domains : %d\n", bo->base.domains);
117 radeon_bo_ref((struct radeon_bo*)bo);
118 return (struct radeon_bo*)bo;
121 static void bo_ref(struct radeon_bo *bo)
125 static struct radeon_bo *bo_unref(struct radeon_bo *bo)
127 struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
128 struct drm_gem_close args;
136 if (bo_gem->priv_ptr) {
137 munmap(bo_gem->priv_ptr, bo->size);
141 args.handle = bo->handle;
142 ioctl(bo->bom->fd, DRM_IOCTL_GEM_CLOSE, &args);
143 memset(bo_gem, 0, sizeof(struct radeon_bo_gem));
148 static int bo_map(struct radeon_bo *bo, int write)
150 struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
151 struct drm_radeon_gem_mmap args;
155 if (bo_gem->map_count++ != 0) {
158 if (bo_gem->priv_ptr) {
160 bo->ptr = bo_gem->priv_ptr;
167 args.handle = bo->handle;
169 args.size = (uint64_t)bo->size;
170 r = drmCommandWriteRead(bo->bom->fd,
175 fprintf(stderr, "error mapping %p 0x%08X (error = %d)\n",
179 ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, bo->bom->fd, args.addr_ptr);
180 if (ptr == MAP_FAILED)
182 bo_gem->priv_ptr = ptr;
183 bo->ptr = bo_gem->priv_ptr;
187 static int bo_unmap(struct radeon_bo *bo)
189 struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
191 if (--bo_gem->map_count > 0) {
194 //munmap(bo->ptr, bo->size);
199 static int bo_wait(struct radeon_bo *bo)
201 struct drm_radeon_gem_wait_idle args;
204 args.handle = bo->handle;
206 ret = drmCommandWriteRead(bo->bom->fd, DRM_RADEON_GEM_WAIT_IDLE,
207 &args, sizeof(args));
208 } while (ret == -EBUSY);
212 static int bo_set_tiling(struct radeon_bo *bo, uint32_t tiling_flags,
215 struct drm_radeon_gem_set_tiling args;
218 args.handle = bo->handle;
219 args.tiling_flags = tiling_flags;
222 r = drmCommandWriteRead(bo->bom->fd,
223 DRM_RADEON_GEM_SET_TILING,
229 static int bo_get_tiling(struct radeon_bo *bo, uint32_t *tiling_flags,
232 struct drm_radeon_gem_set_tiling args;
235 args.handle = bo->handle;
237 r = drmCommandWriteRead(bo->bom->fd,
238 DRM_RADEON_GEM_GET_TILING,
245 *tiling_flags = args.tiling_flags;
250 static struct radeon_bo_funcs bo_gem_funcs = {
262 struct radeon_bo_manager *radeon_bo_manager_gem_ctor(int fd)
264 struct bo_manager_gem *bomg;
266 bomg = (struct bo_manager_gem*)calloc(1, sizeof(struct bo_manager_gem));
270 bomg->base.funcs = &bo_gem_funcs;
272 return (struct radeon_bo_manager*)bomg;
275 void radeon_bo_manager_gem_dtor(struct radeon_bo_manager *bom)
277 struct bo_manager_gem *bomg = (struct bo_manager_gem*)bom;
285 uint32_t radeon_gem_name_bo(struct radeon_bo *bo)
287 struct radeon_bo_gem *bo_gem = (struct radeon_bo_gem*)bo;
291 int radeon_gem_get_kernel_name(struct radeon_bo *bo, uint32_t *name)
293 struct drm_gem_flink flink;
296 flink.handle = bo->handle;
297 r = ioctl(bo->bom->fd, DRM_IOCTL_GEM_FLINK, &flink);
305 int radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain)
307 struct drm_radeon_gem_set_domain args;
310 args.handle = bo->handle;
311 args.read_domains = read_domains;
312 args.write_domain = write_domain;
314 r = drmCommandWriteRead(bo->bom->fd,
315 DRM_RADEON_GEM_SET_DOMAIN,