2 * The authors hereby grant permission to use, copy, modify, distribute,
3 * and license this software and its documentation for any purpose, provided
4 * that existing copyright notices are retained in all copies and that this
5 * notice is included verbatim in any distributions. No written agreement,
6 * license, or royalty fee is required for any of the authorized uses.
7 * Modifications to this software may be copyrighted by their authors
8 * and need not follow the licensing terms described here, provided that
9 * the new terms are clearly indicated on the first page of each file where
16 ** Copyright (C) 2008 Analog Devices, Inc.
18 ************************************************************************************
20 ** This include file contains a list of macro "defines" to enable the programmer
21 ** to use symbolic names for register-access and bit-manipulation.
27 /* Include all Core registers and bit definitions */
28 #include <def_LPBlackfin.h>
30 /* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
32 /* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
33 #include <defBF54x_base.h>
35 /* The following are the #defines needed by ADSP-BF542 that are not in the common header */
39 #define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
40 #define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
41 #define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
42 #define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
43 #define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
44 #define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
45 #define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
46 #define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
47 #define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
48 #define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
49 #define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
50 #define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
51 #define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
52 #define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
53 #define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
54 #define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
55 #define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
56 #define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
57 #define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
58 #define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
59 #define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
60 #define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
61 #define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
62 #define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
63 #define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
67 #define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
68 #define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
69 #define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
70 #define SDH_COMMAND 0xffc0390c /* SDH Command */
71 #define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
72 #define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
73 #define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
74 #define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
75 #define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
76 #define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
77 #define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
78 #define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
79 #define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
80 #define SDH_STATUS 0xffc03934 /* SDH Status */
81 #define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
82 #define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
83 #define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
84 #define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
85 #define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
86 #define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
87 #define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
88 #define SDH_CFG 0xffc039c8 /* SDH Configuration */
89 #define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
90 #define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
91 #define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
92 #define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
93 #define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
94 #define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
95 #define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
96 #define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
97 #define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
99 /* USB Control Registers */
101 #define USB_FADDR 0xffc03c00 /* Function address register */
102 #define USB_POWER 0xffc03c04 /* Power management register */
103 #define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
104 #define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
105 #define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
106 #define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
107 #define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
108 #define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
109 #define USB_FRAME 0xffc03c20 /* USB frame number */
110 #define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
111 #define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
112 #define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
113 #define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
115 /* USB Packet Control Registers */
117 #define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
118 #define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
119 #define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
120 #define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
121 #define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
122 #define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
123 #define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
124 #define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
125 #define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
126 #define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
127 #define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
128 #define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
129 #define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
131 /* USB Endpoint FIFO Registers */
133 #define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
134 #define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
135 #define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
136 #define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
137 #define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
138 #define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
139 #define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
140 #define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
142 /* USB OTG Control Registers */
144 #define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
145 #define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
146 #define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
148 /* USB Phy Control Registers */
150 #define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
151 #define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
152 #define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
153 #define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
154 #define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
156 /* (APHY_CNTRL is for ADI usage only) */
158 #define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
160 /* (APHY_CALIB is for ADI usage only) */
162 #define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
163 #define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
165 /* (PHY_TEST is for ADI usage only) */
167 #define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
168 #define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
169 #define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
171 /* USB Endpoint 0 Control Registers */
173 #define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
174 #define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
175 #define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
176 #define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
177 #define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
178 #define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
179 #define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
180 #define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
181 #define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
183 /* USB Endpoint 1 Control Registers */
185 #define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
186 #define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
187 #define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
188 #define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
189 #define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
190 #define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
191 #define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
192 #define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
193 #define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
194 #define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
196 /* USB Endpoint 2 Control Registers */
198 #define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
199 #define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
200 #define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
201 #define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
202 #define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
203 #define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
204 #define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
205 #define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
206 #define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
207 #define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
209 /* USB Endpoint 3 Control Registers */
211 #define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
212 #define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
213 #define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
214 #define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
215 #define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
216 #define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
217 #define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
218 #define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
219 #define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
220 #define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
222 /* USB Endpoint 4 Control Registers */
224 #define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
225 #define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
226 #define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
227 #define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
228 #define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
229 #define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
230 #define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
231 #define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
232 #define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
233 #define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
235 /* USB Endpoint 5 Control Registers */
237 #define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
238 #define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
239 #define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
240 #define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
241 #define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
242 #define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
243 #define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
244 #define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
245 #define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
246 #define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
248 /* USB Endpoint 6 Control Registers */
250 #define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
251 #define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
252 #define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
253 #define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
254 #define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
255 #define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
256 #define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
257 #define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
258 #define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
259 #define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
261 /* USB Endpoint 7 Control Registers */
263 #define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
264 #define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
265 #define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
266 #define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
267 #define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
268 #define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
269 #define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
270 #define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
271 #define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
272 #define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
273 #define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
274 #define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
276 /* USB Channel 0 Config Registers */
278 #define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
279 #define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
280 #define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
281 #define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
282 #define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
284 /* USB Channel 1 Config Registers */
286 #define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
287 #define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
288 #define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
289 #define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
290 #define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
292 /* USB Channel 2 Config Registers */
294 #define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
295 #define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
296 #define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
297 #define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
298 #define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
300 /* USB Channel 3 Config Registers */
302 #define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
303 #define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
304 #define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
305 #define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
306 #define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
308 /* USB Channel 4 Config Registers */
310 #define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
311 #define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
312 #define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
313 #define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
314 #define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
316 /* USB Channel 5 Config Registers */
318 #define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
319 #define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
320 #define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
321 #define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
322 #define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
324 /* USB Channel 6 Config Registers */
326 #define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
327 #define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
328 #define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
329 #define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
330 #define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
332 /* USB Channel 7 Config Registers */
334 #define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
335 #define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
336 #define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
337 #define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
338 #define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
340 /* Keypad Registers */
342 #define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
343 #define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
344 #define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
345 #define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
346 #define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
347 #define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
350 /* ********************************************************** */
351 /* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
352 /* and MULTI BIT READ MACROS */
353 /* ********************************************************** */
355 /* Bit masks for KPAD_CTL */
357 #define KPAD_EN 0x1 /* Keypad Enable */
359 #define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
360 #define nKPAD_IRQMODE 0x0 /* Interrupt Disabled */
361 #define KPAD_IRQMODE_SK 0x2 /* Single key (single row, single column) press interrupt enable */
362 #define KPAD_IRQMODE_MK 0x4 /* Single key press multiple key press interrupt enable */
364 #define KPAD_ROWEN 0x1c00 /* Row Enable Width */
365 #define KPAD_COLEN 0xe000 /* Column Enable Width */
367 #define SET_KPAD_ROWEN(x) (((x)&0x7)<<10) /* 000: row 0 enabled, 111: rows 0-7 enabled */
368 #define SET_KPAD_COLEN(x) (((x)&0x7)<<13) /* 000: column 0 enabled, 111: columns 0-7 enabled */
370 /* Bit masks for KPAD_PRESCALE */
372 #define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
374 #define SET_KPAD_PRESCALE(x) ((x)&0x3F) /* KPAD_PRESCALE_VAL (Key Prescale) Key Prescale Value (5:0) */
376 /* Bit masks for KPAD_MSEL */
378 #define DBON_SCALE 0xff /* Debounce Scale Value */
379 #define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
381 /* Bit masks for KPAD_ROWCOL */
383 #define KPAD_ROW 0xff /* Rows Pressed */
384 #define KPAD_COL 0xff00 /* Columns Pressed */
386 #define SET_KPAD_DBON_SCALE(x) ((x)&0xFF) /* DBON_SCALE (Debounce Scale) Debounce Delay Multiplier Select [7:0] */
387 #define SET_KPAD_COLDRV_SCALE(x) (((x)&0xFF)<<8) /* COLDRV_SCALE (Column Driver Scale) Column Driver Period Multiplier Select [15:8] */
389 /* Bit masks for KPAD_STAT */
391 #define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
392 #define nKPAD_IRQ 0x0
393 #define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
394 #define KPAD_PRESSED 0x8 /* Key press current status */
395 #define nKPAD_PRESSED 0x0
396 #define KPAD_NO_KEY 0x0 /* No Keypress Status*/
397 #define KPAD_SINGLE_KEY 0x2 /* Single Keypress Status */
398 #define KPAD_MKSROWCOL 0x4 /* Multiple Keypress in the same row or column Status */
399 #define KPAD_MKMROWCOL 0x6 /* Multiple Keypress in the same multiple rows and multiple columns Status */
401 /* Bit masks for KPAD_SOFTEVAL */
403 #define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
404 #define nKPAD_SOFTEVAL_E 0x0
406 /* Bit masks for SDH_COMMAND */
408 #define CMD_IDX 0x3f /* Command Index */
409 #define CMD_RSP 0x40 /* Response */
411 #define CMD_L_RSP 0x80 /* Long Response */
412 #define nCMD_L_RSP 0x0
413 #define CMD_INT_E 0x100 /* Command Interrupt */
414 #define nCMD_INT_E 0x0
415 #define CMD_PEND_E 0x200 /* Command Pending */
416 #define nCMD_PEND_E 0x0
417 #define CMD_E 0x400 /* Command Enable */
420 /* Bit masks for SDH_PWR_CTL */
422 #define PWR_ON 0x3 /* Power On */
424 #define TBD 0x3c /* TBD */
426 #define SD_CMD_OD 0x40 /* Open Drain Output */
427 #define nSD_CMD_OD 0x0
428 #define ROD_CTL 0x80 /* Rod Control */
431 /* Bit masks for SDH_CLK_CTL */
433 #define CLKDIV 0xff /* MC_CLK Divisor */
434 #define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
436 #define PWR_SV_E 0x200 /* Power Save Enable */
437 #define nPWR_SV_E 0x0
438 #define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
439 #define nCLKDIV_BYPASS 0x0
440 #define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
441 #define nWIDE_BUS 0x0
443 /* Bit masks for SDH_RESP_CMD */
445 #define RESP_CMD 0x3f /* Response Command */
447 /* Bit masks for SDH_DATA_CTL */
449 #define DTX_E 0x1 /* Data Transfer Enable */
451 #define DTX_DIR 0x2 /* Data Transfer Direction */
453 #define DTX_MODE 0x4 /* Data Transfer Mode */
454 #define nDTX_MODE 0x0
455 #define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
456 #define nDTX_DMA_E 0x0
457 #define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
459 /* Bit masks for SDH_STATUS */
461 #define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
462 #define nCMD_CRC_FAIL 0x0
463 #define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
464 #define nDAT_CRC_FAIL 0x0
465 #define CMD_TIMEOUT 0x4 /* CMD Time Out */
466 #define nCMD_TIMEOUT 0x0
467 #define DAT_TIMEOUT 0x8 /* Data Time Out */
468 #define nDAT_TIMEOUT 0x0
469 #define TX_UNDERRUN 0x10 /* Transmit Underrun */
470 #define nTX_UNDERRUN 0x0
471 #define RX_OVERRUN 0x20 /* Receive Overrun */
472 #define nRX_OVERRUN 0x0
473 #define CMD_RESP_END 0x40 /* CMD Response End */
474 #define nCMD_RESP_END 0x0
475 #define CMD_SENT 0x80 /* CMD Sent */
476 #define nCMD_SENT 0x0
477 #define DAT_END 0x100 /* Data End */
479 #define START_BIT_ERR 0x200 /* Start Bit Error */
480 #define nSTART_BIT_ERR 0x0
481 #define DAT_BLK_END 0x400 /* Data Block End */
482 #define nDAT_BLK_END 0x0
483 #define CMD_ACT 0x800 /* CMD Active */
485 #define TX_ACT 0x1000 /* Transmit Active */
487 #define RX_ACT 0x2000 /* Receive Active */
489 #define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
490 #define nTX_FIFO_STAT 0x0
491 #define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
492 #define nRX_FIFO_STAT 0x0
493 #define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
494 #define nTX_FIFO_FULL 0x0
495 #define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
496 #define nRX_FIFO_FULL 0x0
497 #define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
498 #define nTX_FIFO_ZERO 0x0
499 #define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
500 #define nRX_DAT_ZERO 0x0
501 #define TX_DAT_RDY 0x100000 /* Transmit Data Available */
502 #define nTX_DAT_RDY 0x0
503 #define RX_FIFO_RDY 0x200000 /* Receive Data Available */
504 #define nRX_FIFO_RDY 0x0
506 /* Bit masks for SDH_STATUS_CLR */
508 #define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
509 #define nCMD_CRC_FAIL_STAT 0x0
510 #define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
511 #define nDAT_CRC_FAIL_STAT 0x0
512 #define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
513 #define nCMD_TIMEOUT_STAT 0x0
514 #define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
515 #define nDAT_TIMEOUT_STAT 0x0
516 #define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
517 #define nTX_UNDERRUN_STAT 0x0
518 #define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
519 #define nRX_OVERRUN_STAT 0x0
520 #define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
521 #define nCMD_RESP_END_STAT 0x0
522 #define CMD_SENT_STAT 0x80 /* CMD Sent Status */
523 #define nCMD_SENT_STAT 0x0
524 #define DAT_END_STAT 0x100 /* Data End Status */
525 #define nDAT_END_STAT 0x0
526 #define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
527 #define nSTART_BIT_ERR_STAT 0x0
528 #define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
529 #define nDAT_BLK_END_STAT 0x0
531 /* Bit masks for SDH_MASK0 */
533 #define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
534 #define nCMD_CRC_FAIL_MASK 0x0
535 #define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
536 #define nDAT_CRC_FAIL_MASK 0x0
537 #define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
538 #define nCMD_TIMEOUT_MASK 0x0
539 #define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
540 #define nDAT_TIMEOUT_MASK 0x0
541 #define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
542 #define nTX_UNDERRUN_MASK 0x0
543 #define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
544 #define nRX_OVERRUN_MASK 0x0
545 #define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
546 #define nCMD_RESP_END_MASK 0x0
547 #define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
548 #define nCMD_SENT_MASK 0x0
549 #define DAT_END_MASK 0x100 /* Data End Mask */
550 #define nDAT_END_MASK 0x0
551 #define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
552 #define nSTART_BIT_ERR_MASK 0x0
553 #define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
554 #define nDAT_BLK_END_MASK 0x0
555 #define CMD_ACT_MASK 0x800 /* CMD Active Mask */
556 #define nCMD_ACT_MASK 0x0
557 #define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
558 #define nTX_ACT_MASK 0x0
559 #define RX_ACT_MASK 0x2000 /* Receive Active Mask */
560 #define nRX_ACT_MASK 0x0
561 #define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
562 #define nTX_FIFO_STAT_MASK 0x0
563 #define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
564 #define nRX_FIFO_STAT_MASK 0x0
565 #define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
566 #define nTX_FIFO_FULL_MASK 0x0
567 #define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
568 #define nRX_FIFO_FULL_MASK 0x0
569 #define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
570 #define nTX_FIFO_ZERO_MASK 0x0
571 #define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
572 #define nRX_DAT_ZERO_MASK 0x0
573 #define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
574 #define nTX_DAT_RDY_MASK 0x0
575 #define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
576 #define nRX_FIFO_RDY_MASK 0x0
578 /* Bit masks for SDH_FIFO_CNT */
580 #define FIFO_COUNT 0x7fff /* FIFO Count */
582 /* Bit masks for SDH_E_STATUS */
584 #define SDIO_INT_DET 0x2 /* SDIO Int Detected */
585 #define nSDIO_INT_DET 0x0
586 #define SD_CARD_DET 0x10 /* SD Card Detect */
587 #define nSD_CARD_DET 0x0
589 /* Bit masks for SDH_E_MASK */
591 #define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
592 #define nSDIO_MSK 0x0
593 #define SCD_MSK 0x40 /* Mask Card Detect */
596 /* Bit masks for SDH_CFG */
598 #define CLKS_EN 0x1 /* Clocks Enable */
600 #define SD4E 0x4 /* SDIO 4-Bit Enable */
602 #define MWE 0x8 /* Moving Window Enable */
604 #define SD_RST 0x10 /* SDMMC Reset */
606 #define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
607 #define nPUP_SDDAT 0x0
608 #define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
609 #define nPUP_SDDAT3 0x0
610 #define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
611 #define nPD_SDDAT3 0x0
613 /* Bit masks for SDH_RD_WAIT_EN */
615 #define RWR 0x1 /* Read Wait Request */
618 /* Bit masks for ATAPI_CONTROL */
620 #define PIO_START 0x1 /* Start PIO/Reg Op */
621 #define nPIO_START 0x0
622 #define MULTI_START 0x2 /* Start Multi-DMA Op */
623 #define nMULTI_START 0x0
624 #define ULTRA_START 0x4 /* Start Ultra-DMA Op */
625 #define nULTRA_START 0x0
626 #define XFER_DIR 0x8 /* Transfer Direction */
627 #define nXFER_DIR 0x0
628 #define IORDY_EN 0x10 /* IORDY Enable */
629 #define nIORDY_EN 0x0
630 #define FIFO_FLUSH 0x20 /* Flush FIFOs */
631 #define nFIFO_FLUSH 0x0
632 #define SOFT_RST 0x40 /* Soft Reset */
633 #define nSOFT_RST 0x0
634 #define DEV_RST 0x80 /* Device Reset */
636 #define TFRCNT_RST 0x100 /* Trans Count Reset */
637 #define nTFRCNT_RST 0x0
638 #define END_ON_TERM 0x200 /* End/Terminate Select */
639 #define nEND_ON_TERM 0x0
640 #define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
641 #define nPIO_USE_DMA 0x0
642 #define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
644 /* Bit masks for ATAPI_STATUS */
646 #define PIO_XFER_ON 0x1 /* PIO transfer in progress */
647 #define nPIO_XFER_ON 0x0
648 #define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
649 #define nMULTI_XFER_ON 0x0
650 #define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
651 #define nULTRA_XFER_ON 0x0
652 #define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
654 /* Bit masks for ATAPI_DEV_ADDR */
656 #define DEV_ADDR 0x1f /* Device Address */
658 /* Bit masks for ATAPI_INT_MASK */
660 #define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
661 #define nATAPI_DEV_INT_MASK 0x0
662 #define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
663 #define nPIO_DONE_MASK 0x0
664 #define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
665 #define nMULTI_DONE_MASK 0x0
666 #define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
667 #define nUDMAIN_DONE_MASK 0x0
668 #define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
669 #define nUDMAOUT_DONE_MASK 0x0
670 #define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
671 #define nHOST_TERM_XFER_MASK 0x0
672 #define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
673 #define nMULTI_TERM_MASK 0x0
674 #define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
675 #define nUDMAIN_TERM_MASK 0x0
676 #define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
677 #define nUDMAOUT_TERM_MASK 0x0
679 /* Bit masks for ATAPI_INT_STATUS */
681 #define ATAPI_DEV_INT 0x1 /* Device interrupt status */
682 #define nATAPI_DEV_INT 0x0
683 #define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
684 #define nPIO_DONE_INT 0x0
685 #define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
686 #define nMULTI_DONE_INT 0x0
687 #define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
688 #define nUDMAIN_DONE_INT 0x0
689 #define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
690 #define nUDMAOUT_DONE_INT 0x0
691 #define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
692 #define nHOST_TERM_XFER_INT 0x0
693 #define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
694 #define nMULTI_TERM_INT 0x0
695 #define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
696 #define nUDMAIN_TERM_INT 0x0
697 #define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
698 #define nUDMAOUT_TERM_INT 0x0
700 /* Bit masks for ATAPI_LINE_STATUS */
702 #define ATAPI_INTR 0x1 /* Device interrupt to host line status */
703 #define nATAPI_INTR 0x0
704 #define ATAPI_DASP 0x2 /* Device dasp to host line status */
705 #define nATAPI_DASP 0x0
706 #define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
707 #define nATAPI_CS0N 0x0
708 #define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
709 #define nATAPI_CS1N 0x0
710 #define ATAPI_ADDR 0x70 /* ATAPI address line status */
711 #define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
712 #define nATAPI_DMAREQ 0x0
713 #define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
714 #define nATAPI_DMAACKN 0x0
715 #define ATAPI_DIOWN 0x200 /* ATAPI write line status */
716 #define nATAPI_DIOWN 0x0
717 #define ATAPI_DIORN 0x400 /* ATAPI read line status */
718 #define nATAPI_DIORN 0x0
719 #define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
720 #define nATAPI_IORDY 0x0
722 /* Bit masks for ATAPI_SM_STATE */
724 #define PIO_CSTATE 0xf /* PIO mode state machine current state */
725 #define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
726 #define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
727 #define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
729 /* Bit masks for ATAPI_TERMINATE */
731 #define ATAPI_HOST_TERM 0x1 /* Host terminationation */
732 #define nATAPI_HOST_TERM 0x0
734 /* Bit masks for ATAPI_REG_TIM_0 */
736 #define T2_REG 0xff /* End of cycle time for register access transfers */
737 #define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
739 /* Bit masks for ATAPI_PIO_TIM_0 */
741 #define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
742 #define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
743 #define T4_REG 0xf000 /* DIOW data hold */
745 /* Bit masks for ATAPI_PIO_TIM_1 */
747 #define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
749 /* Bit masks for ATAPI_MULTI_TIM_0 */
751 #define TD 0xff /* DIOR/DIOW asserted pulsewidth */
752 #define TM 0xff00 /* Time from address valid to DIOR/DIOW */
754 /* Bit masks for ATAPI_MULTI_TIM_1 */
756 #define TKW 0xff /* Selects DIOW negated pulsewidth */
757 #define TKR 0xff00 /* Selects DIOR negated pulsewidth */
759 /* Bit masks for ATAPI_MULTI_TIM_2 */
761 #define TH 0xff /* Selects DIOW data hold */
762 #define TEOC 0xff00 /* Selects end of cycle for DMA */
764 /* Bit masks for ATAPI_ULTRA_TIM_0 */
766 #define TACK 0xff /* Selects setup and hold times for TACK */
767 #define TENV 0xff00 /* Selects envelope time */
769 /* Bit masks for ATAPI_ULTRA_TIM_1 */
771 #define TDVS 0xff /* Selects data valid setup time */
772 #define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
774 /* Bit masks for ATAPI_ULTRA_TIM_2 */
776 #define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
777 #define TMLI 0xff00 /* Selects interlock time */
779 /* Bit masks for ATAPI_ULTRA_TIM_3 */
781 #define TZAH 0xff /* Selects minimum delay required for output */
782 #define READY_PAUSE 0xff00 /* Selects ready to pause */
784 /* Bit masks for USB_FADDR */
786 #define FUNCTION_ADDRESS 0x7f /* Function address */
788 /* Bit masks for USB_POWER */
790 #define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
791 #define nENABLE_SUSPENDM 0x0
792 #define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
793 #define nSUSPEND_MODE 0x0
794 #define RESUME_MODE 0x4 /* DMA Mode */
795 #define nRESUME_MODE 0x0
796 #define RESET 0x8 /* Reset indicator */
798 #define HS_MODE 0x10 /* High Speed mode indicator */
800 #define HS_ENABLE 0x20 /* high Speed Enable */
801 #define nHS_ENABLE 0x0
802 #define SOFT_CONN 0x40 /* Soft connect */
803 #define nSOFT_CONN 0x0
804 #define ISO_UPDATE 0x80 /* Isochronous update */
805 #define nISO_UPDATE 0x0
807 /* Bit masks for USB_INTRTX */
809 #define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
811 #define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
813 #define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
815 #define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
817 #define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
819 #define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
821 #define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
823 #define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
826 /* Bit masks for USB_INTRRX */
828 #define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
830 #define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
832 #define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
834 #define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
836 #define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
838 #define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
840 #define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
843 /* Bit masks for USB_INTRTXE */
845 #define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
846 #define nEP0_TX_E 0x0
847 #define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
848 #define nEP1_TX_E 0x0
849 #define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
850 #define nEP2_TX_E 0x0
851 #define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
852 #define nEP3_TX_E 0x0
853 #define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
854 #define nEP4_TX_E 0x0
855 #define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
856 #define nEP5_TX_E 0x0
857 #define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
858 #define nEP6_TX_E 0x0
859 #define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
860 #define nEP7_TX_E 0x0
862 /* Bit masks for USB_INTRRXE */
864 #define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
865 #define nEP1_RX_E 0x0
866 #define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
867 #define nEP2_RX_E 0x0
868 #define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
869 #define nEP3_RX_E 0x0
870 #define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
871 #define nEP4_RX_E 0x0
872 #define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
873 #define nEP5_RX_E 0x0
874 #define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
875 #define nEP6_RX_E 0x0
876 #define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
877 #define nEP7_RX_E 0x0
879 /* Bit masks for USB_INTRUSB */
881 #define SUSPEND_B 0x1 /* Suspend indicator */
882 #define nSUSPEND_B 0x0
883 #define RESUME_B 0x2 /* Resume indicator */
884 #define nRESUME_B 0x0
885 #define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
886 #define nRESET_OR_BABLE_B 0x0
887 #define SOF_B 0x8 /* Start of frame */
889 #define CONN_B 0x10 /* Connection indicator */
891 #define DISCON_B 0x20 /* Disconnect indicator */
892 #define nDISCON_B 0x0
893 #define SESSION_REQ_B 0x40 /* Session Request */
894 #define nSESSION_REQ_B 0x0
895 #define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
896 #define nVBUS_ERROR_B 0x0
898 /* Bit masks for USB_INTRUSBE */
900 #define SUSPEND_BE 0x1 /* Suspend indicator int enable */
901 #define nSUSPEND_BE 0x0
902 #define RESUME_BE 0x2 /* Resume indicator int enable */
903 #define nRESUME_BE 0x0
904 #define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
905 #define nRESET_OR_BABLE_BE 0x0
906 #define SOF_BE 0x8 /* Start of frame int enable */
908 #define CONN_BE 0x10 /* Connection indicator int enable */
910 #define DISCON_BE 0x20 /* Disconnect indicator int enable */
911 #define nDISCON_BE 0x0
912 #define SESSION_REQ_BE 0x40 /* Session Request int enable */
913 #define nSESSION_REQ_BE 0x0
914 #define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
915 #define nVBUS_ERROR_BE 0x0
917 /* Bit masks for USB_FRAME */
919 #define FRAME_NUMBER 0x7ff /* Frame number */
921 /* Bit masks for USB_INDEX */
923 #define SELECTED_ENDPOINT 0xf /* selected endpoint */
925 /* Bit masks for USB_GLOBAL_CTL */
927 #define GLOBAL_ENA 0x1 /* enables USB module */
928 #define nGLOBAL_ENA 0x0
929 #define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
930 #define nEP1_TX_ENA 0x0
931 #define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
932 #define nEP2_TX_ENA 0x0
933 #define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
934 #define nEP3_TX_ENA 0x0
935 #define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
936 #define nEP4_TX_ENA 0x0
937 #define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
938 #define nEP5_TX_ENA 0x0
939 #define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
940 #define nEP6_TX_ENA 0x0
941 #define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
942 #define nEP7_TX_ENA 0x0
943 #define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
944 #define nEP1_RX_ENA 0x0
945 #define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
946 #define nEP2_RX_ENA 0x0
947 #define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
948 #define nEP3_RX_ENA 0x0
949 #define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
950 #define nEP4_RX_ENA 0x0
951 #define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
952 #define nEP5_RX_ENA 0x0
953 #define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
954 #define nEP6_RX_ENA 0x0
955 #define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
956 #define nEP7_RX_ENA 0x0
958 /* Bit masks for USB_OTG_DEV_CTL */
960 #define SESSION 0x1 /* session indicator */
962 #define HOST_REQ 0x2 /* Host negotiation request */
963 #define nHOST_REQ 0x0
964 #define HOST_MODE 0x4 /* indicates USBDRC is a host */
965 #define nHOST_MODE 0x0
966 #define VBUS0 0x8 /* Vbus level indicator[0] */
968 #define VBUS1 0x10 /* Vbus level indicator[1] */
970 #define LSDEV 0x20 /* Low-speed indicator */
972 #define FSDEV 0x40 /* Full or High-speed indicator */
974 #define B_DEVICE 0x80 /* A' or 'B' device indicator */
975 #define nB_DEVICE 0x0
977 /* Bit masks for USB_OTG_VBUS_IRQ */
979 #define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
980 #define nDRIVE_VBUS_ON 0x0
981 #define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
982 #define nDRIVE_VBUS_OFF 0x0
983 #define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
984 #define nCHRG_VBUS_START 0x0
985 #define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
986 #define nCHRG_VBUS_END 0x0
987 #define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
988 #define nDISCHRG_VBUS_START 0x0
989 #define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
990 #define nDISCHRG_VBUS_END 0x0
992 /* Bit masks for USB_OTG_VBUS_MASK */
994 #define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
995 #define nDRIVE_VBUS_ON_ENA 0x0
996 #define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
997 #define nDRIVE_VBUS_OFF_ENA 0x0
998 #define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
999 #define nCHRG_VBUS_START_ENA 0x0
1000 #define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1001 #define nCHRG_VBUS_END_ENA 0x0
1002 #define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1003 #define nDISCHRG_VBUS_START_ENA 0x0
1004 #define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1005 #define nDISCHRG_VBUS_END_ENA 0x0
1007 /* Bit masks for USB_CSR0 */
1009 #define RXPKTRDY 0x1 /* data packet receive indicator */
1010 #define nRXPKTRDY 0x0
1011 #define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1012 #define nTXPKTRDY 0x0
1013 #define STALL_SENT 0x4 /* STALL handshake sent */
1014 #define nSTALL_SENT 0x0
1015 #define DATAEND 0x8 /* Data end indicator */
1016 #define nDATAEND 0x0
1017 #define SETUPEND 0x10 /* Setup end */
1018 #define nSETUPEND 0x0
1019 #define SENDSTALL 0x20 /* Send STALL handshake */
1020 #define nSENDSTALL 0x0
1021 #define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1022 #define nSERVICED_RXPKTRDY 0x0
1023 #define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1024 #define nSERVICED_SETUPEND 0x0
1025 #define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1026 #define nFLUSHFIFO 0x0
1027 #define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1028 #define nSTALL_RECEIVED_H 0x0
1029 #define SETUPPKT_H 0x8 /* send Setup token host mode */
1030 #define nSETUPPKT_H 0x0
1031 #define ERROR_H 0x10 /* timeout error indicator host mode */
1032 #define nERROR_H 0x0
1033 #define REQPKT_H 0x20 /* Request an IN transaction host mode */
1034 #define nREQPKT_H 0x0
1035 #define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1036 #define nSTATUSPKT_H 0x0
1037 #define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1038 #define nNAK_TIMEOUT_H 0x0
1040 /* Bit masks for USB_COUNT0 */
1042 #define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1044 /* Bit masks for USB_NAKLIMIT0 */
1046 #define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1048 /* Bit masks for USB_TX_MAX_PACKET */
1050 #define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1052 /* Bit masks for USB_RX_MAX_PACKET */
1054 #define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1056 /* Bit masks for USB_TXCSR */
1058 #define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1059 #define nTXPKTRDY_T 0x0
1060 #define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1061 #define nFIFO_NOT_EMPTY_T 0x0
1062 #define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1063 #define nUNDERRUN_T 0x0
1064 #define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1065 #define nFLUSHFIFO_T 0x0
1066 #define STALL_SEND_T 0x10 /* issue a Stall handshake */
1067 #define nSTALL_SEND_T 0x0
1068 #define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1069 #define nSTALL_SENT_T 0x0
1070 #define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1071 #define nCLEAR_DATATOGGLE_T 0x0
1072 #define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1073 #define nINCOMPTX_T 0x0
1074 #define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1075 #define nDMAREQMODE_T 0x0
1076 #define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1077 #define nFORCE_DATATOGGLE_T 0x0
1078 #define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1079 #define nDMAREQ_ENA_T 0x0
1080 #define ISO_T 0x4000 /* enable Isochronous transfers */
1082 #define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1083 #define nAUTOSET_T 0x0
1084 #define ERROR_TH 0x4 /* error condition host mode */
1085 #define nERROR_TH 0x0
1086 #define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1087 #define nSTALL_RECEIVED_TH 0x0
1088 #define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1089 #define nNAK_TIMEOUT_TH 0x0
1091 /* Bit masks for USB_TXCOUNT */
1093 #define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1095 /* Bit masks for USB_RXCSR */
1097 #define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1098 #define nRXPKTRDY_R 0x0
1099 #define FIFO_FULL_R 0x2 /* FIFO not empty */
1100 #define nFIFO_FULL_R 0x0
1101 #define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1102 #define nOVERRUN_R 0x0
1103 #define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1104 #define nDATAERROR_R 0x0
1105 #define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1106 #define nFLUSHFIFO_R 0x0
1107 #define STALL_SEND_R 0x20 /* issue a Stall handshake */
1108 #define nSTALL_SEND_R 0x0
1109 #define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1110 #define nSTALL_SENT_R 0x0
1111 #define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1112 #define nCLEAR_DATATOGGLE_R 0x0
1113 #define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1114 #define nINCOMPRX_R 0x0
1115 #define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1116 #define nDMAREQMODE_R 0x0
1117 #define DISNYET_R 0x1000 /* disable Nyet handshakes */
1118 #define nDISNYET_R 0x0
1119 #define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1120 #define nDMAREQ_ENA_R 0x0
1121 #define ISO_R 0x4000 /* enable Isochronous transfers */
1123 #define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1124 #define nAUTOCLEAR_R 0x0
1125 #define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1126 #define nERROR_RH 0x0
1127 #define REQPKT_RH 0x20 /* request an IN transaction host mode */
1128 #define nREQPKT_RH 0x0
1129 #define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1130 #define nSTALL_RECEIVED_RH 0x0
1131 #define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1132 #define nINCOMPRX_RH 0x0
1133 #define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1134 #define nDMAREQMODE_RH 0x0
1135 #define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1136 #define nAUTOREQ_RH 0x0
1138 /* Bit masks for USB_RXCOUNT */
1140 #define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1142 /* Bit masks for USB_TXTYPE */
1144 #define TARGET_EP_NO_T 0xf /* EP number */
1145 #define PROTOCOL_T 0xc /* transfer type */
1147 /* Bit masks for USB_TXINTERVAL */
1149 #define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1151 /* Bit masks for USB_RXTYPE */
1153 #define TARGET_EP_NO_R 0xf /* EP number */
1154 #define PROTOCOL_R 0xc /* transfer type */
1156 /* Bit masks for USB_RXINTERVAL */
1158 #define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1160 /* Bit masks for USB_DMA_INTERRUPT */
1162 #define DMA0_INT 0x1 /* DMA0 pending interrupt */
1163 #define nDMA0_INT 0x0
1164 #define DMA1_INT 0x2 /* DMA1 pending interrupt */
1165 #define nDMA1_INT 0x0
1166 #define DMA2_INT 0x4 /* DMA2 pending interrupt */
1167 #define nDMA2_INT 0x0
1168 #define DMA3_INT 0x8 /* DMA3 pending interrupt */
1169 #define nDMA3_INT 0x0
1170 #define DMA4_INT 0x10 /* DMA4 pending interrupt */
1171 #define nDMA4_INT 0x0
1172 #define DMA5_INT 0x20 /* DMA5 pending interrupt */
1173 #define nDMA5_INT 0x0
1174 #define DMA6_INT 0x40 /* DMA6 pending interrupt */
1175 #define nDMA6_INT 0x0
1176 #define DMA7_INT 0x80 /* DMA7 pending interrupt */
1177 #define nDMA7_INT 0x0
1179 /* Bit masks for USB_DMAxCONTROL */
1181 #define DMA_ENA 0x1 /* DMA enable */
1182 #define nDMA_ENA 0x0
1183 #define DIRECTION 0x2 /* direction of DMA transfer */
1184 #define nDIRECTION 0x0
1185 #define MODE 0x4 /* DMA Bus error */
1187 #define INT_ENA 0x8 /* Interrupt enable */
1188 #define nINT_ENA 0x0
1189 #define EPNUM 0xf0 /* EP number */
1190 #define BUSERROR 0x100 /* DMA Bus error */
1191 #define nBUSERROR 0x0
1193 /* Bit masks for USB_DMAxADDRHIGH */
1195 #define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1197 /* Bit masks for USB_DMAxADDRLOW */
1199 #define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1201 /* Bit masks for USB_DMAxCOUNTHIGH */
1203 #define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1205 /* Bit masks for USB_DMAxCOUNTLOW */
1207 #define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1210 /* ******************************************* */
1211 /* MULTI BIT MACRO ENUMERATIONS */
1212 /* ******************************************* */
1215 #endif /* _DEF_BF542_H */