2 * $Header: /cvs/src/src/libgloss/mt/startup-64-001.S,v 1.1 2005/12/12 11:16:41 nathan Exp $
4 * interrupt_vectors.s -- the interrupt handler jump table.
7 * There are a total of 32 interrupt vector possible, however, only
8 * 11 of those are currently used (the others are reserved). The
9 * order of vectors is as follows:
11 * 1. Boot Vector. Vector for power-on/reset.
12 * 2. Software Vector. Vector for handling the SI instruction (an
13 * explicit interrupt caused by software).
14 * 3. Break Vector. Vector for handling the Break instruction.
15 * 4. Device 0 Vector. Service vector for device zero.
16 * 5. Device 1 Vector. Service vector for device one.
17 * 6. Device 2 Vector. Service vector for device two.
18 * 7. Device 3 Vector. Service vector for device three.
19 * 8. Device 4 Vector. Service vector for device four.
20 * 9. Device 5 Vector. Service vector for device five.
21 * 10. Device 6 Vector. Service vector for device six.
22 * 11. Device 7 Vector. Service vector for device seven.
24 * The rest of the interrupt vectors are reserved for future use.
27 * Each jump table entry consists of the following two instructions:
29 * jmp Label ; Label as appropriate
30 * nop ; implemented as or r0,r0,r0
32 * The following labels are reserved for the vectors named above,
35 * _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
36 * _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
39 * 26Sep01 (DJK) The memory map is changed and the device interrupts are
42 * 10Oct01 (DJK) The memory map is finalized and the first 4K of address
43 * space is now reserved for memory-mapped I/O devices.
44 * (There is over 2K unused, reserved space in this area.)
46 * 27Jul02 (DJK) Fixed the address for the interrupt mask register. Old
47 * documentation stated the port address as 0x140, but
48 * the implementation uses 0x13c.
50 * 30Jul02 (DJK) Added support for printf. This only supports output to
51 * stderr and stdout. Using the message box interface,
52 * a (newly defined) message or series of messages is
53 * passed to the controller to output bytes as text to
54 * the debug console. These messages are constructed in
55 * the interrupt handler for the SI instruction.
56 * With this implementation, the user is unable to
57 * utilize the message box interface in applications as
58 * specialized interrupt handlers for the external
59 * interrupts are necessary.
63 * Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies, Inc.
67 .section .startup, "a", @progbits
69 _INTERRUPT_VECTOR_TABLE:
71 jmp _BOOTIVEC ; Boot vector
73 jmp _SOFTIVEC ; Vector for SI instruction
75 jmp _BRKIVEC ; Vector for Break instruction
79 ; This is the memory-mapped I/O region.
81 ; Hardware Interrupt Registers
83 .global _DEV0_INTERRUPT_REG
87 .global _DEV1_INTERRUPT_REG
91 .global _DEV2_INTERRUPT_REG
95 .global _DEV3_INTERRUPT_REG
99 .global _DEV4_INTERRUPT_REG
103 .global _DEV5_INTERRUPT_REG
107 .global _DEV6_INTERRUPT_REG
111 .global _DEV7_INTERRUPT_REG
115 ; 60 bytes minus eight registers (four bytes per register)
118 .global _INTERRUPT_MASK_REG
122 ; 256 bytes minus sixteen registers (four bytes per register)
128 ; MorphoSys Decoder Registers
129 .global _MS_DEC_AUTO_INCREMENT_REG
130 _MS_DEC_AUTO_INCREMENT_REG:
133 .global _MS_DEC_SKIP_FACTOR_REG
134 _MS_DEC_SKIP_FACTOR_REG:
137 .global _MS_DEC_CUSTOM_PERMUTATION_REG
138 _MS_DEC_CUSTOM_PERMUTATION_REG:
141 .global _MS_DEC_CONTEXT_BASE_REG
142 _MS_DEC_CONTEXT_BASE_REG:
145 .global _MS_DEC_LOOKUP_TABLE_BASE_REG
146 _MS_DEC_LOOKUP_TABLE_BASE_REG:
149 .global _MS_CIRCULAR_BUFFER_END_REG
150 _MS_CIRCULAR_BUFFER_END_REG:
151 .word (__FRAME_BUFFER_END)
153 .global _MS_CIRCULAR_BUFFER_SIZE_REG
154 _MS_CIRCULAR_BUFFER_SIZE_REG:
155 .word __FRAME_BUFFER_SIZE
157 .global _MS_DATA_BLOCK_END_REG
158 _MS_DATA_BLOCK_END_REG:
161 .global _MS_DATA_BLOCK_SIZE_REG
162 _MS_DATA_BLOCK_SIZE_REG:
165 ; 256 bytes minus nine registers (four bytes per register)
172 .global _DEBUG_HALT_REG
176 .global _DEBUG_BREAK_REG
180 .global _DEBUG_HW_RESERVED0_REG
181 _DEBUG_HW_RESERVED0_REG:
184 .global _DEBUG_HW_RESERVED1_REG
185 _DEBUG_HW_RESERVED1_REG:
188 .global _DEBUG_HW_RESERVED2_REG
189 _DEBUG_HW_RESERVED2_REG:
192 .global _DEBUG_HW_RESERVED3_REG
193 _DEBUG_HW_RESERVED3_REG:
196 .global _DEBUG_HW_RESERVED4_REG
197 _DEBUG_HW_RESERVED4_REG:
200 .global _DEBUG_SW_SYSREQ_REG
201 _DEBUG_SW_SYSREQ_REG:
204 ; 256 bytes minus eight registers (four bytes per register)
210 ; Sequence Generator Registers
217 _RESERVED_SEQ_GEN_REGS:
223 .global _TIMER0_VAL_REG
227 .global _TIMER0_CTRL_REG
231 .global _TIMER1_VAL_REG
235 .global _TIMER1_CTRL_REG
239 .global _TIMER2_VAL_REG
243 .global _TIMER2_CTRL_REG
247 ; 256 bytes minus six registers (four bytes per register)
253 .global _OUTPUT0_CONTROL
257 .global _OUTPUT1_CONTROL
261 .global _OUTPUT2_CONTROL
265 .global _OUTPUT3_CONTROL
269 .global _OUTPUT4_CONTROL
273 .global _OUTPUT5_CONTROL
277 .global _OUTPUT6_CONTROL
281 .global _OUTPUT7_CONTROL
285 ; 256 bytes minus eight registers (four bytes per register)
291 ; Reserved memory-mapped space.
292 .fill (0x1000 - 0x800)
298 .equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
299 .equ SI_IOPORT_BIT, 0x1
300 .equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
301 .equ BRK_IOPORT_BIT, 0x1
306 ; Initialize the interrupt controller's interrupt vector registers
307 ; for devices zero through seven.
308 ldui r1, #%hi16(_IVEC_DEFAULT)
309 ori r1, r1, #%lo16(_IVEC_DEFAULT)
310 stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
311 stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
312 stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
313 stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
314 stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
315 stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
316 stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
317 stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
319 ; Jump to the beginning of the application and enable interrupts.
325 ; Handler for the SI instruction. To perform a system call, the
326 ; C model uses a trapping mechanism which executes an SI instruction.
327 ; The Morpho Technologies simulator simply performs a branch to
328 ; this vector to simulate the SI instruction (this is as the hardware
329 ; behaves). In order to trigger the simulator that a system call
330 ; is needed, a write into the I/O register at address $40005 to
331 ; set bit #2 (0x4) is necessary.
333 ; The above address has been changed to 0x31C and the bit number
334 ; is zero. (The manifest constants have been changed to reflect this.)
338 ; Build a frame to save registers.
341 ldui r9, #%hi16(SI_IOPORT_ADR)
343 ori r9, r9, #%lo16(SI_IOPORT_ADR)
344 ori r10, r0, #SI_IOPORT_BIT
346 ; SYS_call is handled by simulator here...
358 ; Build a frame to save registers.
361 ldui r9, #%hi16(BRK_IOPORT_ADR)
363 ori r9, r9, #%lo16(BRK_IOPORT_ADR)
364 ori r10, r0, #BRK_IOPORT_BIT
368 subi r15, r15, #$4 ; Backup to address of break
375 .global _IVEC_DEFAULT