3 * interrupt_vectors.s -- the interrupt handler jump table.
6 * There are a total of 32 interrupt vector possible, however, only
7 * 11 of those are currently used (the others are reserved). The
8 * order of vectors is as follows:
10 * 1. Boot Vector. Vector for power-on/reset.
11 * 2. Software Vector. Vector for handling the SI instruction (an
12 * explicit interrupt caused by software).
13 * 3. Break Vector. Vector for handling the Break instruction.
14 * 4. Device 0 Vector. Service vector for device zero.
15 * 5. Device 1 Vector. Service vector for device one.
16 * 6. Device 2 Vector. Service vector for device two.
17 * 7. Device 3 Vector. Service vector for device three.
18 * 8. Device 4 Vector. Service vector for device four.
19 * 9. Device 5 Vector. Service vector for device five.
20 * 10. Device 6 Vector. Service vector for device six.
21 * 11. Device 7 Vector. Service vector for device seven.
23 * The rest of the interrupt vectors are reserved for future use.
26 * Each jump table entry consists of the following two instructions:
28 * jmp Label ; Label as appropriate
29 * nop ; implemented as or r0,r0,r0
31 * The following labels are reserved for the vectors named above,
34 * _BOOTIVEC, _SOFTIVEC, _BRKIVEC, _DEV0IVEC, _DEV1IVEC, _DEV2IVEC,
35 * _DEV3IVEC, _DEV4IVEC, _DEV5IVEC, _DEV6IVEC, _DEV7IVEC
37 * 28Apr05 (DJK) Added support for the overflow vector.
39 * XXXXXXX (DJK) Modified for the MS2 target
41 * 09Jan04 (DJK) Modified internal I/O port definitions for the
44 * 10Oct01 (DJK) The memory map is finalized and the first 4K of address
45 * space is now reserved for memory-mapped I/O devices.
46 * (There is over 2K unused, reserved space in this area.)
48 * 26Sep01 (DJK) The memory map is changed and the device interrupts are
53 * Copyright (c) 2001, 2002, 2003, 2004 Morpho Technologies
57 .section .startup, "a", @progbits
60 _INTERRUPT_VECTOR_TABLE:
61 jmp _BOOTIVEC ; Boot vector
63 jmp _SOFTIVEC ; Vector for SI instruction
65 jmp _BRKIVEC ; Vector for Break instruction
67 ; The illegal instruction trap is not implemented.
86 .equ SI_IOPORT_ADR, _DEBUG_SW_SYSREQ_REG
87 .equ SI_IOPORT_BIT, 0x1
88 .equ BRK_IOPORT_ADR, _DEBUG_BREAK_REG
89 .equ BRK_IOPORT_BIT, 0x1
93 ; Initialize the interrupt controller's interrupt vector registers
94 ldui r1, #%hi16(_IVEC_DEFAULT)
95 ori r1, r1, #%lo16(_IVEC_DEFAULT)
96 stw r1, r0, #%lo16(_DEV0_INTERRUPT_REG)
97 stw r1, r0, #%lo16(_DEV1_INTERRUPT_REG)
98 stw r1, r0, #%lo16(_DEV2_INTERRUPT_REG)
99 stw r1, r0, #%lo16(_DEV3_INTERRUPT_REG)
100 stw r1, r0, #%lo16(_DEV4_INTERRUPT_REG)
101 stw r1, r0, #%lo16(_DEV5_INTERRUPT_REG)
102 stw r1, r0, #%lo16(_DEV6_INTERRUPT_REG)
103 stw r1, r0, #%lo16(_DEV7_INTERRUPT_REG)
104 stw r1, r0, #%lo16(_DEV8_INTERRUPT_REG)
105 stw r1, r0, #%lo16(_DEV9_INTERRUPT_REG)
106 stw r1, r0, #%lo16(_DEV10_INTERRUPT_REG)
107 stw r1, r0, #%lo16(_DEV11_INTERRUPT_REG)
108 stw r1, r0, #%lo16(_DEV12_INTERRUPT_REG)
109 stw r1, r0, #%lo16(_DEV13_INTERRUPT_REG)
110 stw r1, r0, #%lo16(_DEV14_INTERRUPT_REG)
111 stw r1, r0, #%lo16(_DEV15_INTERRUPT_REG)
112 stw r1, r0, #%lo16(_DEV16_INTERRUPT_REG)
113 stw r1, r0, #%lo16(_DEV17_INTERRUPT_REG)
114 stw r1, r0, #%lo16(_DEV18_INTERRUPT_REG)
116 ; Statically initialized data must be copied from ROM to RAM.
117 ; This is done in the C run-time start-up code (crt0.o).
119 ; Jump to the beginning of the application and enable interrupts.
124 ; Handler for the SI instruction. To perform a system call, the
125 ; C model uses a trapping mechanism which executes an SI instruction.
126 ; The Morpho Technologies simulator simply performs a branch to
127 ; this vector to simulate the SI instruction (this is as the hardware
128 ; behaves). In order to trigger the simulator that a system call
129 ; is needed a write into the I/O register at address $40005 to
130 ; set bit #2 (0x4) is necessary.
132 ; The above address has been changed to 0x00031C and the bit number
133 ; is zero. (The manifest constants have been changed to reflect this.)
136 ; Build a frame to save registers.
139 ldui r9, #%hi16(SI_IOPORT_ADR)
141 ori r9, r9, #%lo16(SI_IOPORT_ADR)
142 ori r10, r0, #SI_IOPORT_BIT
144 ; SYS_call is handled by simulator here...
156 ; Build a frame to save registers.
159 ldui r9, #%hi16(BRK_IOPORT_ADR)
161 ori r9, r9, #%lo16(BRK_IOPORT_ADR)
162 ori r10, r0, #BRK_IOPORT_BIT
179 or r0, r0, r0 ; added 06Sep05
184 .global _IVEC_DEFAULT
190 .section .internal_io, "a", @nobits
191 .fill 256 ; Fill the first page.
193 ; This is the memory-mapped I/O region.
195 ; Hardware Interrupt Registers
197 .global _DEV0_INTERRUPT_REG
201 .global _DEV1_INTERRUPT_REG
205 .global _DEV2_INTERRUPT_REG
209 .global _DEV3_INTERRUPT_REG
213 .global _DEV4_INTERRUPT_REG
217 .global _DEV5_INTERRUPT_REG
221 .global _DEV6_INTERRUPT_REG
225 .global _DEV7_INTERRUPT_REG
229 .global _DEV8_INTERRUPT_REG
233 .global _DEV9_INTERRUPT_REG
237 .global _DEV10_INTERRUPT_REG
238 _DEV10_INTERRUPT_REG:
241 .global _DEV11_INTERRUPT_REG
242 _DEV11_INTERRUPT_REG:
245 .global _DEV12_INTERRUPT_REG
246 _DEV12_INTERRUPT_REG:
249 .global _DEV13_INTERRUPT_REG
250 _DEV13_INTERRUPT_REG:
253 .global _DEV14_INTERRUPT_REG
254 _DEV14_INTERRUPT_REG:
257 .global _DEV15_INTERRUPT_REG
258 _DEV15_INTERRUPT_REG:
261 .global _DEV16_INTERRUPT_REG
262 _DEV16_INTERRUPT_REG:
265 .global _DEV17_INTERRUPT_REG
266 _DEV17_INTERRUPT_REG:
269 .global _DEV18_INTERRUPT_REG
270 _DEV18_INTERRUPT_REG:
273 ; 128 bytes minus nineteen registers (four bytes per register)
276 .global _INTERRUPT_MASK_REG
280 .global _INTERRUPT_PENDING_REG
281 _INTERRUPT_PENDING_REG:
284 ; 16 bytes minus two registers (four bytes per register)
287 .global _DEV0_INTERRUPT_LEVEL_REG
288 _DEV0_INTERRUPT_LEVEL_REG:
291 .global _DEV1_INTERRUPT_LEVEL_REG
292 _DEV1_INTERRUPT_LEVEL_REG:
295 .global _DEV2_INTERRUPT_LEVEL_REG
296 _DEV2_INTERRUPT_LEVEL_REG:
299 .global _DEV3_INTERRUPT_LEVEL_REG
300 _DEV3_INTERRUPT_LEVEL_REG:
303 .global _DEV4_INTERRUPT_LEVEL_REG
304 _DEV4_INTERRUPT_LEVEL_REG:
307 .global _DEV5_INTERRUPT_LEVEL_REG
308 _DEV5_INTERRUPT_LEVEL_REG:
311 .global _DEV6_INTERRUPT_LEVEL_REG
312 _DEV6_INTERRUPT_LEVEL_REG:
315 .global _DEV7_INTERRUPT_LEVEL_REG
316 _DEV7_INTERRUPT_LEVEL_REG:
319 .global _DEV8_INTERRUPT_LEVEL_REG
320 _DEV8_INTERRUPT_LEVEL_REG:
323 .global _DEV9_INTERRUPT_LEVEL_REG
324 _DEV9_INTERRUPT_LEVEL_REG:
327 .global _DEV10_INTERRUPT_LEVEL_REG
328 _DEV10_INTERRUPT_LEVEL_REG:
331 .global _DEV11_INTERRUPT_LEVEL_REG
332 _DEV11_INTERRUPT_LEVEL_REG:
335 .global _DEV12_INTERRUPT_LEVEL_REG
336 _DEV12_INTERRUPT_LEVEL_REG:
339 .global _DEV13_INTERRUPT_LEVEL_REG
340 _DEV13_INTERRUPT_LEVEL_REG:
343 .global _DEV14_INTERRUPT_LEVEL_REG
344 _DEV14_INTERRUPT_LEVEL_REG:
347 .global _DEV15_INTERRUPT_LEVEL_REG
348 _DEV15_INTERRUPT_LEVEL_REG:
351 .global _DEV16_INTERRUPT_LEVEL_REG
352 _DEV16_INTERRUPT_LEVEL_REG:
355 .global _DEV17_INTERRUPT_LEVEL_REG
356 _DEV17_INTERRUPT_LEVEL_REG:
359 .global _DEV18_INTERRUPT_LEVEL_REG
360 _DEV18_INTERRUPT_LEVEL_REG:
363 ; 128 bytes minus twenty-three registers (four bytes per register)
368 ; MorphoSys Decoder Registers
369 .global _MS_DEC_CIRC_BUFF_SEL_REG
370 _MS_DEC_CIRC_BUFF_SEL_REG:
373 .global _MS_DEC_SKIP_FACTOR_REG
374 _MS_DEC_SKIP_FACTOR_REG:
377 .global _MS_DEC_CUSTOM_PERM_REG
378 _MS_DEC_CUSTOM_PERM_REG:
381 .global _MS_DEC_CTXT_BASE_REG
382 _MS_DEC_CTXT_BASE_REG:
385 .global _MS_DEC_LOOKUP_TBL_REG
386 _MS_DEC_LOOKUP_TBL_REG:
389 .global _MS_CIRC_BUFF0_I_REG
390 _MS_CIRC_BUFF0_I_REG:
391 .word (__FRAME_BUFFER_END)
393 .global _MS_CIRC_BUFF0_P_REG
394 _MS_CIRC_BUFF0_P_REG:
395 .word __FRAME_BUFFER_SIZE
397 .global _MS_DATA_BUFF0_B_REG
398 _MS_DATA_BUFF0_B_REG:
401 .global _MS_DATA_BUFF0_S_REG
402 _MS_DATA_BUFF0_S_REG:
405 .global _MS_CIRC_BUFF1_I_REG
406 _MS_CIRC_BUFF1_I_REG:
407 .word (__FRAME_BUFFER_END)
409 .global _MS_CIRC_BUFF1_P_REG
410 _MS_CIRC_BUFF1_P_REG:
411 .word __FRAME_BUFFER_SIZE
413 .global _MS_DATA_BUFF1_B_REG
414 _MS_DATA_BUFF1_B_REG:
417 .global _MS_DATA_BUFF1_S_REG
418 _MS_DATA_BUFF1_S_REG:
421 .global _MS_CIRC_BUFF2_I_REG
422 _MS_CIRC_BUFF2_I_REG:
423 .word (__FRAME_BUFFER_END)
425 .global _MS_CIRC_BUFF2_P_REG
426 _MS_CIRC_BUFF2_P_REG:
427 .word __FRAME_BUFFER_SIZE
429 .global _MS_DATA_BUFF2_B_REG
430 _MS_DATA_BUFF2_B_REG:
433 .global _MS_DATA_BUFF2_S_REG
434 _MS_DATA_BUFF2_S_REG:
437 .global _MS_CIRC_BUFF3_I_REG
438 _MS_CIRC_BUFF3_I_REG:
439 .word (__FRAME_BUFFER_END)
441 .global _MS_CIRC_BUFF3_P_REG
442 _MS_CIRC_BUFF3_P_REG:
443 .word __FRAME_BUFFER_SIZE
445 .global _MS_DATA_BUFF3_B_REG
446 _MS_DATA_BUFF3_B_REG:
449 .global _MS_DATA_BUFF3_S_REG
450 _MS_DATA_BUFF3_S_REG:
453 .global _MS_CIRC_BUFF4_I_REG
454 _MS_CIRC_BUFF4_I_REG:
455 .word (__FRAME_BUFFER_END)
457 .global _MS_CIRC_BUFF4_P_REG
458 _MS_CIRC_BUFF4_P_REG:
459 .word __FRAME_BUFFER_SIZE
461 .global _MS_DATA_BUFF4_B_REG
462 _MS_DATA_BUFF4_B_REG:
465 .global _MS_DATA_BUFF4_S_REG
466 _MS_DATA_BUFF4_S_REG:
469 .global _MS_CIRC_BUFF5_I_REG
470 _MS_CIRC_BUFF5_I_REG:
471 .word (__FRAME_BUFFER_END)
473 .global _MS_CIRC_BUFF5_P_REG
474 _MS_CIRC_BUFF5_P_REG:
475 .word __FRAME_BUFFER_SIZE
477 .global _MS_DATA_BUFF5_B_REG
478 _MS_DATA_BUFF5_B_REG:
481 .global _MS_DATA_BUFF5_S_REG
482 _MS_DATA_BUFF5_S_REG:
485 .global _MS_CIRC_BUFF6_I_REG
486 _MS_CIRC_BUFF6_I_REG:
487 .word (__FRAME_BUFFER_END)
489 .global _MS_CIRC_BUFF6_P_REG
490 _MS_CIRC_BUFF6_P_REG:
491 .word __FRAME_BUFFER_SIZE
493 .global _MS_DATA_BUFF6_B_REG
494 _MS_DATA_BUFF6_B_REG:
497 .global _MS_DATA_BUFF6_S_REG
498 _MS_DATA_BUFF6_S_REG:
501 .global _MS_CIRC_BUFF7_I_REG
502 _MS_CIRC_BUFF7_I_REG:
503 .word (__FRAME_BUFFER_END)
505 .global _MS_CIRC_BUFF7_P_REG
506 _MS_CIRC_BUFF7_P_REG:
507 .word __FRAME_BUFFER_SIZE
509 .global _MS_DATA_BUFF7_B_REG
510 _MS_DATA_BUFF7_B_REG:
513 .global _MS_DATA_BUFF7_S_REG
514 _MS_DATA_BUFF7_S_REG:
517 .global _MS_OMEGA_PERM1_REG
521 .global _MS_WRITE_FB_ADDR_REG
522 _MS_WRITE_FB_ADDR_REG:
525 .global _MS_OMEGA_PERM2_REG
530 ; 256 bytes minus forty registers (four bytes per register)
537 .global _DEBUG_HALT_REG
541 .global _DEBUG_BREAK_REG
545 .global _DEBUG_CRITICAL_REG
546 _DEBUG_OWNERSHIP_REG:
549 .global _DEBUG_KERNEL_ID_REG
550 _DEBUG_KERNEL_ID_REG:
553 .global _DEBUG_IRQ_STATUS_REG
554 _DEBUG_IRQ_STATUS_REG:
557 ; There are two reserved registers.
560 .global _DEBUG_SW_SYSREQ_REG
561 _DEBUG_SW_SYSREQ_REG:
564 ; 128 bytes minus eight registers (four bytes per register)
567 .global _EXTENDED_GP0_REG
571 .global _EXTENDED_GP1_REG
575 .global _EXTENDED_GP2_REG
579 .global _EXTENDED_GP3_REG
583 .global _EXTENDED_GP4_REG
587 .global _EXTENDED_GP5_REG
591 .global _EXTENDED_GP6_REG
595 .global _EXTENDED_GP7_REG
599 .global _MEM_CTRL_EN_NC_MEM_REG
600 _MEM_CTRL_EN_NC_MEM_REG:
603 .global _MEM_CTRL_BASE0_ADDR_REG
604 _MEM_CTRL_BASE0_ADDR_REG:
607 .global _MEM_CTRL_MASK0_ADDR_REG
608 _MEM_CTRL_MASK0_ADDR_REG:
611 .global _MEM_CTRL_BASE1_ADDR_REG
612 _MEM_CTRL_BASE1_ADDR_REG:
615 .global _MEM_CTRL_MASK1_ADDR_REG
616 _MEM_CTRL_MASK1_ADDR_REG:
619 .global _MEM_CTRL_BASE2_ADDR_REG
620 _MEM_CTRL_BASE2_ADDR_REG:
623 .global _MEM_CTRL_MASK2_ADDR_REG
624 _MEM_CTRL_MASK2_ADDR_REG:
627 .global _MEM_CTRL_BASE3_ADDR_REG
628 _MEM_CTRL_BASE3_ADDR_REG:
631 .global _MEM_CTRL_MASK3_ADDR_REG
632 _MEM_CTRL_MASK3_ADDR_REG:
635 ; 128 bytes minus seventeen registers (four bytes per register)
640 ; Reserved memory-map space
647 .global _TIMER0_VAL_REG
651 .global _TIMER1_VAL_REG
655 .global _TIMER2_VAL_REG
659 .global _TIMER3_VAL_REG
663 ; 256 bytes minus four registers (four bytes per register)
669 ; Output Line Control Registers
670 .global _OUTPUT0_CTRL
674 .global _OUTPUT1_CTRL
678 .global _OUTPUT2_CTRL
682 .global _OUTPUT3_CTRL
686 .global _OUTPUT4_CTRL
690 .global _OUTPUT5_CTRL
694 .global _OUTPUT6_CTRL
698 ; 128 bytes minus seven registers (four bytes per register)
705 ; 128 bytes minus one register (four bytes per register)
711 ; IQ Buffer Registers
712 .global _IQ_BUFF_CTRL_REG
716 .global _IQ_BUFF_STATUS_REG
720 .global _IQ_BUFF_PARAMETER1_REG
721 _IQ_BUFF_PARAMETER1_REG:
724 .global _IQ_BUFF_TRANSFER_SIZE1_REG
725 _IQ_BUFF_TRANSFER_SIZE1_REG:
728 .global _IQ_BUFF_FB_BASE1_REG
729 _IQ_BUFF_FB_BASE1_REG:
732 .global _IQ_BUFF_FB_SIZE1_REG
733 _IQ_BUFF_FB_SIZE1_REG:
736 .global _IQ_BUFF_PARAMETER2_REG
737 _IQ_BUFF_PARAMETER2_REG:
740 .global _IQ_BUFF_TRANSFER_SIZE2_REG
741 _IQ_BUFF_TRANSFER_SIZE2_REG:
744 .global _IQ_BUFF_FB_BASE2_REG
745 _IQ_BUFF_FB_BASE2_REG:
748 .global _IQ_BUFF_FB_SIZE2_REG
749 _IQ_BUFF_FB_SIZE2_REG:
752 ; 256 bytes minus ten registers (four bytes per register)
759 .global _DMA_CTRL_REG
763 .global _DMA_STATUS_REG
767 .global _DMA_CH0_EADDR_REG
771 .global _DMA_CH0_IADDR_REG
775 .global _DMA_CH0_SIZE_REG
779 .global _DMA_CH1_EADDR_REG
783 .global _DMA_CH1_IADDR_REG
787 .global _DMA_CH1_SIZE_REG
791 .global _DMA_CH2_EADDR_REG
795 .global _DMA_CH2_IADDR_REG
799 .global _DMA_CH2_SIZE_REG
803 .global _DMA_CH3_EADDR_REG
807 .global _DMA_CH3_IADDR_REG
811 .global _DMA_CH3_SIZE_REG
815 ; 256 bytes minus fourteen registers (four bytes per register)
822 .global _SEQ_GEN_CTRL_STATUS_REG
823 _SEQ_GEN_CTRL_STATUS_REG:
826 .global _SEQ_GEN_MASK_REGS
830 .global _SEQ_GEN_SHIFT_REG
834 ; 256 bytes minus seven registers (four bytes per register)
839 ; Reserved memory-map space
840 .fill (0x1000 - 0xf00)