linux-core/ati_pcigart.c

   1 /**
   2  * \file ati_pcigart.c
   3  * ATI PCI GART support
   4  *
   5  * \author Gareth Hughes <gareth@valinux.com>
   6  */
   7
   8 /*
   9  * Created: Wed Dec 13 21:52:19 2000 by gareth@valinux.com
  10  *
  11  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  12  * All Rights Reserved.
  13  *
  14  * Permission is hereby granted, free of charge, to any person obtaining a
  15  * copy of this software and associated documentation files (the "Software"),
  16  * to deal in the Software without restriction, including without limitation
  17  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  18  * and/or sell copies of the Software, and to permit persons to whom the
  19  * Software is furnished to do so, subject to the following conditions:
  20  *
  21  * The above copyright notice and this permission notice (including the next
  22  * paragraph) shall be included in all copies or substantial portions of the
  23  * Software.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  26  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  27  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  28  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  29  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  30  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  31  * DEALINGS IN THE SOFTWARE.
  32  */
  33
  34 #include "drmP.h"
  35
  36 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
  37 # define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
  38
  39 #define ATI_PCIE_WRITE 0x4
  40 #define ATI_PCIE_READ 0x8
  41
  42 static __inline__ void gart_insert_page_into_table(struct drm_ati_pcigart_info *gart_info, dma_addr_t addr, u32 *pci_gart)
  43 {
  44         u32 page_base;
  45
  46         page_base = (u32)addr & ATI_PCIGART_PAGE_MASK;
  47         switch(gart_info->gart_reg_if) {
  48         case DRM_ATI_GART_IGP:
  49                 page_base |= (upper_32_bits(addr) & 0xff) << 4;
  50                 page_base |= 0xc;
  51                 break;
  52         case DRM_ATI_GART_PCIE:
  53                 page_base >>= 8;
  54                 page_base |= (upper_32_bits(addr) & 0xff) << 24;
  55                 page_base |= ATI_PCIE_READ | ATI_PCIE_WRITE;
  56                 break;
  57         default:
  58         case DRM_ATI_GART_PCI:
  59                 break;
  60         }
  61         *pci_gart = cpu_to_le32(page_base);
  62 }
  63
  64 static __inline__ dma_addr_t gart_get_page_from_table(struct drm_ati_pcigart_info *gart_info, u32 *pci_gart)
  65 {
  66         dma_addr_t retval;
  67         switch(gart_info->gart_reg_if) {
  68         case DRM_ATI_GART_IGP:
  69                 retval = (*pci_gart & ATI_PCIGART_PAGE_MASK);
  70                 retval += (((*pci_gart & 0xf0) >> 4) << 16) << 16;
  71                 break;
  72         case DRM_ATI_GART_PCIE:
  73                 retval = (*pci_gart & ~0xc);
  74                 retval <<= 8;
  75                 break;
  76         case DRM_ATI_GART_PCI:
  77                 retval = *pci_gart;
  78                 break;
  79         }
  80
  81         return retval;
  82 }
  83
  84 int drm_ati_alloc_pcigart_table(struct drm_device *dev,
  85                                 struct drm_ati_pcigart_info *gart_info)
  86 {
  87         gart_info->table_handle = drm_pci_alloc(dev, gart_info->table_size,
  88                                                 PAGE_SIZE,
  89                                                 gart_info->table_mask);
  90         if (gart_info->table_handle == NULL)
  91                 return -ENOMEM;
  92
  93 #ifdef CONFIG_X86
  94         /* IGPs only exist on x86 in any case */
  95         if (gart_info->gart_reg_if == DRM_ATI_GART_IGP)
  96                 set_memory_uc(gart_info->table_handle->vaddr, gart_info->table_size >> PAGE_SHIFT);
  97 #endif
  98
  99         memset(gart_info->table_handle->vaddr, 0, gart_info->table_size);
 100         return 0;
 101 }
 102 EXPORT_SYMBOL(drm_ati_alloc_pcigart_table);
 103
 104 static void drm_ati_free_pcigart_table(struct drm_device *dev,
 105                                        struct drm_ati_pcigart_info *gart_info)
 106 {
 107 #ifdef CONFIG_X86
 108         /* IGPs only exist on x86 in any case */
 109         if (gart_info->gart_reg_if == DRM_ATI_GART_IGP)
 110                 set_memory_wb(gart_info->table_handle->vaddr, gart_info->table_size >> PAGE_SHIFT);
 111 #endif
 112         drm_pci_free(dev, gart_info->table_handle);
 113         gart_info->table_handle = NULL;
 114 }
 115
 116 int drm_ati_pcigart_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 117 {
 118         struct drm_sg_mem *entry = dev->sg;
 119         unsigned long pages;
 120         int i;
 121         int max_pages;
 122
 123         /* we need to support large memory configurations */
 124         if (!entry) {
 125                 return 0;
 126         }
 127
 128         if (gart_info->bus_addr) {
 129
 130                 max_pages = (gart_info->table_size / sizeof(u32));
 131                 pages = (entry->pages <= max_pages)
 132                   ? entry->pages : max_pages;
 133
 134                 for (i = 0; i < pages; i++) {
 135                         if (!entry->busaddr[i])
 136                                 break;
 137                         pci_unmap_page(dev->pdev, entry->busaddr[i],
 138                                          PAGE_SIZE, PCI_DMA_TODEVICE);
 139                 }
 140
 141                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
 142                         gart_info->bus_addr = 0;
 143         }
 144
 145
 146         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN
 147             && gart_info->table_handle) {
 148
 149                 drm_ati_free_pcigart_table(dev, gart_info);
 150         }
 151
 152         return 1;
 153 }
 154 EXPORT_SYMBOL(drm_ati_pcigart_cleanup);
 155
 156 int drm_ati_pcigart_init(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
 157 {
 158         struct drm_sg_mem *entry = dev->sg;
 159         void *address = NULL;
 160         unsigned long pages;
 161         u32 *pci_gart;
 162         dma_addr_t bus_address = 0;
 163         int i, j, ret = 0;
 164         int max_pages;
 165         dma_addr_t entry_addr;
 166
 167
 168         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN && gart_info->table_handle == NULL) {
 169                 DRM_DEBUG("PCI: no table in VRAM: using normal RAM\n");
 170
 171                 ret = drm_ati_alloc_pcigart_table(dev, gart_info);
 172                 if (ret) {
 173                         DRM_ERROR("cannot allocate PCI GART page!\n");
 174                         goto done;
 175                 }
 176         }
 177
 178         if (gart_info->gart_table_location == DRM_ATI_GART_MAIN) {
 179                 address = gart_info->table_handle->vaddr;
 180                 bus_address = gart_info->table_handle->busaddr;
 181         } else {
 182                 address = gart_info->addr;
 183                 bus_address = gart_info->bus_addr;
 184         }
 185
 186         if (!entry) {
 187                 DRM_ERROR("no scatter/gather memory!\n");
 188                 goto done;
 189         }
 190
 191         pci_gart = (u32 *) address;
 192
 193         max_pages = (gart_info->table_size / sizeof(u32));
 194         pages = (entry->pages <= max_pages)
 195             ? entry->pages : max_pages;
 196
 197         for (i = 0; i < pages; i++) {
 198                 /* we need to support large memory configurations */
 199                 entry->busaddr[i] = pci_map_page(dev->pdev, entry->pagelist[i],
 200                                                  0, PAGE_SIZE, PCI_DMA_TODEVICE);
 201                 if (entry->busaddr[i] == 0) {
 202                         DRM_ERROR("unable to map PCIGART pages!\n");
 203                         drm_ati_pcigart_cleanup(dev, gart_info);
 204                         address = NULL;
 205                         bus_address = 0;
 206                         goto done;
 207                 }
 208
 209                 entry_addr = entry->busaddr[i];
 210                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
 211                         gart_insert_page_into_table(gart_info, entry_addr, pci_gart);
 212                         pci_gart++;
 213                         entry_addr += ATI_PCIGART_PAGE_SIZE;
 214                 }
 215         }
 216
 217         ret = 1;
 218
 219         mb();
 220
 221       done:
 222         gart_info->addr = address;
 223         gart_info->bus_addr = bus_address;
 224         return ret;
 225 }
 226 EXPORT_SYMBOL(drm_ati_pcigart_init);
 227
 228 static int ati_pcigart_needs_unbind_cache_adjust(struct drm_ttm_backend *backend)
 229 {
 230         return ((backend->flags & DRM_BE_FLAG_BOUND_CACHED) ? 0 : 1);
 231 }
 232
 233 static int ati_pcigart_populate(struct drm_ttm_backend *backend,
 234                                 unsigned long num_pages,
 235                                 struct page **pages,
 236                                 struct page *dummy_read_page)
 237 {
 238         struct ati_pcigart_ttm_backend *atipci_be =
 239                 container_of(backend, struct ati_pcigart_ttm_backend, backend);
 240
 241         atipci_be->pages = pages;
 242         atipci_be->num_pages = num_pages;
 243         atipci_be->populated = 1;
 244         return 0;
 245 }
 246
 247 static int ati_pcigart_bind_ttm(struct drm_ttm_backend *backend,
 248                                 struct drm_bo_mem_reg *bo_mem)
 249 {
 250         struct ati_pcigart_ttm_backend *atipci_be =
 251                 container_of(backend, struct ati_pcigart_ttm_backend, backend);
 252         off_t j;
 253         int i;
 254         struct drm_ati_pcigart_info *info = atipci_be->gart_info;
 255         u32 *pci_gart;
 256         dma_addr_t offset = bo_mem->mm_node->start;
 257         dma_addr_t page_base;
 258
 259         pci_gart = info->addr;
 260
 261         j = offset;
 262         while (j < (offset + atipci_be->num_pages)) {
 263                 if (gart_get_page_from_table(info, pci_gart+j))
 264                         return -EBUSY;
 265                 j++;
 266         }
 267
 268         for (i = 0, j = offset; i < atipci_be->num_pages; i++, j++) {
 269                 struct page *cur_page = atipci_be->pages[i];
 270                 /* write value */
 271                 page_base = page_to_phys(cur_page);
 272                 gart_insert_page_into_table(info, page_base, pci_gart + j);
 273         }
 274
 275         mb();
 276
 277         atipci_be->gart_flush_fn(atipci_be->dev);
 278
 279         atipci_be->bound = 1;
 280         atipci_be->offset = offset;
 281         /* need to traverse table and add entries */
 282         DRM_DEBUG("\n");
 283         return 0;
 284 }
 285
 286 static int ati_pcigart_unbind_ttm(struct drm_ttm_backend *backend)
 287 {
 288         struct ati_pcigart_ttm_backend *atipci_be =
 289                 container_of(backend, struct ati_pcigart_ttm_backend, backend);
 290         struct drm_ati_pcigart_info *info = atipci_be->gart_info;
 291         unsigned long offset = atipci_be->offset;
 292         int i;
 293         off_t j;
 294         u32 *pci_gart = info->addr;
 295
 296         if (atipci_be->bound != 1)
 297                 return -EINVAL;
 298
 299         for (i = 0, j = offset; i < atipci_be->num_pages; i++, j++) {
 300                 *(pci_gart + j) = 0;
 301         }
 302         atipci_be->gart_flush_fn(atipci_be->dev);
 303         atipci_be->bound = 0;
 304         atipci_be->offset = 0;
 305         return 0;
 306 }
 307
 308 static void ati_pcigart_clear_ttm(struct drm_ttm_backend *backend)
 309 {
 310         struct ati_pcigart_ttm_backend *atipci_be =
 311                 container_of(backend, struct ati_pcigart_ttm_backend, backend);
 312
 313         DRM_DEBUG("\n");
 314         if (atipci_be->pages) {
 315                 backend->func->unbind(backend);
 316                 atipci_be->pages = NULL;
 317
 318         }
 319         atipci_be->num_pages = 0;
 320 }
 321
 322 static void ati_pcigart_destroy_ttm(struct drm_ttm_backend *backend)
 323 {
 324         struct ati_pcigart_ttm_backend *atipci_be;
 325         if (backend) {
 326                 DRM_DEBUG("\n");
 327                 atipci_be = container_of(backend, struct ati_pcigart_ttm_backend, backend);
 328                 if (atipci_be) {
 329                         if (atipci_be->pages) {
 330                                 backend->func->clear(backend);
 331                         }
 332                         drm_ctl_free(atipci_be, sizeof(*atipci_be), DRM_MEM_TTM);
 333                 }
 334         }
 335 }
 336
 337 static struct drm_ttm_backend_func ati_pcigart_ttm_backend =
 338 {
 339         .needs_ub_cache_adjust = ati_pcigart_needs_unbind_cache_adjust,
 340         .populate = ati_pcigart_populate,
 341         .clear = ati_pcigart_clear_ttm,
 342         .bind = ati_pcigart_bind_ttm,
 343         .unbind = ati_pcigart_unbind_ttm,
 344         .destroy =  ati_pcigart_destroy_ttm,
 345 };
 346
 347 struct drm_ttm_backend *ati_pcigart_init_ttm(struct drm_device *dev, struct drm_ati_pcigart_info *info, void (*gart_flush_fn)(struct drm_device *dev))
 348 {
 349         struct ati_pcigart_ttm_backend *atipci_be;
 350
 351         atipci_be = drm_ctl_calloc(1, sizeof (*atipci_be), DRM_MEM_TTM);
 352         if (!atipci_be)
 353                 return NULL;
 354
 355         atipci_be->populated = 0;
 356         atipci_be->backend.func = &ati_pcigart_ttm_backend;
 357 //      atipci_be->backend.mem_type = DRM_BO_MEM_TT;
 358         atipci_be->gart_info = info;
 359         atipci_be->gart_flush_fn = gart_flush_fn;
 360         atipci_be->dev = dev;
 361
 362         return &atipci_be->backend;
 363 }
 364 EXPORT_SYMBOL(ati_pcigart_init_ttm);