linux-core/atombios_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon_drv.h"
  29
  30 #include "drm_crtc_helper.h"
  31 #include "atom.h"
  32 #include "atom-bits.h"
  33
  34 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
  35 {
  36         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  37         struct drm_device *dev = crtc->dev;
  38         struct drm_radeon_private *dev_priv = dev->dev_private;
  39         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
  40         ENABLE_CRTC_PS_ALLOCATION args;
  41
  42         memset(&args, 0, sizeof(args));
  43
  44         args.ucCRTC = radeon_crtc->crtc_id;
  45         args.ucEnable = state;
  46
  47         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
  48 }
  49
  50 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
  51 {
  52         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  53         struct drm_device *dev = crtc->dev;
  54         struct drm_radeon_private *dev_priv = dev->dev_private;
  55         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
  56         ENABLE_CRTC_PS_ALLOCATION args;
  57
  58         memset(&args, 0, sizeof(args));
  59
  60         args.ucCRTC = radeon_crtc->crtc_id;
  61         args.ucEnable = state;
  62
  63         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
  64 }
  65
  66 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
  67 {
  68         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  69         struct drm_device *dev = crtc->dev;
  70         struct drm_radeon_private *dev_priv = dev->dev_private;
  71         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
  72         BLANK_CRTC_PS_ALLOCATION args;
  73
  74         memset(&args, 0, sizeof(args));
  75
  76         args.ucCRTC = radeon_crtc->crtc_id;
  77         args.ucBlanking = state;
  78
  79         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&args);
  80 }
  81
  82 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
  83 {
  84         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
  85         struct drm_device *dev = crtc->dev;
  86         struct drm_radeon_private *dev_priv = dev->dev_private;
  87
  88         switch(mode) {
  89         case DRM_MODE_DPMS_ON:
  90         case DRM_MODE_DPMS_STANDBY:
  91         case DRM_MODE_DPMS_SUSPEND:
  92                 if (radeon_is_dce3(dev_priv))
  93                         atombios_enable_crtc_memreq(crtc, 1);
  94                 atombios_enable_crtc(crtc, 1);
  95                 atombios_blank_crtc(crtc, 0);
  96
  97                 radeon_crtc_load_lut(crtc);
  98                 break;
  99         case DRM_MODE_DPMS_OFF:
 100                 atombios_blank_crtc(crtc, 1);
 101                 atombios_enable_crtc(crtc, 0);
 102                 if (radeon_is_dce3(dev_priv))
 103                         atombios_enable_crtc_memreq(crtc, 0);
 104                 break;
 105         }
 106 }
 107
 108
 109 void atombios_crtc_set_timing(struct drm_crtc *crtc, SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_param)
 110 {
 111         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 112         struct drm_device *dev = crtc->dev;
 113         struct drm_radeon_private *dev_priv = dev->dev_private;
 114         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
 115         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
 116
 117         conv_param.usH_Total                = cpu_to_le16(crtc_param->usH_Total);
 118         conv_param.usH_Disp                 = cpu_to_le16(crtc_param->usH_Disp);
 119         conv_param.usH_SyncStart            = cpu_to_le16(crtc_param->usH_SyncStart);
 120         conv_param.usH_SyncWidth            = cpu_to_le16(crtc_param->usH_SyncWidth);
 121         conv_param.usV_Total                = cpu_to_le16(crtc_param->usV_Total);
 122         conv_param.usV_Disp                 = cpu_to_le16(crtc_param->usV_Disp);
 123         conv_param.usV_SyncStart            = cpu_to_le16(crtc_param->usV_SyncStart);
 124         conv_param.usV_SyncWidth            = cpu_to_le16(crtc_param->usV_SyncWidth);
 125         conv_param.susModeMiscInfo.usAccess = cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
 126         conv_param.ucCRTC                   = crtc_param->ucCRTC;
 127         conv_param.ucOverscanRight          = crtc_param->ucOverscanRight;
 128         conv_param.ucOverscanLeft           = crtc_param->ucOverscanLeft;
 129         conv_param.ucOverscanBottom         = crtc_param->ucOverscanBottom;
 130         conv_param.ucOverscanTop            = crtc_param->ucOverscanTop;
 131         conv_param.ucReserved               = crtc_param->ucReserved;
 132
 133         printk("executing set crtc timing\n");
 134         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&conv_param);
 135 }
 136
 137 void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode,
 138                            int pll_flags)
 139 {
 140         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 141         struct drm_device *dev = crtc->dev;
 142         struct drm_radeon_private *dev_priv = dev->dev_private;
 143         uint8_t frev, crev;
 144         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
 145         SET_PIXEL_CLOCK_PS_ALLOCATION spc_param;
 146         PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
 147         PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
 148         uint32_t sclock = mode->clock;
 149         uint32_t ref_div = 0, fb_div = 0, post_div = 0;
 150
 151         memset(&spc_param, 0, sizeof(SET_PIXEL_CLOCK_PS_ALLOCATION));
 152
 153         if (radeon_is_avivo(dev_priv)) {
 154                 uint32_t temp;
 155
 156                 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 157
 158                 radeon_compute_pll(&dev_priv->mode_info.pll, mode->clock,
 159                                    &temp, &fb_div, &ref_div, &post_div, pll_flags);
 160                 sclock = temp;
 161
 162                 if (radeon_crtc->crtc_id == 0) {
 163                         temp = RADEON_READ(AVIVO_P1PLL_INT_SS_CNTL);
 164                         RADEON_WRITE(AVIVO_P1PLL_INT_SS_CNTL, temp & ~1);
 165                 } else {
 166                         temp = RADEON_READ(AVIVO_P2PLL_INT_SS_CNTL);
 167                         RADEON_WRITE(AVIVO_P2PLL_INT_SS_CNTL, temp & ~1);
 168                 }
 169         } else {
 170 #if 0 // TODO r400
 171                 sclock = save->dot_clock_freq;
 172                 fb_div = save->feedback_div;
 173                 post_div = save->post_div;
 174                 ref_div = save->ppll_ref_div;
 175 #endif
 176         }
 177
 178         /* */
 179
 180         atom_parse_cmd_header(dev_priv->mode_info.atom_context, index, &frev, &crev);
 181
 182         switch(frev) {
 183         case 1:
 184                 switch(crev) {
 185                 case 1:
 186                 case 2:
 187                         spc2_ptr = (PIXEL_CLOCK_PARAMETERS_V2*)&spc_param.sPCLKInput;
 188                         spc2_ptr->usPixelClock = cpu_to_le16(sclock);
 189                         spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
 190                         spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
 191                         spc2_ptr->ucPostDiv = post_div;
 192                         spc2_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 193                         spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
 194                         spc2_ptr->ucRefDivSrc = 1;
 195                         break;
 196                 case 3:
 197                         spc3_ptr = (PIXEL_CLOCK_PARAMETERS_V3*)&spc_param.sPCLKInput;
 198                         spc3_ptr->usPixelClock = cpu_to_le16(sclock);
 199                         spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
 200                         spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
 201                         spc3_ptr->ucPostDiv = post_div;
 202                         spc3_ptr->ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
 203                         spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
 204
 205                         /* TODO insert output encoder object stuff herre for r600 */
 206                         break;
 207                 default:
 208                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 209                         return;
 210                 }
 211                 break;
 212         default:
 213                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
 214                 return;
 215         }
 216
 217         printk("executing set pll\n");
 218         atom_execute_table(dev_priv->mode_info.atom_context, index, (uint32_t *)&spc_param);
 219 }
 220
 221 void atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y)
 222 {
 223         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 224         struct drm_device *dev = crtc->dev;
 225         struct drm_radeon_private *dev_priv = dev->dev_private;
 226         struct radeon_framebuffer *radeon_fb;
 227         struct drm_radeon_gem_object *obj_priv;
 228         uint32_t fb_location, fb_format, fb_pitch_pixels;
 229
 230         if (!crtc->fb)
 231                 return;
 232
 233         radeon_fb = to_radeon_framebuffer(crtc->fb);
 234
 235         obj_priv = radeon_fb->obj->driver_private;
 236
 237         fb_location = obj_priv->bo->offset + dev_priv->fb_location;
 238
 239         switch(crtc->fb->bits_per_pixel) {
 240         case 15:
 241                 fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
 242                 break;
 243         case 16:
 244                 fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
 245                 break;
 246         case 24:
 247         case 32:
 248                 fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
 249                 break;
 250         default:
 251                 DRM_ERROR("Unsupported screen depth %d\n", crtc->fb->bits_per_pixel);
 252                 return;
 253         }
 254
 255         /* TODO tiling */
 256         if (radeon_crtc->crtc_id == 0)
 257                 RADEON_WRITE(AVIVO_D1VGA_CONTROL, 0);
 258         else
 259                 RADEON_WRITE(AVIVO_D2VGA_CONTROL, 0);
 260
 261         RADEON_WRITE(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1GRPH_UPDATE_LOCK);
 262
 263         RADEON_WRITE(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
 264         RADEON_WRITE(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, fb_location);
 265         RADEON_WRITE(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
 266
 267         RADEON_WRITE(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
 268         RADEON_WRITE(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
 269         RADEON_WRITE(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, x);
 270         RADEON_WRITE(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, y);
 271         RADEON_WRITE(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, x + crtc->mode.hdisplay);
 272         RADEON_WRITE(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, y + crtc->mode.vdisplay);
 273
 274         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
 275         RADEON_WRITE(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
 276         RADEON_WRITE(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
 277
 278         /* unlock the grph regs */
 279         RADEON_WRITE(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, 0);
 280
 281         /* lock the mode regs */
 282         RADEON_WRITE(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, AVIVO_D1SCL_UPDATE_LOCK);
 283
 284         RADEON_WRITE(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
 285                      crtc->mode.vdisplay);
 286         RADEON_WRITE(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, (x << 16) | y);
 287         RADEON_WRITE(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
 288                      (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
 289         /* unlock the mode regs */
 290         RADEON_WRITE(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0);
 291 }
 292
 293 void atombios_crtc_mode_set(struct drm_crtc *crtc,
 294                             struct drm_display_mode *mode,
 295                             struct drm_display_mode *adjusted_mode,
 296                             int x, int y)
 297 {
 298         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 299         struct drm_device *dev = crtc->dev;
 300         struct drm_radeon_private *dev_priv = dev->dev_private;
 301         struct drm_encoder *encoder;
 302         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
 303         int pll_flags = 0;
 304         /* TODO color tiling */
 305
 306         memset(&crtc_timing, 0, sizeof(crtc_timing));
 307
 308         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 309
 310
 311
 312         }
 313
 314         crtc_timing.ucCRTC = radeon_crtc->crtc_id;
 315         crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
 316         crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
 317         crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
 318         crtc_timing.usH_SyncWidth = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
 319
 320         crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
 321         crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
 322         crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
 323         crtc_timing.usV_SyncWidth = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
 324
 325         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 326                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
 327
 328         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 329                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
 330
 331         if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
 332                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
 333
 334         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
 335                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
 336
 337         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 338                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
 339
 340         if (radeon_is_avivo(dev_priv)) {
 341                 atombios_crtc_set_base(crtc, x, y);
 342         }
 343
 344         atombios_crtc_set_pll(crtc, adjusted_mode, pll_flags);
 345
 346         atombios_crtc_set_timing(crtc, &crtc_timing);
 347 }
 348
 349 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
 350                                    struct drm_display_mode *mode,
 351                                    struct drm_display_mode *adjusted_mode)
 352 {
 353         return true;
 354 }
 355
 356
 357 static void atombios_crtc_prepare(struct drm_crtc *crtc)
 358 {
 359         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 360 }
 361
 362 static void atombios_crtc_commit(struct drm_crtc *crtc)
 363 {
 364         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 365 }
 366
 367 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
 368         .dpms = atombios_crtc_dpms,
 369         .mode_fixup = atombios_crtc_mode_fixup,
 370         .mode_set = atombios_crtc_mode_set,
 371         .mode_set_base = atombios_crtc_set_base,
 372         .prepare = atombios_crtc_prepare,
 373         .commit = atombios_crtc_commit,
 374 };
 375
 376 void radeon_atombios_init_crtc(struct drm_device *dev,
 377                                struct radeon_crtc *radeon_crtc)
 378 {
 379         if (radeon_crtc->crtc_id == 1)
 380                 radeon_crtc->crtc_offset = AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
 381         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
 382 }