2 * Copyright © 2006 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
31 * register definitions for the i82807aa.
33 * Documentation on this chipset can be found in datasheet #29069001 at
38 * VCH Revision & GMBus Base Addr
41 # define VR00_BASE_ADDRESS_MASK 0x007f
44 * Functionality Enable
49 * Enable the panel fitter
51 # define VR01_PANEL_FIT_ENABLE (1 << 3)
53 * Enables the LCD display.
55 * This must not be set while VR01_DVO_BYPASS_ENABLE is set.
57 # define VR01_LCD_ENABLE (1 << 2)
58 /** Enables the DVO repeater. */
59 # define VR01_DVO_BYPASS_ENABLE (1 << 1)
60 /** Enables the DVO clock */
61 # define VR01_DVO_ENABLE (1 << 0)
64 * LCD Interface Format
67 /** Enables LVDS output instead of CMOS */
68 # define VR10_LVDS_ENABLE (1 << 4)
69 /** Enables 18-bit LVDS output. */
70 # define VR10_INTERFACE_1X18 (0 << 2)
71 /** Enables 24-bit LVDS or CMOS output */
72 # define VR10_INTERFACE_1X24 (1 << 2)
73 /** Enables 2x18-bit LVDS or CMOS output. */
74 # define VR10_INTERFACE_2X18 (2 << 2)
75 /** Enables 2x24-bit LVDS output */
76 # define VR10_INTERFACE_2X24 (3 << 2)
79 * VR20 LCD Horizontal Display Size
84 * LCD Vertical Display Size
89 * Panel power down status
92 /** Read only bit indicating that the panel is not in a safe poweroff state. */
93 # define VR30_PANEL_ON (1 << 15)
96 # define VR40_STALL_ENABLE (1 << 13)
97 # define VR40_VERTICAL_INTERP_ENABLE (1 << 12)
98 # define VR40_ENHANCED_PANEL_FITTING (1 << 11)
99 # define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10)
100 # define VR40_AUTO_RATIO_ENABLE (1 << 9)
101 # define VR40_CLOCK_GATING_ENABLE (1 << 8)
104 * Panel Fitting Vertical Ratio
105 * (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
110 * Panel Fitting Horizontal Ratio
111 * (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
116 * Horizontal Image Size
135 /* Graphics BIOS scratch 0
138 # define VR8E_PANEL_TYPE_MASK (0xf << 0)
139 # define VR8E_PANEL_INTERFACE_CMOS (0 << 4)
140 # define VR8E_PANEL_INTERFACE_LVDS (1 << 4)
141 # define VR8E_FORCE_DEFAULT_PANEL (1 << 5)
143 /* Graphics BIOS scratch 1
146 # define VR8F_VCH_PRESENT (1 << 0)
147 # define VR8F_DISPLAY_CONN (1 << 1)
148 # define VR8F_POWER_MASK (0x3c)
149 # define VR8F_POWER_POS (2)
155 uint16_t width, height;
162 struct vch_capabilities {
163 struct aimdb_block aimdb_block;
165 uint8_t set_panel_type;
166 uint8_t slave_address;
167 uint8_t capabilities;
168 #define VCH_PANEL_FITTING_SUPPORT (0x3 << 0)
169 #define VCH_PANEL_FITTING_TEXT (1 << 2)
170 #define VCH_PANEL_FITTING_GRAPHICS (1 << 3)
171 #define VCH_PANEL_FITTING_RATIO (1 << 4)
172 #define VCH_DITHERING (1 << 5)
173 uint8_t backlight_gpio;
174 uint8_t set_panel_type_us_gpios;
175 } __attribute__ ((packed));
178 static void ivch_dump_regs(struct intel_dvo_device *dvo);
181 * Reads a register on the ivch.
183 * Each of the 256 registers are 16 bits long.
185 static bool ivch_read(struct intel_dvo_device *dvo, int addr, uint16_t *data)
187 struct ivch_priv *priv = dvo->dev_priv;
188 struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
192 struct i2c_msg msgs[] = {
194 .addr = i2cbus->slave_addr,
200 .addr = i2cbus->slave_addr,
210 if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) {
211 *data = (in_buf[1] << 8) | in_buf[0];
216 DRM_DEBUG("Unable to read register 0x%02x from %s:%02x.\n",
217 addr, i2cbus->adapter.name, i2cbus->slave_addr);
222 /** Writes a 16-bit register on the ivch */
223 static bool ivch_write(struct intel_dvo_device *dvo, int addr, uint16_t data)
225 struct ivch_priv *priv = dvo->dev_priv;
226 struct intel_i2c_chan *i2cbus = dvo->i2c_bus;
228 struct i2c_msg msg = {
229 .addr = i2cbus->slave_addr,
236 out_buf[1] = data & 0xff;
237 out_buf[2] = data >> 8;
239 if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
243 DRM_DEBUG("Unable to write register 0x%02x to %s:%d.\n",
244 addr, i2cbus->adapter.name, i2cbus->slave_addr);
250 /** Probes the given bus and slave address for an ivch */
251 static bool ivch_init(struct intel_dvo_device *dvo,
252 struct intel_i2c_chan *i2cbus)
254 struct ivch_priv *priv;
257 priv = kzalloc(sizeof(struct ivch_priv), GFP_KERNEL);
261 dvo->i2c_bus = i2cbus;
262 dvo->i2c_bus->slave_addr = dvo->slave_addr;
263 dvo->dev_priv = priv;
266 if (!ivch_read(dvo, VR00, &temp))
270 /* Since the identification bits are probably zeroes, which doesn't seem
271 * very unique, check that the value in the base address field matches
272 * the address it's responding on.
274 if ((temp & VR00_BASE_ADDRESS_MASK) != dvo->slave_addr) {
275 DRM_DEBUG("ivch detect failed due to address mismatch "
277 (temp & VR00_BASE_ADDRESS_MASK), dvo->slave_addr);
282 if (!xf86I2CDevInit(&priv->d)) {
286 ivch_read(dvo, VR20, &priv->width);
287 ivch_read(dvo, VR21, &priv->height);
296 static enum drm_connector_status ivch_detect(struct intel_dvo_device *dvo)
298 return connector_status_connected;
301 static enum drm_mode_status ivch_mode_valid(struct intel_dvo_device *dvo,
302 struct drm_display_mode *mode)
304 if (mode->clock > 112000)
305 return MODE_CLOCK_HIGH;
310 /** Sets the power state of the panel connected to the ivch */
311 static void ivch_dpms(struct intel_dvo_device *dvo, int mode)
314 uint16_t vr01, vr30, backlight;
316 /* Set the new power state of the panel. */
317 if (!ivch_read(dvo, VR01, &vr01))
320 if (mode == DPMSModeOn)
324 ivch_write(dvo, VR80, backlight);
326 if (mode == DPMSModeOn)
327 vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE;
329 vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE);
331 ivch_write(dvo, VR01, vr01);
333 /* Wait for the panel to make its state transition */
334 for (i = 0; i < 100; i++) {
335 if (!ivch_read(dvo, VR30, &vr30))
338 if (((vr30 & VR30_PANEL_ON) != 0) == (mode == DPMSModeOn))
342 /* wait some more; vch may fail to resync sometimes without this */
346 static void ivch_mode_set(struct intel_dvo_device *dvo,
347 struct drm_display_mode *mode,
348 struct drm_display_mode *adjusted_mode)
354 vr40 = (VR40_STALL_ENABLE | VR40_VERTICAL_INTERP_ENABLE |
355 VR40_HORIZONTAL_INTERP_ENABLE);
357 if (mode->hdisplay != adjusted_mode->hdisplay ||
358 mode->vdisplay != adjusted_mode->vdisplay) {
359 uint16_t x_ratio, y_ratio;
361 vr01 |= VR01_PANEL_FIT_ENABLE;
362 vr40 |= VR40_CLOCK_GATING_ENABLE;
363 x_ratio = (((mode->hdisplay - 1) << 16) /
364 (adjusted_mode->hdisplay - 1)) >> 2;
365 y_ratio = (((mode->vdisplay - 1) << 16) /
366 (adjusted_mode->vdisplay - 1)) >> 2;
367 ivch_write (dvo, VR42, x_ratio);
368 ivch_write (dvo, VR41, y_ratio);
370 vr01 &= ~VR01_PANEL_FIT_ENABLE;
371 vr40 &= ~VR40_CLOCK_GATING_ENABLE;
373 vr40 &= ~VR40_AUTO_RATIO_ENABLE;
375 ivch_write(dvo, VR01, vr01);
376 ivch_write(dvo, VR40, vr40);
381 static void ivch_dump_regs(struct intel_dvo_device *dvo)
385 ivch_read(dvo, VR00, &val);
386 DRM_DEBUG("VR00: 0x%04x\n", val);
387 ivch_read(dvo, VR01, &val);
388 DRM_DEBUG("VR01: 0x%04x\n", val);
389 ivch_read(dvo, VR30, &val);
390 DRM_DEBUG("VR30: 0x%04x\n", val);
391 ivch_read(dvo, VR40, &val);
392 DRM_DEBUG("VR40: 0x%04x\n", val);
395 ivch_read(dvo, VR80, &val);
396 DRM_DEBUG("VR80: 0x%04x\n", val);
397 ivch_read(dvo, VR81, &val);
398 DRM_DEBUG("VR81: 0x%04x\n", val);
399 ivch_read(dvo, VR82, &val);
400 DRM_DEBUG("VR82: 0x%04x\n", val);
401 ivch_read(dvo, VR83, &val);
402 DRM_DEBUG("VR83: 0x%04x\n", val);
403 ivch_read(dvo, VR84, &val);
404 DRM_DEBUG("VR84: 0x%04x\n", val);
405 ivch_read(dvo, VR85, &val);
406 DRM_DEBUG("VR85: 0x%04x\n", val);
407 ivch_read(dvo, VR86, &val);
408 DRM_DEBUG("VR86: 0x%04x\n", val);
409 ivch_read(dvo, VR87, &val);
410 DRM_DEBUG("VR87: 0x%04x\n", val);
411 ivch_read(dvo, VR88, &val);
412 DRM_DEBUG("VR88: 0x%04x\n", val);
414 /* Scratch register 0 - AIM Panel type */
415 ivch_read(dvo, VR8E, &val);
416 DRM_DEBUG("VR8E: 0x%04x\n", val);
418 /* Scratch register 1 - Status register */
419 ivch_read(dvo, VR8F, &val);
420 DRM_DEBUG("VR8F: 0x%04x\n", val);
423 static void ivch_save(struct intel_dvo_device *dvo)
425 struct ivch_priv *priv = dvo->dev_priv;
427 ivch_read(dvo, VR01, &priv->save_VR01);
428 ivch_read(dvo, VR40, &priv->save_VR40);
431 static void ivch_restore(struct intel_dvo_device *dvo)
433 struct ivch_priv *priv = dvo->dev_priv;
435 ivch_write(dvo, VR01, priv->save_VR01);
436 ivch_write(dvo, VR40, priv->save_VR40);
439 static void ivch_destroy(struct intel_dvo_device *dvo)
441 struct ivch_priv *priv = dvo->dev_priv;
445 dvo->dev_priv = NULL;
449 struct intel_dvo_dev_ops ivch_ops= {
453 .restore = ivch_restore,
454 .mode_valid = ivch_mode_valid,
455 .mode_set = ivch_mode_set,
456 .detect = ivch_detect,
457 .dump_regs = ivch_dump_regs,
458 .destroy = ivch_destroy,