4 /* WARNING: These defines must be the same as what the Xserver uses.
5 * if you change them, you must change the defines in the Xserver.
11 #define I810_DMA_BUF_ORDER 12
12 #define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER)
13 #define I810_DMA_BUF_NR 256
14 #define I810_NR_SAREA_CLIPRECTS 8
16 /* Each region is a minimum of 64k, and there are at most 64 of them.
18 #define I810_NR_TEX_REGIONS 64
19 #define I810_LOG_MIN_TEX_REGION_SIZE 16
22 #define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
23 #define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
24 #define I810_UPLOAD_CTX 0x4
25 #define I810_UPLOAD_BUFFERS 0x8
26 #define I810_UPLOAD_TEX0 0x10
27 #define I810_UPLOAD_TEX1 0x20
28 #define I810_UPLOAD_CLIPRECTS 0x40
30 /* Indices into buf.Setup where various bits of state are mirrored per
31 * context and per buffer. These can be fired at the card as a unit,
32 * or in a piecewise fashion as required.
36 * - backbuffer linear offset and pitch -- invarient in the current dri
37 * - zbuffer linear offset and pitch -- also invarient
38 * - drawing origin in back and depth buffers.
40 * Keep the depth/back buffer state here to accommodate private buffers
43 #define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */
44 #define I810_DESTREG_DI1 1
45 #define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */
46 #define I810_DESTREG_DV1 3
47 #define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */
48 #define I810_DESTREG_DR1 5
49 #define I810_DESTREG_DR2 6
50 #define I810_DESTREG_DR3 7
51 #define I810_DESTREG_DR4 8
52 #define I810_DEST_SETUP_SIZE 10
56 #define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */
57 #define I810_CTXREG_CF1 1
58 #define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */
59 #define I810_CTXREG_ST1 3
60 #define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */
61 #define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */
62 #define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */
63 #define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
64 #define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */
65 #define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
66 #define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
67 #define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
68 #define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */
69 #define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */
70 #define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */
71 #define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */
72 #define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
73 #define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */
74 #define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */
75 #define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */
76 #define I810_CTX_SETUP_SIZE 20
78 /* Texture state (per tex unit)
80 #define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */
81 #define I810_TEXREG_MI1 1
82 #define I810_TEXREG_MI2 2
83 #define I810_TEXREG_MI3 3
84 #define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */
85 #define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */
86 #define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */
87 #define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */
88 #define I810_TEX_SETUP_SIZE 8
90 /* Flags for clear ioctl
92 #define I810_FRONT 0x1
94 #define I810_DEPTH 0x4
96 typedef enum _drm_i810_init_func {
98 I810_CLEANUP_DMA = 0x02,
99 I810_INIT_DMA_1_4 = 0x03
100 } drm_i810_init_func_t;
102 /* This is the init structure after v1.2 */
103 typedef struct _drm_i810_init {
104 drm_i810_init_func_t func;
105 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
109 unsigned int mmio_offset;
110 unsigned int buffers_offset;
112 int sarea_priv_offset;
113 unsigned int ring_start;
114 unsigned int ring_end;
115 unsigned int ring_size;
116 unsigned int front_offset;
117 unsigned int back_offset;
118 unsigned int depth_offset;
119 unsigned int overlay_offset;
120 unsigned int overlay_physical;
124 unsigned int pitch_bits;
127 /* This is the init structure prior to v1.2 */
128 typedef struct _drm_i810_pre12_init {
129 drm_i810_init_func_t func;
130 #if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
134 unsigned int mmio_offset;
135 unsigned int buffers_offset;
137 int sarea_priv_offset;
138 unsigned int ring_start;
139 unsigned int ring_end;
140 unsigned int ring_size;
141 unsigned int front_offset;
142 unsigned int back_offset;
143 unsigned int depth_offset;
147 unsigned int pitch_bits;
148 } drm_i810_pre12_init_t;
150 /* Warning: If you change the SAREA structure you must change the Xserver
151 * structure as well */
153 typedef struct _drm_i810_tex_region {
154 unsigned char next, prev; /* indices to form a circular LRU */
155 unsigned char in_use; /* owned by a client, or free? */
156 int age; /* tracked by clients to update local LRU's */
157 } drm_i810_tex_region_t;
159 typedef struct _drm_i810_sarea {
160 unsigned int ContextState[I810_CTX_SETUP_SIZE];
161 unsigned int BufferState[I810_DEST_SETUP_SIZE];
162 unsigned int TexState[2][I810_TEX_SETUP_SIZE];
166 drm_clip_rect_t boxes[I810_NR_SAREA_CLIPRECTS];
168 /* Maintain an LRU of contiguous regions of texture space. If
169 * you think you own a region of texture memory, and it has an
170 * age different to the one you set, then you are mistaken and
171 * it has been stolen by another client. If global texAge
172 * hasn't changed, there is no need to walk the list.
174 * These regions can be used as a proxy for the fine-grained
175 * texture information of other clients - by maintaining them
176 * in the same lru which is used to age their own textures,
177 * clients have an approximate lru for the whole of global
178 * texture space, and can make informed decisions as to which
179 * areas to kick out. There is no need to choose whether to
180 * kick out your own texture or someone else's - simply eject
181 * them all in LRU order.
184 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
185 /* Last elt is sentinal */
186 int texAge; /* last time texture was uploaded */
187 int last_enqueue; /* last time a buffer was enqueued */
188 int last_dispatch; /* age of the most recently dispatched buffer */
189 int last_quiescent; /* */
190 int ctxOwner; /* last context to upload state */
194 int pf_enabled; /* is pageflipping allowed? */
196 int pf_current_page; /* which buffer is being displayed? */
199 /* WARNING: If you change any of these defines, make sure to change the
200 * defines in the Xserver file (xf86drmMga.h)
203 /* i810 specific ioctls
204 * The device specific ioctl range is 0x40 to 0x79.
206 #define DRM_I810_INIT 0x00
207 #define DRM_I810_VERTEX 0x01
208 #define DRM_I810_CLEAR 0x02
209 #define DRM_I810_FLUSH 0x03
210 #define DRM_I810_GETAGE 0x04
211 #define DRM_I810_GETBUF 0x05
212 #define DRM_I810_SWAP 0x06
213 #define DRM_I810_COPY 0x07
214 #define DRM_I810_DOCOPY 0x08
215 #define DRM_I810_OV0INFO 0x09
216 #define DRM_I810_FSTATUS 0x0a
217 #define DRM_I810_OV0FLIP 0x0b
218 #define DRM_I810_MC 0x0c
219 #define DRM_I810_RSTATUS 0x0d
220 #define DRM_I810_FLIP 0x0e
222 #define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
223 #define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
224 #define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
225 #define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH)
226 #define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE)
227 #define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
228 #define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP)
229 #define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
230 #define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY)
231 #define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
232 #define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS)
233 #define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
234 #define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
235 #define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS)
236 #define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP)
238 typedef struct _drm_i810_clear {
244 /* These may be placeholders if we have more cliprects than
245 * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to
246 * false, indicating that the buffer will be dispatched again with a
247 * new set of cliprects.
249 typedef struct _drm_i810_vertex {
250 int idx; /* buffer index */
251 int used; /* nr bytes in use */
252 int discard; /* client is finished with the buffer? */
255 typedef struct _drm_i810_copy_t {
256 int idx; /* buffer index */
257 int used; /* nr bytes in use */
258 void *address; /* Address to copy from */
261 #define PR_TRIANGLES (0x0<<18)
262 #define PR_TRISTRIP_0 (0x1<<18)
263 #define PR_TRISTRIP_1 (0x2<<18)
264 #define PR_TRIFAN (0x3<<18)
265 #define PR_POLYGON (0x4<<18)
266 #define PR_LINES (0x5<<18)
267 #define PR_LINESTRIP (0x6<<18)
268 #define PR_RECTS (0x7<<18)
269 #define PR_MASK (0x7<<18)
271 typedef struct drm_i810_dma {
278 typedef struct _drm_i810_overlay_t {
279 unsigned int offset; /* Address of the Overlay Regs */
280 unsigned int physical;
281 } drm_i810_overlay_t;
283 typedef struct _drm_i810_mc {
284 int idx; /* buffer index */
285 int used; /* nr bytes in use */
286 int num_blocks; /* number of GFXBlocks */
287 int *length; /* List of lengths for GFXBlocks (FUTURE) */
288 unsigned int last_render; /* Last Render Request */
291 #endif /* _I810_DRM_H_ */