linux-core/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_compat.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define WATCH_COHERENCY 0
  35 #define WATCH_BUF       0
  36 #define WATCH_EXEC      0
  37 #define WATCH_LRU       0
  38 #define WATCH_RELOC     0
  39 #define WATCH_INACTIVE  0
  40 #define WATCH_PWRITE    0
  41
  42 #if WATCH_BUF | WATCH_EXEC | WATCH_PWRITE
  43 static void
  44 i915_gem_dump_object(struct drm_gem_object *obj, int len,
  45                      const char *where, uint32_t mark);
  46 #endif
  47
  48 static int
  49 i915_gem_object_set_domain(struct drm_gem_object *obj,
  50                             uint32_t read_domains,
  51                             uint32_t write_domain);
  52 int
  53 i915_gem_set_domain(struct drm_gem_object *obj,
  54                     struct drm_file *file_priv,
  55                     uint32_t read_domains,
  56                     uint32_t write_domain);
  57
  58 static void
  59 i915_gem_clflush_object(struct drm_gem_object *obj);
  60
  61 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
  62                      unsigned long end)
  63 {
  64         struct drm_i915_private *dev_priv = dev->dev_private;
  65
  66         if (start >= end ||
  67             (start & (PAGE_SIZE - 1)) != 0 ||
  68             (end & (PAGE_SIZE - 1)) != 0) {
  69                 return -EINVAL;
  70         }
  71
  72         drm_memrange_init(&dev_priv->mm.gtt_space, start,
  73                           end - start);
  74
  75         dev->gtt_total = (uint32_t) (end - start);
  76
  77         return 0;
  78 }
  79
  80 int
  81 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  82                     struct drm_file *file_priv)
  83 {
  84         struct drm_i915_gem_init *args = data;
  85         int ret;
  86
  87         mutex_lock(&dev->struct_mutex);
  88         ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
  89         mutex_unlock(&dev->struct_mutex);
  90
  91         return ret;
  92 }
  93
  94
  95 /**
  96  * Creates a new mm object and returns a handle to it.
  97  */
  98 int
  99 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 100                       struct drm_file *file_priv)
 101 {
 102         struct drm_i915_gem_create *args = data;
 103         struct drm_gem_object *obj;
 104         int handle, ret;
 105
 106         args->size = roundup(args->size, PAGE_SIZE);
 107
 108         /* Allocate the new object */
 109         obj = drm_gem_object_alloc(dev, args->size);
 110         if (obj == NULL)
 111                 return -ENOMEM;
 112
 113         ret = drm_gem_handle_create(file_priv, obj, &handle);
 114         mutex_lock(&dev->struct_mutex);
 115         drm_gem_object_handle_unreference(obj);
 116         mutex_unlock(&dev->struct_mutex);
 117
 118         if (ret)
 119                 return ret;
 120
 121         args->handle = handle;
 122
 123         return 0;
 124 }
 125
 126 /**
 127  * Reads data from the object referenced by handle.
 128  *
 129  * On error, the contents of *data are undefined.
 130  */
 131 int
 132 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 133                      struct drm_file *file_priv)
 134 {
 135         struct drm_i915_gem_pread *args = data;
 136         struct drm_gem_object *obj;
 137         ssize_t read;
 138         loff_t offset;
 139         int ret;
 140
 141         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 142         if (obj == NULL)
 143                 return -EINVAL;
 144
 145         mutex_lock(&dev->struct_mutex);
 146         ret = i915_gem_set_domain(obj, file_priv,
 147                                   I915_GEM_DOMAIN_CPU, 0);
 148         if (ret) {
 149                 drm_gem_object_unreference(obj);
 150                 mutex_unlock(&dev->struct_mutex);
 151                 return ret;
 152         }
 153         offset = args->offset;
 154
 155         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
 156                         args->size, &offset);
 157         if (read != args->size) {
 158                 drm_gem_object_unreference(obj);
 159                 mutex_unlock(&dev->struct_mutex);
 160                 if (read < 0)
 161                         return read;
 162                 else
 163                         return -EINVAL;
 164         }
 165
 166         drm_gem_object_unreference(obj);
 167         mutex_unlock(&dev->struct_mutex);
 168
 169         return 0;
 170 }
 171
 172 #include "drm_compat.h"
 173
 174 /**
 175  * Writes data to the object referenced by handle.
 176  *
 177  * On error, the contents of the buffer that were to be modified are undefined.
 178  */
 179 int
 180 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 181                       struct drm_file *file_priv)
 182 {
 183         struct drm_i915_gem_pwrite *args = data;
 184         struct drm_gem_object *obj;
 185         struct drm_i915_gem_object *obj_priv;
 186         ssize_t remain;
 187         loff_t offset;
 188         char __user *user_data;
 189         char *vaddr;
 190         int i, o, l;
 191         int ret = 0;
 192         unsigned long pfn;
 193         unsigned long unwritten;
 194
 195         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 196         if (obj == NULL)
 197                 return -EINVAL;
 198
 199         /** Bounds check destination.
 200          *
 201          * XXX: This could use review for overflow issues...
 202          */
 203         if (args->offset > obj->size || args->size > obj->size ||
 204             args->offset + args->size > obj->size)
 205                 return -EFAULT;
 206
 207         user_data = (char __user *) (uintptr_t) args->data_ptr;
 208         remain = args->size;
 209         if (!access_ok(VERIFY_READ, user_data, remain))
 210                 return -EFAULT;
 211
 212
 213         mutex_lock(&dev->struct_mutex);
 214         ret = i915_gem_object_pin(obj, 0);
 215         if (ret) {
 216                 drm_gem_object_unreference(obj);
 217                 mutex_unlock(&dev->struct_mutex);
 218                 return ret;
 219         }
 220         ret = i915_gem_set_domain(obj, file_priv,
 221                                   I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 222         if (ret)
 223                 goto fail;
 224
 225         obj_priv = obj->driver_private;
 226         offset = obj_priv->gtt_offset + args->offset;
 227         obj_priv->dirty = 1;
 228
 229         while (remain > 0) {
 230
 231                 /** Operation in this page
 232                  *
 233                  * i = page number
 234                  * o = offset within page
 235                  * l = bytes to copy
 236                  */
 237                 i = offset >> PAGE_SHIFT;
 238                 o = offset & (PAGE_SIZE-1);
 239                 l = remain;
 240                 if ((o + l) > PAGE_SIZE)
 241                         l = PAGE_SIZE - o;
 242
 243                 pfn = (dev->agp->base >> PAGE_SHIFT) + i;
 244
 245 #ifdef DRM_KMAP_ATOMIC_PROT_PFN
 246                 /* kmap_atomic can't map IO pages on non-HIGHMEM kernels
 247                  */
 248                 vaddr = kmap_atomic_prot_pfn(pfn, KM_USER0,
 249                                              __pgprot(__PAGE_KERNEL));
 250 #if WATCH_PWRITE
 251                 DRM_INFO("pwrite i %d o %d l %d pfn %ld vaddr %p\n",
 252                          i, o, l, pfn, vaddr);
 253 #endif
 254                 unwritten = __copy_from_user_inatomic_nocache(vaddr + o, user_data, l);
 255                 kunmap_atomic(vaddr, KM_USER0);
 256
 257                 if (unwritten)
 258 #endif
 259                 {
 260                         vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
 261 #if WATCH_PWRITE
 262                         DRM_INFO("pwrite slow i %d o %d l %d pfn %ld vaddr %p\n",
 263                                  i, o, l, pfn, vaddr);
 264 #endif
 265                         if (vaddr == NULL) {
 266                                 ret = -EFAULT;
 267                                 goto fail;
 268                         }
 269                         unwritten = __copy_from_user(vaddr + o, user_data, l);
 270 #if WATCH_PWRITE
 271                         DRM_INFO("unwritten %ld\n", unwritten);
 272 #endif
 273                         iounmap(vaddr);
 274                         if (unwritten) {
 275                                 ret = -EFAULT;
 276                                 goto fail;
 277                         }
 278                 }
 279
 280                 remain -= l;
 281                 user_data += l;
 282                 offset += l;
 283         }
 284 #if WATCH_PWRITE && 1
 285         i915_gem_clflush_object(obj);
 286         i915_gem_dump_object(obj, args->offset + args->size, __func__, ~0);
 287         i915_gem_clflush_object(obj);
 288 #endif
 289
 290 fail:
 291         i915_gem_object_unpin (obj);
 292         drm_gem_object_unreference(obj);
 293         mutex_unlock(&dev->struct_mutex);
 294
 295 #if WATCH_PWRITE
 296         if (ret)
 297                 DRM_INFO("pwrite failed %d\n", ret);
 298 #endif
 299         return ret;
 300 }
 301
 302 /**
 303  * Called when user space prepares to use an object
 304  */
 305 int
 306 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 307                           struct drm_file *file_priv)
 308 {
 309         struct drm_i915_gem_set_domain *args = data;
 310         struct drm_gem_object *obj;
 311         int ret;
 312
 313         if (!(dev->driver->driver_features & DRIVER_GEM))
 314                 return -ENODEV;
 315
 316         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 317         if (obj == NULL)
 318                 return -EINVAL;
 319
 320         mutex_lock(&dev->struct_mutex);
 321         ret = i915_gem_set_domain(obj, file_priv,
 322                                   args->read_domains, args->write_domain);
 323         drm_gem_object_unreference(obj);
 324         mutex_unlock(&dev->struct_mutex);
 325         return ret;
 326 }
 327
 328 /**
 329  * Called when user space has done writes to this buffer
 330  */
 331 int
 332 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 333                       struct drm_file *file_priv)
 334 {
 335         struct drm_i915_gem_sw_finish *args = data;
 336         struct drm_gem_object *obj;
 337         struct drm_i915_gem_object *obj_priv;
 338         int ret = 0;
 339
 340         if (!(dev->driver->driver_features & DRIVER_GEM))
 341                 return -ENODEV;
 342
 343         mutex_lock(&dev->struct_mutex);
 344         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 345         if (obj == NULL) {
 346                 mutex_unlock(&dev->struct_mutex);
 347                 return -EINVAL;
 348         }
 349
 350 #if WATCH_BUF
 351         DRM_INFO("%s: sw_finish %d (%p)\n",
 352                  __func__, args->handle, obj);
 353 #endif
 354         obj_priv = obj->driver_private;
 355
 356         /** Pinned buffers may be scanout, so flush the cache
 357          */
 358         if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) {
 359                 i915_gem_clflush_object(obj);
 360                 drm_agp_chipset_flush(dev);
 361         }
 362         drm_gem_object_unreference(obj);
 363         mutex_unlock(&dev->struct_mutex);
 364         return ret;
 365 }
 366
 367 /**
 368  * Maps the contents of an object, returning the address it is mapped
 369  * into.
 370  *
 371  * While the mapping holds a reference on the contents of the object, it doesn't
 372  * imply a ref on the object itself.
 373  */
 374 int
 375 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 376                    struct drm_file *file_priv)
 377 {
 378         struct drm_i915_gem_mmap *args = data;
 379         struct drm_gem_object *obj;
 380         loff_t offset;
 381         unsigned long addr;
 382
 383         if (!(dev->driver->driver_features & DRIVER_GEM))
 384                 return -ENODEV;
 385
 386         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 387         if (obj == NULL)
 388                 return -EINVAL;
 389
 390         offset = args->offset;
 391
 392         down_write(&current->mm->mmap_sem);
 393         addr = do_mmap(obj->filp, 0, args->size,
 394                        PROT_READ | PROT_WRITE, MAP_SHARED,
 395                        args->offset);
 396         up_write(&current->mm->mmap_sem);
 397         mutex_lock(&dev->struct_mutex);
 398         drm_gem_object_unreference(obj);
 399         mutex_unlock(&dev->struct_mutex);
 400         if (IS_ERR((void *)addr))
 401                 return addr;
 402
 403         args->addr_ptr = (uint64_t) addr;
 404
 405         return 0;
 406 }
 407
 408 static void
 409 i915_gem_object_free_page_list(struct drm_gem_object *obj)
 410 {
 411         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 412         int page_count = obj->size / PAGE_SIZE;
 413         int i;
 414
 415         if (obj_priv->page_list == NULL)
 416                 return;
 417
 418
 419         for (i = 0; i < page_count; i++)
 420                 if (obj_priv->page_list[i] != NULL) {
 421                         if (obj_priv->dirty)
 422                                 set_page_dirty(obj_priv->page_list[i]);
 423                         mark_page_accessed(obj_priv->page_list[i]);
 424                         page_cache_release(obj_priv->page_list[i]);
 425                 }
 426         obj_priv->dirty = 0;
 427
 428         drm_free(obj_priv->page_list,
 429                  page_count * sizeof(struct page *),
 430                  DRM_MEM_DRIVER);
 431         obj_priv->page_list = NULL;
 432 }
 433
 434 static void
 435 i915_gem_object_move_to_active(struct drm_gem_object *obj)
 436 {
 437         struct drm_device *dev = obj->dev;
 438         struct drm_i915_private *dev_priv = dev->dev_private;
 439         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 440
 441         /* Add a reference if we're newly entering the active list. */
 442         if (!obj_priv->active) {
 443                 drm_gem_object_reference(obj);
 444                 obj_priv->active = 1;
 445         }
 446         /* Move from whatever list we were on to the tail of execution. */
 447         list_move_tail(&obj_priv->list,
 448                        &dev_priv->mm.active_list);
 449 }
 450
 451 #if WATCH_INACTIVE
 452 static void
 453 i915_verify_inactive(struct drm_device *dev, char *file, int line)
 454 {
 455         drm_i915_private_t *dev_priv = dev->dev_private;
 456         struct drm_gem_object *obj;
 457         struct drm_i915_gem_object *obj_priv;
 458
 459         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 460                 obj = obj_priv->obj;
 461                 if (obj_priv->pin_count || obj_priv->active || (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))
 462                         DRM_ERROR("inactive %p (p %d a %d w %x)  %s:%d\n",
 463                                   obj,
 464                                   obj_priv->pin_count, obj_priv->active, obj->write_domain, file, line);
 465         }
 466 }
 467 #else
 468 #define i915_verify_inactive(dev,file,line)
 469 #endif
 470
 471 static void
 472 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
 473 {
 474         struct drm_device *dev = obj->dev;
 475         struct drm_i915_private *dev_priv = dev->dev_private;
 476         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 477
 478         i915_verify_inactive(dev, __FILE__, __LINE__);
 479         if (obj_priv->pin_count != 0)
 480                 list_del_init(&obj_priv->list);
 481         else
 482                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
 483
 484         if (obj_priv->active) {
 485                 obj_priv->active = 0;
 486                 drm_gem_object_unreference(obj);
 487         }
 488         i915_verify_inactive(dev, __FILE__, __LINE__);
 489 }
 490
 491 /**
 492  * Creates a new sequence number, emitting a write of it to the status page
 493  * plus an interrupt, which will trigger i915_user_interrupt_handler.
 494  *
 495  * Must be called with struct_lock held.
 496  *
 497  * Returned sequence numbers are nonzero on success.
 498  */
 499 static uint32_t
 500 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
 501 {
 502         struct drm_i915_private *dev_priv = dev->dev_private;
 503         struct drm_i915_gem_request *request;
 504         uint32_t seqno;
 505         int was_empty;
 506         RING_LOCALS;
 507
 508         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
 509         if (request == NULL)
 510                 return 0;
 511
 512         /* Grab the seqno we're going to make this request be, and bump the
 513          * next (skipping 0 so it can be the reserved no-seqno value).
 514          */
 515         seqno = dev_priv->mm.next_gem_seqno;
 516         dev_priv->mm.next_gem_seqno++;
 517         if (dev_priv->mm.next_gem_seqno == 0)
 518                 dev_priv->mm.next_gem_seqno++;
 519
 520         BEGIN_LP_RING(4);
 521         OUT_RING(MI_STORE_DWORD_INDEX);
 522         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 523         OUT_RING(seqno);
 524
 525         OUT_RING(GFX_OP_USER_INTERRUPT);
 526         ADVANCE_LP_RING();
 527
 528         DRM_DEBUG("%d\n", seqno);
 529
 530         request->seqno = seqno;
 531         request->emitted_jiffies = jiffies;
 532         request->flush_domains = flush_domains;
 533         was_empty = list_empty(&dev_priv->mm.request_list);
 534         list_add_tail(&request->list, &dev_priv->mm.request_list);
 535
 536         if (was_empty)
 537                 schedule_delayed_work (&dev_priv->mm.retire_work, HZ);
 538         return seqno;
 539 }
 540
 541 /**
 542  * Command execution barrier
 543  *
 544  * Ensures that all commands in the ring are finished
 545  * before signalling the CPU
 546  */
 547
 548 uint32_t
 549 i915_retire_commands(struct drm_device *dev)
 550 {
 551         struct drm_i915_private *dev_priv = dev->dev_private;
 552         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 553         uint32_t flush_domains = 0;
 554         RING_LOCALS;
 555
 556         /* The sampler always gets flushed on i965 (sigh) */
 557         if (IS_I965G(dev))
 558                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
 559         BEGIN_LP_RING(2);
 560         OUT_RING(cmd);
 561         OUT_RING(0); /* noop */
 562         ADVANCE_LP_RING();
 563         return flush_domains;
 564 }
 565
 566 /**
 567  * Moves buffers associated only with the given active seqno from the active
 568  * to inactive list, potentially freeing them.
 569  */
 570 static void
 571 i915_gem_retire_request(struct drm_device *dev,
 572                         struct drm_i915_gem_request *request)
 573 {
 574         struct drm_i915_private *dev_priv = dev->dev_private;
 575
 576         if (request->flush_domains != 0) {
 577                 struct drm_i915_gem_object *obj_priv, *next;
 578
 579                 /* First clear any buffers that were only waiting for a flush
 580                  * matching the one just retired.
 581                  */
 582
 583                 list_for_each_entry_safe(obj_priv, next,
 584                                          &dev_priv->mm.flushing_list, list) {
 585                         struct drm_gem_object *obj = obj_priv->obj;
 586
 587                         if (obj->write_domain & request->flush_domains) {
 588                                 obj->write_domain = 0;
 589                                 i915_gem_object_move_to_inactive(obj);
 590                         }
 591                 }
 592
 593         }
 594
 595         /* Move any buffers on the active list that are no longer referenced
 596          * by the ringbuffer to the flushing/inactive lists as appropriate.
 597          */
 598         while (!list_empty(&dev_priv->mm.active_list)) {
 599                 struct drm_gem_object *obj;
 600                 struct drm_i915_gem_object *obj_priv;
 601
 602                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
 603                                             struct drm_i915_gem_object,
 604                                             list);
 605                 obj = obj_priv->obj;
 606
 607                 /* If the seqno being retired doesn't match the oldest in the
 608                  * list, then the oldest in the list must still be newer than
 609                  * this seqno.
 610                  */
 611                 if (obj_priv->last_rendering_seqno != request->seqno)
 612                         return;
 613 #if WATCH_LRU
 614                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
 615                          __func__, request->seqno, obj);
 616 #endif
 617
 618                 if (obj->write_domain != 0) {
 619                         list_move_tail(&obj_priv->list,
 620                                        &dev_priv->mm.flushing_list);
 621                 } else {
 622                         i915_gem_object_move_to_inactive(obj);
 623                 }
 624         }
 625 }
 626
 627 /**
 628  * Returns true if seq1 is later than seq2.
 629  */
 630 static int
 631 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
 632 {
 633         return (int32_t)(seq1 - seq2) >= 0;
 634 }
 635
 636 uint32_t
 637 i915_get_gem_seqno(struct drm_device *dev)
 638 {
 639         struct drm_i915_private *dev_priv = dev->dev_private;
 640
 641         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
 642 }
 643
 644 /**
 645  * This function clears the request list as sequence numbers are passed.
 646  */
 647 void
 648 i915_gem_retire_requests(struct drm_device *dev)
 649 {
 650         struct drm_i915_private *dev_priv = dev->dev_private;
 651         uint32_t seqno;
 652
 653         seqno = i915_get_gem_seqno(dev);
 654
 655         while (!list_empty(&dev_priv->mm.request_list)) {
 656                 struct drm_i915_gem_request *request;
 657                 uint32_t retiring_seqno;
 658
 659                 request = list_first_entry(&dev_priv->mm.request_list,
 660                                            struct drm_i915_gem_request,
 661                                            list);
 662                 retiring_seqno = request->seqno;
 663
 664                 if (i915_seqno_passed(seqno, retiring_seqno) || dev_priv->mm.wedged) {
 665                         i915_gem_retire_request(dev, request);
 666
 667                         list_del(&request->list);
 668                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
 669                 } else
 670                         break;
 671         }
 672 }
 673
 674 void
 675 i915_gem_retire_work_handler(struct work_struct *work)
 676 {
 677         struct drm_i915_private *dev_priv;
 678         struct drm_device *dev;
 679
 680         dev_priv = container_of(work, struct drm_i915_private,
 681                                 mm.retire_work.work);
 682         dev = dev_priv->dev;
 683
 684         mutex_lock(&dev->struct_mutex);
 685         i915_gem_retire_requests(dev);
 686         if (!list_empty(&dev_priv->mm.request_list))
 687                 schedule_delayed_work (&dev_priv->mm.retire_work, HZ);
 688         mutex_unlock(&dev->struct_mutex);
 689 }
 690
 691 /**
 692  * Waits for a sequence number to be signaled, and cleans up the
 693  * request and object lists appropriately for that event.
 694  */
 695 int
 696 i915_wait_request(struct drm_device *dev, uint32_t seqno)
 697 {
 698         struct drm_i915_private *dev_priv = dev->dev_private;
 699         int ret = 0;
 700
 701         BUG_ON(seqno == 0);
 702
 703         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
 704                 dev_priv->mm.waiting_gem_seqno = seqno;
 705                 i915_user_irq_on(dev);
 706                 ret = wait_event_interruptible(dev_priv->irq_queue,
 707                                                i915_seqno_passed(i915_get_gem_seqno(dev),
 708                                                                  seqno) || dev_priv->mm.wedged);
 709                 i915_user_irq_off(dev);
 710                 dev_priv->mm.waiting_gem_seqno = 0;
 711         }
 712         if (dev_priv->mm.wedged)
 713                 ret = -EIO;
 714
 715         if (ret)
 716                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
 717                           __func__, ret, seqno, i915_get_gem_seqno(dev));
 718
 719         /* Directly dispatch request retiring.  While we have the work queue
 720          * to handle this, the waiter on a request often wants an associated
 721          * buffer to have made it to the inactive list, and we would need
 722          * a separate wait queue to handle that.
 723          */
 724         if (ret == 0)
 725                 i915_gem_retire_requests(dev);
 726
 727         return ret;
 728 }
 729
 730 static void
 731 i915_gem_flush(struct drm_device *dev,
 732                uint32_t invalidate_domains,
 733                uint32_t flush_domains)
 734 {
 735         struct drm_i915_private *dev_priv = dev->dev_private;
 736         uint32_t cmd;
 737         RING_LOCALS;
 738
 739 #if WATCH_EXEC
 740         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
 741                   invalidate_domains, flush_domains);
 742 #endif
 743
 744         if (flush_domains & I915_GEM_DOMAIN_CPU)
 745                 drm_agp_chipset_flush(dev);
 746
 747         if ((invalidate_domains|flush_domains) & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) {
 748                 /*
 749                  * read/write caches:
 750                  *
 751                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 752                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 753                  * also flushed at 2d versus 3d pipeline switches.
 754                  *
 755                  * read-only caches:
 756                  *
 757                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 758                  * MI_READ_FLUSH is set, and is always flushed on 965.
 759                  *
 760                  * I915_GEM_DOMAIN_COMMAND may not exist?
 761                  *
 762                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 763                  * invalidated when MI_EXE_FLUSH is set.
 764                  *
 765                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 766                  * invalidated with every MI_FLUSH.
 767                  *
 768                  * TLBs:
 769                  *
 770                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 771                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 772                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 773                  * are flushed at any MI_FLUSH.
 774                  */
 775
 776                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 777                 if ((invalidate_domains|flush_domains) &
 778                     I915_GEM_DOMAIN_RENDER)
 779                         cmd &= ~MI_NO_WRITE_FLUSH;
 780                 if (!IS_I965G(dev)) {
 781                         /*
 782                          * On the 965, the sampler cache always gets flushed
 783                          * and this bit is reserved.
 784                          */
 785                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 786                                 cmd |= MI_READ_FLUSH;
 787                 }
 788                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 789                         cmd |= MI_EXE_FLUSH;
 790
 791 #if WATCH_EXEC
 792                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 793 #endif
 794                 BEGIN_LP_RING(2);
 795                 OUT_RING(cmd);
 796                 OUT_RING(0); /* noop */
 797                 ADVANCE_LP_RING();
 798         }
 799 }
 800
 801 /**
 802  * Ensures that all rendering to the object has completed and the object is
 803  * safe to unbind from the GTT or access from the CPU.
 804  */
 805 static int
 806 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
 807 {
 808         struct drm_device *dev = obj->dev;
 809         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 810         int ret;
 811
 812         /* If there are writes queued to the buffer, flush and
 813          * create a new seqno to wait for.
 814          */
 815         if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) {
 816                 uint32_t write_domain = obj->write_domain;
 817 #if WATCH_BUF
 818                 DRM_INFO("%s: flushing object %p from write domain %08x\n",
 819                           __func__, obj, write_domain);
 820 #endif
 821                 i915_gem_flush(dev, 0, write_domain);
 822                 obj->write_domain = 0;
 823
 824                 i915_gem_object_move_to_active(obj);
 825                 obj_priv->last_rendering_seqno = i915_add_request(dev,
 826                                                                   write_domain);
 827                 BUG_ON(obj_priv->last_rendering_seqno == 0);
 828 #if WATCH_LRU
 829                 DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj);
 830 #endif
 831         }
 832         /* If there is rendering queued on the buffer being evicted, wait for
 833          * it.
 834          */
 835         if (obj_priv->active) {
 836 #if WATCH_BUF
 837                 DRM_INFO("%s: object %p wait for seqno %08x\n",
 838                           __func__, obj, obj_priv->last_rendering_seqno);
 839 #endif
 840                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
 841                 if (ret != 0)
 842                         return ret;
 843         }
 844
 845         return 0;
 846 }
 847
 848 /**
 849  * Unbinds an object from the GTT aperture.
 850  */
 851 static int
 852 i915_gem_object_unbind(struct drm_gem_object *obj)
 853 {
 854         struct drm_device *dev = obj->dev;
 855         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 856         int ret = 0;
 857
 858 #if WATCH_BUF
 859         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
 860         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
 861 #endif
 862         if (obj_priv->gtt_space == NULL)
 863                 return 0;
 864
 865         if (obj_priv->pin_count != 0) {
 866                 DRM_ERROR("Attempting to unbind pinned buffer\n");
 867                 return -EINVAL;
 868         }
 869
 870         /* Wait for any rendering to complete
 871          */
 872         ret = i915_gem_object_wait_rendering(obj);
 873         if (ret) {
 874                 DRM_ERROR ("wait_rendering failed: %d\n", ret);
 875                 return ret;
 876         }
 877
 878         /* Move the object to the CPU domain to ensure that
 879          * any possible CPU writes while it's not in the GTT
 880          * are flushed when we go to remap it. This will
 881          * also ensure that all pending GPU writes are finished
 882          * before we unbind.
 883          */
 884         ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU,
 885                                          I915_GEM_DOMAIN_CPU);
 886         if (ret) {
 887                 DRM_ERROR("set_domain failed: %d\n", ret);
 888                 return ret;
 889         }
 890
 891         if (obj_priv->agp_mem != NULL) {
 892                 drm_unbind_agp(obj_priv->agp_mem);
 893                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
 894                 obj_priv->agp_mem = NULL;
 895         }
 896
 897         BUG_ON(obj_priv->active);
 898
 899         i915_gem_object_free_page_list(obj);
 900
 901         if (obj_priv->gtt_space) {
 902                 atomic_dec(&dev->gtt_count);
 903                 atomic_sub(obj->size, &dev->gtt_memory);
 904
 905                 drm_memrange_put_block(obj_priv->gtt_space);
 906                 obj_priv->gtt_space = NULL;
 907         }
 908
 909         /* Remove ourselves from the LRU list if present. */
 910         if (!list_empty(&obj_priv->list))
 911                 list_del_init(&obj_priv->list);
 912
 913         return 0;
 914 }
 915
 916 #if WATCH_BUF | WATCH_EXEC | WATCH_PWRITE
 917 static void
 918 i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end,
 919                    uint32_t bias, uint32_t mark)
 920 {
 921         uint32_t *mem = kmap_atomic(page, KM_USER0);
 922         int i;
 923         for (i = start; i < end; i += 4)
 924                 DRM_INFO("%08x: %08x%s\n",
 925                           (int) (bias + i), mem[i / 4],
 926                           (bias + i == mark) ? " ********" : "");
 927         kunmap_atomic(mem, KM_USER0);
 928         /* give syslog time to catch up */
 929         msleep(1);
 930 }
 931
 932 static void
 933 i915_gem_dump_object(struct drm_gem_object *obj, int len,
 934                      const char *where, uint32_t mark)
 935 {
 936         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 937         int page;
 938
 939         DRM_INFO("%s: object at offset %08x\n", where, obj_priv->gtt_offset);
 940         for (page = 0; page < (len + PAGE_SIZE-1) / PAGE_SIZE; page++) {
 941                 int page_len, chunk, chunk_len;
 942
 943                 page_len = len - page * PAGE_SIZE;
 944                 if (page_len > PAGE_SIZE)
 945                         page_len = PAGE_SIZE;
 946
 947                 for (chunk = 0; chunk < page_len; chunk += 128) {
 948                         chunk_len = page_len - chunk;
 949                         if (chunk_len > 128)
 950                                 chunk_len = 128;
 951                         i915_gem_dump_page(obj_priv->page_list[page],
 952                                            chunk, chunk + chunk_len,
 953                                            obj_priv->gtt_offset +
 954                                            page * PAGE_SIZE,
 955                                            mark);
 956                 }
 957         }
 958 }
 959 #endif
 960
 961 #if WATCH_LRU
 962 static void
 963 i915_dump_lru(struct drm_device *dev, const char *where)
 964 {
 965         struct drm_i915_private         *dev_priv = dev->dev_private;
 966         struct drm_i915_gem_object      *obj_priv;
 967
 968         DRM_INFO("active list %s {\n", where);
 969         list_for_each_entry(obj_priv, &dev_priv->mm.active_list,
 970                             list)
 971         {
 972                 DRM_INFO("    %p: %08x\n", obj_priv,
 973                          obj_priv->last_rendering_seqno);
 974         }
 975         DRM_INFO("}\n");
 976         DRM_INFO("flushing list %s {\n", where);
 977         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list,
 978                             list)
 979         {
 980                 DRM_INFO("    %p: %08x\n", obj_priv,
 981                          obj_priv->last_rendering_seqno);
 982         }
 983         DRM_INFO("}\n");
 984         DRM_INFO("inactive %s {\n", where);
 985         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 986                 DRM_INFO("    %p: %08x\n", obj_priv,
 987                          obj_priv->last_rendering_seqno);
 988         }
 989         DRM_INFO("}\n");
 990 }
 991 #endif
 992
 993 static int
 994 i915_gem_evict_something(struct drm_device *dev)
 995 {
 996         struct drm_i915_private *dev_priv = dev->dev_private;
 997         struct drm_gem_object *obj;
 998         struct drm_i915_gem_object *obj_priv;
 999         int ret = 0;
1000
1001         for (;;) {
1002                 /* If there's an inactive buffer available now, grab it
1003                  * and be done.
1004                  */
1005                 if (!list_empty(&dev_priv->mm.inactive_list)) {
1006                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1007                                                     struct drm_i915_gem_object,
1008                                                     list);
1009                         obj = obj_priv->obj;
1010                         BUG_ON(obj_priv->pin_count != 0);
1011 #if WATCH_LRU
1012                         DRM_INFO("%s: evicting %p\n", __func__, obj);
1013 #endif
1014                         BUG_ON(obj_priv->active);
1015
1016                         /* Wait on the rendering and unbind the buffer. */
1017                         ret = i915_gem_object_unbind(obj);
1018                         break;
1019                 }
1020
1021                 /* If we didn't get anything, but the ring is still processing
1022                  * things, wait for one of those things to finish and hopefully
1023                  * leave us a buffer to evict.
1024                  */
1025                 if (!list_empty(&dev_priv->mm.request_list)) {
1026                         struct drm_i915_gem_request *request;
1027
1028                         request = list_first_entry(&dev_priv->mm.request_list,
1029                                                    struct drm_i915_gem_request,
1030                                                    list);
1031
1032                         ret = i915_wait_request(dev, request->seqno);
1033                         if (ret)
1034                                 break;
1035
1036                         /* if waiting caused an object to become inactive,
1037                          * then loop around and wait for it. Otherwise, we
1038                          * assume that waiting freed and unbound something,
1039                          * so there should now be some space in the GTT
1040                          */
1041                         if (!list_empty(&dev_priv->mm.inactive_list))
1042                                 continue;
1043                         break;
1044                 }
1045
1046                 /* If we didn't have anything on the request list but there
1047                  * are buffers awaiting a flush, emit one and try again.
1048                  * When we wait on it, those buffers waiting for that flush
1049                  * will get moved to inactive.
1050                  */
1051                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1052                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1053                                                     struct drm_i915_gem_object,
1054                                                     list);
1055                         obj = obj_priv->obj;
1056
1057                         i915_gem_flush(dev,
1058                                        obj->write_domain,
1059                                        obj->write_domain);
1060                         i915_add_request(dev, obj->write_domain);
1061
1062                         obj = NULL;
1063                         continue;
1064                 }
1065
1066                 DRM_ERROR("inactive empty %d request empty %d flushing empty %d\n",
1067                           list_empty(&dev_priv->mm.inactive_list),
1068                           list_empty(&dev_priv->mm.request_list),
1069                           list_empty(&dev_priv->mm.flushing_list));
1070                 /* If we didn't do any of the above, there's nothing to be done
1071                  * and we just can't fit it in.
1072                  */
1073                 return -ENOMEM;
1074         }
1075         return ret;
1076 }
1077
1078 static int
1079 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1080 {
1081         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1082         int page_count, i;
1083         struct address_space *mapping;
1084         struct inode *inode;
1085         struct page *page;
1086         int ret;
1087
1088         if (obj_priv->page_list)
1089                 return 0;
1090
1091         /* Get the list of pages out of our struct file.  They'll be pinned
1092          * at this point until we release them.
1093          */
1094         page_count = obj->size / PAGE_SIZE;
1095         BUG_ON(obj_priv->page_list != NULL);
1096         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1097                                          DRM_MEM_DRIVER);
1098         if (obj_priv->page_list == NULL) {
1099                 DRM_ERROR("Faled to allocate page list\n");
1100                 return -ENOMEM;
1101         }
1102
1103         inode = obj->filp->f_path.dentry->d_inode;
1104         mapping = inode->i_mapping;
1105         for (i = 0; i < page_count; i++) {
1106                 page = find_get_page(mapping, i);
1107                 if (page == NULL || !PageUptodate(page)) {
1108                         if (page) {
1109                                 page_cache_release(page);
1110                                 page = NULL;
1111                         }
1112                         ret = shmem_getpage(inode, i, &page, SGP_DIRTY, NULL);
1113
1114                         if (ret) {
1115                                 DRM_ERROR("shmem_getpage failed: %d\n", ret);
1116                                 i915_gem_object_free_page_list(obj);
1117                                 return ret;
1118                         }
1119                         unlock_page(page);
1120                 }
1121                 obj_priv->page_list[i] = page;
1122         }
1123         return 0;
1124 }
1125
1126 /**
1127  * Finds free space in the GTT aperture and binds the object there.
1128  */
1129 static int
1130 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1131 {
1132         struct drm_device *dev = obj->dev;
1133         struct drm_i915_private *dev_priv = dev->dev_private;
1134         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1135         struct drm_memrange_node *free_space;
1136         int page_count, ret;
1137
1138         if (alignment == 0)
1139                 alignment = PAGE_SIZE;
1140         if (alignment & (PAGE_SIZE - 1)) {
1141                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1142                 return -EINVAL;
1143         }
1144
1145  search_free:
1146         free_space = drm_memrange_search_free(&dev_priv->mm.gtt_space,
1147                                               obj->size,
1148                                               alignment, 0);
1149         if (free_space != NULL) {
1150                 obj_priv->gtt_space =
1151                         drm_memrange_get_block(free_space, obj->size,
1152                                                alignment);
1153                 if (obj_priv->gtt_space != NULL) {
1154                         obj_priv->gtt_space->private = obj;
1155                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1156                 }
1157         }
1158         if (obj_priv->gtt_space == NULL) {
1159                 /* If the gtt is empty and we're still having trouble
1160                  * fitting our object in, we're out of memory.
1161                  */
1162 #if WATCH_LRU
1163                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1164 #endif
1165                 if (list_empty(&dev_priv->mm.inactive_list) &&
1166                     list_empty(&dev_priv->mm.flushing_list) &&
1167                     list_empty(&dev_priv->mm.active_list)) {
1168                         DRM_ERROR("GTT full, but LRU list empty\n");
1169                         return -ENOMEM;
1170                 }
1171
1172                 ret = i915_gem_evict_something(dev);
1173                 if (ret != 0) {
1174                         DRM_ERROR("Failed to evict a buffer %d\n", ret);
1175                         return ret;
1176                 }
1177                 goto search_free;
1178         }
1179
1180 #if WATCH_BUF
1181         DRM_INFO("Binding object of size %d at 0x%08x\n",
1182                  obj->size, obj_priv->gtt_offset);
1183 #endif
1184         ret = i915_gem_object_get_page_list(obj);
1185         if (ret) {
1186                 drm_memrange_put_block(obj_priv->gtt_space);
1187                 obj_priv->gtt_space = NULL;
1188                 return ret;
1189         }
1190
1191         page_count = obj->size / PAGE_SIZE;
1192         /* Create an AGP memory structure pointing at our pages, and bind it
1193          * into the GTT.
1194          */
1195         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1196                                                obj_priv->page_list,
1197                                                page_count,
1198                                                obj_priv->gtt_offset);
1199         if (obj_priv->agp_mem == NULL) {
1200                 i915_gem_object_free_page_list(obj);
1201                 drm_memrange_put_block(obj_priv->gtt_space);
1202                 obj_priv->gtt_space = NULL;
1203                 return -ENOMEM;
1204         }
1205         atomic_inc(&dev->gtt_count);
1206         atomic_add(obj->size, &dev->gtt_memory);
1207
1208         /* Assert that the object is not currently in any GPU domain. As it
1209          * wasn't in the GTT, there shouldn't be any way it could have been in
1210          * a GPU cache
1211          */
1212         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1213         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1214
1215         return 0;
1216 }
1217
1218 static void
1219 i915_gem_clflush_object(struct drm_gem_object *obj)
1220 {
1221         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1222
1223         /* If we don't have a page list set up, then we're not pinned
1224          * to GPU, and we can ignore the cache flush because it'll happen
1225          * again at bind time.
1226          */
1227         if (obj_priv->page_list == NULL)
1228                 return;
1229
1230         drm_ttm_cache_flush(obj_priv->page_list, obj->size / PAGE_SIZE);
1231 }
1232
1233 /*
1234  * Set the next domain for the specified object. This
1235  * may not actually perform the necessary flushing/invaliding though,
1236  * as that may want to be batched with other set_domain operations
1237  *
1238  * This is (we hope) the only really tricky part of gem. The goal
1239  * is fairly simple -- track which caches hold bits of the object
1240  * and make sure they remain coherent. A few concrete examples may
1241  * help to explain how it works. For shorthand, we use the notation
1242  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1243  * a pair of read and write domain masks.
1244  *
1245  * Case 1: the batch buffer
1246  *
1247  *      1. Allocated
1248  *      2. Written by CPU
1249  *      3. Mapped to GTT
1250  *      4. Read by GPU
1251  *      5. Unmapped from GTT
1252  *      6. Freed
1253  *
1254  *      Let's take these a step at a time
1255  *
1256  *      1. Allocated
1257  *              Pages allocated from the kernel may still have
1258  *              cache contents, so we set them to (CPU, CPU) always.
1259  *      2. Written by CPU (using pwrite)
1260  *              The pwrite function calls set_domain (CPU, CPU) and
1261  *              this function does nothing (as nothing changes)
1262  *      3. Mapped by GTT
1263  *              This function asserts that the object is not
1264  *              currently in any GPU-based read or write domains
1265  *      4. Read by GPU
1266  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1267  *              As write_domain is zero, this function adds in the
1268  *              current read domains (CPU+COMMAND, 0).
1269  *              flush_domains is set to CPU.
1270  *              invalidate_domains is set to COMMAND
1271  *              clflush is run to get data out of the CPU caches
1272  *              then i915_dev_set_domain calls i915_gem_flush to
1273  *              emit an MI_FLUSH and drm_agp_chipset_flush
1274  *      5. Unmapped from GTT
1275  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1276  *              flush_domains and invalidate_domains end up both zero
1277  *              so no flushing/invalidating happens
1278  *      6. Freed
1279  *              yay, done
1280  *
1281  * Case 2: The shared render buffer
1282  *
1283  *      1. Allocated
1284  *      2. Mapped to GTT
1285  *      3. Read/written by GPU
1286  *      4. set_domain to (CPU,CPU)
1287  *      5. Read/written by CPU
1288  *      6. Read/written by GPU
1289  *
1290  *      1. Allocated
1291  *              Same as last example, (CPU, CPU)
1292  *      2. Mapped to GTT
1293  *              Nothing changes (assertions find that it is not in the GPU)
1294  *      3. Read/written by GPU
1295  *              execbuffer calls set_domain (RENDER, RENDER)
1296  *              flush_domains gets CPU
1297  *              invalidate_domains gets GPU
1298  *              clflush (obj)
1299  *              MI_FLUSH and drm_agp_chipset_flush
1300  *      4. set_domain (CPU, CPU)
1301  *              flush_domains gets GPU
1302  *              invalidate_domains gets CPU
1303  *              wait_rendering (obj) to make sure all drawing is complete.
1304  *              This will include an MI_FLUSH to get the data from GPU
1305  *              to memory
1306  *              clflush (obj) to invalidate the CPU cache
1307  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1308  *      5. Read/written by CPU
1309  *              cache lines are loaded and dirtied
1310  *      6. Read written by GPU
1311  *              Same as last GPU access
1312  *
1313  * Case 3: The constant buffer
1314  *
1315  *      1. Allocated
1316  *      2. Written by CPU
1317  *      3. Read by GPU
1318  *      4. Updated (written) by CPU again
1319  *      5. Read by GPU
1320  *
1321  *      1. Allocated
1322  *              (CPU, CPU)
1323  *      2. Written by CPU
1324  *              (CPU, CPU)
1325  *      3. Read by GPU
1326  *              (CPU+RENDER, 0)
1327  *              flush_domains = CPU
1328  *              invalidate_domains = RENDER
1329  *              clflush (obj)
1330  *              MI_FLUSH
1331  *              drm_agp_chipset_flush
1332  *      4. Updated (written) by CPU again
1333  *              (CPU, CPU)
1334  *              flush_domains = 0 (no previous write domain)
1335  *              invalidate_domains = 0 (no new read domains)
1336  *      5. Read by GPU
1337  *              (CPU+RENDER, 0)
1338  *              flush_domains = CPU
1339  *              invalidate_domains = RENDER
1340  *              clflush (obj)
1341  *              MI_FLUSH
1342  *              drm_agp_chipset_flush
1343  */
1344 static int
1345 i915_gem_object_set_domain(struct drm_gem_object *obj,
1346                             uint32_t read_domains,
1347                             uint32_t write_domain)
1348 {
1349         struct drm_device               *dev = obj->dev;
1350         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1351         uint32_t                        invalidate_domains = 0;
1352         uint32_t                        flush_domains = 0;
1353         int                             ret;
1354
1355 #if WATCH_BUF
1356         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1357                  __func__, obj,
1358                  obj->read_domains, read_domains,
1359                  obj->write_domain, write_domain);
1360 #endif
1361         /*
1362          * If the object isn't moving to a new write domain,
1363          * let the object stay in multiple read domains
1364          */
1365         if (write_domain == 0)
1366                 read_domains |= obj->read_domains;
1367         else
1368                 obj_priv->dirty = 1;
1369
1370         /*
1371          * Flush the current write domain if
1372          * the new read domains don't match. Invalidate
1373          * any read domains which differ from the old
1374          * write domain
1375          */
1376         if (obj->write_domain && obj->write_domain != read_domains) {
1377                 flush_domains |= obj->write_domain;
1378                 invalidate_domains |= read_domains & ~obj->write_domain;
1379         }
1380         /*
1381          * Invalidate any read caches which may have
1382          * stale data. That is, any new read domains.
1383          */
1384         invalidate_domains |= read_domains & ~obj->read_domains;
1385         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
1386 #if WATCH_BUF
1387                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1388                          __func__, flush_domains, invalidate_domains);
1389 #endif
1390                 /*
1391                  * If we're invaliding the CPU cache and flushing a GPU cache,
1392                  * then pause for rendering so that the GPU caches will be
1393                  * flushed before the cpu cache is invalidated
1394                  */
1395                 if ((invalidate_domains & I915_GEM_DOMAIN_CPU) &&
1396                     (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))) {
1397                         ret = i915_gem_object_wait_rendering(obj);
1398                         if (ret)
1399                                 return ret;
1400                 }
1401                 i915_gem_clflush_object(obj);
1402         }
1403
1404         if ((write_domain | flush_domains) != 0)
1405                 obj->write_domain = write_domain;
1406         obj->read_domains = read_domains;
1407         dev->invalidate_domains |= invalidate_domains;
1408         dev->flush_domains |= flush_domains;
1409 #if WATCH_BUF
1410         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1411                  __func__,
1412                  obj->read_domains, obj->write_domain,
1413                  dev->invalidate_domains, dev->flush_domains);
1414 #endif
1415         return 0;
1416 }
1417
1418 /**
1419  * Once all of the objects have been set in the proper domain,
1420  * perform the necessary flush and invalidate operations.
1421  *
1422  * Returns the write domains flushed, for use in flush tracking.
1423  */
1424 static uint32_t
1425 i915_gem_dev_set_domain(struct drm_device *dev)
1426 {
1427         uint32_t flush_domains = dev->flush_domains;
1428
1429         /*
1430          * Now that all the buffers are synced to the proper domains,
1431          * flush and invalidate the collected domains
1432          */
1433         if (dev->invalidate_domains | dev->flush_domains) {
1434 #if WATCH_EXEC
1435                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
1436                           __func__,
1437                          dev->invalidate_domains,
1438                          dev->flush_domains);
1439 #endif
1440                 i915_gem_flush(dev,
1441                                dev->invalidate_domains,
1442                                dev->flush_domains);
1443                 dev->invalidate_domains = 0;
1444                 dev->flush_domains = 0;
1445         }
1446
1447         return flush_domains;
1448 }
1449
1450 #if WATCH_COHERENCY
1451 static void
1452 i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle)
1453 {
1454         struct drm_device *dev = obj->dev;
1455         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1456         int page;
1457         uint32_t *gtt_mapping;
1458         uint32_t *backing_map = NULL;
1459         int bad_count = 0;
1460
1461         DRM_INFO("%s: checking coherency of object %p@0x%08x (%d, %dkb):\n",
1462                  __func__, obj, obj_priv->gtt_offset, handle,
1463                  obj->size / 1024);
1464
1465         gtt_mapping = ioremap(dev->agp->base + obj_priv->gtt_offset,
1466                               obj->size);
1467         if (gtt_mapping == NULL) {
1468                 DRM_ERROR("failed to map GTT space\n");
1469                 return;
1470         }
1471
1472         for (page = 0; page < obj->size / PAGE_SIZE; page++) {
1473                 int i;
1474
1475                 backing_map = kmap_atomic(obj_priv->page_list[page], KM_USER0);
1476
1477                 if (backing_map == NULL) {
1478                         DRM_ERROR("failed to map backing page\n");
1479                         goto out;
1480                 }
1481
1482                 for (i = 0; i < PAGE_SIZE / 4; i++) {
1483                         uint32_t cpuval = backing_map[i];
1484                         uint32_t gttval = readl(gtt_mapping +
1485                                                 page * 1024 + i);
1486
1487                         if (cpuval != gttval) {
1488                                 DRM_INFO("incoherent CPU vs GPU at 0x%08x: "
1489                                          "0x%08x vs 0x%08x\n",
1490                                          (int)(obj_priv->gtt_offset +
1491                                                page * PAGE_SIZE + i * 4),
1492                                          cpuval, gttval);
1493                                 if (bad_count++ >= 8) {
1494                                         DRM_INFO("...\n");
1495                                         goto out;
1496                                 }
1497                         }
1498                 }
1499                 kunmap_atomic(backing_map, KM_USER0);
1500                 backing_map = NULL;
1501         }
1502
1503  out:
1504         if (backing_map != NULL)
1505                 kunmap_atomic(backing_map, KM_USER0);
1506         iounmap(gtt_mapping);
1507
1508         /* give syslog time to catch up */
1509         msleep(1);
1510
1511         /* Directly flush the object, since we just loaded values with the CPU
1512          * from thebacking pages and we don't want to disturb the cache
1513          * management that we're trying to observe.
1514          */
1515
1516         i915_gem_clflush_object(obj);
1517 }
1518 #endif
1519
1520 /**
1521  * Pin an object to the GTT and evaluate the relocations landing in it.
1522  */
1523 static int
1524 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1525                                  struct drm_file *file_priv,
1526                                  struct drm_i915_gem_exec_object *entry)
1527 {
1528         struct drm_device *dev = obj->dev;
1529         struct drm_i915_gem_relocation_entry reloc;
1530         struct drm_i915_gem_relocation_entry __user *relocs;
1531         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1532         int i, ret;
1533         uint32_t last_reloc_offset = -1;
1534         void *reloc_page = NULL;
1535
1536         /* Choose the GTT offset for our buffer and put it there. */
1537         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
1538         if (ret)
1539                 return ret;
1540
1541         entry->offset = obj_priv->gtt_offset;
1542
1543         relocs = (struct drm_i915_gem_relocation_entry __user *)
1544                  (uintptr_t) entry->relocs_ptr;
1545         /* Apply the relocations, using the GTT aperture to avoid cache
1546          * flushing requirements.
1547          */
1548         for (i = 0; i < entry->relocation_count; i++) {
1549                 struct drm_gem_object *target_obj;
1550                 struct drm_i915_gem_object *target_obj_priv;
1551                 uint32_t reloc_val, reloc_offset, *reloc_entry;
1552                 int ret;
1553
1554                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
1555                 if (ret != 0) {
1556                         i915_gem_object_unpin(obj);
1557                         return ret;
1558                 }
1559
1560                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
1561                                                    reloc.target_handle);
1562                 if (target_obj == NULL) {
1563                         i915_gem_object_unpin(obj);
1564                         return -EINVAL;
1565                 }
1566                 target_obj_priv = target_obj->driver_private;
1567
1568                 /* The target buffer should have appeared before us in the
1569                  * exec_object list, so it should have a GTT space bound by now.
1570                  */
1571                 if (target_obj_priv->gtt_space == NULL) {
1572                         DRM_ERROR("No GTT space found for object %d\n",
1573                                   reloc.target_handle);
1574                         drm_gem_object_unreference(target_obj);
1575                         i915_gem_object_unpin(obj);
1576                         return -EINVAL;
1577                 }
1578
1579                 if (reloc.offset > obj->size - 4) {
1580                         DRM_ERROR("Relocation beyond object bounds: "
1581                                   "obj %p target %d offset %d size %d.\n",
1582                                   obj, reloc.target_handle,
1583                                   (int) reloc.offset, (int) obj->size);
1584                         drm_gem_object_unreference(target_obj);
1585                         i915_gem_object_unpin(obj);
1586                         return -EINVAL;
1587                 }
1588                 if (reloc.offset & 3) {
1589                         DRM_ERROR("Relocation not 4-byte aligned: "
1590                                   "obj %p target %d offset %d.\n",
1591                                   obj, reloc.target_handle,
1592                                   (int) reloc.offset);
1593                         drm_gem_object_unreference(target_obj);
1594                         i915_gem_object_unpin(obj);
1595                         return -EINVAL;
1596                 }
1597
1598                 if (reloc.write_domain && target_obj->pending_write_domain &&
1599                     reloc.write_domain != target_obj->pending_write_domain) {
1600                         DRM_ERROR("Write domain conflict: "
1601                                   "obj %p target %d offset %d "
1602                                   "new %08x old %08x\n",
1603                                   obj, reloc.target_handle,
1604                                   (int) reloc.offset,
1605                                   reloc.write_domain,
1606                                   target_obj->pending_write_domain);
1607                         drm_gem_object_unreference(target_obj);
1608                         i915_gem_object_unpin(obj);
1609                         return -EINVAL;
1610                 }
1611
1612 #if WATCH_RELOC
1613                 DRM_INFO("%s: obj %p offset %08x target %d "
1614                          "read %08x write %08x gtt %08x "
1615                          "presumed %08x delta %08x\n",
1616                          __func__,
1617                          obj,
1618                          (int) reloc.offset,
1619                          (int) reloc.target_handle,
1620                          (int) reloc.read_domains,
1621                          (int) reloc.write_domain,
1622                          (int) target_obj_priv->gtt_offset,
1623                          (int) reloc.presumed_offset,
1624                          reloc.delta);
1625 #endif
1626
1627                 target_obj->pending_read_domains |= reloc.read_domains;
1628                 target_obj->pending_write_domain |= reloc.write_domain;
1629
1630                 /* If the relocation already has the right value in it, no
1631                  * more work needs to be done.
1632                  */
1633                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
1634                         drm_gem_object_unreference(target_obj);
1635                         continue;
1636                 }
1637
1638                 /* Now that we're going to actually write some data in,
1639                  * make sure that any rendering using this buffer's contents
1640                  * is completed.
1641                  */
1642                 i915_gem_object_wait_rendering(obj);
1643
1644                 /* As we're writing through the gtt, flush
1645                  * any CPU writes before we write the relocations
1646                  */
1647                 if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
1648                         i915_gem_clflush_object(obj);
1649                         drm_agp_chipset_flush(dev);
1650                         obj->write_domain = 0;
1651                 }
1652
1653                 /* Map the page containing the relocation we're going to
1654                  * perform.
1655                  */
1656                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1657                 if (reloc_page == NULL ||
1658                     (last_reloc_offset & ~(PAGE_SIZE - 1)) !=
1659                     (reloc_offset & ~(PAGE_SIZE - 1))) {
1660                         if (reloc_page != NULL)
1661                                 iounmap(reloc_page);
1662
1663                         reloc_page = ioremap(dev->agp->base +
1664                                              (reloc_offset & ~(PAGE_SIZE - 1)),
1665                                              PAGE_SIZE);
1666                         last_reloc_offset = reloc_offset;
1667                         if (reloc_page == NULL) {
1668                                 drm_gem_object_unreference(target_obj);
1669                                 i915_gem_object_unpin(obj);
1670                                 return -ENOMEM;
1671                         }
1672                 }
1673
1674                 reloc_entry = (uint32_t *)((char *)reloc_page +
1675                                            (reloc_offset & (PAGE_SIZE - 1)));
1676                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1677
1678 #if WATCH_BUF
1679                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1680                           obj, (unsigned int) reloc.offset,
1681                           readl(reloc_entry), reloc_val);
1682 #endif
1683                 writel(reloc_val, reloc_entry);
1684
1685                 /* Write the updated presumed offset for this entry back out
1686                  * to the user.
1687                  */
1688                 reloc.presumed_offset = target_obj_priv->gtt_offset;
1689                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
1690                 if (ret != 0) {
1691                         drm_gem_object_unreference(target_obj);
1692                         i915_gem_object_unpin(obj);
1693                         return ret;
1694                 }
1695
1696                 drm_gem_object_unreference(target_obj);
1697         }
1698
1699         if (reloc_page != NULL)
1700                 iounmap(reloc_page);
1701
1702 #if WATCH_BUF
1703         if (0)
1704                 i915_gem_dump_object(obj, 128, __func__, ~0);
1705 #endif
1706         return 0;
1707 }
1708
1709 /** Dispatch a batchbuffer to the ring
1710  */
1711 static int
1712 i915_dispatch_gem_execbuffer(struct drm_device *dev,
1713                               struct drm_i915_gem_execbuffer *exec,
1714                               uint64_t exec_offset)
1715 {
1716         struct drm_i915_private *dev_priv = dev->dev_private;
1717         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
1718                                              (uintptr_t) exec->cliprects_ptr;
1719         int nbox = exec->num_cliprects;
1720         int i = 0, count;
1721         uint32_t        exec_start, exec_len;
1722         RING_LOCALS;
1723
1724         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
1725         exec_len = (uint32_t) exec->batch_len;
1726
1727         if ((exec_start | exec_len) & 0x7) {
1728                 DRM_ERROR("alignment\n");
1729                 return -EINVAL;
1730         }
1731
1732         if (!exec_start)
1733                 return -EINVAL;
1734
1735         count = nbox ? nbox : 1;
1736
1737         for (i = 0; i < count; i++) {
1738                 if (i < nbox) {
1739                         int ret = i915_emit_box(dev, boxes, i,
1740                                                 exec->DR1, exec->DR4);
1741                         if (ret)
1742                                 return ret;
1743                 }
1744
1745                 if (IS_I830(dev) || IS_845G(dev)) {
1746                         BEGIN_LP_RING(4);
1747                         OUT_RING(MI_BATCH_BUFFER);
1748                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1749                         OUT_RING(exec_start + exec_len - 4);
1750                         OUT_RING(0);
1751                         ADVANCE_LP_RING();
1752                 } else {
1753                         BEGIN_LP_RING(2);
1754                         if (IS_I965G(dev)) {
1755                                 OUT_RING(MI_BATCH_BUFFER_START |
1756                                          (2 << 6) |
1757                                          MI_BATCH_NON_SECURE_I965);
1758                                 OUT_RING(exec_start);
1759                         } else {
1760                                 OUT_RING(MI_BATCH_BUFFER_START |
1761                                          (2 << 6));
1762                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1763                         }
1764                         ADVANCE_LP_RING();
1765                 }
1766         }
1767
1768         /* XXX breadcrumb */
1769         return 0;
1770 }
1771
1772 /* Throttle our rendering by waiting until the ring has completed our requests
1773  * emitted over 20 msec ago.
1774  *
1775  * This should get us reasonable parallelism between CPU and GPU but also
1776  * relatively low latency when blocking on a particular request to finish.
1777  */
1778 static int
1779 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
1780 {
1781         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1782         int ret = 0;
1783         uint32_t seqno;
1784
1785         mutex_lock(&dev->struct_mutex);
1786         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
1787         i915_file_priv->mm.last_gem_throttle_seqno = i915_file_priv->mm.last_gem_seqno;
1788         if (seqno)
1789                 ret = i915_wait_request(dev, seqno);
1790         mutex_unlock(&dev->struct_mutex);
1791         return ret;
1792 }
1793
1794 int
1795 i915_gem_execbuffer(struct drm_device *dev, void *data,
1796                     struct drm_file *file_priv)
1797 {
1798         struct drm_i915_private *dev_priv = dev->dev_private;
1799         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1800         struct drm_i915_gem_execbuffer *args = data;
1801         struct drm_i915_gem_exec_object *exec_list = NULL;
1802         struct drm_gem_object **object_list = NULL;
1803         struct drm_gem_object *batch_obj;
1804         int ret, i, pinned = 0;
1805         uint64_t exec_offset;
1806         uint32_t seqno, flush_domains;
1807
1808 #if WATCH_EXEC
1809         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1810                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1811 #endif
1812
1813         /* Copy in the exec list from userland */
1814         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
1815                                DRM_MEM_DRIVER);
1816         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
1817                                  DRM_MEM_DRIVER);
1818         if (exec_list == NULL || object_list == NULL) {
1819                 DRM_ERROR("Failed to allocate exec or object list "
1820                           "for %d buffers\n",
1821                           args->buffer_count);
1822                 ret = -ENOMEM;
1823                 goto pre_mutex_err;
1824         }
1825         ret = copy_from_user(exec_list,
1826                              (struct drm_i915_relocation_entry __user *)
1827                              (uintptr_t) args->buffers_ptr,
1828                              sizeof(*exec_list) * args->buffer_count);
1829         if (ret != 0) {
1830                 DRM_ERROR("copy %d exec entries failed %d\n",
1831                           args->buffer_count, ret);
1832                 goto pre_mutex_err;
1833         }
1834
1835         mutex_lock(&dev->struct_mutex);
1836
1837         i915_verify_inactive(dev, __FILE__, __LINE__);
1838
1839         if (dev_priv->mm.wedged) {
1840                 DRM_ERROR("Execbuf while wedged\n");
1841                 mutex_unlock(&dev->struct_mutex);
1842                 return -EIO;
1843         }
1844
1845         if (dev_priv->mm.suspended) {
1846                 DRM_ERROR("Execbuf while VT-switched.\n");
1847                 mutex_unlock(&dev->struct_mutex);
1848                 return -EBUSY;
1849         }
1850
1851         /* Zero the gloabl flush/invalidate flags. These
1852          * will be modified as each object is bound to the
1853          * gtt
1854          */
1855         dev->invalidate_domains = 0;
1856         dev->flush_domains = 0;
1857
1858         /* Look up object handles and perform the relocations */
1859         for (i = 0; i < args->buffer_count; i++) {
1860                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
1861                                                        exec_list[i].handle);
1862                 if (object_list[i] == NULL) {
1863                         DRM_ERROR("Invalid object handle %d at index %d\n",
1864                                    exec_list[i].handle, i);
1865                         ret = -EINVAL;
1866                         goto err;
1867                 }
1868
1869                 object_list[i]->pending_read_domains = 0;
1870                 object_list[i]->pending_write_domain = 0;
1871                 ret = i915_gem_object_pin_and_relocate(object_list[i],
1872                                                        file_priv,
1873                                                        &exec_list[i]);
1874                 if (ret) {
1875                         DRM_ERROR("object bind and relocate failed %d\n", ret);
1876                         goto err;
1877                 }
1878                 pinned = i + 1;
1879         }
1880
1881         /* Set the pending read domains for the batch buffer to COMMAND */
1882         batch_obj = object_list[args->buffer_count-1];
1883         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1884         batch_obj->pending_write_domain = 0;
1885
1886         i915_verify_inactive(dev, __FILE__, __LINE__);
1887
1888         for (i = 0; i < args->buffer_count; i++) {
1889                 struct drm_gem_object *obj = object_list[i];
1890                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1891
1892                 if (obj_priv->gtt_space == NULL) {
1893                         /* We evicted the buffer in the process of validating
1894                          * our set of buffers in.  We could try to recover by
1895                          * kicking them everything out and trying again from
1896                          * the start.
1897                          */
1898                         ret = -ENOMEM;
1899                         goto err;
1900                 }
1901
1902                 /* make sure all previous memory operations have passed */
1903                 ret = i915_gem_object_set_domain(obj,
1904                                                  obj->pending_read_domains,
1905                                                  obj->pending_write_domain);
1906                 if (ret)
1907                         goto err;
1908         }
1909
1910         i915_verify_inactive(dev, __FILE__, __LINE__);
1911
1912         /* Flush/invalidate caches and chipset buffer */
1913         flush_domains = i915_gem_dev_set_domain(dev);
1914
1915         i915_verify_inactive(dev, __FILE__, __LINE__);
1916
1917 #if WATCH_COHERENCY
1918         for (i = 0; i < args->buffer_count; i++) {
1919                 i915_gem_object_check_coherency(object_list[i],
1920                                                 exec_list[i].handle);
1921         }
1922 #endif
1923
1924         exec_offset = exec_list[args->buffer_count - 1].offset;
1925
1926 #if WATCH_EXEC
1927         i915_gem_dump_object(object_list[args->buffer_count - 1],
1928                               args->batch_len,
1929                               __func__,
1930                               ~0);
1931 #endif
1932
1933         /* Exec the batchbuffer */
1934         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
1935         if (ret) {
1936                 DRM_ERROR("dispatch failed %d\n", ret);
1937                 goto err;
1938         }
1939
1940         /*
1941          * Ensure that the commands in the batch buffer are
1942          * finished before the interrupt fires
1943          */
1944         flush_domains |= i915_retire_commands(dev);
1945
1946         i915_verify_inactive(dev, __FILE__, __LINE__);
1947
1948         /*
1949          * Get a seqno representing the execution of the current buffer,
1950          * which we can wait on.  We would like to mitigate these interrupts,
1951          * likely by only creating seqnos occasionally (so that we have
1952          * *some* interrupts representing completion of buffers that we can
1953          * wait on when trying to clear up gtt space).
1954          */
1955         seqno = i915_add_request(dev, flush_domains);
1956         BUG_ON(seqno == 0);
1957         i915_file_priv->mm.last_gem_seqno = seqno;
1958         for (i = 0; i < args->buffer_count; i++) {
1959                 struct drm_gem_object *obj = object_list[i];
1960                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1961
1962                 i915_gem_object_move_to_active(obj);
1963                 obj_priv->last_rendering_seqno = seqno;
1964 #if WATCH_LRU
1965                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
1966 #endif
1967         }
1968 #if WATCH_LRU
1969         i915_dump_lru(dev, __func__);
1970 #endif
1971
1972         i915_verify_inactive(dev, __FILE__, __LINE__);
1973
1974         /* Copy the new buffer offsets back to the user's exec list. */
1975         ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1976                            (uintptr_t) args->buffers_ptr,
1977                            exec_list,
1978                            sizeof(*exec_list) * args->buffer_count);
1979         if (ret)
1980                 DRM_ERROR("failed to copy %d exec entries "
1981                           "back to user (%d)\n",
1982                            args->buffer_count, ret);
1983 err:
1984         if (object_list != NULL) {
1985                 for (i = 0; i < pinned; i++)
1986                         i915_gem_object_unpin(object_list[i]);
1987
1988                 for (i = 0; i < args->buffer_count; i++)
1989                         drm_gem_object_unreference(object_list[i]);
1990         }
1991         mutex_unlock(&dev->struct_mutex);
1992
1993 pre_mutex_err:
1994         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
1995                  DRM_MEM_DRIVER);
1996         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
1997                  DRM_MEM_DRIVER);
1998
1999         return ret;
2000 }
2001
2002 int
2003 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2004 {
2005         struct drm_device *dev = obj->dev;
2006         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2007         int ret;
2008
2009         i915_verify_inactive(dev, __FILE__, __LINE__);
2010         if (obj_priv->gtt_space == NULL) {
2011                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2012                 if (ret != 0) {
2013                         DRM_ERROR("Failure to bind: %d", ret);
2014                         return ret;
2015                 }
2016         }
2017         obj_priv->pin_count++;
2018
2019         /* If the object is not active and not pending a flush,
2020          * remove it from the inactive list
2021          */
2022         if (obj_priv->pin_count == 1) {
2023                 atomic_inc(&dev->pin_count);
2024                 atomic_add(obj->size, &dev->pin_memory);
2025                 if (!obj_priv->active && (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) == 0 &&
2026                     !list_empty(&obj_priv->list))
2027                         list_del_init(&obj_priv->list);
2028         }
2029         i915_verify_inactive(dev, __FILE__, __LINE__);
2030
2031         return 0;
2032 }
2033
2034 void
2035 i915_gem_object_unpin(struct drm_gem_object *obj)
2036 {
2037         struct drm_device *dev = obj->dev;
2038         struct drm_i915_private *dev_priv = dev->dev_private;
2039         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2040
2041         i915_verify_inactive(dev, __FILE__, __LINE__);
2042         obj_priv->pin_count--;
2043         BUG_ON(obj_priv->pin_count < 0);
2044         BUG_ON(obj_priv->gtt_space == NULL);
2045
2046         /* If the object is no longer pinned, and is
2047          * neither active nor being flushed, then stick it on
2048          * the inactive list
2049          */
2050         if (obj_priv->pin_count == 0) {
2051                 if (!obj_priv->active && (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) == 0)
2052                         list_move_tail(&obj_priv->list,
2053                                        &dev_priv->mm.inactive_list);
2054                 atomic_dec(&dev->pin_count);
2055                 atomic_sub(obj->size, &dev->pin_memory);
2056         }
2057         i915_verify_inactive(dev, __FILE__, __LINE__);
2058 }
2059
2060 int
2061 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2062                    struct drm_file *file_priv)
2063 {
2064         struct drm_i915_gem_pin *args = data;
2065         struct drm_gem_object *obj;
2066         struct drm_i915_gem_object *obj_priv;
2067         int ret;
2068
2069         mutex_lock(&dev->struct_mutex);
2070
2071         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2072         if (obj == NULL) {
2073                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2074                           args->handle);
2075                 mutex_unlock(&dev->struct_mutex);
2076                 return -EINVAL;
2077         }
2078         obj_priv = obj->driver_private;
2079
2080         ret = i915_gem_object_pin(obj, args->alignment);
2081         if (ret != 0) {
2082                 drm_gem_object_unreference(obj);
2083                 mutex_unlock(&dev->struct_mutex);
2084                 return ret;
2085         }
2086
2087         /** XXX - flush the CPU caches for pinned objects
2088          * as the X server doesn't manage domains yet
2089          */
2090         if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
2091                 i915_gem_clflush_object(obj);
2092                 drm_agp_chipset_flush(dev);
2093                 obj->write_domain = 0;
2094         }
2095         args->offset = obj_priv->gtt_offset;
2096         drm_gem_object_unreference(obj);
2097         mutex_unlock(&dev->struct_mutex);
2098
2099         return 0;
2100 }
2101
2102 int
2103 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2104                      struct drm_file *file_priv)
2105 {
2106         struct drm_i915_gem_pin *args = data;
2107         struct drm_gem_object *obj;
2108
2109         mutex_lock(&dev->struct_mutex);
2110
2111         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2112         if (obj == NULL) {
2113                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2114                           args->handle);
2115                 mutex_unlock(&dev->struct_mutex);
2116                 return -EINVAL;
2117         }
2118
2119         i915_gem_object_unpin(obj);
2120
2121         drm_gem_object_unreference(obj);
2122         mutex_unlock(&dev->struct_mutex);
2123         return 0;
2124 }
2125
2126 int
2127 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2128                     struct drm_file *file_priv)
2129 {
2130         struct drm_i915_gem_busy *args = data;
2131         struct drm_gem_object *obj;
2132         struct drm_i915_gem_object *obj_priv;
2133
2134         mutex_lock(&dev->struct_mutex);
2135         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2136         if (obj == NULL) {
2137                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2138                           args->handle);
2139                 mutex_unlock(&dev->struct_mutex);
2140                 return -EINVAL;
2141         }
2142
2143         obj_priv = obj->driver_private;
2144         args->busy = obj_priv->active;
2145
2146         drm_gem_object_unreference(obj);
2147         mutex_unlock(&dev->struct_mutex);
2148         return 0;
2149 }
2150
2151 int
2152 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2153                         struct drm_file *file_priv)
2154 {
2155     return i915_gem_ring_throttle(dev, file_priv);
2156 }
2157
2158 int i915_gem_init_object(struct drm_gem_object *obj)
2159 {
2160         struct drm_i915_gem_object *obj_priv;
2161
2162         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2163         if (obj_priv == NULL)
2164                 return -ENOMEM;
2165
2166         /*
2167          * We've just allocated pages from the kernel,
2168          * so they've just been written by the CPU with
2169          * zeros. They'll need to be clflushed before we
2170          * use them with the GPU.
2171          */
2172         obj->write_domain = I915_GEM_DOMAIN_CPU;
2173         obj->read_domains = I915_GEM_DOMAIN_CPU;
2174
2175         obj->driver_private = obj_priv;
2176         obj_priv->obj = obj;
2177         INIT_LIST_HEAD(&obj_priv->list);
2178         return 0;
2179 }
2180
2181 void i915_gem_free_object(struct drm_gem_object *obj)
2182 {
2183         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2184
2185         while (obj_priv->pin_count > 0)
2186                 i915_gem_object_unpin(obj);
2187
2188         i915_gem_object_unbind(obj);
2189
2190         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2191 }
2192
2193 int
2194 i915_gem_set_domain(struct drm_gem_object *obj,
2195                     struct drm_file *file_priv,
2196                     uint32_t read_domains,
2197                     uint32_t write_domain)
2198 {
2199         struct drm_device *dev = obj->dev;
2200         int ret;
2201         uint32_t flush_domains;
2202
2203         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
2204
2205         ret = i915_gem_object_set_domain(obj, read_domains, write_domain);
2206         if (ret)
2207                 return ret;
2208         flush_domains = i915_gem_dev_set_domain(obj->dev);
2209
2210         if (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))
2211                 (void) i915_add_request(dev, flush_domains);
2212
2213         return 0;
2214 }
2215
2216 /** Unbinds all objects that are on the given buffer list. */
2217 static int
2218 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2219 {
2220         struct drm_gem_object *obj;
2221         struct drm_i915_gem_object *obj_priv;
2222         int ret;
2223
2224         while (!list_empty(head)) {
2225                 obj_priv = list_first_entry(head,
2226                                             struct drm_i915_gem_object,
2227                                             list);
2228                 obj = obj_priv->obj;
2229
2230                 if (obj_priv->pin_count != 0) {
2231                         DRM_ERROR("Pinned object in unbind list\n");
2232                         mutex_unlock(&dev->struct_mutex);
2233                         return -EINVAL;
2234                 }
2235
2236                 ret = i915_gem_object_unbind(obj);
2237                 if (ret != 0) {
2238                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2239                                   ret);
2240                         mutex_unlock(&dev->struct_mutex);
2241                         return ret;
2242                 }
2243         }
2244
2245
2246         return 0;
2247 }
2248
2249 static int
2250 i915_gem_idle(struct drm_device *dev)
2251 {
2252         struct drm_i915_private *dev_priv = dev->dev_private;
2253         uint32_t seqno, cur_seqno, last_seqno;
2254         int stuck;
2255
2256         if (dev_priv->mm.suspended)
2257                 return 0;
2258
2259         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
2260          * We need to replace this with a semaphore, or something.
2261          */
2262         dev_priv->mm.suspended = 1;
2263
2264         i915_kernel_lost_context(dev);
2265
2266         /* Flush the GPU along with all non-CPU write domains
2267          */
2268         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2269                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2270         seqno = i915_add_request(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2271
2272         if (seqno == 0) {
2273                 mutex_unlock(&dev->struct_mutex);
2274                 return -ENOMEM;
2275         }
2276
2277         dev_priv->mm.waiting_gem_seqno = seqno;
2278         last_seqno = 0;
2279         stuck = 0;
2280         for (;;) {
2281                 cur_seqno = i915_get_gem_seqno(dev);
2282                 if (i915_seqno_passed(cur_seqno, seqno))
2283                         break;
2284                 if (last_seqno == cur_seqno) {
2285                         if (stuck++ > 100) {
2286                                 DRM_ERROR("hardware wedged\n");
2287                                 dev_priv->mm.wedged = 1;
2288                                 DRM_WAKEUP(&dev_priv->irq_queue);
2289                                 break;
2290                         }
2291                 }
2292                 msleep(10);
2293                 last_seqno = cur_seqno;
2294         }
2295         dev_priv->mm.waiting_gem_seqno = 0;
2296
2297         i915_gem_retire_requests(dev);
2298
2299         /* Active and flushing should now be empty as we've
2300          * waited for a sequence higher than any pending execbuffer
2301          */
2302         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2303         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2304
2305         /* Request should now be empty as we've also waited
2306          * for the last request in the list
2307          */
2308         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2309
2310         /* Move all buffers out of the GTT. */
2311         i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2312
2313         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2314         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2315         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2316         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2317         return 0;
2318 }
2319
2320 int
2321 i915_gem_init_ringbuffer(struct drm_device *dev)
2322 {
2323         struct drm_i915_private *dev_priv = dev->dev_private;
2324         struct drm_gem_object *obj;
2325         struct drm_i915_gem_object *obj_priv;
2326         int ret;
2327
2328         obj = drm_gem_object_alloc(dev, 128 * 1024);
2329         if (obj == NULL) {
2330                 DRM_ERROR("Failed to allocate ringbuffer\n");
2331                 return -ENOMEM;
2332         }
2333         obj_priv = obj->driver_private;
2334
2335         ret = i915_gem_object_pin(obj, 4096);
2336         if (ret != 0) {
2337                 drm_gem_object_unreference(obj);
2338                 return ret;
2339         }
2340
2341         /* Set up the kernel mapping for the ring. */
2342         dev_priv->ring.Size = obj->size;
2343         dev_priv->ring.tail_mask = obj->size - 1;
2344
2345         dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset;
2346         dev_priv->ring.map.size = obj->size;
2347         dev_priv->ring.map.type = 0;
2348         dev_priv->ring.map.flags = 0;
2349         dev_priv->ring.map.mtrr = 0;
2350
2351         drm_core_ioremap(&dev_priv->ring.map, dev);
2352         if (dev_priv->ring.map.handle == NULL) {
2353                 DRM_ERROR("Failed to map ringbuffer.\n");
2354                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2355                 drm_gem_object_unreference(obj);
2356                 return -EINVAL;
2357         }
2358         dev_priv->ring.ring_obj = obj;
2359         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
2360
2361         /* Stop the ring if it's running. */
2362         I915_WRITE(PRB0_CTL, 0);
2363         I915_WRITE(PRB0_HEAD, 0);
2364         I915_WRITE(PRB0_TAIL, 0);
2365         I915_WRITE(PRB0_START, 0);
2366
2367         /* Initialize the ring. */
2368         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
2369         I915_WRITE(PRB0_CTL, (((obj->size - 4096) & RING_NR_PAGES) |
2370                               RING_NO_REPORT |
2371                               RING_VALID));
2372
2373         /* Update our cache of the ring state */
2374         i915_kernel_lost_context(dev);
2375
2376         return 0;
2377 }
2378
2379 void
2380 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2381 {
2382         struct drm_i915_private *dev_priv = dev->dev_private;
2383
2384         if (dev_priv->ring.ring_obj == NULL)
2385                 return;
2386
2387         drm_core_ioremapfree(&dev_priv->ring.map, dev);
2388
2389         i915_gem_object_unpin(dev_priv->ring.ring_obj);
2390         drm_gem_object_unreference(dev_priv->ring.ring_obj);
2391
2392         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2393 }
2394
2395 int
2396 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2397                        struct drm_file *file_priv)
2398 {
2399         struct drm_i915_private *dev_priv = dev->dev_private;
2400         int ret;
2401
2402         if (dev_priv->mm.wedged) {
2403                 DRM_ERROR("Renabling wedged hardware, good luck\n");
2404                 dev_priv->mm.wedged = 0;
2405         }
2406
2407         ret = i915_gem_init_ringbuffer(dev);
2408         if (ret != 0)
2409                 return ret;
2410
2411         mutex_lock(&dev->struct_mutex);
2412         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2413         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2414         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2415         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2416         dev_priv->mm.suspended = 0;
2417         mutex_unlock(&dev->struct_mutex);
2418         return 0;
2419 }
2420
2421 int
2422 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2423                        struct drm_file *file_priv)
2424 {
2425         int ret;
2426
2427         mutex_lock(&dev->struct_mutex);
2428         ret = i915_gem_idle(dev);
2429         if (ret == 0)
2430                 i915_gem_cleanup_ringbuffer(dev);
2431         mutex_unlock(&dev->struct_mutex);
2432
2433         return 0;
2434 }
2435
2436 static int i915_gem_active_info(char *buf, char **start, off_t offset,
2437                                 int request, int *eof, void *data)
2438 {
2439         struct drm_minor *minor = (struct drm_minor *) data;
2440         struct drm_device *dev = minor->dev;
2441         struct drm_i915_private *dev_priv = dev->dev_private;
2442         struct drm_i915_gem_object *obj_priv;
2443         int len = 0;
2444
2445         if (offset > DRM_PROC_LIMIT) {
2446                 *eof = 1;
2447                 return 0;
2448         }
2449
2450         *start = &buf[offset];
2451         *eof = 0;
2452         DRM_PROC_PRINT("Active:\n");
2453         list_for_each_entry(obj_priv, &dev_priv->mm.active_list,
2454                             list)
2455         {
2456                 struct drm_gem_object *obj = obj_priv->obj;
2457                 if (obj->name) {
2458                         DRM_PROC_PRINT("    %p(%d): %08x %08x %d\n",
2459                                        obj, obj->name,
2460                                        obj->read_domains, obj->write_domain,
2461                                        obj_priv->last_rendering_seqno);
2462                 } else {
2463                         DRM_PROC_PRINT("       %p: %08x %08x %d\n",
2464                                        obj,
2465                                        obj->read_domains, obj->write_domain,
2466                                        obj_priv->last_rendering_seqno);
2467                 }
2468         }
2469         if (len > request + offset)
2470                 return request;
2471         *eof = 1;
2472         return len - offset;
2473 }
2474
2475 static int i915_gem_flushing_info(char *buf, char **start, off_t offset,
2476                                   int request, int *eof, void *data)
2477 {
2478         struct drm_minor *minor = (struct drm_minor *) data;
2479         struct drm_device *dev = minor->dev;
2480         struct drm_i915_private *dev_priv = dev->dev_private;
2481         struct drm_i915_gem_object *obj_priv;
2482         int len = 0;
2483
2484         if (offset > DRM_PROC_LIMIT) {
2485                 *eof = 1;
2486                 return 0;
2487         }
2488
2489         *start = &buf[offset];
2490         *eof = 0;
2491         DRM_PROC_PRINT("Flushing:\n");
2492         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list,
2493                             list)
2494         {
2495                 struct drm_gem_object *obj = obj_priv->obj;
2496                 if (obj->name) {
2497                         DRM_PROC_PRINT("    %p(%d): %08x %08x %d\n",
2498                                        obj, obj->name,
2499                                        obj->read_domains, obj->write_domain,
2500                                        obj_priv->last_rendering_seqno);
2501                 } else {
2502                         DRM_PROC_PRINT("       %p: %08x %08x %d\n", obj,
2503                                        obj->read_domains, obj->write_domain,
2504                                        obj_priv->last_rendering_seqno);
2505                 }
2506         }
2507         if (len > request + offset)
2508                 return request;
2509         *eof = 1;
2510         return len - offset;
2511 }
2512
2513 static int i915_gem_inactive_info(char *buf, char **start, off_t offset,
2514                                   int request, int *eof, void *data)
2515 {
2516         struct drm_minor *minor = (struct drm_minor *) data;
2517         struct drm_device *dev = minor->dev;
2518         struct drm_i915_private *dev_priv = dev->dev_private;
2519         struct drm_i915_gem_object *obj_priv;
2520         int len = 0;
2521
2522         if (offset > DRM_PROC_LIMIT) {
2523                 *eof = 1;
2524                 return 0;
2525         }
2526
2527         *start = &buf[offset];
2528         *eof = 0;
2529         DRM_PROC_PRINT("Inactive:\n");
2530         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list,
2531                             list)
2532         {
2533                 struct drm_gem_object *obj = obj_priv->obj;
2534                 if (obj->name) {
2535                         DRM_PROC_PRINT("    %p(%d): %08x %08x %d\n",
2536                                        obj, obj->name,
2537                                        obj->read_domains, obj->write_domain,
2538                                        obj_priv->last_rendering_seqno);
2539                 } else {
2540                         DRM_PROC_PRINT("       %p: %08x %08x %d\n", obj,
2541                                        obj->read_domains, obj->write_domain,
2542                                        obj_priv->last_rendering_seqno);
2543                 }
2544         }
2545         if (len > request + offset)
2546                 return request;
2547         *eof = 1;
2548         return len - offset;
2549 }
2550
2551 static int i915_gem_request_info(char *buf, char **start, off_t offset,
2552                                  int request, int *eof, void *data)
2553 {
2554         struct drm_minor *minor = (struct drm_minor *) data;
2555         struct drm_device *dev = minor->dev;
2556         struct drm_i915_private *dev_priv = dev->dev_private;
2557         struct drm_i915_gem_request *gem_request;
2558         int len = 0;
2559
2560         if (offset > DRM_PROC_LIMIT) {
2561                 *eof = 1;
2562                 return 0;
2563         }
2564
2565         *start = &buf[offset];
2566         *eof = 0;
2567         DRM_PROC_PRINT("Request:\n");
2568         list_for_each_entry(gem_request, &dev_priv->mm.request_list,
2569                             list)
2570         {
2571                 DRM_PROC_PRINT ("    %d @ %d %08x\n",
2572                                 gem_request->seqno,
2573                                 (int) (jiffies - gem_request->emitted_jiffies),
2574                                 gem_request->flush_domains);
2575         }
2576         if (len > request + offset)
2577                 return request;
2578         *eof = 1;
2579         return len - offset;
2580 }
2581
2582 static int i915_gem_seqno_info(char *buf, char **start, off_t offset,
2583                                int request, int *eof, void *data)
2584 {
2585         struct drm_minor *minor = (struct drm_minor *) data;
2586         struct drm_device *dev = minor->dev;
2587         struct drm_i915_private *dev_priv = dev->dev_private;
2588         int len = 0;
2589
2590         if (offset > DRM_PROC_LIMIT) {
2591                 *eof = 1;
2592                 return 0;
2593         }
2594
2595         *start = &buf[offset];
2596         *eof = 0;
2597         DRM_PROC_PRINT("Current sequence: %d\n", i915_get_gem_seqno(dev));
2598         DRM_PROC_PRINT("Waiter sequence:  %d\n", dev_priv->mm.waiting_gem_seqno);
2599         DRM_PROC_PRINT("IRQ sequence:     %d\n", dev_priv->mm.irq_gem_seqno);
2600         if (len > request + offset)
2601                 return request;
2602         *eof = 1;
2603         return len - offset;
2604 }
2605
2606
2607 static int i915_interrupt_info(char *buf, char **start, off_t offset,
2608                                int request, int *eof, void *data)
2609 {
2610         struct drm_minor *minor = (struct drm_minor *) data;
2611         struct drm_device *dev = minor->dev;
2612         struct drm_i915_private *dev_priv = dev->dev_private;
2613         int len = 0;
2614
2615         if (offset > DRM_PROC_LIMIT) {
2616                 *eof = 1;
2617                 return 0;
2618         }
2619
2620         *start = &buf[offset];
2621         *eof = 0;
2622         DRM_PROC_PRINT("Interrupt enable:    %08x\n",
2623                        I915_READ(IER));
2624         DRM_PROC_PRINT("Interrupt identity:  %08x\n",
2625                        I915_READ(IIR));
2626         DRM_PROC_PRINT("Interrupt mask:      %08x\n",
2627                        I915_READ(IMR));
2628         DRM_PROC_PRINT("Pipe A stat:         %08x\n",
2629                        I915_READ(PIPEASTAT));
2630         DRM_PROC_PRINT("Pipe B stat:         %08x\n",
2631                        I915_READ(PIPEBSTAT));
2632         DRM_PROC_PRINT("Interrupts received: %d\n",
2633                        atomic_read(&dev_priv->irq_received));
2634         DRM_PROC_PRINT("Current sequence:    %d\n",
2635                        i915_get_gem_seqno(dev));
2636         DRM_PROC_PRINT("Waiter sequence:     %d\n",
2637                        dev_priv->mm.waiting_gem_seqno);
2638         DRM_PROC_PRINT("IRQ sequence:        %d\n",
2639                        dev_priv->mm.irq_gem_seqno);
2640         if (len > request + offset)
2641                 return request;
2642         *eof = 1;
2643         return len - offset;
2644 }
2645
2646 static struct drm_proc_list {
2647         const char *name;       /**< file name */
2648         int (*f) (char *, char **, off_t, int, int *, void *);          /**< proc callback*/
2649 } i915_gem_proc_list[] = {
2650         {"i915_gem_active", i915_gem_active_info},
2651         {"i915_gem_flushing", i915_gem_flushing_info},
2652         {"i915_gem_inactive", i915_gem_inactive_info},
2653         {"i915_gem_request", i915_gem_request_info},
2654         {"i915_gem_seqno", i915_gem_seqno_info},
2655         {"i915_gem_interrupt", i915_interrupt_info},
2656 };
2657
2658 #define I915_GEM_PROC_ENTRIES ARRAY_SIZE(i915_gem_proc_list)
2659
2660 int i915_gem_proc_init(struct drm_minor *minor)
2661 {
2662         struct proc_dir_entry *ent;
2663         int i, j;
2664
2665         for (i = 0; i < I915_GEM_PROC_ENTRIES; i++) {
2666                 ent = create_proc_entry(i915_gem_proc_list[i].name,
2667                                         S_IFREG | S_IRUGO, minor->dev_root);
2668                 if (!ent) {
2669                         DRM_ERROR("Cannot create /proc/dri/.../%s\n",
2670                                   i915_gem_proc_list[i].name);
2671                         for (j = 0; j < i; j++)
2672                                 remove_proc_entry(i915_gem_proc_list[i].name,
2673                                                   minor->dev_root);
2674                         return -1;
2675                 }
2676                 ent->read_proc = i915_gem_proc_list[i].f;
2677                 ent->data = minor;
2678         }
2679         return 0;
2680 }
2681
2682 void i915_gem_proc_cleanup(struct drm_minor *minor)
2683 {
2684         int i;
2685
2686         if (!minor->dev_root)
2687                 return;
2688
2689         for (i = 0; i < I915_GEM_PROC_ENTRIES; i++)
2690                 remove_proc_entry(i915_gem_proc_list[i].name, minor->dev_root);
2691 }
2692
2693 void
2694 i915_gem_lastclose(struct drm_device *dev)
2695 {
2696         int ret;
2697         struct drm_i915_private *dev_priv = dev->dev_private;
2698
2699         mutex_lock(&dev->struct_mutex);
2700
2701         if (dev_priv->ring.ring_obj != NULL) {
2702                 ret = i915_gem_idle(dev);
2703                 if (ret)
2704                         DRM_ERROR("failed to idle hardware: %d\n", ret);
2705
2706                 i915_gem_cleanup_ringbuffer(dev);
2707         }
2708
2709         mutex_unlock(&dev->struct_mutex);
2710 }