linux-core/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32
  33 #define WATCH_COHERENCY 0
  34 #define WATCH_BUF       0
  35 #define WATCH_EXEC      0
  36 #define WATCH_LRU       0
  37 #define WATCH_RELOC     0
  38 #define WATCH_INACTIVE  0
  39 #define WATCH_PWRITE    0
  40
  41 #if WATCH_BUF | WATCH_EXEC | WATCH_PWRITE
  42 static void
  43 i915_gem_dump_object(struct drm_gem_object *obj, int len,
  44                      const char *where, uint32_t mark);
  45 #endif
  46
  47 static int
  48 i915_gem_object_set_domain(struct drm_gem_object *obj,
  49                             uint32_t read_domains,
  50                             uint32_t write_domain);
  51 int
  52 i915_gem_set_domain(struct drm_gem_object *obj,
  53                     struct drm_file *file_priv,
  54                     uint32_t read_domains,
  55                     uint32_t write_domain);
  56
  57 static void
  58 i915_gem_clflush_object(struct drm_gem_object *obj);
  59
  60 int
  61 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  62                     struct drm_file *file_priv)
  63 {
  64         drm_i915_private_t *dev_priv = dev->dev_private;
  65         struct drm_i915_gem_init *args = data;
  66
  67         mutex_lock(&dev->struct_mutex);
  68
  69         if (args->gtt_start >= args->gtt_end ||
  70             (args->gtt_start & (PAGE_SIZE - 1)) != 0 ||
  71             (args->gtt_end & (PAGE_SIZE - 1)) != 0) {
  72                 mutex_unlock(&dev->struct_mutex);
  73                 return -EINVAL;
  74         }
  75
  76         drm_memrange_init(&dev_priv->mm.gtt_space, args->gtt_start,
  77             args->gtt_end - args->gtt_start);
  78
  79         dev->gtt_total = (uint32_t) (args->gtt_end - args->gtt_start);
  80
  81         mutex_unlock(&dev->struct_mutex);
  82
  83         return 0;
  84 }
  85
  86
  87 /**
  88  * Creates a new mm object and returns a handle to it.
  89  */
  90 int
  91 i915_gem_create_ioctl(struct drm_device *dev, void *data,
  92                       struct drm_file *file_priv)
  93 {
  94         struct drm_i915_gem_create *args = data;
  95         struct drm_gem_object *obj;
  96         int handle, ret;
  97
  98         args->size = roundup(args->size, PAGE_SIZE);
  99
 100         /* Allocate the new object */
 101         obj = drm_gem_object_alloc(dev, args->size);
 102         if (obj == NULL)
 103                 return -ENOMEM;
 104
 105         ret = drm_gem_handle_create(file_priv, obj, &handle);
 106         mutex_lock(&dev->struct_mutex);
 107         drm_gem_object_handle_unreference(obj);
 108         mutex_unlock(&dev->struct_mutex);
 109
 110         if (ret)
 111                 return ret;
 112
 113         args->handle = handle;
 114
 115         return 0;
 116 }
 117
 118 /**
 119  * Reads data from the object referenced by handle.
 120  *
 121  * On error, the contents of *data are undefined.
 122  */
 123 int
 124 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 125                      struct drm_file *file_priv)
 126 {
 127         struct drm_i915_gem_pread *args = data;
 128         struct drm_gem_object *obj;
 129         ssize_t read;
 130         loff_t offset;
 131         int ret;
 132
 133         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 134         if (obj == NULL)
 135                 return -EINVAL;
 136
 137         mutex_lock(&dev->struct_mutex);
 138         ret = i915_gem_set_domain(obj, file_priv,
 139                                   I915_GEM_DOMAIN_CPU, 0);
 140         if (ret) {
 141                 drm_gem_object_unreference(obj);
 142                 mutex_unlock(&dev->struct_mutex);
 143                 return ret;
 144         }
 145         offset = args->offset;
 146
 147         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
 148                         args->size, &offset);
 149         if (read != args->size) {
 150                 drm_gem_object_unreference(obj);
 151                 mutex_unlock(&dev->struct_mutex);
 152                 if (read < 0)
 153                         return read;
 154                 else
 155                         return -EINVAL;
 156         }
 157
 158         drm_gem_object_unreference(obj);
 159         mutex_unlock(&dev->struct_mutex);
 160
 161         return 0;
 162 }
 163
 164 #include "drm_compat.h"
 165
 166 /**
 167  * Writes data to the object referenced by handle.
 168  *
 169  * On error, the contents of the buffer that were to be modified are undefined.
 170  */
 171 int
 172 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 173                       struct drm_file *file_priv)
 174 {
 175         struct drm_i915_gem_pwrite *args = data;
 176         struct drm_gem_object *obj;
 177         struct drm_i915_gem_object *obj_priv;
 178         ssize_t remain;
 179         loff_t offset;
 180         char __user *user_data;
 181         char *vaddr;
 182         int i, o, l;
 183         int ret = 0;
 184         unsigned long pfn;
 185         unsigned long unwritten;
 186
 187         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 188         if (obj == NULL)
 189                 return -EINVAL;
 190
 191         /** Bounds check destination.
 192          *
 193          * XXX: This could use review for overflow issues...
 194          */
 195         if (args->offset > obj->size || args->size > obj->size ||
 196             args->offset + args->size > obj->size)
 197                 return -EFAULT;
 198
 199         user_data = (char __user *) (uintptr_t) args->data_ptr;
 200         remain = args->size;
 201         if (!access_ok(VERIFY_READ, user_data, remain))
 202                 return -EFAULT;
 203
 204
 205         mutex_lock(&dev->struct_mutex);
 206         ret = i915_gem_object_pin(obj, 0);
 207         if (ret) {
 208                 drm_gem_object_unreference(obj);
 209                 mutex_unlock(&dev->struct_mutex);
 210                 return ret;
 211         }
 212         ret = i915_gem_set_domain(obj, file_priv,
 213                                   I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
 214         if (ret)
 215                 goto fail;
 216
 217         obj_priv = obj->driver_private;
 218         offset = obj_priv->gtt_offset + args->offset;
 219         obj_priv->dirty = 1;
 220
 221         while (remain > 0) {
 222
 223                 /** Operation in this page
 224                  *
 225                  * i = page number
 226                  * o = offset within page
 227                  * l = bytes to copy
 228                  */
 229                 i = offset >> PAGE_SHIFT;
 230                 o = offset & (PAGE_SIZE-1);
 231                 l = remain;
 232                 if ((o + l) > PAGE_SIZE)
 233                         l = PAGE_SIZE - o;
 234
 235                 pfn = (dev->agp->base >> PAGE_SHIFT) + i;
 236
 237 #ifdef DRM_KMAP_ATOMIC_PROT_PFN
 238                 /* kmap_atomic can't map IO pages on non-HIGHMEM kernels
 239                  */
 240                 vaddr = kmap_atomic_prot_pfn(pfn, KM_USER0,
 241                                              __pgprot(__PAGE_KERNEL));
 242 #if WATCH_PWRITE
 243                 DRM_INFO("pwrite i %d o %d l %d pfn %ld vaddr %p\n",
 244                          i, o, l, pfn, vaddr);
 245 #endif
 246                 unwritten = __copy_from_user_inatomic_nocache(vaddr + o, user_data, l);
 247                 kunmap_atomic(vaddr, KM_USER0);
 248
 249                 if (unwritten)
 250 #endif
 251                 {
 252                         vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
 253 #if WATCH_PWRITE
 254                         DRM_INFO("pwrite slow i %d o %d l %d pfn %ld vaddr %p\n",
 255                                  i, o, l, pfn, vaddr);
 256 #endif
 257                         if (vaddr == NULL) {
 258                                 ret = -EFAULT;
 259                                 goto fail;
 260                         }
 261                         unwritten = __copy_from_user(vaddr + o, user_data, l);
 262 #if WATCH_PWRITE
 263                         DRM_INFO("unwritten %ld\n", unwritten);
 264 #endif
 265                         iounmap(vaddr);
 266                         if (unwritten) {
 267                                 ret = -EFAULT;
 268                                 goto fail;
 269                         }
 270                 }
 271
 272                 remain -= l;
 273                 user_data += l;
 274                 offset += l;
 275         }
 276 #if WATCH_PWRITE && 1
 277         i915_gem_clflush_object(obj);
 278         i915_gem_dump_object(obj, args->offset + args->size, __func__, ~0);
 279         i915_gem_clflush_object(obj);
 280 #endif
 281
 282 fail:
 283         i915_gem_object_unpin (obj);
 284         drm_gem_object_unreference(obj);
 285         mutex_unlock(&dev->struct_mutex);
 286
 287 #if WATCH_PWRITE
 288         if (ret)
 289                 DRM_INFO("pwrite failed %d\n", ret);
 290 #endif
 291         return ret;
 292 }
 293
 294 /**
 295  * Called when user space prepares to use an object
 296  */
 297 int
 298 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 299                           struct drm_file *file_priv)
 300 {
 301         struct drm_i915_gem_set_domain *args = data;
 302         struct drm_gem_object *obj;
 303         int ret;
 304
 305         if (!(dev->driver->driver_features & DRIVER_GEM))
 306                 return -ENODEV;
 307
 308         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 309         if (obj == NULL)
 310                 return -EINVAL;
 311
 312         mutex_lock(&dev->struct_mutex);
 313         ret = i915_gem_set_domain(obj, file_priv,
 314                                   args->read_domains, args->write_domain);
 315         drm_gem_object_unreference(obj);
 316         mutex_unlock(&dev->struct_mutex);
 317         return ret;
 318 }
 319
 320 /**
 321  * Called when user space has done writes to this buffer
 322  */
 323 int
 324 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 325                       struct drm_file *file_priv)
 326 {
 327         struct drm_i915_gem_sw_finish *args = data;
 328         struct drm_gem_object *obj;
 329         struct drm_i915_gem_object *obj_priv;
 330         int ret = 0;
 331
 332         if (!(dev->driver->driver_features & DRIVER_GEM))
 333                 return -ENODEV;
 334
 335         mutex_lock(&dev->struct_mutex);
 336         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 337         if (obj == NULL) {
 338                 mutex_unlock(&dev->struct_mutex);
 339                 return -EINVAL;
 340         }
 341
 342 #if WATCH_BUF
 343         DRM_INFO("%s: sw_finish %d (%p)\n",
 344                  __func__, args->handle, obj);
 345 #endif
 346         obj_priv = obj->driver_private;
 347
 348         /** Pinned buffers may be scanout, so flush the cache
 349          */
 350         if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) {
 351                 i915_gem_clflush_object(obj);
 352                 drm_agp_chipset_flush(dev);
 353         }
 354         drm_gem_object_unreference(obj);
 355         mutex_unlock(&dev->struct_mutex);
 356         return ret;
 357 }
 358
 359 /**
 360  * Maps the contents of an object, returning the address it is mapped
 361  * into.
 362  *
 363  * While the mapping holds a reference on the contents of the object, it doesn't
 364  * imply a ref on the object itself.
 365  */
 366 int
 367 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 368                    struct drm_file *file_priv)
 369 {
 370         struct drm_i915_gem_mmap *args = data;
 371         struct drm_gem_object *obj;
 372         loff_t offset;
 373         unsigned long addr;
 374
 375         if (!(dev->driver->driver_features & DRIVER_GEM))
 376                 return -ENODEV;
 377
 378         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 379         if (obj == NULL)
 380                 return -EINVAL;
 381
 382         offset = args->offset;
 383
 384         down_write(&current->mm->mmap_sem);
 385         addr = do_mmap(obj->filp, 0, args->size,
 386                        PROT_READ | PROT_WRITE, MAP_SHARED,
 387                        args->offset);
 388         up_write(&current->mm->mmap_sem);
 389         mutex_lock(&dev->struct_mutex);
 390         drm_gem_object_unreference(obj);
 391         mutex_unlock(&dev->struct_mutex);
 392         if (IS_ERR((void *)addr))
 393                 return addr;
 394
 395         args->addr_ptr = (uint64_t) addr;
 396
 397         return 0;
 398 }
 399
 400 static void
 401 i915_gem_object_free_page_list(struct drm_gem_object *obj)
 402 {
 403         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 404         int page_count = obj->size / PAGE_SIZE;
 405         int i;
 406
 407         if (obj_priv->page_list == NULL)
 408                 return;
 409
 410
 411         for (i = 0; i < page_count; i++)
 412                 if (obj_priv->page_list[i] != NULL) {
 413                         if (obj_priv->dirty)
 414                                 set_page_dirty(obj_priv->page_list[i]);
 415                         mark_page_accessed(obj_priv->page_list[i]);
 416                         page_cache_release(obj_priv->page_list[i]);
 417                 }
 418         obj_priv->dirty = 0;
 419
 420         drm_free(obj_priv->page_list,
 421                  page_count * sizeof(struct page *),
 422                  DRM_MEM_DRIVER);
 423         obj_priv->page_list = NULL;
 424 }
 425
 426 static void
 427 i915_gem_object_move_to_active(struct drm_gem_object *obj)
 428 {
 429         struct drm_device *dev = obj->dev;
 430         drm_i915_private_t *dev_priv = dev->dev_private;
 431         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 432
 433         /* Add a reference if we're newly entering the active list. */
 434         if (!obj_priv->active) {
 435                 drm_gem_object_reference(obj);
 436                 obj_priv->active = 1;
 437         }
 438         /* Move from whatever list we were on to the tail of execution. */
 439         list_move_tail(&obj_priv->list,
 440                        &dev_priv->mm.active_list);
 441 }
 442
 443 #if WATCH_INACTIVE
 444 static void
 445 i915_verify_inactive(struct drm_device *dev, char *file, int line)
 446 {
 447         drm_i915_private_t *dev_priv = dev->dev_private;
 448         struct drm_gem_object *obj;
 449         struct drm_i915_gem_object *obj_priv;
 450
 451         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 452                 obj = obj_priv->obj;
 453                 if (obj_priv->pin_count || obj_priv->active || (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))
 454                         DRM_ERROR("inactive %p (p %d a %d w %x)  %s:%d\n",
 455                                   obj,
 456                                   obj_priv->pin_count, obj_priv->active, obj->write_domain, file, line);
 457         }
 458 }
 459 #else
 460 #define i915_verify_inactive(dev,file,line)
 461 #endif
 462
 463 static void
 464 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
 465 {
 466         struct drm_device *dev = obj->dev;
 467         drm_i915_private_t *dev_priv = dev->dev_private;
 468         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 469
 470         i915_verify_inactive(dev, __FILE__, __LINE__);
 471         if (obj_priv->pin_count != 0)
 472                 list_del_init(&obj_priv->list);
 473         else
 474                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
 475
 476         if (obj_priv->active) {
 477                 obj_priv->active = 0;
 478                 drm_gem_object_unreference(obj);
 479         }
 480         i915_verify_inactive(dev, __FILE__, __LINE__);
 481 }
 482
 483 /**
 484  * Creates a new sequence number, emitting a write of it to the status page
 485  * plus an interrupt, which will trigger i915_user_interrupt_handler.
 486  *
 487  * Must be called with struct_lock held.
 488  *
 489  * Returned sequence numbers are nonzero on success.
 490  */
 491 static uint32_t
 492 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
 493 {
 494         drm_i915_private_t *dev_priv = dev->dev_private;
 495         struct drm_i915_gem_request *request;
 496         uint32_t seqno;
 497         int was_empty;
 498         RING_LOCALS;
 499
 500         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
 501         if (request == NULL)
 502                 return 0;
 503
 504         /* Grab the seqno we're going to make this request be, and bump the
 505          * next (skipping 0 so it can be the reserved no-seqno value).
 506          */
 507         seqno = dev_priv->mm.next_gem_seqno;
 508         dev_priv->mm.next_gem_seqno++;
 509         if (dev_priv->mm.next_gem_seqno == 0)
 510                 dev_priv->mm.next_gem_seqno++;
 511
 512         BEGIN_LP_RING(4);
 513         OUT_RING(CMD_STORE_DWORD_IDX);
 514         OUT_RING(I915_GEM_HWS_INDEX << STORE_DWORD_INDEX_SHIFT);
 515         OUT_RING(seqno);
 516
 517         OUT_RING(GFX_OP_USER_INTERRUPT);
 518         ADVANCE_LP_RING();
 519
 520         DRM_DEBUG("%d\n", seqno);
 521
 522         request->seqno = seqno;
 523         request->emitted_jiffies = jiffies;
 524         request->flush_domains = flush_domains;
 525         was_empty = list_empty(&dev_priv->mm.request_list);
 526         list_add_tail(&request->list, &dev_priv->mm.request_list);
 527
 528         if (was_empty)
 529                 schedule_delayed_work (&dev_priv->mm.retire_work, HZ);
 530         return seqno;
 531 }
 532
 533 /**
 534  * Command execution barrier
 535  *
 536  * Ensures that all commands in the ring are finished
 537  * before signalling the CPU
 538  */
 539
 540 uint32_t
 541 i915_retire_commands(struct drm_device *dev)
 542 {
 543         drm_i915_private_t *dev_priv = dev->dev_private;
 544         uint32_t cmd = CMD_MI_FLUSH | MI_NO_WRITE_FLUSH;
 545         uint32_t flush_domains = 0;
 546         RING_LOCALS;
 547
 548         /* The sampler always gets flushed on i965 (sigh) */
 549         if (IS_I965G(dev))
 550                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
 551         BEGIN_LP_RING(2);
 552         OUT_RING(cmd);
 553         OUT_RING(0); /* noop */
 554         ADVANCE_LP_RING();
 555         return flush_domains;
 556 }
 557
 558 /**
 559  * Moves buffers associated only with the given active seqno from the active
 560  * to inactive list, potentially freeing them.
 561  */
 562 static void
 563 i915_gem_retire_request(struct drm_device *dev,
 564                         struct drm_i915_gem_request *request)
 565 {
 566         drm_i915_private_t *dev_priv = dev->dev_private;
 567
 568         if (request->flush_domains != 0) {
 569                 struct drm_i915_gem_object *obj_priv, *next;
 570
 571                 /* First clear any buffers that were only waiting for a flush
 572                  * matching the one just retired.
 573                  */
 574
 575                 list_for_each_entry_safe(obj_priv, next,
 576                                          &dev_priv->mm.flushing_list, list) {
 577                         struct drm_gem_object *obj = obj_priv->obj;
 578
 579                         if (obj->write_domain & request->flush_domains) {
 580                                 obj->write_domain = 0;
 581                                 i915_gem_object_move_to_inactive(obj);
 582                         }
 583                 }
 584
 585         }
 586
 587         /* Move any buffers on the active list that are no longer referenced
 588          * by the ringbuffer to the flushing/inactive lists as appropriate.
 589          */
 590         while (!list_empty(&dev_priv->mm.active_list)) {
 591                 struct drm_gem_object *obj;
 592                 struct drm_i915_gem_object *obj_priv;
 593
 594                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
 595                                             struct drm_i915_gem_object,
 596                                             list);
 597                 obj = obj_priv->obj;
 598
 599                 /* If the seqno being retired doesn't match the oldest in the
 600                  * list, then the oldest in the list must still be newer than
 601                  * this seqno.
 602                  */
 603                 if (obj_priv->last_rendering_seqno != request->seqno)
 604                         return;
 605 #if WATCH_LRU
 606                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
 607                          __func__, request->seqno, obj);
 608 #endif
 609
 610                 if (obj->write_domain != 0) {
 611                         list_move_tail(&obj_priv->list,
 612                                        &dev_priv->mm.flushing_list);
 613                 } else {
 614                         i915_gem_object_move_to_inactive(obj);
 615                 }
 616         }
 617 }
 618
 619 /**
 620  * Returns true if seq1 is later than seq2.
 621  */
 622 static int
 623 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
 624 {
 625         return (int32_t)(seq1 - seq2) >= 0;
 626 }
 627
 628 uint32_t
 629 i915_get_gem_seqno(struct drm_device *dev)
 630 {
 631         drm_i915_private_t *dev_priv = dev->dev_private;
 632
 633         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
 634 }
 635
 636 /**
 637  * This function clears the request list as sequence numbers are passed.
 638  */
 639 void
 640 i915_gem_retire_requests(struct drm_device *dev)
 641 {
 642         drm_i915_private_t *dev_priv = dev->dev_private;
 643         uint32_t seqno;
 644
 645         seqno = i915_get_gem_seqno(dev);
 646
 647         while (!list_empty(&dev_priv->mm.request_list)) {
 648                 struct drm_i915_gem_request *request;
 649                 uint32_t retiring_seqno;
 650
 651                 request = list_first_entry(&dev_priv->mm.request_list,
 652                                            struct drm_i915_gem_request,
 653                                            list);
 654                 retiring_seqno = request->seqno;
 655
 656                 if (i915_seqno_passed(seqno, retiring_seqno) || dev_priv->mm.wedged) {
 657                         i915_gem_retire_request(dev, request);
 658
 659                         list_del(&request->list);
 660                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
 661                 } else
 662                         break;
 663         }
 664 }
 665
 666 void
 667 i915_gem_retire_work_handler(struct work_struct *work)
 668 {
 669         drm_i915_private_t *dev_priv;
 670         struct drm_device *dev;
 671
 672         dev_priv = container_of(work, drm_i915_private_t,
 673                                 mm.retire_work.work);
 674         dev = dev_priv->dev;
 675
 676         mutex_lock(&dev->struct_mutex);
 677         i915_gem_retire_requests(dev);
 678         if (!list_empty(&dev_priv->mm.request_list))
 679                 schedule_delayed_work (&dev_priv->mm.retire_work, HZ);
 680         mutex_unlock(&dev->struct_mutex);
 681 }
 682
 683 /**
 684  * Waits for a sequence number to be signaled, and cleans up the
 685  * request and object lists appropriately for that event.
 686  */
 687 int
 688 i915_wait_request(struct drm_device *dev, uint32_t seqno)
 689 {
 690         drm_i915_private_t *dev_priv = dev->dev_private;
 691         int ret = 0;
 692
 693         BUG_ON(seqno == 0);
 694
 695         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
 696                 dev_priv->mm.waiting_gem_seqno = seqno;
 697                 i915_user_irq_on(dev_priv);
 698                 ret = wait_event_interruptible(dev_priv->irq_queue,
 699                                                i915_seqno_passed(i915_get_gem_seqno(dev),
 700                                                                  seqno) || dev_priv->mm.wedged);
 701                 i915_user_irq_off(dev_priv);
 702                 dev_priv->mm.waiting_gem_seqno = 0;
 703         }
 704         if (dev_priv->mm.wedged)
 705                 ret = -EIO;
 706
 707         if (ret)
 708                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
 709                           __func__, ret, seqno, i915_get_gem_seqno(dev));
 710
 711         /* Directly dispatch request retiring.  While we have the work queue
 712          * to handle this, the waiter on a request often wants an associated
 713          * buffer to have made it to the inactive list, and we would need
 714          * a separate wait queue to handle that.
 715          */
 716         if (ret == 0)
 717                 i915_gem_retire_requests(dev);
 718
 719         return ret;
 720 }
 721
 722 static void
 723 i915_gem_flush(struct drm_device *dev,
 724                uint32_t invalidate_domains,
 725                uint32_t flush_domains)
 726 {
 727         drm_i915_private_t *dev_priv = dev->dev_private;
 728         uint32_t cmd;
 729         RING_LOCALS;
 730
 731 #if WATCH_EXEC
 732         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
 733                   invalidate_domains, flush_domains);
 734 #endif
 735
 736         if (flush_domains & I915_GEM_DOMAIN_CPU)
 737                 drm_agp_chipset_flush(dev);
 738
 739         if ((invalidate_domains|flush_domains) & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) {
 740                 /*
 741                  * read/write caches:
 742                  *
 743                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 744                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 745                  * also flushed at 2d versus 3d pipeline switches.
 746                  *
 747                  * read-only caches:
 748                  *
 749                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 750                  * MI_READ_FLUSH is set, and is always flushed on 965.
 751                  *
 752                  * I915_GEM_DOMAIN_COMMAND may not exist?
 753                  *
 754                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 755                  * invalidated when MI_EXE_FLUSH is set.
 756                  *
 757                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 758                  * invalidated with every MI_FLUSH.
 759                  *
 760                  * TLBs:
 761                  *
 762                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 763                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 764                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 765                  * are flushed at any MI_FLUSH.
 766                  */
 767
 768                 cmd = CMD_MI_FLUSH | MI_NO_WRITE_FLUSH;
 769                 if ((invalidate_domains|flush_domains) &
 770                     I915_GEM_DOMAIN_RENDER)
 771                         cmd &= ~MI_NO_WRITE_FLUSH;
 772                 if (!IS_I965G(dev)) {
 773                         /*
 774                          * On the 965, the sampler cache always gets flushed
 775                          * and this bit is reserved.
 776                          */
 777                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 778                                 cmd |= MI_READ_FLUSH;
 779                 }
 780                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 781                         cmd |= MI_EXE_FLUSH;
 782
 783 #if WATCH_EXEC
 784                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 785 #endif
 786                 BEGIN_LP_RING(2);
 787                 OUT_RING(cmd);
 788                 OUT_RING(0); /* noop */
 789                 ADVANCE_LP_RING();
 790         }
 791 }
 792
 793 /**
 794  * Ensures that all rendering to the object has completed and the object is
 795  * safe to unbind from the GTT or access from the CPU.
 796  */
 797 static int
 798 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
 799 {
 800         struct drm_device *dev = obj->dev;
 801         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 802         int ret;
 803
 804         /* If there are writes queued to the buffer, flush and
 805          * create a new seqno to wait for.
 806          */
 807         if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) {
 808                 uint32_t write_domain = obj->write_domain;
 809 #if WATCH_BUF
 810                 DRM_INFO("%s: flushing object %p from write domain %08x\n",
 811                           __func__, obj, write_domain);
 812 #endif
 813                 i915_gem_flush(dev, 0, write_domain);
 814                 obj->write_domain = 0;
 815
 816                 i915_gem_object_move_to_active(obj);
 817                 obj_priv->last_rendering_seqno = i915_add_request(dev,
 818                                                                   write_domain);
 819                 BUG_ON(obj_priv->last_rendering_seqno == 0);
 820 #if WATCH_LRU
 821                 DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj);
 822 #endif
 823         }
 824         /* If there is rendering queued on the buffer being evicted, wait for
 825          * it.
 826          */
 827         if (obj_priv->active) {
 828 #if WATCH_BUF
 829                 DRM_INFO("%s: object %p wait for seqno %08x\n",
 830                           __func__, obj, obj_priv->last_rendering_seqno);
 831 #endif
 832                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
 833                 if (ret != 0)
 834                         return ret;
 835         }
 836
 837         return 0;
 838 }
 839
 840 /**
 841  * Unbinds an object from the GTT aperture.
 842  */
 843 static int
 844 i915_gem_object_unbind(struct drm_gem_object *obj)
 845 {
 846         struct drm_device *dev = obj->dev;
 847         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 848         int ret = 0;
 849
 850 #if WATCH_BUF
 851         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
 852         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
 853 #endif
 854         if (obj_priv->gtt_space == NULL)
 855                 return 0;
 856
 857         if (obj_priv->pin_count != 0) {
 858                 DRM_ERROR("Attempting to unbind pinned buffer\n");
 859                 return -EINVAL;
 860         }
 861
 862         /* Wait for any rendering to complete
 863          */
 864         ret = i915_gem_object_wait_rendering(obj);
 865         if (ret) {
 866                 DRM_ERROR ("wait_rendering failed: %d\n", ret);
 867                 return ret;
 868         }
 869
 870         /* Move the object to the CPU domain to ensure that
 871          * any possible CPU writes while it's not in the GTT
 872          * are flushed when we go to remap it. This will
 873          * also ensure that all pending GPU writes are finished
 874          * before we unbind.
 875          */
 876         ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU,
 877                                          I915_GEM_DOMAIN_CPU);
 878         if (ret) {
 879                 DRM_ERROR("set_domain failed: %d\n", ret);
 880                 return ret;
 881         }
 882
 883         if (obj_priv->agp_mem != NULL) {
 884                 drm_unbind_agp(obj_priv->agp_mem);
 885                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
 886                 obj_priv->agp_mem = NULL;
 887         }
 888
 889         BUG_ON(obj_priv->active);
 890
 891         i915_gem_object_free_page_list(obj);
 892
 893         if (obj_priv->gtt_space) {
 894                 atomic_dec(&dev->gtt_count);
 895                 atomic_sub(obj->size, &dev->gtt_memory);
 896
 897                 drm_memrange_put_block(obj_priv->gtt_space);
 898                 obj_priv->gtt_space = NULL;
 899         }
 900
 901         /* Remove ourselves from the LRU list if present. */
 902         if (!list_empty(&obj_priv->list))
 903                 list_del_init(&obj_priv->list);
 904
 905         return 0;
 906 }
 907
 908 #if WATCH_BUF | WATCH_EXEC | WATCH_PWRITE
 909 static void
 910 i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end,
 911                    uint32_t bias, uint32_t mark)
 912 {
 913         uint32_t *mem = kmap_atomic(page, KM_USER0);
 914         int i;
 915         for (i = start; i < end; i += 4)
 916                 DRM_INFO("%08x: %08x%s\n",
 917                           (int) (bias + i), mem[i / 4],
 918                           (bias + i == mark) ? " ********" : "");
 919         kunmap_atomic(mem, KM_USER0);
 920         /* give syslog time to catch up */
 921         msleep(1);
 922 }
 923
 924 static void
 925 i915_gem_dump_object(struct drm_gem_object *obj, int len,
 926                      const char *where, uint32_t mark)
 927 {
 928         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 929         int page;
 930
 931         DRM_INFO("%s: object at offset %08x\n", where, obj_priv->gtt_offset);
 932         for (page = 0; page < (len + PAGE_SIZE-1) / PAGE_SIZE; page++) {
 933                 int page_len, chunk, chunk_len;
 934
 935                 page_len = len - page * PAGE_SIZE;
 936                 if (page_len > PAGE_SIZE)
 937                         page_len = PAGE_SIZE;
 938
 939                 for (chunk = 0; chunk < page_len; chunk += 128) {
 940                         chunk_len = page_len - chunk;
 941                         if (chunk_len > 128)
 942                                 chunk_len = 128;
 943                         i915_gem_dump_page(obj_priv->page_list[page],
 944                                            chunk, chunk + chunk_len,
 945                                            obj_priv->gtt_offset +
 946                                            page * PAGE_SIZE,
 947                                            mark);
 948                 }
 949         }
 950 }
 951 #endif
 952
 953 #if WATCH_LRU
 954 static void
 955 i915_dump_lru(struct drm_device *dev, const char *where)
 956 {
 957         drm_i915_private_t              *dev_priv = dev->dev_private;
 958         struct drm_i915_gem_object      *obj_priv;
 959
 960         DRM_INFO("active list %s {\n", where);
 961         list_for_each_entry(obj_priv, &dev_priv->mm.active_list,
 962                             list)
 963         {
 964                 DRM_INFO("    %p: %08x\n", obj_priv,
 965                          obj_priv->last_rendering_seqno);
 966         }
 967         DRM_INFO("}\n");
 968         DRM_INFO("flushing list %s {\n", where);
 969         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list,
 970                             list)
 971         {
 972                 DRM_INFO("    %p: %08x\n", obj_priv,
 973                          obj_priv->last_rendering_seqno);
 974         }
 975         DRM_INFO("}\n");
 976         DRM_INFO("inactive %s {\n", where);
 977         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 978                 DRM_INFO("    %p: %08x\n", obj_priv,
 979                          obj_priv->last_rendering_seqno);
 980         }
 981         DRM_INFO("}\n");
 982 }
 983 #endif
 984
 985 static int
 986 i915_gem_evict_something(struct drm_device *dev)
 987 {
 988         drm_i915_private_t *dev_priv = dev->dev_private;
 989         struct drm_gem_object *obj;
 990         struct drm_i915_gem_object *obj_priv;
 991         int ret = 0;
 992
 993         for (;;) {
 994                 /* If there's an inactive buffer available now, grab it
 995                  * and be done.
 996                  */
 997                 if (!list_empty(&dev_priv->mm.inactive_list)) {
 998                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
 999                                                     struct drm_i915_gem_object,
1000                                                     list);
1001                         obj = obj_priv->obj;
1002                         BUG_ON(obj_priv->pin_count != 0);
1003 #if WATCH_LRU
1004                         DRM_INFO("%s: evicting %p\n", __func__, obj);
1005 #endif
1006                         BUG_ON(obj_priv->active);
1007
1008                         /* Wait on the rendering and unbind the buffer. */
1009                         ret = i915_gem_object_unbind(obj);
1010                         break;
1011                 }
1012
1013                 /* If we didn't get anything, but the ring is still processing
1014                  * things, wait for one of those things to finish and hopefully
1015                  * leave us a buffer to evict.
1016                  */
1017                 if (!list_empty(&dev_priv->mm.request_list)) {
1018                         struct drm_i915_gem_request *request;
1019
1020                         request = list_first_entry(&dev_priv->mm.request_list,
1021                                                    struct drm_i915_gem_request,
1022                                                    list);
1023
1024                         ret = i915_wait_request(dev, request->seqno);
1025                         if (ret)
1026                                 break;
1027
1028                         /* if waiting caused an object to become inactive,
1029                          * then loop around and wait for it. Otherwise, we
1030                          * assume that waiting freed and unbound something,
1031                          * so there should now be some space in the GTT
1032                          */
1033                         if (!list_empty(&dev_priv->mm.inactive_list))
1034                                 continue;
1035                         break;
1036                 }
1037
1038                 /* If we didn't have anything on the request list but there
1039                  * are buffers awaiting a flush, emit one and try again.
1040                  * When we wait on it, those buffers waiting for that flush
1041                  * will get moved to inactive.
1042                  */
1043                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1044                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1045                                                     struct drm_i915_gem_object,
1046                                                     list);
1047                         obj = obj_priv->obj;
1048
1049                         i915_gem_flush(dev,
1050                                        obj->write_domain,
1051                                        obj->write_domain);
1052                         i915_add_request(dev, obj->write_domain);
1053
1054                         obj = NULL;
1055                         continue;
1056                 }
1057
1058                 DRM_ERROR("inactive empty %d request empty %d flushing empty %d\n",
1059                           list_empty(&dev_priv->mm.inactive_list),
1060                           list_empty(&dev_priv->mm.request_list),
1061                           list_empty(&dev_priv->mm.flushing_list));
1062                 /* If we didn't do any of the above, there's nothing to be done
1063                  * and we just can't fit it in.
1064                  */
1065                 return -ENOMEM;
1066         }
1067         return ret;
1068 }
1069
1070 static int
1071 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1072 {
1073         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1074         int page_count, i;
1075         struct address_space *mapping;
1076         struct inode *inode;
1077         struct page *page;
1078         int ret;
1079
1080         if (obj_priv->page_list)
1081                 return 0;
1082
1083         /* Get the list of pages out of our struct file.  They'll be pinned
1084          * at this point until we release them.
1085          */
1086         page_count = obj->size / PAGE_SIZE;
1087         BUG_ON(obj_priv->page_list != NULL);
1088         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1089                                          DRM_MEM_DRIVER);
1090         if (obj_priv->page_list == NULL) {
1091                 DRM_ERROR("Faled to allocate page list\n");
1092                 return -ENOMEM;
1093         }
1094
1095         inode = obj->filp->f_path.dentry->d_inode;
1096         mapping = inode->i_mapping;
1097         for (i = 0; i < page_count; i++) {
1098                 page = find_get_page(mapping, i);
1099                 if (page == NULL || !PageUptodate(page)) {
1100                         if (page) {
1101                                 page_cache_release(page);
1102                                 page = NULL;
1103                         }
1104                         ret = shmem_getpage(inode, i, &page, SGP_DIRTY, NULL);
1105
1106                         if (ret) {
1107                                 DRM_ERROR("shmem_getpage failed: %d\n", ret);
1108                                 i915_gem_object_free_page_list(obj);
1109                                 return ret;
1110                         }
1111                         unlock_page(page);
1112                 }
1113                 obj_priv->page_list[i] = page;
1114         }
1115         return 0;
1116 }
1117
1118 /**
1119  * Finds free space in the GTT aperture and binds the object there.
1120  */
1121 static int
1122 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1123 {
1124         struct drm_device *dev = obj->dev;
1125         drm_i915_private_t *dev_priv = dev->dev_private;
1126         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1127         struct drm_memrange_node *free_space;
1128         int page_count, ret;
1129
1130         if (alignment == 0)
1131                 alignment = PAGE_SIZE;
1132         if (alignment & (PAGE_SIZE - 1)) {
1133                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1134                 return -EINVAL;
1135         }
1136
1137  search_free:
1138         free_space = drm_memrange_search_free(&dev_priv->mm.gtt_space,
1139                                               obj->size,
1140                                               alignment, 0);
1141         if (free_space != NULL) {
1142                 obj_priv->gtt_space =
1143                         drm_memrange_get_block(free_space, obj->size,
1144                                                alignment);
1145                 if (obj_priv->gtt_space != NULL) {
1146                         obj_priv->gtt_space->private = obj;
1147                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1148                 }
1149         }
1150         if (obj_priv->gtt_space == NULL) {
1151                 /* If the gtt is empty and we're still having trouble
1152                  * fitting our object in, we're out of memory.
1153                  */
1154 #if WATCH_LRU
1155                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1156 #endif
1157                 if (list_empty(&dev_priv->mm.inactive_list) &&
1158                     list_empty(&dev_priv->mm.flushing_list) &&
1159                     list_empty(&dev_priv->mm.active_list)) {
1160                         DRM_ERROR("GTT full, but LRU list empty\n");
1161                         return -ENOMEM;
1162                 }
1163
1164                 ret = i915_gem_evict_something(dev);
1165                 if (ret != 0) {
1166                         DRM_ERROR("Failed to evict a buffer %d\n", ret);
1167                         return ret;
1168                 }
1169                 goto search_free;
1170         }
1171
1172 #if WATCH_BUF
1173         DRM_INFO("Binding object of size %d at 0x%08x\n",
1174                  obj->size, obj_priv->gtt_offset);
1175 #endif
1176         ret = i915_gem_object_get_page_list(obj);
1177         if (ret) {
1178                 drm_memrange_put_block(obj_priv->gtt_space);
1179                 obj_priv->gtt_space = NULL;
1180                 return ret;
1181         }
1182
1183         page_count = obj->size / PAGE_SIZE;
1184         /* Create an AGP memory structure pointing at our pages, and bind it
1185          * into the GTT.
1186          */
1187         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1188                                                obj_priv->page_list,
1189                                                page_count,
1190                                                obj_priv->gtt_offset);
1191         if (obj_priv->agp_mem == NULL) {
1192                 i915_gem_object_free_page_list(obj);
1193                 drm_memrange_put_block(obj_priv->gtt_space);
1194                 obj_priv->gtt_space = NULL;
1195                 return -ENOMEM;
1196         }
1197         atomic_inc(&dev->gtt_count);
1198         atomic_add(obj->size, &dev->gtt_memory);
1199
1200         /* Assert that the object is not currently in any GPU domain. As it
1201          * wasn't in the GTT, there shouldn't be any way it could have been in
1202          * a GPU cache
1203          */
1204         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1205         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1206
1207         return 0;
1208 }
1209
1210 static void
1211 i915_gem_clflush_object(struct drm_gem_object *obj)
1212 {
1213         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1214
1215         /* If we don't have a page list set up, then we're not pinned
1216          * to GPU, and we can ignore the cache flush because it'll happen
1217          * again at bind time.
1218          */
1219         if (obj_priv->page_list == NULL)
1220                 return;
1221
1222         drm_ttm_cache_flush(obj_priv->page_list, obj->size / PAGE_SIZE);
1223 }
1224
1225 /*
1226  * Set the next domain for the specified object. This
1227  * may not actually perform the necessary flushing/invaliding though,
1228  * as that may want to be batched with other set_domain operations
1229  *
1230  * This is (we hope) the only really tricky part of gem. The goal
1231  * is fairly simple -- track which caches hold bits of the object
1232  * and make sure they remain coherent. A few concrete examples may
1233  * help to explain how it works. For shorthand, we use the notation
1234  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1235  * a pair of read and write domain masks.
1236  *
1237  * Case 1: the batch buffer
1238  *
1239  *      1. Allocated
1240  *      2. Written by CPU
1241  *      3. Mapped to GTT
1242  *      4. Read by GPU
1243  *      5. Unmapped from GTT
1244  *      6. Freed
1245  *
1246  *      Let's take these a step at a time
1247  *
1248  *      1. Allocated
1249  *              Pages allocated from the kernel may still have
1250  *              cache contents, so we set them to (CPU, CPU) always.
1251  *      2. Written by CPU (using pwrite)
1252  *              The pwrite function calls set_domain (CPU, CPU) and
1253  *              this function does nothing (as nothing changes)
1254  *      3. Mapped by GTT
1255  *              This function asserts that the object is not
1256  *              currently in any GPU-based read or write domains
1257  *      4. Read by GPU
1258  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1259  *              As write_domain is zero, this function adds in the
1260  *              current read domains (CPU+COMMAND, 0).
1261  *              flush_domains is set to CPU.
1262  *              invalidate_domains is set to COMMAND
1263  *              clflush is run to get data out of the CPU caches
1264  *              then i915_dev_set_domain calls i915_gem_flush to
1265  *              emit an MI_FLUSH and drm_agp_chipset_flush
1266  *      5. Unmapped from GTT
1267  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1268  *              flush_domains and invalidate_domains end up both zero
1269  *              so no flushing/invalidating happens
1270  *      6. Freed
1271  *              yay, done
1272  *
1273  * Case 2: The shared render buffer
1274  *
1275  *      1. Allocated
1276  *      2. Mapped to GTT
1277  *      3. Read/written by GPU
1278  *      4. set_domain to (CPU,CPU)
1279  *      5. Read/written by CPU
1280  *      6. Read/written by GPU
1281  *
1282  *      1. Allocated
1283  *              Same as last example, (CPU, CPU)
1284  *      2. Mapped to GTT
1285  *              Nothing changes (assertions find that it is not in the GPU)
1286  *      3. Read/written by GPU
1287  *              execbuffer calls set_domain (RENDER, RENDER)
1288  *              flush_domains gets CPU
1289  *              invalidate_domains gets GPU
1290  *              clflush (obj)
1291  *              MI_FLUSH and drm_agp_chipset_flush
1292  *      4. set_domain (CPU, CPU)
1293  *              flush_domains gets GPU
1294  *              invalidate_domains gets CPU
1295  *              wait_rendering (obj) to make sure all drawing is complete.
1296  *              This will include an MI_FLUSH to get the data from GPU
1297  *              to memory
1298  *              clflush (obj) to invalidate the CPU cache
1299  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1300  *      5. Read/written by CPU
1301  *              cache lines are loaded and dirtied
1302  *      6. Read written by GPU
1303  *              Same as last GPU access
1304  *
1305  * Case 3: The constant buffer
1306  *
1307  *      1. Allocated
1308  *      2. Written by CPU
1309  *      3. Read by GPU
1310  *      4. Updated (written) by CPU again
1311  *      5. Read by GPU
1312  *
1313  *      1. Allocated
1314  *              (CPU, CPU)
1315  *      2. Written by CPU
1316  *              (CPU, CPU)
1317  *      3. Read by GPU
1318  *              (CPU+RENDER, 0)
1319  *              flush_domains = CPU
1320  *              invalidate_domains = RENDER
1321  *              clflush (obj)
1322  *              MI_FLUSH
1323  *              drm_agp_chipset_flush
1324  *      4. Updated (written) by CPU again
1325  *              (CPU, CPU)
1326  *              flush_domains = 0 (no previous write domain)
1327  *              invalidate_domains = 0 (no new read domains)
1328  *      5. Read by GPU
1329  *              (CPU+RENDER, 0)
1330  *              flush_domains = CPU
1331  *              invalidate_domains = RENDER
1332  *              clflush (obj)
1333  *              MI_FLUSH
1334  *              drm_agp_chipset_flush
1335  */
1336 static int
1337 i915_gem_object_set_domain(struct drm_gem_object *obj,
1338                             uint32_t read_domains,
1339                             uint32_t write_domain)
1340 {
1341         struct drm_device               *dev = obj->dev;
1342         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1343         uint32_t                        invalidate_domains = 0;
1344         uint32_t                        flush_domains = 0;
1345         int                             ret;
1346
1347 #if WATCH_BUF
1348         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1349                  __func__, obj,
1350                  obj->read_domains, read_domains,
1351                  obj->write_domain, write_domain);
1352 #endif
1353         /*
1354          * If the object isn't moving to a new write domain,
1355          * let the object stay in multiple read domains
1356          */
1357         if (write_domain == 0)
1358                 read_domains |= obj->read_domains;
1359         else
1360                 obj_priv->dirty = 1;
1361
1362         /*
1363          * Flush the current write domain if
1364          * the new read domains don't match. Invalidate
1365          * any read domains which differ from the old
1366          * write domain
1367          */
1368         if (obj->write_domain && obj->write_domain != read_domains) {
1369                 flush_domains |= obj->write_domain;
1370                 invalidate_domains |= read_domains & ~obj->write_domain;
1371         }
1372         /*
1373          * Invalidate any read caches which may have
1374          * stale data. That is, any new read domains.
1375          */
1376         invalidate_domains |= read_domains & ~obj->read_domains;
1377         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
1378 #if WATCH_BUF
1379                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1380                          __func__, flush_domains, invalidate_domains);
1381 #endif
1382                 /*
1383                  * If we're invaliding the CPU cache and flushing a GPU cache,
1384                  * then pause for rendering so that the GPU caches will be
1385                  * flushed before the cpu cache is invalidated
1386                  */
1387                 if ((invalidate_domains & I915_GEM_DOMAIN_CPU) &&
1388                     (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))) {
1389                         ret = i915_gem_object_wait_rendering(obj);
1390                         if (ret)
1391                                 return ret;
1392                 }
1393                 i915_gem_clflush_object(obj);
1394         }
1395
1396         if ((write_domain | flush_domains) != 0)
1397                 obj->write_domain = write_domain;
1398         obj->read_domains = read_domains;
1399         dev->invalidate_domains |= invalidate_domains;
1400         dev->flush_domains |= flush_domains;
1401 #if WATCH_BUF
1402         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1403                  __func__,
1404                  obj->read_domains, obj->write_domain,
1405                  dev->invalidate_domains, dev->flush_domains);
1406 #endif
1407         return 0;
1408 }
1409
1410 /**
1411  * Once all of the objects have been set in the proper domain,
1412  * perform the necessary flush and invalidate operations.
1413  *
1414  * Returns the write domains flushed, for use in flush tracking.
1415  */
1416 static uint32_t
1417 i915_gem_dev_set_domain(struct drm_device *dev)
1418 {
1419         uint32_t flush_domains = dev->flush_domains;
1420
1421         /*
1422          * Now that all the buffers are synced to the proper domains,
1423          * flush and invalidate the collected domains
1424          */
1425         if (dev->invalidate_domains | dev->flush_domains) {
1426 #if WATCH_EXEC
1427                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
1428                           __func__,
1429                          dev->invalidate_domains,
1430                          dev->flush_domains);
1431 #endif
1432                 i915_gem_flush(dev,
1433                                dev->invalidate_domains,
1434                                dev->flush_domains);
1435                 dev->invalidate_domains = 0;
1436                 dev->flush_domains = 0;
1437         }
1438
1439         return flush_domains;
1440 }
1441
1442 #if WATCH_COHERENCY
1443 static void
1444 i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle)
1445 {
1446         struct drm_device *dev = obj->dev;
1447         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1448         int page;
1449         uint32_t *gtt_mapping;
1450         uint32_t *backing_map = NULL;
1451         int bad_count = 0;
1452
1453         DRM_INFO("%s: checking coherency of object %p@0x%08x (%d, %dkb):\n",
1454                  __func__, obj, obj_priv->gtt_offset, handle,
1455                  obj->size / 1024);
1456
1457         gtt_mapping = ioremap(dev->agp->base + obj_priv->gtt_offset,
1458                               obj->size);
1459         if (gtt_mapping == NULL) {
1460                 DRM_ERROR("failed to map GTT space\n");
1461                 return;
1462         }
1463
1464         for (page = 0; page < obj->size / PAGE_SIZE; page++) {
1465                 int i;
1466
1467                 backing_map = kmap_atomic(obj_priv->page_list[page], KM_USER0);
1468
1469                 if (backing_map == NULL) {
1470                         DRM_ERROR("failed to map backing page\n");
1471                         goto out;
1472                 }
1473
1474                 for (i = 0; i < PAGE_SIZE / 4; i++) {
1475                         uint32_t cpuval = backing_map[i];
1476                         uint32_t gttval = readl(gtt_mapping +
1477                                                 page * 1024 + i);
1478
1479                         if (cpuval != gttval) {
1480                                 DRM_INFO("incoherent CPU vs GPU at 0x%08x: "
1481                                          "0x%08x vs 0x%08x\n",
1482                                          (int)(obj_priv->gtt_offset +
1483                                                page * PAGE_SIZE + i * 4),
1484                                          cpuval, gttval);
1485                                 if (bad_count++ >= 8) {
1486                                         DRM_INFO("...\n");
1487                                         goto out;
1488                                 }
1489                         }
1490                 }
1491                 kunmap_atomic(backing_map, KM_USER0);
1492                 backing_map = NULL;
1493         }
1494
1495  out:
1496         if (backing_map != NULL)
1497                 kunmap_atomic(backing_map, KM_USER0);
1498         iounmap(gtt_mapping);
1499
1500         /* give syslog time to catch up */
1501         msleep(1);
1502
1503         /* Directly flush the object, since we just loaded values with the CPU
1504          * from thebacking pages and we don't want to disturb the cache
1505          * management that we're trying to observe.
1506          */
1507
1508         i915_gem_clflush_object(obj);
1509 }
1510 #endif
1511
1512 /**
1513  * Pin an object to the GTT and evaluate the relocations landing in it.
1514  */
1515 static int
1516 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1517                                  struct drm_file *file_priv,
1518                                  struct drm_i915_gem_exec_object *entry)
1519 {
1520         struct drm_device *dev = obj->dev;
1521         struct drm_i915_gem_relocation_entry reloc;
1522         struct drm_i915_gem_relocation_entry __user *relocs;
1523         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1524         int i, ret;
1525         uint32_t last_reloc_offset = -1;
1526         void *reloc_page = NULL;
1527
1528         /* Choose the GTT offset for our buffer and put it there. */
1529         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
1530         if (ret)
1531                 return ret;
1532
1533         entry->offset = obj_priv->gtt_offset;
1534
1535         relocs = (struct drm_i915_gem_relocation_entry __user *)
1536                  (uintptr_t) entry->relocs_ptr;
1537         /* Apply the relocations, using the GTT aperture to avoid cache
1538          * flushing requirements.
1539          */
1540         for (i = 0; i < entry->relocation_count; i++) {
1541                 struct drm_gem_object *target_obj;
1542                 struct drm_i915_gem_object *target_obj_priv;
1543                 uint32_t reloc_val, reloc_offset, *reloc_entry;
1544                 int ret;
1545
1546                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
1547                 if (ret != 0) {
1548                         i915_gem_object_unpin(obj);
1549                         return ret;
1550                 }
1551
1552                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
1553                                                    reloc.target_handle);
1554                 if (target_obj == NULL) {
1555                         i915_gem_object_unpin(obj);
1556                         return -EINVAL;
1557                 }
1558                 target_obj_priv = target_obj->driver_private;
1559
1560                 /* The target buffer should have appeared before us in the
1561                  * exec_object list, so it should have a GTT space bound by now.
1562                  */
1563                 if (target_obj_priv->gtt_space == NULL) {
1564                         DRM_ERROR("No GTT space found for object %d\n",
1565                                   reloc.target_handle);
1566                         drm_gem_object_unreference(target_obj);
1567                         i915_gem_object_unpin(obj);
1568                         return -EINVAL;
1569                 }
1570
1571                 if (reloc.offset > obj->size - 4) {
1572                         DRM_ERROR("Relocation beyond object bounds: "
1573                                   "obj %p target %d offset %d size %d.\n",
1574                                   obj, reloc.target_handle,
1575                                   (int) reloc.offset, (int) obj->size);
1576                         drm_gem_object_unreference(target_obj);
1577                         i915_gem_object_unpin(obj);
1578                         return -EINVAL;
1579                 }
1580                 if (reloc.offset & 3) {
1581                         DRM_ERROR("Relocation not 4-byte aligned: "
1582                                   "obj %p target %d offset %d.\n",
1583                                   obj, reloc.target_handle,
1584                                   (int) reloc.offset);
1585                         drm_gem_object_unreference(target_obj);
1586                         i915_gem_object_unpin(obj);
1587                         return -EINVAL;
1588                 }
1589
1590                 if (reloc.write_domain && target_obj->pending_write_domain &&
1591                     reloc.write_domain != target_obj->pending_write_domain) {
1592                         DRM_ERROR("Write domain conflict: "
1593                                   "obj %p target %d offset %d "
1594                                   "new %08x old %08x\n",
1595                                   obj, reloc.target_handle,
1596                                   (int) reloc.offset,
1597                                   reloc.write_domain,
1598                                   target_obj->pending_write_domain);
1599                         drm_gem_object_unreference(target_obj);
1600                         i915_gem_object_unpin(obj);
1601                         return -EINVAL;
1602                 }
1603
1604 #if WATCH_RELOC
1605                 DRM_INFO("%s: obj %p offset %08x target %d "
1606                          "read %08x write %08x gtt %08x "
1607                          "presumed %08x delta %08x\n",
1608                          __func__,
1609                          obj,
1610                          (int) reloc.offset,
1611                          (int) reloc.target_handle,
1612                          (int) reloc.read_domains,
1613                          (int) reloc.write_domain,
1614                          (int) target_obj_priv->gtt_offset,
1615                          (int) reloc.presumed_offset,
1616                          reloc.delta);
1617 #endif
1618
1619                 target_obj->pending_read_domains |= reloc.read_domains;
1620                 target_obj->pending_write_domain |= reloc.write_domain;
1621
1622                 /* If the relocation already has the right value in it, no
1623                  * more work needs to be done.
1624                  */
1625                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
1626                         drm_gem_object_unreference(target_obj);
1627                         continue;
1628                 }
1629
1630                 /* Now that we're going to actually write some data in,
1631                  * make sure that any rendering using this buffer's contents
1632                  * is completed.
1633                  */
1634                 i915_gem_object_wait_rendering(obj);
1635
1636                 /* As we're writing through the gtt, flush
1637                  * any CPU writes before we write the relocations
1638                  */
1639                 if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
1640                         i915_gem_clflush_object(obj);
1641                         drm_agp_chipset_flush(dev);
1642                         obj->write_domain = 0;
1643                 }
1644
1645                 /* Map the page containing the relocation we're going to
1646                  * perform.
1647                  */
1648                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1649                 if (reloc_page == NULL ||
1650                     (last_reloc_offset & ~(PAGE_SIZE - 1)) !=
1651                     (reloc_offset & ~(PAGE_SIZE - 1))) {
1652                         if (reloc_page != NULL)
1653                                 iounmap(reloc_page);
1654
1655                         reloc_page = ioremap(dev->agp->base +
1656                                              (reloc_offset & ~(PAGE_SIZE - 1)),
1657                                              PAGE_SIZE);
1658                         last_reloc_offset = reloc_offset;
1659                         if (reloc_page == NULL) {
1660                                 drm_gem_object_unreference(target_obj);
1661                                 i915_gem_object_unpin(obj);
1662                                 return -ENOMEM;
1663                         }
1664                 }
1665
1666                 reloc_entry = (uint32_t *)((char *)reloc_page +
1667                                            (reloc_offset & (PAGE_SIZE - 1)));
1668                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1669
1670 #if WATCH_BUF
1671                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1672                           obj, (unsigned int) reloc.offset,
1673                           readl(reloc_entry), reloc_val);
1674 #endif
1675                 writel(reloc_val, reloc_entry);
1676
1677                 /* Write the updated presumed offset for this entry back out
1678                  * to the user.
1679                  */
1680                 reloc.presumed_offset = target_obj_priv->gtt_offset;
1681                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
1682                 if (ret != 0) {
1683                         drm_gem_object_unreference(target_obj);
1684                         i915_gem_object_unpin(obj);
1685                         return ret;
1686                 }
1687
1688                 drm_gem_object_unreference(target_obj);
1689         }
1690
1691         if (reloc_page != NULL)
1692                 iounmap(reloc_page);
1693
1694 #if WATCH_BUF
1695         if (0)
1696                 i915_gem_dump_object(obj, 128, __func__, ~0);
1697 #endif
1698         return 0;
1699 }
1700
1701 /** Dispatch a batchbuffer to the ring
1702  */
1703 static int
1704 i915_dispatch_gem_execbuffer(struct drm_device *dev,
1705                               struct drm_i915_gem_execbuffer *exec,
1706                               uint64_t exec_offset)
1707 {
1708         drm_i915_private_t *dev_priv = dev->dev_private;
1709         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
1710                                              (uintptr_t) exec->cliprects_ptr;
1711         int nbox = exec->num_cliprects;
1712         int i = 0, count;
1713         uint32_t        exec_start, exec_len;
1714         RING_LOCALS;
1715
1716         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
1717         exec_len = (uint32_t) exec->batch_len;
1718
1719         if ((exec_start | exec_len) & 0x7) {
1720                 DRM_ERROR("alignment\n");
1721                 return -EINVAL;
1722         }
1723
1724         if (!exec_start)
1725                 return -EINVAL;
1726
1727         count = nbox ? nbox : 1;
1728
1729         for (i = 0; i < count; i++) {
1730                 if (i < nbox) {
1731                         int ret = i915_emit_box(dev, boxes, i,
1732                                                 exec->DR1, exec->DR4);
1733                         if (ret)
1734                                 return ret;
1735                 }
1736
1737                 if (IS_I830(dev) || IS_845G(dev)) {
1738                         BEGIN_LP_RING(4);
1739                         OUT_RING(MI_BATCH_BUFFER);
1740                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1741                         OUT_RING(exec_start + exec_len - 4);
1742                         OUT_RING(0);
1743                         ADVANCE_LP_RING();
1744                 } else {
1745                         BEGIN_LP_RING(2);
1746                         if (IS_I965G(dev)) {
1747                                 OUT_RING(MI_BATCH_BUFFER_START |
1748                                          (2 << 6) |
1749                                          MI_BATCH_NON_SECURE_I965);
1750                                 OUT_RING(exec_start);
1751                         } else {
1752                                 OUT_RING(MI_BATCH_BUFFER_START |
1753                                          (2 << 6));
1754                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1755                         }
1756                         ADVANCE_LP_RING();
1757                 }
1758         }
1759
1760         /* XXX breadcrumb */
1761         return 0;
1762 }
1763
1764 /* Throttle our rendering by waiting until the ring has completed our requests
1765  * emitted over 20 msec ago.
1766  *
1767  * This should get us reasonable parallelism between CPU and GPU but also
1768  * relatively low latency when blocking on a particular request to finish.
1769  */
1770 static int
1771 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
1772 {
1773         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1774         int ret = 0;
1775         uint32_t seqno;
1776
1777         mutex_lock(&dev->struct_mutex);
1778         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
1779         i915_file_priv->mm.last_gem_throttle_seqno = i915_file_priv->mm.last_gem_seqno;
1780         if (seqno)
1781                 ret = i915_wait_request(dev, seqno);
1782         mutex_unlock(&dev->struct_mutex);
1783         return ret;
1784 }
1785
1786 int
1787 i915_gem_execbuffer(struct drm_device *dev, void *data,
1788                     struct drm_file *file_priv)
1789 {
1790         drm_i915_private_t *dev_priv = dev->dev_private;
1791         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1792         struct drm_i915_gem_execbuffer *args = data;
1793         struct drm_i915_gem_exec_object *exec_list = NULL;
1794         struct drm_gem_object **object_list = NULL;
1795         struct drm_gem_object *batch_obj;
1796         int ret, i, pinned = 0;
1797         uint64_t exec_offset;
1798         uint32_t seqno, flush_domains;
1799
1800 #if WATCH_EXEC
1801         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1802                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1803 #endif
1804
1805         /* Copy in the exec list from userland */
1806         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
1807                                DRM_MEM_DRIVER);
1808         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
1809                                  DRM_MEM_DRIVER);
1810         if (exec_list == NULL || object_list == NULL) {
1811                 DRM_ERROR("Failed to allocate exec or object list "
1812                           "for %d buffers\n",
1813                           args->buffer_count);
1814                 ret = -ENOMEM;
1815                 goto pre_mutex_err;
1816         }
1817         ret = copy_from_user(exec_list,
1818                              (struct drm_i915_relocation_entry __user *)
1819                              (uintptr_t) args->buffers_ptr,
1820                              sizeof(*exec_list) * args->buffer_count);
1821         if (ret != 0) {
1822                 DRM_ERROR("copy %d exec entries failed %d\n",
1823                           args->buffer_count, ret);
1824                 goto pre_mutex_err;
1825         }
1826
1827         mutex_lock(&dev->struct_mutex);
1828
1829         i915_verify_inactive(dev, __FILE__, __LINE__);
1830
1831         if (dev_priv->mm.wedged) {
1832                 DRM_ERROR("Execbuf while wedged\n");
1833                 mutex_unlock(&dev->struct_mutex);
1834                 return -EIO;
1835         }
1836
1837         if (dev_priv->mm.suspended) {
1838                 DRM_ERROR("Execbuf while VT-switched.\n");
1839                 mutex_unlock(&dev->struct_mutex);
1840                 return -EBUSY;
1841         }
1842
1843         /* Zero the gloabl flush/invalidate flags. These
1844          * will be modified as each object is bound to the
1845          * gtt
1846          */
1847         dev->invalidate_domains = 0;
1848         dev->flush_domains = 0;
1849
1850         /* Look up object handles and perform the relocations */
1851         for (i = 0; i < args->buffer_count; i++) {
1852                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
1853                                                        exec_list[i].handle);
1854                 if (object_list[i] == NULL) {
1855                         DRM_ERROR("Invalid object handle %d at index %d\n",
1856                                    exec_list[i].handle, i);
1857                         ret = -EINVAL;
1858                         goto err;
1859                 }
1860
1861                 object_list[i]->pending_read_domains = 0;
1862                 object_list[i]->pending_write_domain = 0;
1863                 ret = i915_gem_object_pin_and_relocate(object_list[i],
1864                                                        file_priv,
1865                                                        &exec_list[i]);
1866                 if (ret) {
1867                         DRM_ERROR("object bind and relocate failed %d\n", ret);
1868                         goto err;
1869                 }
1870                 pinned = i + 1;
1871         }
1872
1873         /* Set the pending read domains for the batch buffer to COMMAND */
1874         batch_obj = object_list[args->buffer_count-1];
1875         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1876         batch_obj->pending_write_domain = 0;
1877
1878         i915_verify_inactive(dev, __FILE__, __LINE__);
1879
1880         for (i = 0; i < args->buffer_count; i++) {
1881                 struct drm_gem_object *obj = object_list[i];
1882                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1883
1884                 if (obj_priv->gtt_space == NULL) {
1885                         /* We evicted the buffer in the process of validating
1886                          * our set of buffers in.  We could try to recover by
1887                          * kicking them everything out and trying again from
1888                          * the start.
1889                          */
1890                         ret = -ENOMEM;
1891                         goto err;
1892                 }
1893
1894                 /* make sure all previous memory operations have passed */
1895                 ret = i915_gem_object_set_domain(obj,
1896                                                  obj->pending_read_domains,
1897                                                  obj->pending_write_domain);
1898                 if (ret)
1899                         goto err;
1900         }
1901
1902         i915_verify_inactive(dev, __FILE__, __LINE__);
1903
1904         /* Flush/invalidate caches and chipset buffer */
1905         flush_domains = i915_gem_dev_set_domain(dev);
1906
1907         i915_verify_inactive(dev, __FILE__, __LINE__);
1908
1909 #if WATCH_COHERENCY
1910         for (i = 0; i < args->buffer_count; i++) {
1911                 i915_gem_object_check_coherency(object_list[i],
1912                                                 exec_list[i].handle);
1913         }
1914 #endif
1915
1916         exec_offset = exec_list[args->buffer_count - 1].offset;
1917
1918 #if WATCH_EXEC
1919         i915_gem_dump_object(object_list[args->buffer_count - 1],
1920                               args->batch_len,
1921                               __func__,
1922                               ~0);
1923 #endif
1924
1925         /* Exec the batchbuffer */
1926         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
1927         if (ret) {
1928                 DRM_ERROR("dispatch failed %d\n", ret);
1929                 goto err;
1930         }
1931
1932         /*
1933          * Ensure that the commands in the batch buffer are
1934          * finished before the interrupt fires
1935          */
1936         flush_domains |= i915_retire_commands(dev);
1937
1938         i915_verify_inactive(dev, __FILE__, __LINE__);
1939
1940         /*
1941          * Get a seqno representing the execution of the current buffer,
1942          * which we can wait on.  We would like to mitigate these interrupts,
1943          * likely by only creating seqnos occasionally (so that we have
1944          * *some* interrupts representing completion of buffers that we can
1945          * wait on when trying to clear up gtt space).
1946          */
1947         seqno = i915_add_request(dev, flush_domains);
1948         BUG_ON(seqno == 0);
1949         i915_file_priv->mm.last_gem_seqno = seqno;
1950         for (i = 0; i < args->buffer_count; i++) {
1951                 struct drm_gem_object *obj = object_list[i];
1952                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1953
1954                 i915_gem_object_move_to_active(obj);
1955                 obj_priv->last_rendering_seqno = seqno;
1956 #if WATCH_LRU
1957                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
1958 #endif
1959         }
1960 #if WATCH_LRU
1961         i915_dump_lru(dev, __func__);
1962 #endif
1963
1964         i915_verify_inactive(dev, __FILE__, __LINE__);
1965
1966         /* Copy the new buffer offsets back to the user's exec list. */
1967         ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1968                            (uintptr_t) args->buffers_ptr,
1969                            exec_list,
1970                            sizeof(*exec_list) * args->buffer_count);
1971         if (ret)
1972                 DRM_ERROR("failed to copy %d exec entries "
1973                           "back to user (%d)\n",
1974                            args->buffer_count, ret);
1975 err:
1976         if (object_list != NULL) {
1977                 for (i = 0; i < pinned; i++)
1978                         i915_gem_object_unpin(object_list[i]);
1979
1980                 for (i = 0; i < args->buffer_count; i++)
1981                         drm_gem_object_unreference(object_list[i]);
1982         }
1983         mutex_unlock(&dev->struct_mutex);
1984
1985 pre_mutex_err:
1986         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
1987                  DRM_MEM_DRIVER);
1988         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
1989                  DRM_MEM_DRIVER);
1990
1991         return ret;
1992 }
1993
1994 int
1995 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
1996 {
1997         struct drm_device *dev = obj->dev;
1998         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1999         int ret;
2000
2001         i915_verify_inactive(dev, __FILE__, __LINE__);
2002         if (obj_priv->gtt_space == NULL) {
2003                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2004                 if (ret != 0) {
2005                         DRM_ERROR("Failure to bind: %d", ret);
2006                         return ret;
2007                 }
2008         }
2009         obj_priv->pin_count++;
2010
2011         /* If the object is not active and not pending a flush,
2012          * remove it from the inactive list
2013          */
2014         if (obj_priv->pin_count == 1) {
2015                 atomic_inc(&dev->pin_count);
2016                 atomic_add(obj->size, &dev->pin_memory);
2017                 if (!obj_priv->active && (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) == 0 &&
2018                     !list_empty(&obj_priv->list))
2019                         list_del_init(&obj_priv->list);
2020         }
2021         i915_verify_inactive(dev, __FILE__, __LINE__);
2022
2023         return 0;
2024 }
2025
2026 void
2027 i915_gem_object_unpin(struct drm_gem_object *obj)
2028 {
2029         struct drm_device *dev = obj->dev;
2030         drm_i915_private_t *dev_priv = dev->dev_private;
2031         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2032
2033         i915_verify_inactive(dev, __FILE__, __LINE__);
2034         obj_priv->pin_count--;
2035         BUG_ON(obj_priv->pin_count < 0);
2036         BUG_ON(obj_priv->gtt_space == NULL);
2037
2038         /* If the object is no longer pinned, and is
2039          * neither active nor being flushed, then stick it on
2040          * the inactive list
2041          */
2042         if (obj_priv->pin_count == 0) {
2043                 if (!obj_priv->active && (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) == 0)
2044                         list_move_tail(&obj_priv->list,
2045                                        &dev_priv->mm.inactive_list);
2046                 atomic_dec(&dev->pin_count);
2047                 atomic_sub(obj->size, &dev->pin_memory);
2048         }
2049         i915_verify_inactive(dev, __FILE__, __LINE__);
2050 }
2051
2052 int
2053 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2054                    struct drm_file *file_priv)
2055 {
2056         struct drm_i915_gem_pin *args = data;
2057         struct drm_gem_object *obj;
2058         struct drm_i915_gem_object *obj_priv;
2059         int ret;
2060
2061         mutex_lock(&dev->struct_mutex);
2062
2063         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2064         if (obj == NULL) {
2065                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2066                           args->handle);
2067                 mutex_unlock(&dev->struct_mutex);
2068                 return -EINVAL;
2069         }
2070         obj_priv = obj->driver_private;
2071
2072         ret = i915_gem_object_pin(obj, args->alignment);
2073         if (ret != 0) {
2074                 drm_gem_object_unreference(obj);
2075                 mutex_unlock(&dev->struct_mutex);
2076                 return ret;
2077         }
2078
2079         /** XXX - flush the CPU caches for pinned objects
2080          * as the X server doesn't manage domains yet
2081          */
2082         if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
2083                 i915_gem_clflush_object(obj);
2084                 drm_agp_chipset_flush(dev);
2085                 obj->write_domain = 0;
2086         }
2087         args->offset = obj_priv->gtt_offset;
2088         drm_gem_object_unreference(obj);
2089         mutex_unlock(&dev->struct_mutex);
2090
2091         return 0;
2092 }
2093
2094 int
2095 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2096                      struct drm_file *file_priv)
2097 {
2098         struct drm_i915_gem_pin *args = data;
2099         struct drm_gem_object *obj;
2100
2101         mutex_lock(&dev->struct_mutex);
2102
2103         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2104         if (obj == NULL) {
2105                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2106                           args->handle);
2107                 mutex_unlock(&dev->struct_mutex);
2108                 return -EINVAL;
2109         }
2110
2111         i915_gem_object_unpin(obj);
2112
2113         drm_gem_object_unreference(obj);
2114         mutex_unlock(&dev->struct_mutex);
2115         return 0;
2116 }
2117
2118 int
2119 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2120                     struct drm_file *file_priv)
2121 {
2122         struct drm_i915_gem_busy *args = data;
2123         struct drm_gem_object *obj;
2124         struct drm_i915_gem_object *obj_priv;
2125
2126         mutex_lock(&dev->struct_mutex);
2127         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2128         if (obj == NULL) {
2129                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2130                           args->handle);
2131                 mutex_unlock(&dev->struct_mutex);
2132                 return -EINVAL;
2133         }
2134
2135         obj_priv = obj->driver_private;
2136         args->busy = obj_priv->active;
2137
2138         drm_gem_object_unreference(obj);
2139         mutex_unlock(&dev->struct_mutex);
2140         return 0;
2141 }
2142
2143 int
2144 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2145                         struct drm_file *file_priv)
2146 {
2147     return i915_gem_ring_throttle(dev, file_priv);
2148 }
2149
2150 int i915_gem_init_object(struct drm_gem_object *obj)
2151 {
2152         struct drm_i915_gem_object *obj_priv;
2153
2154         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2155         if (obj_priv == NULL)
2156                 return -ENOMEM;
2157
2158         /*
2159          * We've just allocated pages from the kernel,
2160          * so they've just been written by the CPU with
2161          * zeros. They'll need to be clflushed before we
2162          * use them with the GPU.
2163          */
2164         obj->write_domain = I915_GEM_DOMAIN_CPU;
2165         obj->read_domains = I915_GEM_DOMAIN_CPU;
2166
2167         obj->driver_private = obj_priv;
2168         obj_priv->obj = obj;
2169         INIT_LIST_HEAD(&obj_priv->list);
2170         return 0;
2171 }
2172
2173 void i915_gem_free_object(struct drm_gem_object *obj)
2174 {
2175         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2176
2177         while (obj_priv->pin_count > 0)
2178                 i915_gem_object_unpin(obj);
2179
2180         i915_gem_object_unbind(obj);
2181
2182         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2183 }
2184
2185 int
2186 i915_gem_set_domain(struct drm_gem_object *obj,
2187                     struct drm_file *file_priv,
2188                     uint32_t read_domains,
2189                     uint32_t write_domain)
2190 {
2191         struct drm_device *dev = obj->dev;
2192         int ret;
2193         uint32_t flush_domains;
2194
2195         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
2196
2197         ret = i915_gem_object_set_domain(obj, read_domains, write_domain);
2198         if (ret)
2199                 return ret;
2200         flush_domains = i915_gem_dev_set_domain(obj->dev);
2201
2202         if (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))
2203                 (void) i915_add_request(dev, flush_domains);
2204
2205         return 0;
2206 }
2207
2208 /** Unbinds all objects that are on the given buffer list. */
2209 static int
2210 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2211 {
2212         struct drm_gem_object *obj;
2213         struct drm_i915_gem_object *obj_priv;
2214         int ret;
2215
2216         while (!list_empty(head)) {
2217                 obj_priv = list_first_entry(head,
2218                                             struct drm_i915_gem_object,
2219                                             list);
2220                 obj = obj_priv->obj;
2221
2222                 if (obj_priv->pin_count != 0) {
2223                         DRM_ERROR("Pinned object in unbind list\n");
2224                         mutex_unlock(&dev->struct_mutex);
2225                         return -EINVAL;
2226                 }
2227
2228                 ret = i915_gem_object_unbind(obj);
2229                 if (ret != 0) {
2230                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2231                                   ret);
2232                         mutex_unlock(&dev->struct_mutex);
2233                         return ret;
2234                 }
2235         }
2236
2237
2238         return 0;
2239 }
2240
2241 static int
2242 i915_gem_idle(struct drm_device *dev)
2243 {
2244         drm_i915_private_t *dev_priv = dev->dev_private;
2245         uint32_t seqno, cur_seqno, last_seqno;
2246         int stuck;
2247
2248         if (dev_priv->mm.suspended)
2249                 return 0;
2250
2251         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
2252          * We need to replace this with a semaphore, or something.
2253          */
2254         dev_priv->mm.suspended = 1;
2255
2256         i915_kernel_lost_context(dev);
2257
2258         /* Flush the GPU along with all non-CPU write domains
2259          */
2260         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2261                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2262         seqno = i915_add_request(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2263
2264         if (seqno == 0) {
2265                 mutex_unlock(&dev->struct_mutex);
2266                 return -ENOMEM;
2267         }
2268
2269         dev_priv->mm.waiting_gem_seqno = seqno;
2270         last_seqno = 0;
2271         stuck = 0;
2272         for (;;) {
2273                 cur_seqno = i915_get_gem_seqno(dev);
2274                 if (i915_seqno_passed(cur_seqno, seqno))
2275                         break;
2276                 if (last_seqno == cur_seqno) {
2277                         if (stuck++ > 100) {
2278                                 DRM_ERROR("hardware wedged\n");
2279                                 dev_priv->mm.wedged = 1;
2280                                 DRM_WAKEUP(&dev_priv->irq_queue);
2281                                 break;
2282                         }
2283                 }
2284                 msleep(10);
2285                 last_seqno = cur_seqno;
2286         }
2287         dev_priv->mm.waiting_gem_seqno = 0;
2288
2289         i915_gem_retire_requests(dev);
2290
2291         /* Active and flushing should now be empty as we've
2292          * waited for a sequence higher than any pending execbuffer
2293          */
2294         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2295         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2296
2297         /* Request should now be empty as we've also waited
2298          * for the last request in the list
2299          */
2300         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2301
2302         /* Move all buffers out of the GTT. */
2303         i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2304
2305         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2306         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2307         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2308         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2309         return 0;
2310 }
2311
2312 static int
2313 i915_gem_init_ringbuffer(struct drm_device *dev)
2314 {
2315         drm_i915_private_t *dev_priv = dev->dev_private;
2316         struct drm_gem_object *obj;
2317         struct drm_i915_gem_object *obj_priv;
2318         int ret;
2319
2320         obj = drm_gem_object_alloc(dev, 128 * 1024);
2321         if (obj == NULL) {
2322                 DRM_ERROR("Failed to allocate ringbuffer\n");
2323                 return -ENOMEM;
2324         }
2325         obj_priv = obj->driver_private;
2326
2327         ret = i915_gem_object_pin(obj, 4096);
2328         if (ret != 0) {
2329                 drm_gem_object_unreference(obj);
2330                 return ret;
2331         }
2332
2333         /* Set up the kernel mapping for the ring. */
2334         dev_priv->ring.Size = obj->size;
2335         dev_priv->ring.tail_mask = obj->size - 1;
2336
2337         dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset;
2338         dev_priv->ring.map.size = obj->size;
2339         dev_priv->ring.map.type = 0;
2340         dev_priv->ring.map.flags = 0;
2341         dev_priv->ring.map.mtrr = 0;
2342
2343         drm_core_ioremap(&dev_priv->ring.map, dev);
2344         if (dev_priv->ring.map.handle == NULL) {
2345                 DRM_ERROR("Failed to map ringbuffer.\n");
2346                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2347                 drm_gem_object_unreference(obj);
2348                 return -EINVAL;
2349         }
2350         dev_priv->ring.ring_obj = obj;
2351         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
2352
2353         /* Stop the ring if it's running. */
2354         I915_WRITE(LP_RING + RING_LEN, 0);
2355         I915_WRITE(LP_RING + RING_HEAD, 0);
2356         I915_WRITE(LP_RING + RING_TAIL, 0);
2357         I915_WRITE(LP_RING + RING_START, 0);
2358
2359         /* Initialize the ring. */
2360         I915_WRITE(LP_RING + RING_START, obj_priv->gtt_offset);
2361         I915_WRITE(LP_RING + RING_LEN,
2362                    ((obj->size - 4096) & RING_NR_PAGES) |
2363                    RING_NO_REPORT |
2364                    RING_VALID);
2365
2366         /* Update our cache of the ring state */
2367         i915_kernel_lost_context(dev);
2368
2369         return 0;
2370 }
2371
2372 static void
2373 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2374 {
2375         drm_i915_private_t *dev_priv = dev->dev_private;
2376
2377         if (dev_priv->ring.ring_obj == NULL)
2378                 return;
2379
2380         drm_core_ioremapfree(&dev_priv->ring.map, dev);
2381
2382         i915_gem_object_unpin(dev_priv->ring.ring_obj);
2383         drm_gem_object_unreference(dev_priv->ring.ring_obj);
2384
2385         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2386 }
2387
2388 int
2389 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2390                        struct drm_file *file_priv)
2391 {
2392         drm_i915_private_t *dev_priv = dev->dev_private;
2393         int ret;
2394
2395         if (dev_priv->mm.wedged) {
2396                 DRM_ERROR("Renabling wedged hardware, good luck\n");
2397                 dev_priv->mm.wedged = 0;
2398         }
2399
2400         ret = i915_gem_init_ringbuffer(dev);
2401         if (ret != 0)
2402                 return ret;
2403
2404         mutex_lock(&dev->struct_mutex);
2405         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2406         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2407         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2408         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2409         dev_priv->mm.suspended = 0;
2410         mutex_unlock(&dev->struct_mutex);
2411         return 0;
2412 }
2413
2414 int
2415 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2416                        struct drm_file *file_priv)
2417 {
2418         int ret;
2419
2420         mutex_lock(&dev->struct_mutex);
2421         ret = i915_gem_idle(dev);
2422         if (ret == 0)
2423                 i915_gem_cleanup_ringbuffer(dev);
2424         mutex_unlock(&dev->struct_mutex);
2425
2426         return 0;
2427 }
2428
2429 static int i915_gem_active_info(char *buf, char **start, off_t offset,
2430                                 int request, int *eof, void *data)
2431 {
2432         struct drm_minor *minor = (struct drm_minor *) data;
2433         struct drm_device *dev = minor->dev;
2434         drm_i915_private_t *dev_priv = dev->dev_private;
2435         struct drm_i915_gem_object *obj_priv;
2436         int len = 0;
2437
2438         if (offset > DRM_PROC_LIMIT) {
2439                 *eof = 1;
2440                 return 0;
2441         }
2442
2443         *start = &buf[offset];
2444         *eof = 0;
2445         DRM_PROC_PRINT("Active:\n");
2446         list_for_each_entry(obj_priv, &dev_priv->mm.active_list,
2447                             list)
2448         {
2449                 struct drm_gem_object *obj = obj_priv->obj;
2450                 if (obj->name) {
2451                         DRM_PROC_PRINT("    %p(%d): %08x %08x %d\n",
2452                                        obj, obj->name,
2453                                        obj->read_domains, obj->write_domain,
2454                                        obj_priv->last_rendering_seqno);
2455                 } else {
2456                         DRM_PROC_PRINT("       %p: %08x %08x %d\n",
2457                                        obj,
2458                                        obj->read_domains, obj->write_domain,
2459                                        obj_priv->last_rendering_seqno);
2460                 }
2461         }
2462         if (len > request + offset)
2463                 return request;
2464         *eof = 1;
2465         return len - offset;
2466 }
2467
2468 static int i915_gem_flushing_info(char *buf, char **start, off_t offset,
2469                                   int request, int *eof, void *data)
2470 {
2471         struct drm_minor *minor = (struct drm_minor *) data;
2472         struct drm_device *dev = minor->dev;
2473         drm_i915_private_t *dev_priv = dev->dev_private;
2474         struct drm_i915_gem_object *obj_priv;
2475         int len = 0;
2476
2477         if (offset > DRM_PROC_LIMIT) {
2478                 *eof = 1;
2479                 return 0;
2480         }
2481
2482         *start = &buf[offset];
2483         *eof = 0;
2484         DRM_PROC_PRINT("Flushing:\n");
2485         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list,
2486                             list)
2487         {
2488                 struct drm_gem_object *obj = obj_priv->obj;
2489                 if (obj->name) {
2490                         DRM_PROC_PRINT("    %p(%d): %08x %08x %d\n",
2491                                        obj, obj->name,
2492                                        obj->read_domains, obj->write_domain,
2493                                        obj_priv->last_rendering_seqno);
2494                 } else {
2495                         DRM_PROC_PRINT("       %p: %08x %08x %d\n", obj,
2496                                        obj->read_domains, obj->write_domain,
2497                                        obj_priv->last_rendering_seqno);
2498                 }
2499         }
2500         if (len > request + offset)
2501                 return request;
2502         *eof = 1;
2503         return len - offset;
2504 }
2505
2506 static int i915_gem_inactive_info(char *buf, char **start, off_t offset,
2507                                   int request, int *eof, void *data)
2508 {
2509         struct drm_minor *minor = (struct drm_minor *) data;
2510         struct drm_device *dev = minor->dev;
2511         drm_i915_private_t *dev_priv = dev->dev_private;
2512         struct drm_i915_gem_object *obj_priv;
2513         int len = 0;
2514
2515         if (offset > DRM_PROC_LIMIT) {
2516                 *eof = 1;
2517                 return 0;
2518         }
2519
2520         *start = &buf[offset];
2521         *eof = 0;
2522         DRM_PROC_PRINT("Inactive:\n");
2523         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list,
2524                             list)
2525         {
2526                 struct drm_gem_object *obj = obj_priv->obj;
2527                 if (obj->name) {
2528                         DRM_PROC_PRINT("    %p(%d): %08x %08x %d\n",
2529                                        obj, obj->name,
2530                                        obj->read_domains, obj->write_domain,
2531                                        obj_priv->last_rendering_seqno);
2532                 } else {
2533                         DRM_PROC_PRINT("       %p: %08x %08x %d\n", obj,
2534                                        obj->read_domains, obj->write_domain,
2535                                        obj_priv->last_rendering_seqno);
2536                 }
2537         }
2538         if (len > request + offset)
2539                 return request;
2540         *eof = 1;
2541         return len - offset;
2542 }
2543
2544 static int i915_gem_request_info(char *buf, char **start, off_t offset,
2545                                  int request, int *eof, void *data)
2546 {
2547         struct drm_minor *minor = (struct drm_minor *) data;
2548         struct drm_device *dev = minor->dev;
2549         drm_i915_private_t *dev_priv = dev->dev_private;
2550         struct drm_i915_gem_request *gem_request;
2551         int len = 0;
2552
2553         if (offset > DRM_PROC_LIMIT) {
2554                 *eof = 1;
2555                 return 0;
2556         }
2557
2558         *start = &buf[offset];
2559         *eof = 0;
2560         DRM_PROC_PRINT("Request:\n");
2561         list_for_each_entry(gem_request, &dev_priv->mm.request_list,
2562                             list)
2563         {
2564                 DRM_PROC_PRINT ("    %d @ %d %08x\n",
2565                                 gem_request->seqno,
2566                                 (int) (jiffies - gem_request->emitted_jiffies),
2567                                 gem_request->flush_domains);
2568         }
2569         if (len > request + offset)
2570                 return request;
2571         *eof = 1;
2572         return len - offset;
2573 }
2574
2575 static int i915_gem_seqno_info(char *buf, char **start, off_t offset,
2576                                int request, int *eof, void *data)
2577 {
2578         struct drm_minor *minor = (struct drm_minor *) data;
2579         struct drm_device *dev = minor->dev;
2580         drm_i915_private_t *dev_priv = dev->dev_private;
2581         int len = 0;
2582
2583         if (offset > DRM_PROC_LIMIT) {
2584                 *eof = 1;
2585                 return 0;
2586         }
2587
2588         *start = &buf[offset];
2589         *eof = 0;
2590         DRM_PROC_PRINT("Current sequence: %d\n", i915_get_gem_seqno(dev));
2591         DRM_PROC_PRINT("Waiter sequence:  %d\n", dev_priv->mm.waiting_gem_seqno);
2592         DRM_PROC_PRINT("IRQ sequence:     %d\n", dev_priv->mm.irq_gem_seqno);
2593         if (len > request + offset)
2594                 return request;
2595         *eof = 1;
2596         return len - offset;
2597 }
2598
2599
2600 static int i915_interrupt_info(char *buf, char **start, off_t offset,
2601                                int request, int *eof, void *data)
2602 {
2603         struct drm_minor *minor = (struct drm_minor *) data;
2604         struct drm_device *dev = minor->dev;
2605         drm_i915_private_t *dev_priv = dev->dev_private;
2606         int len = 0;
2607
2608         if (offset > DRM_PROC_LIMIT) {
2609                 *eof = 1;
2610                 return 0;
2611         }
2612
2613         *start = &buf[offset];
2614         *eof = 0;
2615         DRM_PROC_PRINT("Interrupt enable:    %08x\n",
2616                        I915_READ(I915REG_INT_ENABLE_R));
2617         DRM_PROC_PRINT("Interrupt identity:  %08x\n",
2618                        I915_READ(I915REG_INT_IDENTITY_R));
2619         DRM_PROC_PRINT("Interrupt mask:      %08x\n",
2620                        I915_READ(I915REG_INT_MASK_R));
2621         DRM_PROC_PRINT("Pipe A stat:         %08x\n",
2622                        I915_READ(I915REG_PIPEASTAT));
2623         DRM_PROC_PRINT("Pipe B stat:         %08x\n",
2624                        I915_READ(I915REG_PIPEBSTAT));
2625         DRM_PROC_PRINT("Interrupts received: %d\n",
2626                        atomic_read(&dev_priv->irq_received));
2627         DRM_PROC_PRINT("Current sequence:    %d\n",
2628                        i915_get_gem_seqno(dev));
2629         DRM_PROC_PRINT("Waiter sequence:     %d\n",
2630                        dev_priv->mm.waiting_gem_seqno);
2631         DRM_PROC_PRINT("IRQ sequence:        %d\n",
2632                        dev_priv->mm.irq_gem_seqno);
2633         if (len > request + offset)
2634                 return request;
2635         *eof = 1;
2636         return len - offset;
2637 }
2638
2639 static struct drm_proc_list {
2640         const char *name;       /**< file name */
2641         int (*f) (char *, char **, off_t, int, int *, void *);          /**< proc callback*/
2642 } i915_gem_proc_list[] = {
2643         {"i915_gem_active", i915_gem_active_info},
2644         {"i915_gem_flushing", i915_gem_flushing_info},
2645         {"i915_gem_inactive", i915_gem_inactive_info},
2646         {"i915_gem_request", i915_gem_request_info},
2647         {"i915_gem_seqno", i915_gem_seqno_info},
2648         {"i915_gem_interrupt", i915_interrupt_info},
2649 };
2650
2651 #define I915_GEM_PROC_ENTRIES ARRAY_SIZE(i915_gem_proc_list)
2652
2653 int i915_gem_proc_init(struct drm_minor *minor)
2654 {
2655         struct proc_dir_entry *ent;
2656         int i, j;
2657
2658         for (i = 0; i < I915_GEM_PROC_ENTRIES; i++) {
2659                 ent = create_proc_entry(i915_gem_proc_list[i].name,
2660                                         S_IFREG | S_IRUGO, minor->dev_root);
2661                 if (!ent) {
2662                         DRM_ERROR("Cannot create /proc/dri/.../%s\n",
2663                                   i915_gem_proc_list[i].name);
2664                         for (j = 0; j < i; j++)
2665                                 remove_proc_entry(i915_gem_proc_list[i].name,
2666                                                   minor->dev_root);
2667                         return -1;
2668                 }
2669                 ent->read_proc = i915_gem_proc_list[i].f;
2670                 ent->data = minor;
2671         }
2672         return 0;
2673 }
2674
2675 void i915_gem_proc_cleanup(struct drm_minor *minor)
2676 {
2677         int i;
2678
2679         if (!minor->dev_root)
2680                 return;
2681
2682         for (i = 0; i < I915_GEM_PROC_ENTRIES; i++)
2683                 remove_proc_entry(i915_gem_proc_list[i].name, minor->dev_root);
2684 }
2685
2686 void
2687 i915_gem_lastclose(struct drm_device *dev)
2688 {
2689         int ret;
2690         drm_i915_private_t *dev_priv = dev->dev_private;
2691
2692         mutex_lock(&dev->struct_mutex);
2693
2694         if (dev_priv->ring.ring_obj != NULL) {
2695                 ret = i915_gem_idle(dev);
2696                 if (ret)
2697                         DRM_ERROR("failed to idle hardware: %d\n", ret);
2698
2699                 i915_gem_cleanup_ringbuffer(dev);
2700         }
2701
2702         mutex_unlock(&dev->struct_mutex);
2703 }