linux-core/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32
  33 #define WATCH_COHERENCY 0
  34 #define WATCH_BUF       0
  35 #define WATCH_EXEC      0
  36 #define WATCH_LRU       0
  37 #define WATCH_RELOC     0
  38 #define WATCH_INACTIVE  0
  39
  40 static int
  41 i915_gem_object_set_domain(struct drm_gem_object *obj,
  42                             uint32_t read_domains,
  43                             uint32_t write_domain);
  44 int
  45 i915_gem_set_domain(struct drm_gem_object *obj,
  46                     struct drm_file *file_priv,
  47                     uint32_t read_domains,
  48                     uint32_t write_domain);
  49
  50 static void
  51 i915_gem_clflush_object(struct drm_gem_object *obj);
  52
  53 int
  54 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  55                     struct drm_file *file_priv)
  56 {
  57         drm_i915_private_t *dev_priv = dev->dev_private;
  58         struct drm_i915_gem_init *args = data;
  59
  60         mutex_lock(&dev->struct_mutex);
  61
  62         if (args->gtt_start >= args->gtt_end ||
  63             (args->gtt_start & (PAGE_SIZE - 1)) != 0 ||
  64             (args->gtt_end & (PAGE_SIZE - 1)) != 0) {
  65                 mutex_unlock(&dev->struct_mutex);
  66                 return -EINVAL;
  67         }
  68
  69         drm_memrange_init(&dev_priv->mm.gtt_space, args->gtt_start,
  70             args->gtt_end - args->gtt_start);
  71
  72         dev->gtt_total = (uint32_t) (args->gtt_end - args->gtt_start);
  73
  74         mutex_unlock(&dev->struct_mutex);
  75
  76         return 0;
  77 }
  78
  79
  80 /**
  81  * Creates a new mm object and returns a handle to it.
  82  */
  83 int
  84 i915_gem_create_ioctl(struct drm_device *dev, void *data,
  85                       struct drm_file *file_priv)
  86 {
  87         struct drm_i915_gem_create *args = data;
  88         struct drm_gem_object *obj;
  89         int handle, ret;
  90
  91         args->size = roundup(args->size, PAGE_SIZE);
  92
  93         /* Allocate the new object */
  94         obj = drm_gem_object_alloc(dev, args->size);
  95         if (obj == NULL)
  96                 return -ENOMEM;
  97
  98         ret = drm_gem_handle_create(file_priv, obj, &handle);
  99         mutex_lock(&dev->struct_mutex);
 100         drm_gem_object_handle_unreference(obj);
 101         mutex_unlock(&dev->struct_mutex);
 102
 103         if (ret)
 104                 return ret;
 105
 106         args->handle = handle;
 107
 108         return 0;
 109 }
 110
 111 /**
 112  * Reads data from the object referenced by handle.
 113  *
 114  * On error, the contents of *data are undefined.
 115  */
 116 int
 117 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 118                      struct drm_file *file_priv)
 119 {
 120         struct drm_i915_gem_pread *args = data;
 121         struct drm_gem_object *obj;
 122         ssize_t read;
 123         loff_t offset;
 124         int ret;
 125
 126         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 127         if (obj == NULL)
 128                 return -EINVAL;
 129
 130         mutex_lock(&dev->struct_mutex);
 131         ret = i915_gem_set_domain(obj, file_priv,
 132                                   I915_GEM_DOMAIN_CPU, 0);
 133         if (ret) {
 134                 drm_gem_object_unreference(obj);
 135                 mutex_unlock(&dev->struct_mutex);
 136                 return ret;
 137         }
 138         offset = args->offset;
 139
 140         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
 141                         args->size, &offset);
 142         if (read != args->size) {
 143                 drm_gem_object_unreference(obj);
 144                 mutex_unlock(&dev->struct_mutex);
 145                 if (read < 0)
 146                         return read;
 147                 else
 148                         return -EINVAL;
 149         }
 150
 151         drm_gem_object_unreference(obj);
 152         mutex_unlock(&dev->struct_mutex);
 153
 154         return 0;
 155 }
 156
 157 /**
 158  * Writes data to the object referenced by handle.
 159  *
 160  * On error, the contents of the buffer that were to be modified are undefined.
 161  */
 162 int
 163 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 164                       struct drm_file *file_priv)
 165 {
 166         struct drm_i915_gem_pwrite *args = data;
 167         struct drm_gem_object *obj;
 168         ssize_t written;
 169         loff_t offset;
 170         int ret;
 171
 172         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 173         if (obj == NULL)
 174                 return -EINVAL;
 175
 176         mutex_lock(&dev->struct_mutex);
 177         ret = i915_gem_set_domain(obj, file_priv,
 178                                   I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
 179         if (ret) {
 180                 drm_gem_object_unreference(obj);
 181                 mutex_unlock(&dev->struct_mutex);
 182                 return ret;
 183         }
 184         offset = args->offset;
 185
 186         written = vfs_write(obj->filp,
 187                             (char __user *)(uintptr_t) args->data_ptr,
 188                             args->size, &offset);
 189
 190         if (written != args->size) {
 191                 drm_gem_object_unreference(obj);
 192                 mutex_unlock(&dev->struct_mutex);
 193                 if (written < 0)
 194                         return written;
 195                 else
 196                         return -EINVAL;
 197         }
 198
 199         drm_gem_object_unreference(obj);
 200         mutex_unlock(&dev->struct_mutex);
 201
 202         return 0;
 203 }
 204
 205 /**
 206  * Called when user space prepares to use an object
 207  */
 208 int
 209 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 210                           struct drm_file *file_priv)
 211 {
 212         struct drm_i915_gem_set_domain *args = data;
 213         struct drm_gem_object *obj;
 214         int ret;
 215
 216         if (!(dev->driver->driver_features & DRIVER_GEM))
 217                 return -ENODEV;
 218
 219         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 220         if (obj == NULL)
 221                 return -EINVAL;
 222
 223         mutex_lock(&dev->struct_mutex);
 224         ret = i915_gem_set_domain(obj, file_priv,
 225                                   args->read_domains, args->write_domain);
 226         drm_gem_object_unreference(obj);
 227         mutex_unlock(&dev->struct_mutex);
 228         return ret;
 229 }
 230
 231 /**
 232  * Called when user space has done writes to this buffer
 233  */
 234 int
 235 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 236                       struct drm_file *file_priv)
 237 {
 238         struct drm_i915_gem_sw_finish *args = data;
 239         struct drm_gem_object *obj;
 240         struct drm_i915_gem_object *obj_priv;
 241         int ret = 0;
 242
 243         if (!(dev->driver->driver_features & DRIVER_GEM))
 244                 return -ENODEV;
 245
 246         mutex_lock(&dev->struct_mutex);
 247         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 248         if (obj == NULL) {
 249                 mutex_unlock(&dev->struct_mutex);
 250                 return -EINVAL;
 251         }
 252
 253 #if WATCH_BUF
 254         DRM_INFO("%s: sw_finish %d (%p)\n",
 255                  __func__, args->handle, obj);
 256 #endif
 257         obj_priv = obj->driver_private;
 258
 259         /** Pinned buffers may be scanout, so flush the cache
 260          */
 261         if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) {
 262                 i915_gem_clflush_object(obj);
 263                 drm_agp_chipset_flush(dev);
 264         }
 265         drm_gem_object_unreference(obj);
 266         mutex_unlock(&dev->struct_mutex);
 267         return ret;
 268 }
 269
 270 /**
 271  * Maps the contents of an object, returning the address it is mapped
 272  * into.
 273  *
 274  * While the mapping holds a reference on the contents of the object, it doesn't
 275  * imply a ref on the object itself.
 276  */
 277 int
 278 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 279                    struct drm_file *file_priv)
 280 {
 281         struct drm_i915_gem_mmap *args = data;
 282         struct drm_gem_object *obj;
 283         loff_t offset;
 284         unsigned long addr;
 285
 286         if (!(dev->driver->driver_features & DRIVER_GEM))
 287                 return -ENODEV;
 288
 289         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 290         if (obj == NULL)
 291                 return -EINVAL;
 292
 293         offset = args->offset;
 294
 295         down_write(&current->mm->mmap_sem);
 296         addr = do_mmap(obj->filp, 0, args->size,
 297                        PROT_READ | PROT_WRITE, MAP_SHARED,
 298                        args->offset);
 299         up_write(&current->mm->mmap_sem);
 300         mutex_lock(&dev->struct_mutex);
 301         drm_gem_object_unreference(obj);
 302         mutex_unlock(&dev->struct_mutex);
 303         if (IS_ERR((void *)addr))
 304                 return addr;
 305
 306         args->addr_ptr = (uint64_t) addr;
 307
 308         return 0;
 309 }
 310
 311 static void
 312 i915_gem_object_free_page_list(struct drm_gem_object *obj)
 313 {
 314         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 315         int page_count = obj->size / PAGE_SIZE;
 316         int i;
 317
 318         if (obj_priv->page_list == NULL)
 319                 return;
 320
 321
 322         for (i = 0; i < page_count; i++)
 323                 if (obj_priv->page_list[i] != NULL) {
 324                         if (obj_priv->dirty)
 325                                 set_page_dirty(obj_priv->page_list[i]);
 326                         mark_page_accessed(obj_priv->page_list[i]);
 327                         page_cache_release(obj_priv->page_list[i]);
 328                 }
 329         obj_priv->dirty = 0;
 330
 331         drm_free(obj_priv->page_list,
 332                  page_count * sizeof(struct page *),
 333                  DRM_MEM_DRIVER);
 334         obj_priv->page_list = NULL;
 335 }
 336
 337 static void
 338 i915_gem_object_move_to_active(struct drm_gem_object *obj)
 339 {
 340         struct drm_device *dev = obj->dev;
 341         drm_i915_private_t *dev_priv = dev->dev_private;
 342         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 343
 344         /* Add a reference if we're newly entering the active list. */
 345         if (!obj_priv->active) {
 346                 drm_gem_object_reference(obj);
 347                 obj_priv->active = 1;
 348         }
 349         /* Move from whatever list we were on to the tail of execution. */
 350         list_move_tail(&obj_priv->list,
 351                        &dev_priv->mm.active_list);
 352 }
 353
 354 #if WATCH_INACTIVE
 355 static void
 356 i915_verify_inactive(struct drm_device *dev, char *file, int line)
 357 {
 358         drm_i915_private_t *dev_priv = dev->dev_private;
 359         struct drm_gem_object *obj;
 360         struct drm_i915_gem_object *obj_priv;
 361
 362         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 363                 obj = obj_priv->obj;
 364                 if (obj_priv->pin_count || obj_priv->active || (obj->write_domain & ~I915_GEM_DOMAIN_CPU))
 365                         DRM_ERROR("inactive %p (p %d a %d w %x)  %s:%d\n",
 366                                   obj,
 367                                   obj_priv->pin_count, obj_priv->active, obj->write_domain, file, line);
 368         }
 369 }
 370 #else
 371 #define i915_verify_inactive(dev,file,line)
 372 #endif
 373
 374 static void
 375 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
 376 {
 377         struct drm_device *dev = obj->dev;
 378         drm_i915_private_t *dev_priv = dev->dev_private;
 379         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 380
 381         i915_verify_inactive(dev, __FILE__, __LINE__);
 382         if (obj_priv->pin_count != 0)
 383                 list_del_init(&obj_priv->list);
 384         else
 385                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
 386
 387         if (obj_priv->active) {
 388                 obj_priv->active = 0;
 389                 drm_gem_object_unreference(obj);
 390         }
 391         i915_verify_inactive(dev, __FILE__, __LINE__);
 392 }
 393
 394 /**
 395  * Creates a new sequence number, emitting a write of it to the status page
 396  * plus an interrupt, which will trigger i915_user_interrupt_handler.
 397  *
 398  * Must be called with struct_lock held.
 399  *
 400  * Returned sequence numbers are nonzero on success.
 401  */
 402 static uint32_t
 403 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
 404 {
 405         drm_i915_private_t *dev_priv = dev->dev_private;
 406         struct drm_i915_gem_request *request;
 407         uint32_t seqno;
 408         int was_empty;
 409         RING_LOCALS;
 410
 411         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
 412         if (request == NULL)
 413                 return 0;
 414
 415         /* Grab the seqno we're going to make this request be, and bump the
 416          * next (skipping 0 so it can be the reserved no-seqno value).
 417          */
 418         seqno = dev_priv->mm.next_gem_seqno;
 419         dev_priv->mm.next_gem_seqno++;
 420         if (dev_priv->mm.next_gem_seqno == 0)
 421                 dev_priv->mm.next_gem_seqno++;
 422
 423         BEGIN_LP_RING(4);
 424         OUT_RING(CMD_STORE_DWORD_IDX);
 425         OUT_RING(I915_GEM_HWS_INDEX << STORE_DWORD_INDEX_SHIFT);
 426         OUT_RING(seqno);
 427
 428         OUT_RING(GFX_OP_USER_INTERRUPT);
 429         ADVANCE_LP_RING();
 430
 431         DRM_DEBUG("%d\n", seqno);
 432
 433         request->seqno = seqno;
 434         request->emitted_jiffies = jiffies;
 435         request->flush_domains = flush_domains;
 436         was_empty = list_empty(&dev_priv->mm.request_list);
 437         list_add_tail(&request->list, &dev_priv->mm.request_list);
 438
 439         if (was_empty)
 440                 schedule_delayed_work (&dev_priv->mm.retire_work, HZ);
 441         return seqno;
 442 }
 443
 444 /**
 445  * Command execution barrier
 446  *
 447  * Ensures that all commands in the ring are finished
 448  * before signalling the CPU
 449  */
 450
 451 uint32_t
 452 i915_retire_commands(struct drm_device *dev)
 453 {
 454         drm_i915_private_t *dev_priv = dev->dev_private;
 455         uint32_t cmd = CMD_MI_FLUSH | MI_NO_WRITE_FLUSH;
 456         uint32_t flush_domains = 0;
 457         RING_LOCALS;
 458
 459         /* The sampler always gets flushed on i965 (sigh) */
 460         if (IS_I965G(dev))
 461                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
 462         BEGIN_LP_RING(2);
 463         OUT_RING(cmd);
 464         OUT_RING(0); /* noop */
 465         ADVANCE_LP_RING();
 466         return flush_domains;
 467 }
 468
 469 /**
 470  * Moves buffers associated only with the given active seqno from the active
 471  * to inactive list, potentially freeing them.
 472  */
 473 static void
 474 i915_gem_retire_request(struct drm_device *dev,
 475                         struct drm_i915_gem_request *request)
 476 {
 477         drm_i915_private_t *dev_priv = dev->dev_private;
 478
 479         if (request->flush_domains != 0) {
 480                 struct drm_i915_gem_object *obj_priv, *next;
 481
 482                 /* First clear any buffers that were only waiting for a flush
 483                  * matching the one just retired.
 484                  */
 485
 486                 list_for_each_entry_safe(obj_priv, next,
 487                                          &dev_priv->mm.flushing_list, list) {
 488                         struct drm_gem_object *obj = obj_priv->obj;
 489
 490                         if (obj->write_domain & request->flush_domains) {
 491                                 obj->write_domain = 0;
 492                                 i915_gem_object_move_to_inactive(obj);
 493                         }
 494                 }
 495
 496         }
 497
 498         /* Move any buffers on the active list that are no longer referenced
 499          * by the ringbuffer to the flushing/inactive lists as appropriate.
 500          */
 501         while (!list_empty(&dev_priv->mm.active_list)) {
 502                 struct drm_gem_object *obj;
 503                 struct drm_i915_gem_object *obj_priv;
 504
 505                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
 506                                             struct drm_i915_gem_object,
 507                                             list);
 508                 obj = obj_priv->obj;
 509
 510                 /* If the seqno being retired doesn't match the oldest in the
 511                  * list, then the oldest in the list must still be newer than
 512                  * this seqno.
 513                  */
 514                 if (obj_priv->last_rendering_seqno != request->seqno)
 515                         return;
 516 #if WATCH_LRU
 517                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
 518                          __func__, request->seqno, obj);
 519 #endif
 520
 521                 if (obj->write_domain != 0) {
 522                         list_move_tail(&obj_priv->list,
 523                                        &dev_priv->mm.flushing_list);
 524                 } else {
 525                         i915_gem_object_move_to_inactive(obj);
 526                 }
 527         }
 528 }
 529
 530 /**
 531  * Returns true if seq1 is later than seq2.
 532  */
 533 static int
 534 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
 535 {
 536         return (int32_t)(seq1 - seq2) >= 0;
 537 }
 538
 539 uint32_t
 540 i915_get_gem_seqno(struct drm_device *dev)
 541 {
 542         drm_i915_private_t *dev_priv = dev->dev_private;
 543
 544         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
 545 }
 546
 547 /**
 548  * This function clears the request list as sequence numbers are passed.
 549  */
 550 void
 551 i915_gem_retire_requests(struct drm_device *dev)
 552 {
 553         drm_i915_private_t *dev_priv = dev->dev_private;
 554         uint32_t seqno;
 555
 556         seqno = i915_get_gem_seqno(dev);
 557
 558         while (!list_empty(&dev_priv->mm.request_list)) {
 559                 struct drm_i915_gem_request *request;
 560                 uint32_t retiring_seqno;
 561
 562                 request = list_first_entry(&dev_priv->mm.request_list,
 563                                            struct drm_i915_gem_request,
 564                                            list);
 565                 retiring_seqno = request->seqno;
 566
 567                 if (i915_seqno_passed(seqno, retiring_seqno)) {
 568                         i915_gem_retire_request(dev, request);
 569
 570                         list_del(&request->list);
 571                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
 572                 } else
 573                         break;
 574         }
 575 }
 576
 577 void
 578 i915_gem_retire_work_handler(struct work_struct *work)
 579 {
 580         drm_i915_private_t *dev_priv;
 581         struct drm_device *dev;
 582
 583         dev_priv = container_of(work, drm_i915_private_t,
 584                                 mm.retire_work.work);
 585         dev = dev_priv->dev;
 586
 587         mutex_lock(&dev->struct_mutex);
 588         i915_gem_retire_requests(dev);
 589         if (!list_empty(&dev_priv->mm.request_list))
 590                 schedule_delayed_work (&dev_priv->mm.retire_work, HZ);
 591         mutex_unlock(&dev->struct_mutex);
 592 }
 593
 594 /**
 595  * Waits for a sequence number to be signaled, and cleans up the
 596  * request and object lists appropriately for that event.
 597  */
 598 int
 599 i915_wait_request(struct drm_device *dev, uint32_t seqno)
 600 {
 601         drm_i915_private_t *dev_priv = dev->dev_private;
 602         int ret = 0;
 603
 604         BUG_ON(seqno == 0);
 605
 606         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
 607                 dev_priv->mm.waiting_gem_seqno = seqno;
 608                 i915_user_irq_on(dev_priv);
 609                 ret = wait_event_interruptible(dev_priv->irq_queue,
 610                                                i915_seqno_passed(i915_get_gem_seqno(dev),
 611                                                                  seqno));
 612                 i915_user_irq_off(dev_priv);
 613                 dev_priv->mm.waiting_gem_seqno = 0;
 614         }
 615         if (ret)
 616                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
 617                           __func__, ret, seqno, i915_get_gem_seqno(dev));
 618
 619         /* Directly dispatch request retiring.  While we have the work queue
 620          * to handle this, the waiter on a request often wants an associated
 621          * buffer to have made it to the inactive list, and we would need
 622          * a separate wait queue to handle that.
 623          */
 624         if (ret == 0)
 625                 i915_gem_retire_requests(dev);
 626
 627         return ret;
 628 }
 629
 630 static void
 631 i915_gem_flush(struct drm_device *dev,
 632                uint32_t invalidate_domains,
 633                uint32_t flush_domains)
 634 {
 635         drm_i915_private_t *dev_priv = dev->dev_private;
 636         uint32_t cmd;
 637         RING_LOCALS;
 638
 639 #if WATCH_EXEC
 640         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
 641                   invalidate_domains, flush_domains);
 642 #endif
 643
 644         if (flush_domains & I915_GEM_DOMAIN_CPU)
 645                 drm_agp_chipset_flush(dev);
 646
 647         if ((invalidate_domains|flush_domains) & ~I915_GEM_DOMAIN_CPU) {
 648                 /*
 649                  * read/write caches:
 650                  *
 651                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 652                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 653                  * also flushed at 2d versus 3d pipeline switches.
 654                  *
 655                  * read-only caches:
 656                  *
 657                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 658                  * MI_READ_FLUSH is set, and is always flushed on 965.
 659                  *
 660                  * I915_GEM_DOMAIN_COMMAND may not exist?
 661                  *
 662                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 663                  * invalidated when MI_EXE_FLUSH is set.
 664                  *
 665                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 666                  * invalidated with every MI_FLUSH.
 667                  *
 668                  * TLBs:
 669                  *
 670                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 671                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 672                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 673                  * are flushed at any MI_FLUSH.
 674                  */
 675
 676                 cmd = CMD_MI_FLUSH | MI_NO_WRITE_FLUSH;
 677                 if ((invalidate_domains|flush_domains) &
 678                     I915_GEM_DOMAIN_RENDER)
 679                         cmd &= ~MI_NO_WRITE_FLUSH;
 680                 if (!IS_I965G(dev)) {
 681                         /*
 682                          * On the 965, the sampler cache always gets flushed
 683                          * and this bit is reserved.
 684                          */
 685                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 686                                 cmd |= MI_READ_FLUSH;
 687                 }
 688                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 689                         cmd |= MI_EXE_FLUSH;
 690
 691 #if WATCH_EXEC
 692                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 693 #endif
 694                 BEGIN_LP_RING(2);
 695                 OUT_RING(cmd);
 696                 OUT_RING(0); /* noop */
 697                 ADVANCE_LP_RING();
 698         }
 699 }
 700
 701 /**
 702  * Ensures that all rendering to the object has completed and the object is
 703  * safe to unbind from the GTT or access from the CPU.
 704  */
 705 static int
 706 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
 707 {
 708         struct drm_device *dev = obj->dev;
 709         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 710         int ret;
 711
 712         /* If there are writes queued to the buffer, flush and
 713          * create a new seqno to wait for.
 714          */
 715         if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU)) {
 716                 uint32_t write_domain = obj->write_domain;
 717 #if WATCH_BUF
 718                 DRM_INFO("%s: flushing object %p from write domain %08x\n",
 719                           __func__, obj, write_domain);
 720 #endif
 721                 i915_gem_flush(dev, 0, write_domain);
 722                 obj->write_domain = 0;
 723
 724                 i915_gem_object_move_to_active(obj);
 725                 obj_priv->last_rendering_seqno = i915_add_request(dev,
 726                                                                   write_domain);
 727                 BUG_ON(obj_priv->last_rendering_seqno == 0);
 728 #if WATCH_LRU
 729                 DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj);
 730 #endif
 731         }
 732         /* If there is rendering queued on the buffer being evicted, wait for
 733          * it.
 734          */
 735         if (obj_priv->active) {
 736 #if WATCH_BUF
 737                 DRM_INFO("%s: object %p wait for seqno %08x\n",
 738                           __func__, obj, obj_priv->last_rendering_seqno);
 739 #endif
 740                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
 741                 if (ret != 0)
 742                         return ret;
 743         }
 744
 745         return 0;
 746 }
 747
 748 /**
 749  * Unbinds an object from the GTT aperture.
 750  */
 751 static int
 752 i915_gem_object_unbind(struct drm_gem_object *obj)
 753 {
 754         struct drm_device *dev = obj->dev;
 755         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 756         int ret = 0;
 757
 758 #if WATCH_BUF
 759         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
 760         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
 761 #endif
 762         if (obj_priv->gtt_space == NULL)
 763                 return 0;
 764
 765         if (obj_priv->pin_count != 0) {
 766                 DRM_ERROR("Attempting to unbind pinned buffer\n");
 767                 return -EINVAL;
 768         }
 769
 770         /* Wait for any rendering to complete
 771          */
 772         ret = i915_gem_object_wait_rendering(obj);
 773         if (ret) {
 774                 DRM_ERROR ("wait_rendering failed: %d\n", ret);
 775                 return ret;
 776         }
 777
 778         /* Move the object to the CPU domain to ensure that
 779          * any possible CPU writes while it's not in the GTT
 780          * are flushed when we go to remap it. This will
 781          * also ensure that all pending GPU writes are finished
 782          * before we unbind.
 783          */
 784         ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU,
 785                                          I915_GEM_DOMAIN_CPU);
 786         if (ret) {
 787                 DRM_ERROR("set_domain failed: %d\n", ret);
 788                 return ret;
 789         }
 790
 791         if (obj_priv->agp_mem != NULL) {
 792                 drm_unbind_agp(obj_priv->agp_mem);
 793                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
 794                 obj_priv->agp_mem = NULL;
 795         }
 796
 797         BUG_ON(obj_priv->active);
 798
 799         i915_gem_object_free_page_list(obj);
 800
 801         atomic_dec(&dev->gtt_count);
 802         atomic_sub(obj->size, &dev->gtt_memory);
 803
 804         drm_memrange_put_block(obj_priv->gtt_space);
 805         obj_priv->gtt_space = NULL;
 806
 807         /* Remove ourselves from the LRU list if present. */
 808         if (!list_empty(&obj_priv->list))
 809                 list_del_init(&obj_priv->list);
 810
 811         return 0;
 812 }
 813
 814 #if WATCH_BUF | WATCH_EXEC
 815 static void
 816 i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end,
 817                    uint32_t bias, uint32_t mark)
 818 {
 819         uint32_t *mem = kmap_atomic(page, KM_USER0);
 820         int i;
 821         for (i = start; i < end; i += 4)
 822                 DRM_INFO("%08x: %08x%s\n",
 823                           (int) (bias + i), mem[i / 4],
 824                           (bias + i == mark) ? " ********" : "");
 825         kunmap_atomic(mem, KM_USER0);
 826         /* give syslog time to catch up */
 827         msleep(1);
 828 }
 829
 830 static void
 831 i915_gem_dump_object(struct drm_gem_object *obj, int len,
 832                      const char *where, uint32_t mark)
 833 {
 834         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 835         int page;
 836
 837         DRM_INFO("%s: object at offset %08x\n", where, obj_priv->gtt_offset);
 838         for (page = 0; page < (len + PAGE_SIZE-1) / PAGE_SIZE; page++) {
 839                 int page_len, chunk, chunk_len;
 840
 841                 page_len = len - page * PAGE_SIZE;
 842                 if (page_len > PAGE_SIZE)
 843                         page_len = PAGE_SIZE;
 844
 845                 for (chunk = 0; chunk < page_len; chunk += 128) {
 846                         chunk_len = page_len - chunk;
 847                         if (chunk_len > 128)
 848                                 chunk_len = 128;
 849                         i915_gem_dump_page(obj_priv->page_list[page],
 850                                            chunk, chunk + chunk_len,
 851                                            obj_priv->gtt_offset +
 852                                            page * PAGE_SIZE,
 853                                            mark);
 854                 }
 855         }
 856 }
 857 #endif
 858
 859 #if WATCH_LRU
 860 static void
 861 i915_dump_lru(struct drm_device *dev, const char *where)
 862 {
 863         drm_i915_private_t              *dev_priv = dev->dev_private;
 864         struct drm_i915_gem_object      *obj_priv;
 865
 866         DRM_INFO("active list %s {\n", where);
 867         list_for_each_entry(obj_priv, &dev_priv->mm.active_list,
 868                             list)
 869         {
 870                 DRM_INFO("    %p: %08x\n", obj_priv,
 871                          obj_priv->last_rendering_seqno);
 872         }
 873         DRM_INFO("}\n");
 874         DRM_INFO("flushing list %s {\n", where);
 875         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list,
 876                             list)
 877         {
 878                 DRM_INFO("    %p: %08x\n", obj_priv,
 879                          obj_priv->last_rendering_seqno);
 880         }
 881         DRM_INFO("}\n");
 882         DRM_INFO("inactive %s {\n", where);
 883         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
 884                 DRM_INFO("    %p: %08x\n", obj_priv,
 885                          obj_priv->last_rendering_seqno);
 886         }
 887         DRM_INFO("}\n");
 888 }
 889 #endif
 890
 891 static int
 892 i915_gem_evict_something(struct drm_device *dev)
 893 {
 894         drm_i915_private_t *dev_priv = dev->dev_private;
 895         struct drm_gem_object *obj;
 896         struct drm_i915_gem_object *obj_priv;
 897         int ret = 0;
 898
 899         for (;;) {
 900                 /* If there's an inactive buffer available now, grab it
 901                  * and be done.
 902                  */
 903                 if (!list_empty(&dev_priv->mm.inactive_list)) {
 904                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
 905                                                     struct drm_i915_gem_object,
 906                                                     list);
 907                         obj = obj_priv->obj;
 908                         BUG_ON(obj_priv->pin_count != 0);
 909 #if WATCH_LRU
 910                         DRM_INFO("%s: evicting %p\n", __func__, obj);
 911 #endif
 912                         BUG_ON(obj_priv->active);
 913
 914                         /* Wait on the rendering and unbind the buffer. */
 915                         ret = i915_gem_object_unbind(obj);
 916                         break;
 917                 }
 918
 919                 /* If we didn't get anything, but the ring is still processing
 920                  * things, wait for one of those things to finish and hopefully
 921                  * leave us a buffer to evict.
 922                  */
 923                 if (!list_empty(&dev_priv->mm.request_list)) {
 924                         struct drm_i915_gem_request *request;
 925
 926                         request = list_first_entry(&dev_priv->mm.request_list,
 927                                                    struct drm_i915_gem_request,
 928                                                    list);
 929
 930                         ret = i915_wait_request(dev, request->seqno);
 931
 932                         /* if waiting caused an object to become inactive,
 933                          * then loop around and wait for it. Otherwise, we
 934                          * assume that waiting freed and unbound something,
 935                          * so there should now be some space in the GTT
 936                          */
 937                         if (!list_empty(&dev_priv->mm.inactive_list))
 938                                 continue;
 939                         break;
 940                 }
 941
 942                 /* If we didn't have anything on the request list but there
 943                  * are buffers awaiting a flush, emit one and try again.
 944                  * When we wait on it, those buffers waiting for that flush
 945                  * will get moved to inactive.
 946                  */
 947                 if (!list_empty(&dev_priv->mm.flushing_list)) {
 948                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
 949                                                     struct drm_i915_gem_object,
 950                                                     list);
 951                         obj = obj_priv->obj;
 952
 953                         i915_gem_flush(dev,
 954                                        obj->write_domain,
 955                                        obj->write_domain);
 956                         i915_add_request(dev, obj->write_domain);
 957
 958                         obj = NULL;
 959                         continue;
 960                 }
 961
 962                 DRM_ERROR("inactive empty %d request empty %d flushing empty %d\n",
 963                           list_empty(&dev_priv->mm.inactive_list),
 964                           list_empty(&dev_priv->mm.request_list),
 965                           list_empty(&dev_priv->mm.flushing_list));
 966                 /* If we didn't do any of the above, there's nothing to be done
 967                  * and we just can't fit it in.
 968                  */
 969                 return -ENOMEM;
 970         }
 971         return ret;
 972 }
 973
 974 static int
 975 i915_gem_object_get_page_list(struct drm_gem_object *obj)
 976 {
 977         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 978         int page_count, i;
 979         struct address_space *mapping;
 980         struct inode *inode;
 981         struct page *page;
 982         int ret;
 983
 984         if (obj_priv->page_list)
 985                 return 0;
 986
 987         /* Get the list of pages out of our struct file.  They'll be pinned
 988          * at this point until we release them.
 989          */
 990         page_count = obj->size / PAGE_SIZE;
 991         BUG_ON(obj_priv->page_list != NULL);
 992         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
 993                                          DRM_MEM_DRIVER);
 994         if (obj_priv->page_list == NULL) {
 995                 DRM_ERROR("Faled to allocate page list\n");
 996                 return -ENOMEM;
 997         }
 998
 999         inode = obj->filp->f_path.dentry->d_inode;
1000         mapping = inode->i_mapping;
1001         for (i = 0; i < page_count; i++) {
1002                 page = find_get_page(mapping, i);
1003                 if (page == NULL || !PageUptodate(page)) {
1004                         if (page) {
1005                                 page_cache_release(page);
1006                                 page = NULL;
1007                         }
1008                         ret = shmem_getpage(inode, i, &page, SGP_DIRTY, NULL);
1009
1010                         if (ret) {
1011                                 DRM_ERROR("shmem_getpage failed: %d\n", ret);
1012                                 i915_gem_object_free_page_list(obj);
1013                                 return ret;
1014                         }
1015                         unlock_page(page);
1016                 }
1017                 obj_priv->page_list[i] = page;
1018         }
1019         return 0;
1020 }
1021
1022 /**
1023  * Finds free space in the GTT aperture and binds the object there.
1024  */
1025 static int
1026 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1027 {
1028         struct drm_device *dev = obj->dev;
1029         drm_i915_private_t *dev_priv = dev->dev_private;
1030         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1031         struct drm_memrange_node *free_space;
1032         int page_count, ret;
1033
1034         if (alignment == 0)
1035                 alignment = PAGE_SIZE;
1036         if (alignment & (PAGE_SIZE - 1)) {
1037                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1038                 return -EINVAL;
1039         }
1040
1041  search_free:
1042         free_space = drm_memrange_search_free(&dev_priv->mm.gtt_space,
1043                                               obj->size,
1044                                               alignment, 0);
1045         if (free_space != NULL) {
1046                 obj_priv->gtt_space =
1047                         drm_memrange_get_block(free_space, obj->size,
1048                                                alignment);
1049                 if (obj_priv->gtt_space != NULL) {
1050                         obj_priv->gtt_space->private = obj;
1051                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1052                 }
1053         }
1054         if (obj_priv->gtt_space == NULL) {
1055                 /* If the gtt is empty and we're still having trouble
1056                  * fitting our object in, we're out of memory.
1057                  */
1058 #if WATCH_LRU
1059                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1060 #endif
1061                 if (list_empty(&dev_priv->mm.inactive_list) &&
1062                     list_empty(&dev_priv->mm.flushing_list) &&
1063                     list_empty(&dev_priv->mm.active_list)) {
1064                         DRM_ERROR("GTT full, but LRU list empty\n");
1065                         return -ENOMEM;
1066                 }
1067
1068                 ret = i915_gem_evict_something(dev);
1069                 if (ret != 0) {
1070                         DRM_ERROR("Failed to evict a buffer %d\n", ret);
1071                         return ret;
1072                 }
1073                 goto search_free;
1074         }
1075
1076 #if WATCH_BUF
1077         DRM_INFO("Binding object of size %d at 0x%08x\n",
1078                  obj->size, obj_priv->gtt_offset);
1079 #endif
1080         ret = i915_gem_object_get_page_list(obj);
1081         if (ret) {
1082                 drm_memrange_put_block(obj_priv->gtt_space);
1083                 obj_priv->gtt_space = NULL;
1084                 return ret;
1085         }
1086
1087         page_count = obj->size / PAGE_SIZE;
1088         /* Create an AGP memory structure pointing at our pages, and bind it
1089          * into the GTT.
1090          */
1091         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1092                                                obj_priv->page_list,
1093                                                page_count,
1094                                                obj_priv->gtt_offset);
1095         if (obj_priv->agp_mem == NULL) {
1096                 i915_gem_object_free_page_list(obj);
1097                 drm_memrange_put_block(obj_priv->gtt_space);
1098                 obj_priv->gtt_space = NULL;
1099                 return -ENOMEM;
1100         }
1101         atomic_inc(&dev->gtt_count);
1102         atomic_add(obj->size, &dev->gtt_memory);
1103
1104         /* Assert that the object is not currently in any GPU domain. As it
1105          * wasn't in the GTT, there shouldn't be any way it could have been in
1106          * a GPU cache
1107          */
1108         BUG_ON(obj->read_domains & ~I915_GEM_DOMAIN_CPU);
1109         BUG_ON(obj->write_domain & ~I915_GEM_DOMAIN_CPU);
1110
1111         return 0;
1112 }
1113
1114 static void
1115 i915_gem_clflush_object(struct drm_gem_object *obj)
1116 {
1117         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1118
1119         /* If we don't have a page list set up, then we're not pinned
1120          * to GPU, and we can ignore the cache flush because it'll happen
1121          * again at bind time.
1122          */
1123         if (obj_priv->page_list == NULL)
1124                 return;
1125
1126         drm_ttm_cache_flush(obj_priv->page_list, obj->size / PAGE_SIZE);
1127 }
1128
1129 /*
1130  * Set the next domain for the specified object. This
1131  * may not actually perform the necessary flushing/invaliding though,
1132  * as that may want to be batched with other set_domain operations
1133  *
1134  * This is (we hope) the only really tricky part of gem. The goal
1135  * is fairly simple -- track which caches hold bits of the object
1136  * and make sure they remain coherent. A few concrete examples may
1137  * help to explain how it works. For shorthand, we use the notation
1138  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1139  * a pair of read and write domain masks.
1140  *
1141  * Case 1: the batch buffer
1142  *
1143  *      1. Allocated
1144  *      2. Written by CPU
1145  *      3. Mapped to GTT
1146  *      4. Read by GPU
1147  *      5. Unmapped from GTT
1148  *      6. Freed
1149  *
1150  *      Let's take these a step at a time
1151  *
1152  *      1. Allocated
1153  *              Pages allocated from the kernel may still have
1154  *              cache contents, so we set them to (CPU, CPU) always.
1155  *      2. Written by CPU (using pwrite)
1156  *              The pwrite function calls set_domain (CPU, CPU) and
1157  *              this function does nothing (as nothing changes)
1158  *      3. Mapped by GTT
1159  *              This function asserts that the object is not
1160  *              currently in any GPU-based read or write domains
1161  *      4. Read by GPU
1162  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1163  *              As write_domain is zero, this function adds in the
1164  *              current read domains (CPU+COMMAND, 0).
1165  *              flush_domains is set to CPU.
1166  *              invalidate_domains is set to COMMAND
1167  *              clflush is run to get data out of the CPU caches
1168  *              then i915_dev_set_domain calls i915_gem_flush to
1169  *              emit an MI_FLUSH and drm_agp_chipset_flush
1170  *      5. Unmapped from GTT
1171  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1172  *              flush_domains and invalidate_domains end up both zero
1173  *              so no flushing/invalidating happens
1174  *      6. Freed
1175  *              yay, done
1176  *
1177  * Case 2: The shared render buffer
1178  *
1179  *      1. Allocated
1180  *      2. Mapped to GTT
1181  *      3. Read/written by GPU
1182  *      4. set_domain to (CPU,CPU)
1183  *      5. Read/written by CPU
1184  *      6. Read/written by GPU
1185  *
1186  *      1. Allocated
1187  *              Same as last example, (CPU, CPU)
1188  *      2. Mapped to GTT
1189  *              Nothing changes (assertions find that it is not in the GPU)
1190  *      3. Read/written by GPU
1191  *              execbuffer calls set_domain (RENDER, RENDER)
1192  *              flush_domains gets CPU
1193  *              invalidate_domains gets GPU
1194  *              clflush (obj)
1195  *              MI_FLUSH and drm_agp_chipset_flush
1196  *      4. set_domain (CPU, CPU)
1197  *              flush_domains gets GPU
1198  *              invalidate_domains gets CPU
1199  *              wait_rendering (obj) to make sure all drawing is complete.
1200  *              This will include an MI_FLUSH to get the data from GPU
1201  *              to memory
1202  *              clflush (obj) to invalidate the CPU cache
1203  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1204  *      5. Read/written by CPU
1205  *              cache lines are loaded and dirtied
1206  *      6. Read written by GPU
1207  *              Same as last GPU access
1208  *
1209  * Case 3: The constant buffer
1210  *
1211  *      1. Allocated
1212  *      2. Written by CPU
1213  *      3. Read by GPU
1214  *      4. Updated (written) by CPU again
1215  *      5. Read by GPU
1216  *
1217  *      1. Allocated
1218  *              (CPU, CPU)
1219  *      2. Written by CPU
1220  *              (CPU, CPU)
1221  *      3. Read by GPU
1222  *              (CPU+RENDER, 0)
1223  *              flush_domains = CPU
1224  *              invalidate_domains = RENDER
1225  *              clflush (obj)
1226  *              MI_FLUSH
1227  *              drm_agp_chipset_flush
1228  *      4. Updated (written) by CPU again
1229  *              (CPU, CPU)
1230  *              flush_domains = 0 (no previous write domain)
1231  *              invalidate_domains = 0 (no new read domains)
1232  *      5. Read by GPU
1233  *              (CPU+RENDER, 0)
1234  *              flush_domains = CPU
1235  *              invalidate_domains = RENDER
1236  *              clflush (obj)
1237  *              MI_FLUSH
1238  *              drm_agp_chipset_flush
1239  */
1240 static int
1241 i915_gem_object_set_domain(struct drm_gem_object *obj,
1242                             uint32_t read_domains,
1243                             uint32_t write_domain)
1244 {
1245         struct drm_device               *dev = obj->dev;
1246         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1247         uint32_t                        invalidate_domains = 0;
1248         uint32_t                        flush_domains = 0;
1249         int                             ret;
1250
1251 #if WATCH_BUF
1252         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1253                  __func__, obj,
1254                  obj->read_domains, read_domains,
1255                  obj->write_domain, write_domain);
1256 #endif
1257         /*
1258          * If the object isn't moving to a new write domain,
1259          * let the object stay in multiple read domains
1260          */
1261         if (write_domain == 0)
1262                 read_domains |= obj->read_domains;
1263         else
1264                 obj_priv->dirty = 1;
1265
1266         /*
1267          * Flush the current write domain if
1268          * the new read domains don't match. Invalidate
1269          * any read domains which differ from the old
1270          * write domain
1271          */
1272         if (obj->write_domain && obj->write_domain != read_domains) {
1273                 flush_domains |= obj->write_domain;
1274                 invalidate_domains |= read_domains & ~obj->write_domain;
1275         }
1276         /*
1277          * Invalidate any read caches which may have
1278          * stale data. That is, any new read domains.
1279          */
1280         invalidate_domains |= read_domains & ~obj->read_domains;
1281         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
1282 #if WATCH_BUF
1283                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1284                          __func__, flush_domains, invalidate_domains);
1285 #endif
1286                 /*
1287                  * If we're invaliding the CPU cache and flushing a GPU cache,
1288                  * then pause for rendering so that the GPU caches will be
1289                  * flushed before the cpu cache is invalidated
1290                  */
1291                 if ((invalidate_domains & I915_GEM_DOMAIN_CPU) &&
1292                     (flush_domains & ~I915_GEM_DOMAIN_CPU)) {
1293                         ret = i915_gem_object_wait_rendering(obj);
1294                         if (ret)
1295                                 return ret;
1296                 }
1297                 i915_gem_clflush_object(obj);
1298         }
1299
1300         if ((write_domain | flush_domains) != 0)
1301                 obj->write_domain = write_domain;
1302         obj->read_domains = read_domains;
1303         dev->invalidate_domains |= invalidate_domains;
1304         dev->flush_domains |= flush_domains;
1305 #if WATCH_BUF
1306         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1307                  __func__,
1308                  obj->read_domains, obj->write_domain,
1309                  dev->invalidate_domains, dev->flush_domains);
1310 #endif
1311         return 0;
1312 }
1313
1314 /**
1315  * Once all of the objects have been set in the proper domain,
1316  * perform the necessary flush and invalidate operations.
1317  *
1318  * Returns the write domains flushed, for use in flush tracking.
1319  */
1320 static uint32_t
1321 i915_gem_dev_set_domain(struct drm_device *dev)
1322 {
1323         uint32_t flush_domains = dev->flush_domains;
1324
1325         /*
1326          * Now that all the buffers are synced to the proper domains,
1327          * flush and invalidate the collected domains
1328          */
1329         if (dev->invalidate_domains | dev->flush_domains) {
1330 #if WATCH_EXEC
1331                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
1332                           __func__,
1333                          dev->invalidate_domains,
1334                          dev->flush_domains);
1335 #endif
1336                 i915_gem_flush(dev,
1337                                dev->invalidate_domains,
1338                                dev->flush_domains);
1339                 dev->invalidate_domains = 0;
1340                 dev->flush_domains = 0;
1341         }
1342
1343         return flush_domains;
1344 }
1345
1346 #if WATCH_COHERENCY
1347 static void
1348 i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle)
1349 {
1350         struct drm_device *dev = obj->dev;
1351         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1352         int page;
1353         uint32_t *gtt_mapping;
1354         uint32_t *backing_map = NULL;
1355         int bad_count = 0;
1356
1357         DRM_INFO("%s: checking coherency of object %p@0x%08x (%d, %dkb):\n",
1358                  __func__, obj, obj_priv->gtt_offset, handle,
1359                  obj->size / 1024);
1360
1361         gtt_mapping = ioremap(dev->agp->base + obj_priv->gtt_offset,
1362                               obj->size);
1363         if (gtt_mapping == NULL) {
1364                 DRM_ERROR("failed to map GTT space\n");
1365                 return;
1366         }
1367
1368         for (page = 0; page < obj->size / PAGE_SIZE; page++) {
1369                 int i;
1370
1371                 backing_map = kmap_atomic(obj_priv->page_list[page], KM_USER0);
1372
1373                 if (backing_map == NULL) {
1374                         DRM_ERROR("failed to map backing page\n");
1375                         goto out;
1376                 }
1377
1378                 for (i = 0; i < PAGE_SIZE / 4; i++) {
1379                         uint32_t cpuval = backing_map[i];
1380                         uint32_t gttval = readl(gtt_mapping +
1381                                                 page * 1024 + i);
1382
1383                         if (cpuval != gttval) {
1384                                 DRM_INFO("incoherent CPU vs GPU at 0x%08x: "
1385                                          "0x%08x vs 0x%08x\n",
1386                                          (int)(obj_priv->gtt_offset +
1387                                                page * PAGE_SIZE + i * 4),
1388                                          cpuval, gttval);
1389                                 if (bad_count++ >= 8) {
1390                                         DRM_INFO("...\n");
1391                                         goto out;
1392                                 }
1393                         }
1394                 }
1395                 kunmap_atomic(backing_map, KM_USER0);
1396                 backing_map = NULL;
1397         }
1398
1399  out:
1400         if (backing_map != NULL)
1401                 kunmap_atomic(backing_map, KM_USER0);
1402         iounmap(gtt_mapping);
1403
1404         /* give syslog time to catch up */
1405         msleep(1);
1406
1407         /* Directly flush the object, since we just loaded values with the CPU
1408          * from thebacking pages and we don't want to disturb the cache
1409          * management that we're trying to observe.
1410          */
1411
1412         i915_gem_clflush_object(obj);
1413 }
1414 #endif
1415
1416 /**
1417  * Pin an object to the GTT and evaluate the relocations landing in it.
1418  */
1419 static int
1420 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1421                                  struct drm_file *file_priv,
1422                                  struct drm_i915_gem_exec_object *entry)
1423 {
1424         struct drm_device *dev = obj->dev;
1425         struct drm_i915_gem_relocation_entry reloc;
1426         struct drm_i915_gem_relocation_entry __user *relocs;
1427         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1428         int i, ret;
1429         uint32_t last_reloc_offset = -1;
1430         void *reloc_page = NULL;
1431
1432         /* Choose the GTT offset for our buffer and put it there. */
1433         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
1434         if (ret)
1435                 return ret;
1436
1437         entry->offset = obj_priv->gtt_offset;
1438
1439         relocs = (struct drm_i915_gem_relocation_entry __user *)
1440                  (uintptr_t) entry->relocs_ptr;
1441         /* Apply the relocations, using the GTT aperture to avoid cache
1442          * flushing requirements.
1443          */
1444         for (i = 0; i < entry->relocation_count; i++) {
1445                 struct drm_gem_object *target_obj;
1446                 struct drm_i915_gem_object *target_obj_priv;
1447                 uint32_t reloc_val, reloc_offset, *reloc_entry;
1448                 int ret;
1449
1450                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
1451                 if (ret != 0) {
1452                         i915_gem_object_unpin(obj);
1453                         return ret;
1454                 }
1455
1456                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
1457                                                    reloc.target_handle);
1458                 if (target_obj == NULL) {
1459                         i915_gem_object_unpin(obj);
1460                         return -EINVAL;
1461                 }
1462                 target_obj_priv = target_obj->driver_private;
1463
1464                 /* The target buffer should have appeared before us in the
1465                  * exec_object list, so it should have a GTT space bound by now.
1466                  */
1467                 if (target_obj_priv->gtt_space == NULL) {
1468                         DRM_ERROR("No GTT space found for object %d\n",
1469                                   reloc.target_handle);
1470                         drm_gem_object_unreference(target_obj);
1471                         i915_gem_object_unpin(obj);
1472                         return -EINVAL;
1473                 }
1474
1475                 if (reloc.offset > obj->size - 4) {
1476                         DRM_ERROR("Relocation beyond object bounds: "
1477                                   "obj %p target %d offset %d size %d.\n",
1478                                   obj, reloc.target_handle,
1479                                   (int) reloc.offset, (int) obj->size);
1480                         drm_gem_object_unreference(target_obj);
1481                         i915_gem_object_unpin(obj);
1482                         return -EINVAL;
1483                 }
1484                 if (reloc.offset & 3) {
1485                         DRM_ERROR("Relocation not 4-byte aligned: "
1486                                   "obj %p target %d offset %d.\n",
1487                                   obj, reloc.target_handle,
1488                                   (int) reloc.offset);
1489                         drm_gem_object_unreference(target_obj);
1490                         i915_gem_object_unpin(obj);
1491                         return -EINVAL;
1492                 }
1493
1494                 if (reloc.write_domain && target_obj->pending_write_domain &&
1495                     reloc.write_domain != target_obj->pending_write_domain) {
1496                         DRM_ERROR("Write domain conflict: "
1497                                   "obj %p target %d offset %d "
1498                                   "new %08x old %08x\n",
1499                                   obj, reloc.target_handle,
1500                                   (int) reloc.offset,
1501                                   reloc.write_domain,
1502                                   target_obj->pending_write_domain);
1503                         drm_gem_object_unreference(target_obj);
1504                         i915_gem_object_unpin(obj);
1505                         return -EINVAL;
1506                 }
1507
1508 #if WATCH_RELOC
1509                 DRM_INFO("%s: obj %p offset %08x target %d "
1510                          "read %08x write %08x gtt %08x "
1511                          "presumed %08x delta %08x\n",
1512                          __func__,
1513                          obj,
1514                          (int) reloc.offset,
1515                          (int) reloc.target_handle,
1516                          (int) reloc.read_domains,
1517                          (int) reloc.write_domain,
1518                          (int) target_obj_priv->gtt_offset,
1519                          (int) reloc.presumed_offset,
1520                          reloc.delta);
1521 #endif
1522
1523                 target_obj->pending_read_domains |= reloc.read_domains;
1524                 target_obj->pending_write_domain |= reloc.write_domain;
1525
1526                 /* If the relocation already has the right value in it, no
1527                  * more work needs to be done.
1528                  */
1529                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
1530                         drm_gem_object_unreference(target_obj);
1531                         continue;
1532                 }
1533
1534                 /* Now that we're going to actually write some data in,
1535                  * make sure that any rendering using this buffer's contents
1536                  * is completed.
1537                  */
1538                 i915_gem_object_wait_rendering(obj);
1539
1540                 /* As we're writing through the gtt, flush
1541                  * any CPU writes before we write the relocations
1542                  */
1543                 if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
1544                         i915_gem_clflush_object(obj);
1545                         drm_agp_chipset_flush(dev);
1546                         obj->write_domain = 0;
1547                 }
1548
1549                 /* Map the page containing the relocation we're going to
1550                  * perform.
1551                  */
1552                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1553                 if (reloc_page == NULL ||
1554                     (last_reloc_offset & ~(PAGE_SIZE - 1)) !=
1555                     (reloc_offset & ~(PAGE_SIZE - 1))) {
1556                         if (reloc_page != NULL)
1557                                 iounmap(reloc_page);
1558
1559                         reloc_page = ioremap(dev->agp->base +
1560                                              (reloc_offset & ~(PAGE_SIZE - 1)),
1561                                              PAGE_SIZE);
1562                         last_reloc_offset = reloc_offset;
1563                         if (reloc_page == NULL) {
1564                                 drm_gem_object_unreference(target_obj);
1565                                 i915_gem_object_unpin(obj);
1566                                 return -ENOMEM;
1567                         }
1568                 }
1569
1570                 reloc_entry = (uint32_t *)((char *)reloc_page +
1571                                            (reloc_offset & (PAGE_SIZE - 1)));
1572                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1573
1574 #if WATCH_BUF
1575                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1576                           obj, (unsigned int) reloc.offset,
1577                           readl(reloc_entry), reloc_val);
1578 #endif
1579                 writel(reloc_val, reloc_entry);
1580
1581                 /* Write the updated presumed offset for this entry back out
1582                  * to the user.
1583                  */
1584                 reloc.presumed_offset = target_obj_priv->gtt_offset;
1585                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
1586                 if (ret != 0) {
1587                         drm_gem_object_unreference(target_obj);
1588                         i915_gem_object_unpin(obj);
1589                         return ret;
1590                 }
1591
1592                 drm_gem_object_unreference(target_obj);
1593         }
1594
1595         if (reloc_page != NULL)
1596                 iounmap(reloc_page);
1597
1598 #if WATCH_BUF
1599         if (0)
1600                 i915_gem_dump_object(obj, 128, __func__, ~0);
1601 #endif
1602         return 0;
1603 }
1604
1605 /** Dispatch a batchbuffer to the ring
1606  */
1607 static int
1608 i915_dispatch_gem_execbuffer(struct drm_device *dev,
1609                               struct drm_i915_gem_execbuffer *exec,
1610                               uint64_t exec_offset)
1611 {
1612         drm_i915_private_t *dev_priv = dev->dev_private;
1613         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
1614                                              (uintptr_t) exec->cliprects_ptr;
1615         int nbox = exec->num_cliprects;
1616         int i = 0, count;
1617         uint32_t        exec_start, exec_len;
1618         RING_LOCALS;
1619
1620         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
1621         exec_len = (uint32_t) exec->batch_len;
1622
1623         if ((exec_start | exec_len) & 0x7) {
1624                 DRM_ERROR("alignment\n");
1625                 return -EINVAL;
1626         }
1627
1628         if (!exec_start)
1629                 return -EINVAL;
1630
1631         count = nbox ? nbox : 1;
1632
1633         for (i = 0; i < count; i++) {
1634                 if (i < nbox) {
1635                         int ret = i915_emit_box(dev, boxes, i,
1636                                                 exec->DR1, exec->DR4);
1637                         if (ret)
1638                                 return ret;
1639                 }
1640
1641                 if (IS_I830(dev) || IS_845G(dev)) {
1642                         BEGIN_LP_RING(4);
1643                         OUT_RING(MI_BATCH_BUFFER);
1644                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1645                         OUT_RING(exec_start + exec_len - 4);
1646                         OUT_RING(0);
1647                         ADVANCE_LP_RING();
1648                 } else {
1649                         BEGIN_LP_RING(2);
1650                         if (IS_I965G(dev)) {
1651                                 OUT_RING(MI_BATCH_BUFFER_START |
1652                                          (2 << 6) |
1653                                          MI_BATCH_NON_SECURE_I965);
1654                                 OUT_RING(exec_start);
1655                         } else {
1656                                 OUT_RING(MI_BATCH_BUFFER_START |
1657                                          (2 << 6));
1658                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1659                         }
1660                         ADVANCE_LP_RING();
1661                 }
1662         }
1663
1664         /* XXX breadcrumb */
1665         return 0;
1666 }
1667
1668 /* Throttle our rendering by waiting until the ring has completed our requests
1669  * emitted over 20 msec ago.
1670  *
1671  * This should get us reasonable parallelism between CPU and GPU but also
1672  * relatively low latency when blocking on a particular request to finish.
1673  */
1674 static int
1675 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
1676 {
1677         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1678         int ret = 0;
1679         uint32_t seqno;
1680
1681         mutex_lock(&dev->struct_mutex);
1682         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
1683         i915_file_priv->mm.last_gem_throttle_seqno = i915_file_priv->mm.last_gem_seqno;
1684         if (seqno)
1685                 ret = i915_wait_request(dev, seqno);
1686         mutex_unlock(&dev->struct_mutex);
1687         return ret;
1688 }
1689
1690 int
1691 i915_gem_execbuffer(struct drm_device *dev, void *data,
1692                     struct drm_file *file_priv)
1693 {
1694         drm_i915_private_t *dev_priv = dev->dev_private;
1695         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1696         struct drm_i915_gem_execbuffer *args = data;
1697         struct drm_i915_gem_exec_object *exec_list = NULL;
1698         struct drm_gem_object **object_list = NULL;
1699         struct drm_gem_object *batch_obj;
1700         int ret, i, pinned = 0;
1701         uint64_t exec_offset;
1702         uint32_t seqno, flush_domains;
1703
1704 #if WATCH_EXEC
1705         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1706                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1707 #endif
1708
1709         /* Copy in the exec list from userland */
1710         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
1711                                DRM_MEM_DRIVER);
1712         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
1713                                  DRM_MEM_DRIVER);
1714         if (exec_list == NULL || object_list == NULL) {
1715                 DRM_ERROR("Failed to allocate exec or object list "
1716                           "for %d buffers\n",
1717                           args->buffer_count);
1718                 ret = -ENOMEM;
1719                 goto pre_mutex_err;
1720         }
1721         ret = copy_from_user(exec_list,
1722                              (struct drm_i915_relocation_entry __user *)
1723                              (uintptr_t) args->buffers_ptr,
1724                              sizeof(*exec_list) * args->buffer_count);
1725         if (ret != 0) {
1726                 DRM_ERROR("copy %d exec entries failed %d\n",
1727                           args->buffer_count, ret);
1728                 goto pre_mutex_err;
1729         }
1730
1731         mutex_lock(&dev->struct_mutex);
1732
1733         i915_verify_inactive(dev, __FILE__, __LINE__);
1734         if (dev_priv->mm.suspended) {
1735                 DRM_ERROR("Execbuf while VT-switched.\n");
1736                 mutex_unlock(&dev->struct_mutex);
1737                 return -EBUSY;
1738         }
1739
1740         /* Zero the gloabl flush/invalidate flags. These
1741          * will be modified as each object is bound to the
1742          * gtt
1743          */
1744         dev->invalidate_domains = 0;
1745         dev->flush_domains = 0;
1746
1747         /* Look up object handles and perform the relocations */
1748         for (i = 0; i < args->buffer_count; i++) {
1749                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
1750                                                        exec_list[i].handle);
1751                 if (object_list[i] == NULL) {
1752                         DRM_ERROR("Invalid object handle %d at index %d\n",
1753                                    exec_list[i].handle, i);
1754                         ret = -EINVAL;
1755                         goto err;
1756                 }
1757
1758                 object_list[i]->pending_read_domains = 0;
1759                 object_list[i]->pending_write_domain = 0;
1760                 ret = i915_gem_object_pin_and_relocate(object_list[i],
1761                                                        file_priv,
1762                                                        &exec_list[i]);
1763                 if (ret) {
1764                         DRM_ERROR("object bind and relocate failed %d\n", ret);
1765                         goto err;
1766                 }
1767                 pinned = i + 1;
1768         }
1769
1770         /* Set the pending read domains for the batch buffer to COMMAND */
1771         batch_obj = object_list[args->buffer_count-1];
1772         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1773         batch_obj->pending_write_domain = 0;
1774
1775         i915_verify_inactive(dev, __FILE__, __LINE__);
1776
1777         for (i = 0; i < args->buffer_count; i++) {
1778                 struct drm_gem_object *obj = object_list[i];
1779                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1780
1781                 if (obj_priv->gtt_space == NULL) {
1782                         /* We evicted the buffer in the process of validating
1783                          * our set of buffers in.  We could try to recover by
1784                          * kicking them everything out and trying again from
1785                          * the start.
1786                          */
1787                         ret = -ENOMEM;
1788                         goto err;
1789                 }
1790
1791                 /* make sure all previous memory operations have passed */
1792                 ret = i915_gem_object_set_domain(obj,
1793                                                  obj->pending_read_domains,
1794                                                  obj->pending_write_domain);
1795                 if (ret)
1796                         goto err;
1797         }
1798
1799         i915_verify_inactive(dev, __FILE__, __LINE__);
1800
1801         /* Flush/invalidate caches and chipset buffer */
1802         flush_domains = i915_gem_dev_set_domain(dev);
1803
1804         i915_verify_inactive(dev, __FILE__, __LINE__);
1805
1806 #if WATCH_COHERENCY
1807         for (i = 0; i < args->buffer_count; i++) {
1808                 i915_gem_object_check_coherency(object_list[i],
1809                                                 exec_list[i].handle);
1810         }
1811 #endif
1812
1813         exec_offset = exec_list[args->buffer_count - 1].offset;
1814
1815 #if WATCH_EXEC
1816         i915_gem_dump_object(object_list[args->buffer_count - 1],
1817                               args->batch_len,
1818                               __func__,
1819                               ~0);
1820 #endif
1821
1822         /* Exec the batchbuffer */
1823         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
1824         if (ret) {
1825                 DRM_ERROR("dispatch failed %d\n", ret);
1826                 goto err;
1827         }
1828
1829         /*
1830          * Ensure that the commands in the batch buffer are
1831          * finished before the interrupt fires
1832          */
1833         flush_domains |= i915_retire_commands(dev);
1834
1835         i915_verify_inactive(dev, __FILE__, __LINE__);
1836
1837         /*
1838          * Get a seqno representing the execution of the current buffer,
1839          * which we can wait on.  We would like to mitigate these interrupts,
1840          * likely by only creating seqnos occasionally (so that we have
1841          * *some* interrupts representing completion of buffers that we can
1842          * wait on when trying to clear up gtt space).
1843          */
1844         seqno = i915_add_request(dev, flush_domains);
1845         BUG_ON(seqno == 0);
1846         i915_file_priv->mm.last_gem_seqno = seqno;
1847         for (i = 0; i < args->buffer_count; i++) {
1848                 struct drm_gem_object *obj = object_list[i];
1849                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1850
1851                 i915_gem_object_move_to_active(obj);
1852                 obj_priv->last_rendering_seqno = seqno;
1853 #if WATCH_LRU
1854                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
1855 #endif
1856         }
1857 #if WATCH_LRU
1858         i915_dump_lru(dev, __func__);
1859 #endif
1860
1861         i915_verify_inactive(dev, __FILE__, __LINE__);
1862
1863         /* Copy the new buffer offsets back to the user's exec list. */
1864         ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1865                            (uintptr_t) args->buffers_ptr,
1866                            exec_list,
1867                            sizeof(*exec_list) * args->buffer_count);
1868         if (ret)
1869                 DRM_ERROR("failed to copy %d exec entries "
1870                           "back to user (%d)\n",
1871                            args->buffer_count, ret);
1872 err:
1873         if (object_list != NULL) {
1874                 for (i = 0; i < pinned; i++)
1875                         i915_gem_object_unpin(object_list[i]);
1876
1877                 for (i = 0; i < args->buffer_count; i++)
1878                         drm_gem_object_unreference(object_list[i]);
1879         }
1880         mutex_unlock(&dev->struct_mutex);
1881
1882 pre_mutex_err:
1883         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
1884                  DRM_MEM_DRIVER);
1885         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
1886                  DRM_MEM_DRIVER);
1887
1888         return ret;
1889 }
1890
1891 int
1892 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
1893 {
1894         struct drm_device *dev = obj->dev;
1895         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1896         int ret;
1897
1898         i915_verify_inactive(dev, __FILE__, __LINE__);
1899         if (obj_priv->gtt_space == NULL) {
1900                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
1901                 if (ret != 0) {
1902                         DRM_ERROR("Failure to bind: %d", ret);
1903                         return ret;
1904                 }
1905         }
1906         obj_priv->pin_count++;
1907
1908         /* If the object is not active and not pending a flush,
1909          * remove it from the inactive list
1910          */
1911         if (obj_priv->pin_count == 1) {
1912                 atomic_inc(&dev->pin_count);
1913                 atomic_add(obj->size, &dev->pin_memory);
1914                 if (!obj_priv->active && (obj->write_domain & ~I915_GEM_DOMAIN_CPU) == 0 &&
1915                     !list_empty(&obj_priv->list))
1916                         list_del_init(&obj_priv->list);
1917         }
1918         i915_verify_inactive(dev, __FILE__, __LINE__);
1919
1920         return 0;
1921 }
1922
1923 void
1924 i915_gem_object_unpin(struct drm_gem_object *obj)
1925 {
1926         struct drm_device *dev = obj->dev;
1927         drm_i915_private_t *dev_priv = dev->dev_private;
1928         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1929
1930         i915_verify_inactive(dev, __FILE__, __LINE__);
1931         obj_priv->pin_count--;
1932         BUG_ON(obj_priv->pin_count < 0);
1933         BUG_ON(obj_priv->gtt_space == NULL);
1934
1935         /* If the object is no longer pinned, and is
1936          * neither active nor being flushed, then stick it on
1937          * the inactive list
1938          */
1939         if (obj_priv->pin_count == 0) {
1940                 if (!obj_priv->active && (obj->write_domain & ~I915_GEM_DOMAIN_CPU) == 0)
1941                         list_move_tail(&obj_priv->list,
1942                                        &dev_priv->mm.inactive_list);
1943                 atomic_dec(&dev->pin_count);
1944                 atomic_sub(obj->size, &dev->pin_memory);
1945         }
1946         i915_verify_inactive(dev, __FILE__, __LINE__);
1947 }
1948
1949 int
1950 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1951                    struct drm_file *file_priv)
1952 {
1953         struct drm_i915_gem_pin *args = data;
1954         struct drm_gem_object *obj;
1955         struct drm_i915_gem_object *obj_priv;
1956         int ret;
1957
1958         mutex_lock(&dev->struct_mutex);
1959
1960         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1961         if (obj == NULL) {
1962                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
1963                           args->handle);
1964                 mutex_unlock(&dev->struct_mutex);
1965                 return -EINVAL;
1966         }
1967         obj_priv = obj->driver_private;
1968
1969         ret = i915_gem_object_pin(obj, args->alignment);
1970         if (ret != 0) {
1971                 drm_gem_object_unreference(obj);
1972                 mutex_unlock(&dev->struct_mutex);
1973                 return ret;
1974         }
1975
1976         /** XXX - flush the CPU caches for pinned objects
1977          * as the X server doesn't manage domains yet
1978          */
1979         if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
1980                 i915_gem_clflush_object(obj);
1981                 drm_agp_chipset_flush(dev);
1982                 obj->write_domain = 0;
1983         }
1984         args->offset = obj_priv->gtt_offset;
1985         drm_gem_object_unreference(obj);
1986         mutex_unlock(&dev->struct_mutex);
1987
1988         return 0;
1989 }
1990
1991 int
1992 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1993                      struct drm_file *file_priv)
1994 {
1995         struct drm_i915_gem_pin *args = data;
1996         struct drm_gem_object *obj;
1997
1998         mutex_lock(&dev->struct_mutex);
1999
2000         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2001         if (obj == NULL) {
2002                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2003                           args->handle);
2004                 mutex_unlock(&dev->struct_mutex);
2005                 return -EINVAL;
2006         }
2007
2008         i915_gem_object_unpin(obj);
2009
2010         drm_gem_object_unreference(obj);
2011         mutex_unlock(&dev->struct_mutex);
2012         return 0;
2013 }
2014
2015 int
2016 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2017                     struct drm_file *file_priv)
2018 {
2019         struct drm_i915_gem_busy *args = data;
2020         struct drm_gem_object *obj;
2021         struct drm_i915_gem_object *obj_priv;
2022
2023         mutex_lock(&dev->struct_mutex);
2024         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2025         if (obj == NULL) {
2026                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2027                           args->handle);
2028                 mutex_unlock(&dev->struct_mutex);
2029                 return -EINVAL;
2030         }
2031
2032         obj_priv = obj->driver_private;
2033         args->busy = obj_priv->active;
2034
2035         drm_gem_object_unreference(obj);
2036         mutex_unlock(&dev->struct_mutex);
2037         return 0;
2038 }
2039
2040 int
2041 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2042                         struct drm_file *file_priv)
2043 {
2044     return i915_gem_ring_throttle(dev, file_priv);
2045 }
2046
2047 int i915_gem_init_object(struct drm_gem_object *obj)
2048 {
2049         struct drm_i915_gem_object *obj_priv;
2050
2051         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2052         if (obj_priv == NULL)
2053                 return -ENOMEM;
2054
2055         /*
2056          * We've just allocated pages from the kernel,
2057          * so they've just been written by the CPU with
2058          * zeros. They'll need to be clflushed before we
2059          * use them with the GPU.
2060          */
2061         obj->write_domain = I915_GEM_DOMAIN_CPU;
2062         obj->read_domains = I915_GEM_DOMAIN_CPU;
2063
2064         obj->driver_private = obj_priv;
2065         obj_priv->obj = obj;
2066         INIT_LIST_HEAD(&obj_priv->list);
2067         return 0;
2068 }
2069
2070 void i915_gem_free_object(struct drm_gem_object *obj)
2071 {
2072         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2073
2074         while (obj_priv->pin_count > 0)
2075                 i915_gem_object_unpin(obj);
2076
2077         i915_gem_object_unbind(obj);
2078
2079         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2080 }
2081
2082 int
2083 i915_gem_set_domain(struct drm_gem_object *obj,
2084                     struct drm_file *file_priv,
2085                     uint32_t read_domains,
2086                     uint32_t write_domain)
2087 {
2088         struct drm_device *dev = obj->dev;
2089         int ret;
2090         uint32_t flush_domains;
2091
2092         BUG_ON(!mutex_is_locked(&dev->struct_mutex));
2093
2094         ret = i915_gem_object_set_domain(obj, read_domains, write_domain);
2095         if (ret)
2096                 return ret;
2097         flush_domains = i915_gem_dev_set_domain(obj->dev);
2098
2099         if (flush_domains & ~I915_GEM_DOMAIN_CPU)
2100                 (void) i915_add_request(dev, flush_domains);
2101
2102         return 0;
2103 }
2104
2105 /** Unbinds all objects that are on the given buffer list. */
2106 static int
2107 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2108 {
2109         struct drm_gem_object *obj;
2110         struct drm_i915_gem_object *obj_priv;
2111         int ret;
2112
2113         while (!list_empty(head)) {
2114                 obj_priv = list_first_entry(head,
2115                                             struct drm_i915_gem_object,
2116                                             list);
2117                 obj = obj_priv->obj;
2118
2119                 if (obj_priv->pin_count != 0) {
2120                         DRM_ERROR("Pinned object in unbind list\n");
2121                         mutex_unlock(&dev->struct_mutex);
2122                         return -EINVAL;
2123                 }
2124
2125                 ret = i915_gem_object_unbind(obj);
2126                 if (ret != 0) {
2127                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2128                                   ret);
2129                         mutex_unlock(&dev->struct_mutex);
2130                         return ret;
2131                 }
2132         }
2133
2134
2135         return 0;
2136 }
2137
2138 static int
2139 i915_gem_idle(struct drm_device *dev)
2140 {
2141         drm_i915_private_t *dev_priv = dev->dev_private;
2142         uint32_t seqno;
2143         int ret;
2144
2145         if (dev_priv->mm.suspended)
2146                 return 0;
2147
2148         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
2149          * We need to replace this with a semaphore, or something.
2150          */
2151         dev_priv->mm.suspended = 1;
2152
2153         i915_kernel_lost_context(dev);
2154
2155         /* Flush the GPU along with all non-CPU write domains
2156          */
2157         i915_gem_flush(dev, ~I915_GEM_DOMAIN_CPU, ~I915_GEM_DOMAIN_CPU);
2158         seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
2159
2160         if (seqno == 0) {
2161                 mutex_unlock(&dev->struct_mutex);
2162                 return -ENOMEM;
2163         }
2164         ret = i915_wait_request(dev, seqno);
2165         if (ret) {
2166                 mutex_unlock(&dev->struct_mutex);
2167                 return ret;
2168         }
2169
2170         /* Active and flushing should now be empty as we've
2171          * waited for a sequence higher than any pending execbuffer
2172          */
2173         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2174         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2175
2176         /* Request should now be empty as we've also waited
2177          * for the last request in the list
2178          */
2179         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2180
2181         /* Move all buffers out of the GTT. */
2182         i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2183
2184         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2185         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2186         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2187         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2188         return 0;
2189 }
2190
2191 static int
2192 i915_gem_init_ringbuffer(struct drm_device *dev)
2193 {
2194         drm_i915_private_t *dev_priv = dev->dev_private;
2195         struct drm_gem_object *obj;
2196         struct drm_i915_gem_object *obj_priv;
2197         int ret;
2198
2199         obj = drm_gem_object_alloc(dev, 128 * 1024);
2200         if (obj == NULL) {
2201                 DRM_ERROR("Failed to allocate ringbuffer\n");
2202                 return -ENOMEM;
2203         }
2204         obj_priv = obj->driver_private;
2205
2206         ret = i915_gem_object_pin(obj, 4096);
2207         if (ret != 0) {
2208                 drm_gem_object_unreference(obj);
2209                 return ret;
2210         }
2211
2212         /* Set up the kernel mapping for the ring. */
2213         dev_priv->ring.Size = obj->size;
2214         dev_priv->ring.tail_mask = obj->size - 1;
2215
2216         dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset;
2217         dev_priv->ring.map.size = obj->size;
2218         dev_priv->ring.map.type = 0;
2219         dev_priv->ring.map.flags = 0;
2220         dev_priv->ring.map.mtrr = 0;
2221
2222         drm_core_ioremap(&dev_priv->ring.map, dev);
2223         if (dev_priv->ring.map.handle == NULL) {
2224                 DRM_ERROR("Failed to map ringbuffer.\n");
2225                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2226                 drm_gem_object_unreference(obj);
2227                 return -EINVAL;
2228         }
2229         dev_priv->ring.ring_obj = obj;
2230         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
2231
2232         /* Stop the ring if it's running. */
2233         I915_WRITE(LP_RING + RING_LEN, 0);
2234         I915_WRITE(LP_RING + RING_HEAD, 0);
2235         I915_WRITE(LP_RING + RING_TAIL, 0);
2236         I915_WRITE(LP_RING + RING_START, 0);
2237
2238         /* Initialize the ring. */
2239         I915_WRITE(LP_RING + RING_START, obj_priv->gtt_offset);
2240         I915_WRITE(LP_RING + RING_LEN,
2241                    ((obj->size - 4096) & RING_NR_PAGES) |
2242                    RING_NO_REPORT |
2243                    RING_VALID);
2244
2245         /* Update our cache of the ring state */
2246         i915_kernel_lost_context(dev);
2247
2248         return 0;
2249 }
2250
2251 static void
2252 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2253 {
2254         drm_i915_private_t *dev_priv = dev->dev_private;
2255
2256         if (dev_priv->ring.ring_obj == NULL)
2257                 return;
2258
2259         drm_core_ioremapfree(&dev_priv->ring.map, dev);
2260
2261         i915_gem_object_unpin(dev_priv->ring.ring_obj);
2262         drm_gem_object_unreference(dev_priv->ring.ring_obj);
2263
2264         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2265 }
2266
2267 int
2268 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2269                        struct drm_file *file_priv)
2270 {
2271         drm_i915_private_t *dev_priv = dev->dev_private;
2272         int ret;
2273
2274         ret = i915_gem_init_ringbuffer(dev);
2275         if (ret != 0)
2276                 return ret;
2277
2278         mutex_lock(&dev->struct_mutex);
2279         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2280         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2281         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2282         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2283         dev_priv->mm.suspended = 0;
2284         mutex_unlock(&dev->struct_mutex);
2285         return 0;
2286 }
2287
2288 int
2289 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2290                        struct drm_file *file_priv)
2291 {
2292         int ret;
2293
2294         mutex_lock(&dev->struct_mutex);
2295         ret = i915_gem_idle(dev);
2296         if (ret == 0)
2297                 i915_gem_cleanup_ringbuffer(dev);
2298         mutex_unlock(&dev->struct_mutex);
2299
2300         return 0;
2301 }
2302
2303 static int i915_gem_active_info(char *buf, char **start, off_t offset,
2304                                 int request, int *eof, void *data)
2305 {
2306         struct drm_minor *minor = (struct drm_minor *) data;
2307         struct drm_device *dev = minor->dev;
2308         drm_i915_private_t *dev_priv = dev->dev_private;
2309         struct drm_i915_gem_object *obj_priv;
2310         int len = 0;
2311
2312         if (offset > DRM_PROC_LIMIT) {
2313                 *eof = 1;
2314                 return 0;
2315         }
2316
2317         *start = &buf[offset];
2318         *eof = 0;
2319         DRM_PROC_PRINT("Active:\n");
2320         list_for_each_entry(obj_priv, &dev_priv->mm.active_list,
2321                             list)
2322         {
2323                 struct drm_gem_object *obj = obj_priv->obj;
2324                 if (obj->name) {
2325                         DRM_PROC_PRINT("    %p(%d): %08x %08x %d\n",
2326                                        obj, obj->name,
2327                                        obj->read_domains, obj->write_domain,
2328                                        obj_priv->last_rendering_seqno);
2329                 } else {
2330                         DRM_PROC_PRINT("       %p: %08x %08x %d\n",
2331                                        obj,
2332                                        obj->read_domains, obj->write_domain,
2333                                        obj_priv->last_rendering_seqno);
2334                 }
2335         }
2336         if (len > request + offset)
2337                 return request;
2338         *eof = 1;
2339         return len - offset;
2340 }
2341
2342 static int i915_gem_flushing_info(char *buf, char **start, off_t offset,
2343                                   int request, int *eof, void *data)
2344 {
2345         struct drm_minor *minor = (struct drm_minor *) data;
2346         struct drm_device *dev = minor->dev;
2347         drm_i915_private_t *dev_priv = dev->dev_private;
2348         struct drm_i915_gem_object *obj_priv;
2349         int len = 0;
2350
2351         if (offset > DRM_PROC_LIMIT) {
2352                 *eof = 1;
2353                 return 0;
2354         }
2355
2356         *start = &buf[offset];
2357         *eof = 0;
2358         DRM_PROC_PRINT("Flushing:\n");
2359         list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list,
2360                             list)
2361         {
2362                 struct drm_gem_object *obj = obj_priv->obj;
2363                 if (obj->name) {
2364                         DRM_PROC_PRINT("    %p(%d): %08x %08x %d\n",
2365                                        obj, obj->name,
2366                                        obj->read_domains, obj->write_domain,
2367                                        obj_priv->last_rendering_seqno);
2368                 } else {
2369                         DRM_PROC_PRINT("       %p: %08x %08x %d\n", obj,
2370                                        obj->read_domains, obj->write_domain,
2371                                        obj_priv->last_rendering_seqno);
2372                 }
2373         }
2374         if (len > request + offset)
2375                 return request;
2376         *eof = 1;
2377         return len - offset;
2378 }
2379
2380 static int i915_gem_inactive_info(char *buf, char **start, off_t offset,
2381                                   int request, int *eof, void *data)
2382 {
2383         struct drm_minor *minor = (struct drm_minor *) data;
2384         struct drm_device *dev = minor->dev;
2385         drm_i915_private_t *dev_priv = dev->dev_private;
2386         struct drm_i915_gem_object *obj_priv;
2387         int len = 0;
2388
2389         if (offset > DRM_PROC_LIMIT) {
2390                 *eof = 1;
2391                 return 0;
2392         }
2393
2394         *start = &buf[offset];
2395         *eof = 0;
2396         DRM_PROC_PRINT("Inactive:\n");
2397         list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list,
2398                             list)
2399         {
2400                 struct drm_gem_object *obj = obj_priv->obj;
2401                 if (obj->name) {
2402                         DRM_PROC_PRINT("    %p(%d): %08x %08x %d\n",
2403                                        obj, obj->name,
2404                                        obj->read_domains, obj->write_domain,
2405                                        obj_priv->last_rendering_seqno);
2406                 } else {
2407                         DRM_PROC_PRINT("       %p: %08x %08x %d\n", obj,
2408                                        obj->read_domains, obj->write_domain,
2409                                        obj_priv->last_rendering_seqno);
2410                 }
2411         }
2412         if (len > request + offset)
2413                 return request;
2414         *eof = 1;
2415         return len - offset;
2416 }
2417
2418 static int i915_gem_request_info(char *buf, char **start, off_t offset,
2419                                  int request, int *eof, void *data)
2420 {
2421         struct drm_minor *minor = (struct drm_minor *) data;
2422         struct drm_device *dev = minor->dev;
2423         drm_i915_private_t *dev_priv = dev->dev_private;
2424         struct drm_i915_gem_request *gem_request;
2425         int len = 0;
2426
2427         if (offset > DRM_PROC_LIMIT) {
2428                 *eof = 1;
2429                 return 0;
2430         }
2431
2432         *start = &buf[offset];
2433         *eof = 0;
2434         DRM_PROC_PRINT("Request:\n");
2435         list_for_each_entry(gem_request, &dev_priv->mm.request_list,
2436                             list)
2437         {
2438                 DRM_PROC_PRINT ("    %d @ %d %08x\n",
2439                                 gem_request->seqno,
2440                                 (int) (jiffies - gem_request->emitted_jiffies),
2441                                 gem_request->flush_domains);
2442         }
2443         if (len > request + offset)
2444                 return request;
2445         *eof = 1;
2446         return len - offset;
2447 }
2448
2449 static int i915_gem_seqno_info(char *buf, char **start, off_t offset,
2450                                int request, int *eof, void *data)
2451 {
2452         struct drm_minor *minor = (struct drm_minor *) data;
2453         struct drm_device *dev = minor->dev;
2454         drm_i915_private_t *dev_priv = dev->dev_private;
2455         int len = 0;
2456
2457         if (offset > DRM_PROC_LIMIT) {
2458                 *eof = 1;
2459                 return 0;
2460         }
2461
2462         *start = &buf[offset];
2463         *eof = 0;
2464         DRM_PROC_PRINT("Current sequence: %d\n", i915_get_gem_seqno(dev));
2465         DRM_PROC_PRINT("Waiter sequence:  %d\n", dev_priv->mm.waiting_gem_seqno);
2466         DRM_PROC_PRINT("IRQ sequence:     %d\n", dev_priv->mm.irq_gem_seqno);
2467         if (len > request + offset)
2468                 return request;
2469         *eof = 1;
2470         return len - offset;
2471 }
2472
2473
2474 static struct drm_proc_list {
2475         const char *name;       /**< file name */
2476         int (*f) (char *, char **, off_t, int, int *, void *);          /**< proc callback*/
2477 } i915_gem_proc_list[] = {
2478         {"gem_active", i915_gem_active_info},
2479         {"gem_flushing", i915_gem_flushing_info},
2480         {"gem_inactive", i915_gem_inactive_info},
2481         {"gem_request", i915_gem_request_info},
2482         {"gem_seqno", i915_gem_seqno_info},
2483 };
2484
2485 #define I915_GEM_PROC_ENTRIES ARRAY_SIZE(i915_gem_proc_list)
2486
2487 int i915_gem_proc_init(struct drm_minor *minor)
2488 {
2489         struct proc_dir_entry *ent;
2490         int i, j;
2491
2492         for (i = 0; i < I915_GEM_PROC_ENTRIES; i++) {
2493                 ent = create_proc_entry(i915_gem_proc_list[i].name,
2494                                         S_IFREG | S_IRUGO, minor->dev_root);
2495                 if (!ent) {
2496                         DRM_ERROR("Cannot create /proc/dri/.../%s\n",
2497                                   i915_gem_proc_list[i].name);
2498                         for (j = 0; j < i; j++)
2499                                 remove_proc_entry(i915_gem_proc_list[i].name,
2500                                                   minor->dev_root);
2501                         return -1;
2502                 }
2503                 ent->read_proc = i915_gem_proc_list[i].f;
2504                 ent->data = minor;
2505         }
2506         return 0;
2507 }
2508
2509 void i915_gem_proc_cleanup(struct drm_minor *minor)
2510 {
2511         int i;
2512
2513         if (!minor->dev_root)
2514                 return;
2515
2516         for (i = 0; i < I915_GEM_PROC_ENTRIES; i++)
2517                 remove_proc_entry(i915_gem_proc_list[i].name, minor->dev_root);
2518 }
2519
2520 void
2521 i915_gem_lastclose(struct drm_device *dev)
2522 {
2523         int ret;
2524
2525         mutex_lock(&dev->struct_mutex);
2526
2527         ret = i915_gem_idle(dev);
2528         if (ret)
2529                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2530
2531         i915_gem_cleanup_ringbuffer(dev);
2532
2533         mutex_unlock(&dev->struct_mutex);
2534 }