2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
33 #define WATCH_COHERENCY 0
38 #define WATCH_INACTIVE 0
41 i915_gem_object_set_domain(struct drm_gem_object *obj,
42 uint32_t read_domains,
43 uint32_t write_domain);
45 i915_gem_set_domain(struct drm_gem_object *obj,
46 struct drm_file *file_priv,
47 uint32_t read_domains,
48 uint32_t write_domain);
51 i915_gem_clflush_object(struct drm_gem_object *obj);
54 i915_gem_init_ioctl(struct drm_device *dev, void *data,
55 struct drm_file *file_priv)
57 drm_i915_private_t *dev_priv = dev->dev_private;
58 struct drm_i915_gem_init *args = data;
60 mutex_lock(&dev->struct_mutex);
62 if (args->gtt_start >= args->gtt_end ||
63 (args->gtt_start & (PAGE_SIZE - 1)) != 0 ||
64 (args->gtt_end & (PAGE_SIZE - 1)) != 0) {
65 mutex_unlock(&dev->struct_mutex);
69 drm_memrange_init(&dev_priv->mm.gtt_space, args->gtt_start,
70 args->gtt_end - args->gtt_start);
72 dev->gtt_total = (uint32_t) (args->gtt_end - args->gtt_start);
74 mutex_unlock(&dev->struct_mutex);
81 * Creates a new mm object and returns a handle to it.
84 i915_gem_create_ioctl(struct drm_device *dev, void *data,
85 struct drm_file *file_priv)
87 struct drm_i915_gem_create *args = data;
88 struct drm_gem_object *obj;
91 args->size = roundup(args->size, PAGE_SIZE);
93 /* Allocate the new object */
94 obj = drm_gem_object_alloc(dev, args->size);
98 ret = drm_gem_handle_create(file_priv, obj, &handle);
99 mutex_lock(&dev->struct_mutex);
100 drm_gem_object_handle_unreference(obj);
101 mutex_unlock(&dev->struct_mutex);
106 args->handle = handle;
112 * Reads data from the object referenced by handle.
114 * On error, the contents of *data are undefined.
117 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
118 struct drm_file *file_priv)
120 struct drm_i915_gem_pread *args = data;
121 struct drm_gem_object *obj;
126 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
130 mutex_lock(&dev->struct_mutex);
131 ret = i915_gem_set_domain(obj, file_priv,
132 I915_GEM_DOMAIN_CPU, 0);
134 drm_gem_object_unreference(obj);
135 mutex_unlock(&dev->struct_mutex);
138 offset = args->offset;
140 read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
141 args->size, &offset);
142 if (read != args->size) {
143 drm_gem_object_unreference(obj);
144 mutex_unlock(&dev->struct_mutex);
151 drm_gem_object_unreference(obj);
152 mutex_unlock(&dev->struct_mutex);
158 * Writes data to the object referenced by handle.
160 * On error, the contents of the buffer that were to be modified are undefined.
163 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
164 struct drm_file *file_priv)
166 struct drm_i915_gem_pwrite *args = data;
167 struct drm_gem_object *obj;
172 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
176 mutex_lock(&dev->struct_mutex);
177 ret = i915_gem_set_domain(obj, file_priv,
178 I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
180 drm_gem_object_unreference(obj);
181 mutex_unlock(&dev->struct_mutex);
184 offset = args->offset;
186 written = vfs_write(obj->filp,
187 (char __user *)(uintptr_t) args->data_ptr,
188 args->size, &offset);
190 if (written != args->size) {
191 drm_gem_object_unreference(obj);
192 mutex_unlock(&dev->struct_mutex);
199 drm_gem_object_unreference(obj);
200 mutex_unlock(&dev->struct_mutex);
206 * Called when user space prepares to use an object
209 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
210 struct drm_file *file_priv)
212 struct drm_i915_gem_set_domain *args = data;
213 struct drm_gem_object *obj;
216 if (!(dev->driver->driver_features & DRIVER_GEM))
219 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
223 mutex_lock(&dev->struct_mutex);
224 ret = i915_gem_set_domain(obj, file_priv,
225 args->read_domains, args->write_domain);
226 drm_gem_object_unreference(obj);
227 mutex_unlock(&dev->struct_mutex);
232 * Called when user space has done writes to this buffer
235 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
236 struct drm_file *file_priv)
238 struct drm_i915_gem_sw_finish *args = data;
239 struct drm_gem_object *obj;
240 struct drm_i915_gem_object *obj_priv;
243 if (!(dev->driver->driver_features & DRIVER_GEM))
246 mutex_lock(&dev->struct_mutex);
247 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
249 mutex_unlock(&dev->struct_mutex);
254 DRM_INFO("%s: sw_finish %d (%p)\n",
255 __func__, args->handle, obj);
257 obj_priv = obj->driver_private;
259 /** Pinned buffers may be scanout, so flush the cache
261 if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) {
262 i915_gem_clflush_object(obj);
263 drm_agp_chipset_flush(dev);
265 drm_gem_object_unreference(obj);
266 mutex_unlock(&dev->struct_mutex);
271 * Maps the contents of an object, returning the address it is mapped
274 * While the mapping holds a reference on the contents of the object, it doesn't
275 * imply a ref on the object itself.
278 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
279 struct drm_file *file_priv)
281 struct drm_i915_gem_mmap *args = data;
282 struct drm_gem_object *obj;
286 if (!(dev->driver->driver_features & DRIVER_GEM))
289 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
293 offset = args->offset;
295 down_write(¤t->mm->mmap_sem);
296 addr = do_mmap(obj->filp, 0, args->size,
297 PROT_READ | PROT_WRITE, MAP_SHARED,
299 up_write(¤t->mm->mmap_sem);
300 mutex_lock(&dev->struct_mutex);
301 drm_gem_object_unreference(obj);
302 mutex_unlock(&dev->struct_mutex);
303 if (IS_ERR((void *)addr))
306 args->addr_ptr = (uint64_t) addr;
312 i915_gem_object_free_page_list(struct drm_gem_object *obj)
314 struct drm_i915_gem_object *obj_priv = obj->driver_private;
315 int page_count = obj->size / PAGE_SIZE;
318 if (obj_priv->page_list == NULL)
322 for (i = 0; i < page_count; i++)
323 if (obj_priv->page_list[i] != NULL) {
325 set_page_dirty(obj_priv->page_list[i]);
326 mark_page_accessed(obj_priv->page_list[i]);
327 page_cache_release(obj_priv->page_list[i]);
331 drm_free(obj_priv->page_list,
332 page_count * sizeof(struct page *),
334 obj_priv->page_list = NULL;
338 i915_gem_object_move_to_active(struct drm_gem_object *obj)
340 struct drm_device *dev = obj->dev;
341 drm_i915_private_t *dev_priv = dev->dev_private;
342 struct drm_i915_gem_object *obj_priv = obj->driver_private;
344 /* Add a reference if we're newly entering the active list. */
345 if (!obj_priv->active) {
346 drm_gem_object_reference(obj);
347 obj_priv->active = 1;
349 /* Move from whatever list we were on to the tail of execution. */
350 list_move_tail(&obj_priv->list,
351 &dev_priv->mm.active_list);
356 i915_verify_inactive(struct drm_device *dev, char *file, int line)
358 drm_i915_private_t *dev_priv = dev->dev_private;
359 struct drm_gem_object *obj;
360 struct drm_i915_gem_object *obj_priv;
362 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
364 if (obj_priv->pin_count || obj_priv->active || (obj->write_domain & ~I915_GEM_DOMAIN_CPU))
365 DRM_ERROR("inactive %p (p %d a %d w %x) %s:%d\n",
367 obj_priv->pin_count, obj_priv->active, obj->write_domain, file, line);
371 #define i915_verify_inactive(dev,file,line)
375 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
377 struct drm_device *dev = obj->dev;
378 drm_i915_private_t *dev_priv = dev->dev_private;
379 struct drm_i915_gem_object *obj_priv = obj->driver_private;
381 i915_verify_inactive(dev, __FILE__, __LINE__);
382 if (obj_priv->pin_count != 0)
383 list_del_init(&obj_priv->list);
385 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
387 if (obj_priv->active) {
388 obj_priv->active = 0;
389 drm_gem_object_unreference(obj);
391 i915_verify_inactive(dev, __FILE__, __LINE__);
395 * Creates a new sequence number, emitting a write of it to the status page
396 * plus an interrupt, which will trigger i915_user_interrupt_handler.
398 * Must be called with struct_lock held.
400 * Returned sequence numbers are nonzero on success.
403 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
405 drm_i915_private_t *dev_priv = dev->dev_private;
406 struct drm_i915_gem_request *request;
411 request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
415 /* Grab the seqno we're going to make this request be, and bump the
416 * next (skipping 0 so it can be the reserved no-seqno value).
418 seqno = dev_priv->mm.next_gem_seqno;
419 dev_priv->mm.next_gem_seqno++;
420 if (dev_priv->mm.next_gem_seqno == 0)
421 dev_priv->mm.next_gem_seqno++;
424 OUT_RING(CMD_STORE_DWORD_IDX);
425 OUT_RING(I915_GEM_HWS_INDEX << STORE_DWORD_INDEX_SHIFT);
428 OUT_RING(GFX_OP_USER_INTERRUPT);
431 DRM_DEBUG("%d\n", seqno);
433 request->seqno = seqno;
434 request->emitted_jiffies = jiffies;
435 request->flush_domains = flush_domains;
436 was_empty = list_empty(&dev_priv->mm.request_list);
437 list_add_tail(&request->list, &dev_priv->mm.request_list);
440 schedule_delayed_work (&dev_priv->mm.retire_work, HZ);
445 * Command execution barrier
447 * Ensures that all commands in the ring are finished
448 * before signalling the CPU
452 i915_retire_commands(struct drm_device *dev)
454 drm_i915_private_t *dev_priv = dev->dev_private;
455 uint32_t cmd = CMD_MI_FLUSH | MI_NO_WRITE_FLUSH;
456 uint32_t flush_domains = 0;
459 /* The sampler always gets flushed on i965 (sigh) */
461 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
464 OUT_RING(0); /* noop */
466 return flush_domains;
470 * Moves buffers associated only with the given active seqno from the active
471 * to inactive list, potentially freeing them.
474 i915_gem_retire_request(struct drm_device *dev,
475 struct drm_i915_gem_request *request)
477 drm_i915_private_t *dev_priv = dev->dev_private;
479 if (request->flush_domains != 0) {
480 struct drm_i915_gem_object *obj_priv, *next;
482 /* First clear any buffers that were only waiting for a flush
483 * matching the one just retired.
486 list_for_each_entry_safe(obj_priv, next,
487 &dev_priv->mm.flushing_list, list) {
488 struct drm_gem_object *obj = obj_priv->obj;
490 if (obj->write_domain & request->flush_domains) {
491 obj->write_domain = 0;
492 i915_gem_object_move_to_inactive(obj);
498 /* Move any buffers on the active list that are no longer referenced
499 * by the ringbuffer to the flushing/inactive lists as appropriate.
501 while (!list_empty(&dev_priv->mm.active_list)) {
502 struct drm_gem_object *obj;
503 struct drm_i915_gem_object *obj_priv;
505 obj_priv = list_first_entry(&dev_priv->mm.active_list,
506 struct drm_i915_gem_object,
510 /* If the seqno being retired doesn't match the oldest in the
511 * list, then the oldest in the list must still be newer than
514 if (obj_priv->last_rendering_seqno != request->seqno)
517 DRM_INFO("%s: retire %d moves to inactive list %p\n",
518 __func__, request->seqno, obj);
521 if (obj->write_domain != 0) {
522 list_move_tail(&obj_priv->list,
523 &dev_priv->mm.flushing_list);
525 i915_gem_object_move_to_inactive(obj);
531 * Returns true if seq1 is later than seq2.
534 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
536 return (int32_t)(seq1 - seq2) >= 0;
540 i915_get_gem_seqno(struct drm_device *dev)
542 drm_i915_private_t *dev_priv = dev->dev_private;
544 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
548 * This function clears the request list as sequence numbers are passed.
551 i915_gem_retire_requests(struct drm_device *dev)
553 drm_i915_private_t *dev_priv = dev->dev_private;
556 seqno = i915_get_gem_seqno(dev);
558 while (!list_empty(&dev_priv->mm.request_list)) {
559 struct drm_i915_gem_request *request;
560 uint32_t retiring_seqno;
562 request = list_first_entry(&dev_priv->mm.request_list,
563 struct drm_i915_gem_request,
565 retiring_seqno = request->seqno;
567 if (i915_seqno_passed(seqno, retiring_seqno)) {
568 i915_gem_retire_request(dev, request);
570 list_del(&request->list);
571 drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
578 i915_gem_retire_work_handler(struct work_struct *work)
580 drm_i915_private_t *dev_priv;
581 struct drm_device *dev;
583 dev_priv = container_of(work, drm_i915_private_t,
584 mm.retire_work.work);
587 mutex_lock(&dev->struct_mutex);
588 i915_gem_retire_requests(dev);
589 if (!list_empty(&dev_priv->mm.request_list))
590 schedule_delayed_work (&dev_priv->mm.retire_work, HZ);
591 mutex_unlock(&dev->struct_mutex);
595 * Waits for a sequence number to be signaled, and cleans up the
596 * request and object lists appropriately for that event.
599 i915_wait_request(struct drm_device *dev, uint32_t seqno)
601 drm_i915_private_t *dev_priv = dev->dev_private;
606 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
607 dev_priv->mm.waiting_gem_seqno = seqno;
608 i915_user_irq_on(dev_priv);
609 ret = wait_event_interruptible(dev_priv->irq_queue,
610 i915_seqno_passed(i915_get_gem_seqno(dev),
612 i915_user_irq_off(dev_priv);
613 dev_priv->mm.waiting_gem_seqno = 0;
616 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
617 __func__, ret, seqno, i915_get_gem_seqno(dev));
619 /* Directly dispatch request retiring. While we have the work queue
620 * to handle this, the waiter on a request often wants an associated
621 * buffer to have made it to the inactive list, and we would need
622 * a separate wait queue to handle that.
625 i915_gem_retire_requests(dev);
631 i915_gem_flush(struct drm_device *dev,
632 uint32_t invalidate_domains,
633 uint32_t flush_domains)
635 drm_i915_private_t *dev_priv = dev->dev_private;
640 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
641 invalidate_domains, flush_domains);
644 if (flush_domains & I915_GEM_DOMAIN_CPU)
645 drm_agp_chipset_flush(dev);
647 if ((invalidate_domains|flush_domains) & ~I915_GEM_DOMAIN_CPU) {
651 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
652 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
653 * also flushed at 2d versus 3d pipeline switches.
657 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
658 * MI_READ_FLUSH is set, and is always flushed on 965.
660 * I915_GEM_DOMAIN_COMMAND may not exist?
662 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
663 * invalidated when MI_EXE_FLUSH is set.
665 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
666 * invalidated with every MI_FLUSH.
670 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
671 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
672 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
673 * are flushed at any MI_FLUSH.
676 cmd = CMD_MI_FLUSH | MI_NO_WRITE_FLUSH;
677 if ((invalidate_domains|flush_domains) &
678 I915_GEM_DOMAIN_RENDER)
679 cmd &= ~MI_NO_WRITE_FLUSH;
680 if (!IS_I965G(dev)) {
682 * On the 965, the sampler cache always gets flushed
683 * and this bit is reserved.
685 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
686 cmd |= MI_READ_FLUSH;
688 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
692 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
696 OUT_RING(0); /* noop */
702 * Ensures that all rendering to the object has completed and the object is
703 * safe to unbind from the GTT or access from the CPU.
706 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
708 struct drm_device *dev = obj->dev;
709 struct drm_i915_gem_object *obj_priv = obj->driver_private;
712 /* If there are writes queued to the buffer, flush and
713 * create a new seqno to wait for.
715 if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU)) {
716 uint32_t write_domain = obj->write_domain;
718 DRM_INFO("%s: flushing object %p from write domain %08x\n",
719 __func__, obj, write_domain);
721 i915_gem_flush(dev, 0, write_domain);
722 obj->write_domain = 0;
724 i915_gem_object_move_to_active(obj);
725 obj_priv->last_rendering_seqno = i915_add_request(dev,
727 BUG_ON(obj_priv->last_rendering_seqno == 0);
729 DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj);
732 /* If there is rendering queued on the buffer being evicted, wait for
735 if (obj_priv->active) {
737 DRM_INFO("%s: object %p wait for seqno %08x\n",
738 __func__, obj, obj_priv->last_rendering_seqno);
740 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
749 * Unbinds an object from the GTT aperture.
752 i915_gem_object_unbind(struct drm_gem_object *obj)
754 struct drm_device *dev = obj->dev;
755 struct drm_i915_gem_object *obj_priv = obj->driver_private;
759 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
760 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
762 if (obj_priv->gtt_space == NULL)
765 if (obj_priv->pin_count != 0) {
766 DRM_ERROR("Attempting to unbind pinned buffer\n");
770 /* Wait for any rendering to complete
772 ret = i915_gem_object_wait_rendering(obj);
774 DRM_ERROR ("wait_rendering failed: %d\n", ret);
778 /* Move the object to the CPU domain to ensure that
779 * any possible CPU writes while it's not in the GTT
780 * are flushed when we go to remap it. This will
781 * also ensure that all pending GPU writes are finished
784 ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU,
785 I915_GEM_DOMAIN_CPU);
787 DRM_ERROR("set_domain failed: %d\n", ret);
791 if (obj_priv->agp_mem != NULL) {
792 drm_unbind_agp(obj_priv->agp_mem);
793 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
794 obj_priv->agp_mem = NULL;
797 BUG_ON(obj_priv->active);
799 i915_gem_object_free_page_list(obj);
801 atomic_dec(&dev->gtt_count);
802 atomic_sub(obj->size, &dev->gtt_memory);
804 drm_memrange_put_block(obj_priv->gtt_space);
805 obj_priv->gtt_space = NULL;
807 /* Remove ourselves from the LRU list if present. */
808 if (!list_empty(&obj_priv->list))
809 list_del_init(&obj_priv->list);
814 #if WATCH_BUF | WATCH_EXEC
816 i915_gem_dump_page(struct page *page, uint32_t start, uint32_t end,
817 uint32_t bias, uint32_t mark)
819 uint32_t *mem = kmap_atomic(page, KM_USER0);
821 for (i = start; i < end; i += 4)
822 DRM_INFO("%08x: %08x%s\n",
823 (int) (bias + i), mem[i / 4],
824 (bias + i == mark) ? " ********" : "");
825 kunmap_atomic(mem, KM_USER0);
826 /* give syslog time to catch up */
831 i915_gem_dump_object(struct drm_gem_object *obj, int len,
832 const char *where, uint32_t mark)
834 struct drm_i915_gem_object *obj_priv = obj->driver_private;
837 DRM_INFO("%s: object at offset %08x\n", where, obj_priv->gtt_offset);
838 for (page = 0; page < (len + PAGE_SIZE-1) / PAGE_SIZE; page++) {
839 int page_len, chunk, chunk_len;
841 page_len = len - page * PAGE_SIZE;
842 if (page_len > PAGE_SIZE)
843 page_len = PAGE_SIZE;
845 for (chunk = 0; chunk < page_len; chunk += 128) {
846 chunk_len = page_len - chunk;
849 i915_gem_dump_page(obj_priv->page_list[page],
850 chunk, chunk + chunk_len,
851 obj_priv->gtt_offset +
861 i915_dump_lru(struct drm_device *dev, const char *where)
863 drm_i915_private_t *dev_priv = dev->dev_private;
864 struct drm_i915_gem_object *obj_priv;
866 DRM_INFO("active list %s {\n", where);
867 list_for_each_entry(obj_priv, &dev_priv->mm.active_list,
870 DRM_INFO(" %p: %08x\n", obj_priv,
871 obj_priv->last_rendering_seqno);
874 DRM_INFO("flushing list %s {\n", where);
875 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list,
878 DRM_INFO(" %p: %08x\n", obj_priv,
879 obj_priv->last_rendering_seqno);
882 DRM_INFO("inactive %s {\n", where);
883 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
884 DRM_INFO(" %p: %08x\n", obj_priv,
885 obj_priv->last_rendering_seqno);
892 i915_gem_evict_something(struct drm_device *dev)
894 drm_i915_private_t *dev_priv = dev->dev_private;
895 struct drm_gem_object *obj;
896 struct drm_i915_gem_object *obj_priv;
900 /* If there's an inactive buffer available now, grab it
903 if (!list_empty(&dev_priv->mm.inactive_list)) {
904 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
905 struct drm_i915_gem_object,
908 BUG_ON(obj_priv->pin_count != 0);
910 DRM_INFO("%s: evicting %p\n", __func__, obj);
912 BUG_ON(obj_priv->active);
914 /* Wait on the rendering and unbind the buffer. */
915 ret = i915_gem_object_unbind(obj);
919 /* If we didn't get anything, but the ring is still processing
920 * things, wait for one of those things to finish and hopefully
921 * leave us a buffer to evict.
923 if (!list_empty(&dev_priv->mm.request_list)) {
924 struct drm_i915_gem_request *request;
926 request = list_first_entry(&dev_priv->mm.request_list,
927 struct drm_i915_gem_request,
930 ret = i915_wait_request(dev, request->seqno);
932 /* if waiting caused an object to become inactive,
933 * then loop around and wait for it. Otherwise, we
934 * assume that waiting freed and unbound something,
935 * so there should now be some space in the GTT
937 if (!list_empty(&dev_priv->mm.inactive_list))
942 /* If we didn't have anything on the request list but there
943 * are buffers awaiting a flush, emit one and try again.
944 * When we wait on it, those buffers waiting for that flush
945 * will get moved to inactive.
947 if (!list_empty(&dev_priv->mm.flushing_list)) {
948 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
949 struct drm_i915_gem_object,
956 i915_add_request(dev, obj->write_domain);
962 DRM_ERROR("inactive empty %d request empty %d flushing empty %d\n",
963 list_empty(&dev_priv->mm.inactive_list),
964 list_empty(&dev_priv->mm.request_list),
965 list_empty(&dev_priv->mm.flushing_list));
966 /* If we didn't do any of the above, there's nothing to be done
967 * and we just can't fit it in.
975 i915_gem_object_get_page_list(struct drm_gem_object *obj)
977 struct drm_i915_gem_object *obj_priv = obj->driver_private;
979 struct address_space *mapping;
984 if (obj_priv->page_list)
987 /* Get the list of pages out of our struct file. They'll be pinned
988 * at this point until we release them.
990 page_count = obj->size / PAGE_SIZE;
991 BUG_ON(obj_priv->page_list != NULL);
992 obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
994 if (obj_priv->page_list == NULL) {
995 DRM_ERROR("Faled to allocate page list\n");
999 inode = obj->filp->f_path.dentry->d_inode;
1000 mapping = inode->i_mapping;
1001 for (i = 0; i < page_count; i++) {
1002 page = find_get_page(mapping, i);
1003 if (page == NULL || !PageUptodate(page)) {
1005 page_cache_release(page);
1008 ret = shmem_getpage(inode, i, &page, SGP_DIRTY, NULL);
1011 DRM_ERROR("shmem_getpage failed: %d\n", ret);
1012 i915_gem_object_free_page_list(obj);
1017 obj_priv->page_list[i] = page;
1023 * Finds free space in the GTT aperture and binds the object there.
1026 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1028 struct drm_device *dev = obj->dev;
1029 drm_i915_private_t *dev_priv = dev->dev_private;
1030 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1031 struct drm_memrange_node *free_space;
1032 int page_count, ret;
1035 alignment = PAGE_SIZE;
1036 if (alignment & (PAGE_SIZE - 1)) {
1037 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1042 free_space = drm_memrange_search_free(&dev_priv->mm.gtt_space,
1045 if (free_space != NULL) {
1046 obj_priv->gtt_space =
1047 drm_memrange_get_block(free_space, obj->size,
1049 if (obj_priv->gtt_space != NULL) {
1050 obj_priv->gtt_space->private = obj;
1051 obj_priv->gtt_offset = obj_priv->gtt_space->start;
1054 if (obj_priv->gtt_space == NULL) {
1055 /* If the gtt is empty and we're still having trouble
1056 * fitting our object in, we're out of memory.
1059 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1061 if (list_empty(&dev_priv->mm.inactive_list) &&
1062 list_empty(&dev_priv->mm.flushing_list) &&
1063 list_empty(&dev_priv->mm.active_list)) {
1064 DRM_ERROR("GTT full, but LRU list empty\n");
1068 ret = i915_gem_evict_something(dev);
1070 DRM_ERROR("Failed to evict a buffer %d\n", ret);
1077 DRM_INFO("Binding object of size %d at 0x%08x\n",
1078 obj->size, obj_priv->gtt_offset);
1080 ret = i915_gem_object_get_page_list(obj);
1082 drm_memrange_put_block(obj_priv->gtt_space);
1083 obj_priv->gtt_space = NULL;
1087 page_count = obj->size / PAGE_SIZE;
1088 /* Create an AGP memory structure pointing at our pages, and bind it
1091 obj_priv->agp_mem = drm_agp_bind_pages(dev,
1092 obj_priv->page_list,
1094 obj_priv->gtt_offset);
1095 if (obj_priv->agp_mem == NULL) {
1096 i915_gem_object_free_page_list(obj);
1097 drm_memrange_put_block(obj_priv->gtt_space);
1098 obj_priv->gtt_space = NULL;
1101 atomic_inc(&dev->gtt_count);
1102 atomic_add(obj->size, &dev->gtt_memory);
1104 /* Assert that the object is not currently in any GPU domain. As it
1105 * wasn't in the GTT, there shouldn't be any way it could have been in
1108 BUG_ON(obj->read_domains & ~I915_GEM_DOMAIN_CPU);
1109 BUG_ON(obj->write_domain & ~I915_GEM_DOMAIN_CPU);
1115 i915_gem_clflush_object(struct drm_gem_object *obj)
1117 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1119 /* If we don't have a page list set up, then we're not pinned
1120 * to GPU, and we can ignore the cache flush because it'll happen
1121 * again at bind time.
1123 if (obj_priv->page_list == NULL)
1126 drm_ttm_cache_flush(obj_priv->page_list, obj->size / PAGE_SIZE);
1130 * Set the next domain for the specified object. This
1131 * may not actually perform the necessary flushing/invaliding though,
1132 * as that may want to be batched with other set_domain operations
1134 * This is (we hope) the only really tricky part of gem. The goal
1135 * is fairly simple -- track which caches hold bits of the object
1136 * and make sure they remain coherent. A few concrete examples may
1137 * help to explain how it works. For shorthand, we use the notation
1138 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1139 * a pair of read and write domain masks.
1141 * Case 1: the batch buffer
1147 * 5. Unmapped from GTT
1150 * Let's take these a step at a time
1153 * Pages allocated from the kernel may still have
1154 * cache contents, so we set them to (CPU, CPU) always.
1155 * 2. Written by CPU (using pwrite)
1156 * The pwrite function calls set_domain (CPU, CPU) and
1157 * this function does nothing (as nothing changes)
1159 * This function asserts that the object is not
1160 * currently in any GPU-based read or write domains
1162 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
1163 * As write_domain is zero, this function adds in the
1164 * current read domains (CPU+COMMAND, 0).
1165 * flush_domains is set to CPU.
1166 * invalidate_domains is set to COMMAND
1167 * clflush is run to get data out of the CPU caches
1168 * then i915_dev_set_domain calls i915_gem_flush to
1169 * emit an MI_FLUSH and drm_agp_chipset_flush
1170 * 5. Unmapped from GTT
1171 * i915_gem_object_unbind calls set_domain (CPU, CPU)
1172 * flush_domains and invalidate_domains end up both zero
1173 * so no flushing/invalidating happens
1177 * Case 2: The shared render buffer
1181 * 3. Read/written by GPU
1182 * 4. set_domain to (CPU,CPU)
1183 * 5. Read/written by CPU
1184 * 6. Read/written by GPU
1187 * Same as last example, (CPU, CPU)
1189 * Nothing changes (assertions find that it is not in the GPU)
1190 * 3. Read/written by GPU
1191 * execbuffer calls set_domain (RENDER, RENDER)
1192 * flush_domains gets CPU
1193 * invalidate_domains gets GPU
1195 * MI_FLUSH and drm_agp_chipset_flush
1196 * 4. set_domain (CPU, CPU)
1197 * flush_domains gets GPU
1198 * invalidate_domains gets CPU
1199 * wait_rendering (obj) to make sure all drawing is complete.
1200 * This will include an MI_FLUSH to get the data from GPU
1202 * clflush (obj) to invalidate the CPU cache
1203 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1204 * 5. Read/written by CPU
1205 * cache lines are loaded and dirtied
1206 * 6. Read written by GPU
1207 * Same as last GPU access
1209 * Case 3: The constant buffer
1214 * 4. Updated (written) by CPU again
1223 * flush_domains = CPU
1224 * invalidate_domains = RENDER
1227 * drm_agp_chipset_flush
1228 * 4. Updated (written) by CPU again
1230 * flush_domains = 0 (no previous write domain)
1231 * invalidate_domains = 0 (no new read domains)
1234 * flush_domains = CPU
1235 * invalidate_domains = RENDER
1238 * drm_agp_chipset_flush
1241 i915_gem_object_set_domain(struct drm_gem_object *obj,
1242 uint32_t read_domains,
1243 uint32_t write_domain)
1245 struct drm_device *dev = obj->dev;
1246 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1247 uint32_t invalidate_domains = 0;
1248 uint32_t flush_domains = 0;
1252 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1254 obj->read_domains, read_domains,
1255 obj->write_domain, write_domain);
1258 * If the object isn't moving to a new write domain,
1259 * let the object stay in multiple read domains
1261 if (write_domain == 0)
1262 read_domains |= obj->read_domains;
1264 obj_priv->dirty = 1;
1267 * Flush the current write domain if
1268 * the new read domains don't match. Invalidate
1269 * any read domains which differ from the old
1272 if (obj->write_domain && obj->write_domain != read_domains) {
1273 flush_domains |= obj->write_domain;
1274 invalidate_domains |= read_domains & ~obj->write_domain;
1277 * Invalidate any read caches which may have
1278 * stale data. That is, any new read domains.
1280 invalidate_domains |= read_domains & ~obj->read_domains;
1281 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
1283 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1284 __func__, flush_domains, invalidate_domains);
1287 * If we're invaliding the CPU cache and flushing a GPU cache,
1288 * then pause for rendering so that the GPU caches will be
1289 * flushed before the cpu cache is invalidated
1291 if ((invalidate_domains & I915_GEM_DOMAIN_CPU) &&
1292 (flush_domains & ~I915_GEM_DOMAIN_CPU)) {
1293 ret = i915_gem_object_wait_rendering(obj);
1297 i915_gem_clflush_object(obj);
1300 if ((write_domain | flush_domains) != 0)
1301 obj->write_domain = write_domain;
1302 obj->read_domains = read_domains;
1303 dev->invalidate_domains |= invalidate_domains;
1304 dev->flush_domains |= flush_domains;
1306 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1308 obj->read_domains, obj->write_domain,
1309 dev->invalidate_domains, dev->flush_domains);
1315 * Once all of the objects have been set in the proper domain,
1316 * perform the necessary flush and invalidate operations.
1318 * Returns the write domains flushed, for use in flush tracking.
1321 i915_gem_dev_set_domain(struct drm_device *dev)
1323 uint32_t flush_domains = dev->flush_domains;
1326 * Now that all the buffers are synced to the proper domains,
1327 * flush and invalidate the collected domains
1329 if (dev->invalidate_domains | dev->flush_domains) {
1331 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
1333 dev->invalidate_domains,
1334 dev->flush_domains);
1337 dev->invalidate_domains,
1338 dev->flush_domains);
1339 dev->invalidate_domains = 0;
1340 dev->flush_domains = 0;
1343 return flush_domains;
1348 i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle)
1350 struct drm_device *dev = obj->dev;
1351 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1353 uint32_t *gtt_mapping;
1354 uint32_t *backing_map = NULL;
1357 DRM_INFO("%s: checking coherency of object %p@0x%08x (%d, %dkb):\n",
1358 __func__, obj, obj_priv->gtt_offset, handle,
1361 gtt_mapping = ioremap(dev->agp->base + obj_priv->gtt_offset,
1363 if (gtt_mapping == NULL) {
1364 DRM_ERROR("failed to map GTT space\n");
1368 for (page = 0; page < obj->size / PAGE_SIZE; page++) {
1371 backing_map = kmap_atomic(obj_priv->page_list[page], KM_USER0);
1373 if (backing_map == NULL) {
1374 DRM_ERROR("failed to map backing page\n");
1378 for (i = 0; i < PAGE_SIZE / 4; i++) {
1379 uint32_t cpuval = backing_map[i];
1380 uint32_t gttval = readl(gtt_mapping +
1383 if (cpuval != gttval) {
1384 DRM_INFO("incoherent CPU vs GPU at 0x%08x: "
1385 "0x%08x vs 0x%08x\n",
1386 (int)(obj_priv->gtt_offset +
1387 page * PAGE_SIZE + i * 4),
1389 if (bad_count++ >= 8) {
1395 kunmap_atomic(backing_map, KM_USER0);
1400 if (backing_map != NULL)
1401 kunmap_atomic(backing_map, KM_USER0);
1402 iounmap(gtt_mapping);
1404 /* give syslog time to catch up */
1407 /* Directly flush the object, since we just loaded values with the CPU
1408 * from thebacking pages and we don't want to disturb the cache
1409 * management that we're trying to observe.
1412 i915_gem_clflush_object(obj);
1417 * Pin an object to the GTT and evaluate the relocations landing in it.
1420 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1421 struct drm_file *file_priv,
1422 struct drm_i915_gem_exec_object *entry)
1424 struct drm_device *dev = obj->dev;
1425 struct drm_i915_gem_relocation_entry reloc;
1426 struct drm_i915_gem_relocation_entry __user *relocs;
1427 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1429 uint32_t last_reloc_offset = -1;
1430 void *reloc_page = NULL;
1432 /* Choose the GTT offset for our buffer and put it there. */
1433 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
1437 entry->offset = obj_priv->gtt_offset;
1439 relocs = (struct drm_i915_gem_relocation_entry __user *)
1440 (uintptr_t) entry->relocs_ptr;
1441 /* Apply the relocations, using the GTT aperture to avoid cache
1442 * flushing requirements.
1444 for (i = 0; i < entry->relocation_count; i++) {
1445 struct drm_gem_object *target_obj;
1446 struct drm_i915_gem_object *target_obj_priv;
1447 uint32_t reloc_val, reloc_offset, *reloc_entry;
1450 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
1452 i915_gem_object_unpin(obj);
1456 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
1457 reloc.target_handle);
1458 if (target_obj == NULL) {
1459 i915_gem_object_unpin(obj);
1462 target_obj_priv = target_obj->driver_private;
1464 /* The target buffer should have appeared before us in the
1465 * exec_object list, so it should have a GTT space bound by now.
1467 if (target_obj_priv->gtt_space == NULL) {
1468 DRM_ERROR("No GTT space found for object %d\n",
1469 reloc.target_handle);
1470 drm_gem_object_unreference(target_obj);
1471 i915_gem_object_unpin(obj);
1475 if (reloc.offset > obj->size - 4) {
1476 DRM_ERROR("Relocation beyond object bounds: "
1477 "obj %p target %d offset %d size %d.\n",
1478 obj, reloc.target_handle,
1479 (int) reloc.offset, (int) obj->size);
1480 drm_gem_object_unreference(target_obj);
1481 i915_gem_object_unpin(obj);
1484 if (reloc.offset & 3) {
1485 DRM_ERROR("Relocation not 4-byte aligned: "
1486 "obj %p target %d offset %d.\n",
1487 obj, reloc.target_handle,
1488 (int) reloc.offset);
1489 drm_gem_object_unreference(target_obj);
1490 i915_gem_object_unpin(obj);
1494 if (reloc.write_domain && target_obj->pending_write_domain &&
1495 reloc.write_domain != target_obj->pending_write_domain) {
1496 DRM_ERROR("Write domain conflict: "
1497 "obj %p target %d offset %d "
1498 "new %08x old %08x\n",
1499 obj, reloc.target_handle,
1502 target_obj->pending_write_domain);
1503 drm_gem_object_unreference(target_obj);
1504 i915_gem_object_unpin(obj);
1509 DRM_INFO("%s: obj %p offset %08x target %d "
1510 "read %08x write %08x gtt %08x "
1511 "presumed %08x delta %08x\n",
1515 (int) reloc.target_handle,
1516 (int) reloc.read_domains,
1517 (int) reloc.write_domain,
1518 (int) target_obj_priv->gtt_offset,
1519 (int) reloc.presumed_offset,
1523 target_obj->pending_read_domains |= reloc.read_domains;
1524 target_obj->pending_write_domain |= reloc.write_domain;
1526 /* If the relocation already has the right value in it, no
1527 * more work needs to be done.
1529 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
1530 drm_gem_object_unreference(target_obj);
1534 /* Now that we're going to actually write some data in,
1535 * make sure that any rendering using this buffer's contents
1538 i915_gem_object_wait_rendering(obj);
1540 /* As we're writing through the gtt, flush
1541 * any CPU writes before we write the relocations
1543 if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
1544 i915_gem_clflush_object(obj);
1545 drm_agp_chipset_flush(dev);
1546 obj->write_domain = 0;
1549 /* Map the page containing the relocation we're going to
1552 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1553 if (reloc_page == NULL ||
1554 (last_reloc_offset & ~(PAGE_SIZE - 1)) !=
1555 (reloc_offset & ~(PAGE_SIZE - 1))) {
1556 if (reloc_page != NULL)
1557 iounmap(reloc_page);
1559 reloc_page = ioremap(dev->agp->base +
1560 (reloc_offset & ~(PAGE_SIZE - 1)),
1562 last_reloc_offset = reloc_offset;
1563 if (reloc_page == NULL) {
1564 drm_gem_object_unreference(target_obj);
1565 i915_gem_object_unpin(obj);
1570 reloc_entry = (uint32_t *)((char *)reloc_page +
1571 (reloc_offset & (PAGE_SIZE - 1)));
1572 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1575 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1576 obj, (unsigned int) reloc.offset,
1577 readl(reloc_entry), reloc_val);
1579 writel(reloc_val, reloc_entry);
1581 /* Write the updated presumed offset for this entry back out
1584 reloc.presumed_offset = target_obj_priv->gtt_offset;
1585 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
1587 drm_gem_object_unreference(target_obj);
1588 i915_gem_object_unpin(obj);
1592 drm_gem_object_unreference(target_obj);
1595 if (reloc_page != NULL)
1596 iounmap(reloc_page);
1600 i915_gem_dump_object(obj, 128, __func__, ~0);
1605 /** Dispatch a batchbuffer to the ring
1608 i915_dispatch_gem_execbuffer(struct drm_device *dev,
1609 struct drm_i915_gem_execbuffer *exec,
1610 uint64_t exec_offset)
1612 drm_i915_private_t *dev_priv = dev->dev_private;
1613 struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
1614 (uintptr_t) exec->cliprects_ptr;
1615 int nbox = exec->num_cliprects;
1617 uint32_t exec_start, exec_len;
1620 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
1621 exec_len = (uint32_t) exec->batch_len;
1623 if ((exec_start | exec_len) & 0x7) {
1624 DRM_ERROR("alignment\n");
1631 count = nbox ? nbox : 1;
1633 for (i = 0; i < count; i++) {
1635 int ret = i915_emit_box(dev, boxes, i,
1636 exec->DR1, exec->DR4);
1641 if (IS_I830(dev) || IS_845G(dev)) {
1643 OUT_RING(MI_BATCH_BUFFER);
1644 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1645 OUT_RING(exec_start + exec_len - 4);
1650 if (IS_I965G(dev)) {
1651 OUT_RING(MI_BATCH_BUFFER_START |
1653 MI_BATCH_NON_SECURE_I965);
1654 OUT_RING(exec_start);
1656 OUT_RING(MI_BATCH_BUFFER_START |
1658 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1664 /* XXX breadcrumb */
1668 /* Throttle our rendering by waiting until the ring has completed our requests
1669 * emitted over 20 msec ago.
1671 * This should get us reasonable parallelism between CPU and GPU but also
1672 * relatively low latency when blocking on a particular request to finish.
1675 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
1677 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1681 mutex_lock(&dev->struct_mutex);
1682 seqno = i915_file_priv->mm.last_gem_throttle_seqno;
1683 i915_file_priv->mm.last_gem_throttle_seqno = i915_file_priv->mm.last_gem_seqno;
1685 ret = i915_wait_request(dev, seqno);
1686 mutex_unlock(&dev->struct_mutex);
1691 i915_gem_execbuffer(struct drm_device *dev, void *data,
1692 struct drm_file *file_priv)
1694 drm_i915_private_t *dev_priv = dev->dev_private;
1695 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1696 struct drm_i915_gem_execbuffer *args = data;
1697 struct drm_i915_gem_exec_object *exec_list = NULL;
1698 struct drm_gem_object **object_list = NULL;
1699 struct drm_gem_object *batch_obj;
1700 int ret, i, pinned = 0;
1701 uint64_t exec_offset;
1702 uint32_t seqno, flush_domains;
1705 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1706 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1709 /* Copy in the exec list from userland */
1710 exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
1712 object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
1714 if (exec_list == NULL || object_list == NULL) {
1715 DRM_ERROR("Failed to allocate exec or object list "
1717 args->buffer_count);
1721 ret = copy_from_user(exec_list,
1722 (struct drm_i915_relocation_entry __user *)
1723 (uintptr_t) args->buffers_ptr,
1724 sizeof(*exec_list) * args->buffer_count);
1726 DRM_ERROR("copy %d exec entries failed %d\n",
1727 args->buffer_count, ret);
1731 mutex_lock(&dev->struct_mutex);
1733 i915_verify_inactive(dev, __FILE__, __LINE__);
1734 if (dev_priv->mm.suspended) {
1735 DRM_ERROR("Execbuf while VT-switched.\n");
1736 mutex_unlock(&dev->struct_mutex);
1740 /* Zero the gloabl flush/invalidate flags. These
1741 * will be modified as each object is bound to the
1744 dev->invalidate_domains = 0;
1745 dev->flush_domains = 0;
1747 /* Look up object handles and perform the relocations */
1748 for (i = 0; i < args->buffer_count; i++) {
1749 object_list[i] = drm_gem_object_lookup(dev, file_priv,
1750 exec_list[i].handle);
1751 if (object_list[i] == NULL) {
1752 DRM_ERROR("Invalid object handle %d at index %d\n",
1753 exec_list[i].handle, i);
1758 object_list[i]->pending_read_domains = 0;
1759 object_list[i]->pending_write_domain = 0;
1760 ret = i915_gem_object_pin_and_relocate(object_list[i],
1764 DRM_ERROR("object bind and relocate failed %d\n", ret);
1770 /* Set the pending read domains for the batch buffer to COMMAND */
1771 batch_obj = object_list[args->buffer_count-1];
1772 batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1773 batch_obj->pending_write_domain = 0;
1775 i915_verify_inactive(dev, __FILE__, __LINE__);
1777 for (i = 0; i < args->buffer_count; i++) {
1778 struct drm_gem_object *obj = object_list[i];
1779 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1781 if (obj_priv->gtt_space == NULL) {
1782 /* We evicted the buffer in the process of validating
1783 * our set of buffers in. We could try to recover by
1784 * kicking them everything out and trying again from
1791 /* make sure all previous memory operations have passed */
1792 ret = i915_gem_object_set_domain(obj,
1793 obj->pending_read_domains,
1794 obj->pending_write_domain);
1799 i915_verify_inactive(dev, __FILE__, __LINE__);
1801 /* Flush/invalidate caches and chipset buffer */
1802 flush_domains = i915_gem_dev_set_domain(dev);
1804 i915_verify_inactive(dev, __FILE__, __LINE__);
1807 for (i = 0; i < args->buffer_count; i++) {
1808 i915_gem_object_check_coherency(object_list[i],
1809 exec_list[i].handle);
1813 exec_offset = exec_list[args->buffer_count - 1].offset;
1816 i915_gem_dump_object(object_list[args->buffer_count - 1],
1822 /* Exec the batchbuffer */
1823 ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
1825 DRM_ERROR("dispatch failed %d\n", ret);
1830 * Ensure that the commands in the batch buffer are
1831 * finished before the interrupt fires
1833 flush_domains |= i915_retire_commands(dev);
1835 i915_verify_inactive(dev, __FILE__, __LINE__);
1838 * Get a seqno representing the execution of the current buffer,
1839 * which we can wait on. We would like to mitigate these interrupts,
1840 * likely by only creating seqnos occasionally (so that we have
1841 * *some* interrupts representing completion of buffers that we can
1842 * wait on when trying to clear up gtt space).
1844 seqno = i915_add_request(dev, flush_domains);
1846 i915_file_priv->mm.last_gem_seqno = seqno;
1847 for (i = 0; i < args->buffer_count; i++) {
1848 struct drm_gem_object *obj = object_list[i];
1849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1851 i915_gem_object_move_to_active(obj);
1852 obj_priv->last_rendering_seqno = seqno;
1854 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
1858 i915_dump_lru(dev, __func__);
1861 i915_verify_inactive(dev, __FILE__, __LINE__);
1863 /* Copy the new buffer offsets back to the user's exec list. */
1864 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1865 (uintptr_t) args->buffers_ptr,
1867 sizeof(*exec_list) * args->buffer_count);
1869 DRM_ERROR("failed to copy %d exec entries "
1870 "back to user (%d)\n",
1871 args->buffer_count, ret);
1873 if (object_list != NULL) {
1874 for (i = 0; i < pinned; i++)
1875 i915_gem_object_unpin(object_list[i]);
1877 for (i = 0; i < args->buffer_count; i++)
1878 drm_gem_object_unreference(object_list[i]);
1880 mutex_unlock(&dev->struct_mutex);
1883 drm_free(object_list, sizeof(*object_list) * args->buffer_count,
1885 drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
1892 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
1894 struct drm_device *dev = obj->dev;
1895 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1898 i915_verify_inactive(dev, __FILE__, __LINE__);
1899 if (obj_priv->gtt_space == NULL) {
1900 ret = i915_gem_object_bind_to_gtt(obj, alignment);
1902 DRM_ERROR("Failure to bind: %d", ret);
1906 obj_priv->pin_count++;
1908 /* If the object is not active and not pending a flush,
1909 * remove it from the inactive list
1911 if (obj_priv->pin_count == 1) {
1912 atomic_inc(&dev->pin_count);
1913 atomic_add(obj->size, &dev->pin_memory);
1914 if (!obj_priv->active && (obj->write_domain & ~I915_GEM_DOMAIN_CPU) == 0 &&
1915 !list_empty(&obj_priv->list))
1916 list_del_init(&obj_priv->list);
1918 i915_verify_inactive(dev, __FILE__, __LINE__);
1924 i915_gem_object_unpin(struct drm_gem_object *obj)
1926 struct drm_device *dev = obj->dev;
1927 drm_i915_private_t *dev_priv = dev->dev_private;
1928 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1930 i915_verify_inactive(dev, __FILE__, __LINE__);
1931 obj_priv->pin_count--;
1932 BUG_ON(obj_priv->pin_count < 0);
1933 BUG_ON(obj_priv->gtt_space == NULL);
1935 /* If the object is no longer pinned, and is
1936 * neither active nor being flushed, then stick it on
1939 if (obj_priv->pin_count == 0) {
1940 if (!obj_priv->active && (obj->write_domain & ~I915_GEM_DOMAIN_CPU) == 0)
1941 list_move_tail(&obj_priv->list,
1942 &dev_priv->mm.inactive_list);
1943 atomic_dec(&dev->pin_count);
1944 atomic_sub(obj->size, &dev->pin_memory);
1946 i915_verify_inactive(dev, __FILE__, __LINE__);
1950 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1951 struct drm_file *file_priv)
1953 struct drm_i915_gem_pin *args = data;
1954 struct drm_gem_object *obj;
1955 struct drm_i915_gem_object *obj_priv;
1958 mutex_lock(&dev->struct_mutex);
1960 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1962 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
1964 mutex_unlock(&dev->struct_mutex);
1967 obj_priv = obj->driver_private;
1969 ret = i915_gem_object_pin(obj, args->alignment);
1971 drm_gem_object_unreference(obj);
1972 mutex_unlock(&dev->struct_mutex);
1976 /** XXX - flush the CPU caches for pinned objects
1977 * as the X server doesn't manage domains yet
1979 if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
1980 i915_gem_clflush_object(obj);
1981 drm_agp_chipset_flush(dev);
1982 obj->write_domain = 0;
1984 args->offset = obj_priv->gtt_offset;
1985 drm_gem_object_unreference(obj);
1986 mutex_unlock(&dev->struct_mutex);
1992 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1993 struct drm_file *file_priv)
1995 struct drm_i915_gem_pin *args = data;
1996 struct drm_gem_object *obj;
1998 mutex_lock(&dev->struct_mutex);
2000 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2002 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2004 mutex_unlock(&dev->struct_mutex);
2008 i915_gem_object_unpin(obj);
2010 drm_gem_object_unreference(obj);
2011 mutex_unlock(&dev->struct_mutex);
2016 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2017 struct drm_file *file_priv)
2019 struct drm_i915_gem_busy *args = data;
2020 struct drm_gem_object *obj;
2021 struct drm_i915_gem_object *obj_priv;
2023 mutex_lock(&dev->struct_mutex);
2024 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2026 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2028 mutex_unlock(&dev->struct_mutex);
2032 obj_priv = obj->driver_private;
2033 args->busy = obj_priv->active;
2035 drm_gem_object_unreference(obj);
2036 mutex_unlock(&dev->struct_mutex);
2041 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2042 struct drm_file *file_priv)
2044 return i915_gem_ring_throttle(dev, file_priv);
2047 int i915_gem_init_object(struct drm_gem_object *obj)
2049 struct drm_i915_gem_object *obj_priv;
2051 obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2052 if (obj_priv == NULL)
2056 * We've just allocated pages from the kernel,
2057 * so they've just been written by the CPU with
2058 * zeros. They'll need to be clflushed before we
2059 * use them with the GPU.
2061 obj->write_domain = I915_GEM_DOMAIN_CPU;
2062 obj->read_domains = I915_GEM_DOMAIN_CPU;
2064 obj->driver_private = obj_priv;
2065 obj_priv->obj = obj;
2066 INIT_LIST_HEAD(&obj_priv->list);
2070 void i915_gem_free_object(struct drm_gem_object *obj)
2072 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2074 while (obj_priv->pin_count > 0)
2075 i915_gem_object_unpin(obj);
2077 i915_gem_object_unbind(obj);
2079 drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2083 i915_gem_set_domain(struct drm_gem_object *obj,
2084 struct drm_file *file_priv,
2085 uint32_t read_domains,
2086 uint32_t write_domain)
2088 struct drm_device *dev = obj->dev;
2090 uint32_t flush_domains;
2092 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
2094 ret = i915_gem_object_set_domain(obj, read_domains, write_domain);
2097 flush_domains = i915_gem_dev_set_domain(obj->dev);
2099 if (flush_domains & ~I915_GEM_DOMAIN_CPU)
2100 (void) i915_add_request(dev, flush_domains);
2105 /** Unbinds all objects that are on the given buffer list. */
2107 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2109 struct drm_gem_object *obj;
2110 struct drm_i915_gem_object *obj_priv;
2113 while (!list_empty(head)) {
2114 obj_priv = list_first_entry(head,
2115 struct drm_i915_gem_object,
2117 obj = obj_priv->obj;
2119 if (obj_priv->pin_count != 0) {
2120 DRM_ERROR("Pinned object in unbind list\n");
2121 mutex_unlock(&dev->struct_mutex);
2125 ret = i915_gem_object_unbind(obj);
2127 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2129 mutex_unlock(&dev->struct_mutex);
2139 i915_gem_idle(struct drm_device *dev)
2141 drm_i915_private_t *dev_priv = dev->dev_private;
2145 if (dev_priv->mm.suspended)
2148 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2149 * We need to replace this with a semaphore, or something.
2151 dev_priv->mm.suspended = 1;
2153 i915_kernel_lost_context(dev);
2155 /* Flush the GPU along with all non-CPU write domains
2157 i915_gem_flush(dev, ~I915_GEM_DOMAIN_CPU, ~I915_GEM_DOMAIN_CPU);
2158 seqno = i915_add_request(dev, ~I915_GEM_DOMAIN_CPU);
2161 mutex_unlock(&dev->struct_mutex);
2164 ret = i915_wait_request(dev, seqno);
2166 mutex_unlock(&dev->struct_mutex);
2170 /* Active and flushing should now be empty as we've
2171 * waited for a sequence higher than any pending execbuffer
2173 BUG_ON(!list_empty(&dev_priv->mm.active_list));
2174 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2176 /* Request should now be empty as we've also waited
2177 * for the last request in the list
2179 BUG_ON(!list_empty(&dev_priv->mm.request_list));
2181 /* Move all buffers out of the GTT. */
2182 i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2184 BUG_ON(!list_empty(&dev_priv->mm.active_list));
2185 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2186 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2187 BUG_ON(!list_empty(&dev_priv->mm.request_list));
2192 i915_gem_init_ringbuffer(struct drm_device *dev)
2194 drm_i915_private_t *dev_priv = dev->dev_private;
2195 struct drm_gem_object *obj;
2196 struct drm_i915_gem_object *obj_priv;
2199 obj = drm_gem_object_alloc(dev, 128 * 1024);
2201 DRM_ERROR("Failed to allocate ringbuffer\n");
2204 obj_priv = obj->driver_private;
2206 ret = i915_gem_object_pin(obj, 4096);
2208 drm_gem_object_unreference(obj);
2212 /* Set up the kernel mapping for the ring. */
2213 dev_priv->ring.Size = obj->size;
2214 dev_priv->ring.tail_mask = obj->size - 1;
2216 dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset;
2217 dev_priv->ring.map.size = obj->size;
2218 dev_priv->ring.map.type = 0;
2219 dev_priv->ring.map.flags = 0;
2220 dev_priv->ring.map.mtrr = 0;
2222 drm_core_ioremap(&dev_priv->ring.map, dev);
2223 if (dev_priv->ring.map.handle == NULL) {
2224 DRM_ERROR("Failed to map ringbuffer.\n");
2225 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2226 drm_gem_object_unreference(obj);
2229 dev_priv->ring.ring_obj = obj;
2230 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
2232 /* Stop the ring if it's running. */
2233 I915_WRITE(LP_RING + RING_LEN, 0);
2234 I915_WRITE(LP_RING + RING_HEAD, 0);
2235 I915_WRITE(LP_RING + RING_TAIL, 0);
2236 I915_WRITE(LP_RING + RING_START, 0);
2238 /* Initialize the ring. */
2239 I915_WRITE(LP_RING + RING_START, obj_priv->gtt_offset);
2240 I915_WRITE(LP_RING + RING_LEN,
2241 ((obj->size - 4096) & RING_NR_PAGES) |
2245 /* Update our cache of the ring state */
2246 i915_kernel_lost_context(dev);
2252 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2254 drm_i915_private_t *dev_priv = dev->dev_private;
2256 if (dev_priv->ring.ring_obj == NULL)
2259 drm_core_ioremapfree(&dev_priv->ring.map, dev);
2261 i915_gem_object_unpin(dev_priv->ring.ring_obj);
2262 drm_gem_object_unreference(dev_priv->ring.ring_obj);
2264 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2268 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2269 struct drm_file *file_priv)
2271 drm_i915_private_t *dev_priv = dev->dev_private;
2274 ret = i915_gem_init_ringbuffer(dev);
2278 mutex_lock(&dev->struct_mutex);
2279 BUG_ON(!list_empty(&dev_priv->mm.active_list));
2280 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2281 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2282 BUG_ON(!list_empty(&dev_priv->mm.request_list));
2283 dev_priv->mm.suspended = 0;
2284 mutex_unlock(&dev->struct_mutex);
2289 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2290 struct drm_file *file_priv)
2294 mutex_lock(&dev->struct_mutex);
2295 ret = i915_gem_idle(dev);
2297 i915_gem_cleanup_ringbuffer(dev);
2298 mutex_unlock(&dev->struct_mutex);
2303 static int i915_gem_active_info(char *buf, char **start, off_t offset,
2304 int request, int *eof, void *data)
2306 struct drm_minor *minor = (struct drm_minor *) data;
2307 struct drm_device *dev = minor->dev;
2308 drm_i915_private_t *dev_priv = dev->dev_private;
2309 struct drm_i915_gem_object *obj_priv;
2312 if (offset > DRM_PROC_LIMIT) {
2317 *start = &buf[offset];
2319 DRM_PROC_PRINT("Active:\n");
2320 list_for_each_entry(obj_priv, &dev_priv->mm.active_list,
2323 struct drm_gem_object *obj = obj_priv->obj;
2325 DRM_PROC_PRINT(" %p(%d): %08x %08x %d\n",
2327 obj->read_domains, obj->write_domain,
2328 obj_priv->last_rendering_seqno);
2330 DRM_PROC_PRINT(" %p: %08x %08x %d\n",
2332 obj->read_domains, obj->write_domain,
2333 obj_priv->last_rendering_seqno);
2336 if (len > request + offset)
2339 return len - offset;
2342 static int i915_gem_flushing_info(char *buf, char **start, off_t offset,
2343 int request, int *eof, void *data)
2345 struct drm_minor *minor = (struct drm_minor *) data;
2346 struct drm_device *dev = minor->dev;
2347 drm_i915_private_t *dev_priv = dev->dev_private;
2348 struct drm_i915_gem_object *obj_priv;
2351 if (offset > DRM_PROC_LIMIT) {
2356 *start = &buf[offset];
2358 DRM_PROC_PRINT("Flushing:\n");
2359 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list,
2362 struct drm_gem_object *obj = obj_priv->obj;
2364 DRM_PROC_PRINT(" %p(%d): %08x %08x %d\n",
2366 obj->read_domains, obj->write_domain,
2367 obj_priv->last_rendering_seqno);
2369 DRM_PROC_PRINT(" %p: %08x %08x %d\n", obj,
2370 obj->read_domains, obj->write_domain,
2371 obj_priv->last_rendering_seqno);
2374 if (len > request + offset)
2377 return len - offset;
2380 static int i915_gem_inactive_info(char *buf, char **start, off_t offset,
2381 int request, int *eof, void *data)
2383 struct drm_minor *minor = (struct drm_minor *) data;
2384 struct drm_device *dev = minor->dev;
2385 drm_i915_private_t *dev_priv = dev->dev_private;
2386 struct drm_i915_gem_object *obj_priv;
2389 if (offset > DRM_PROC_LIMIT) {
2394 *start = &buf[offset];
2396 DRM_PROC_PRINT("Inactive:\n");
2397 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list,
2400 struct drm_gem_object *obj = obj_priv->obj;
2402 DRM_PROC_PRINT(" %p(%d): %08x %08x %d\n",
2404 obj->read_domains, obj->write_domain,
2405 obj_priv->last_rendering_seqno);
2407 DRM_PROC_PRINT(" %p: %08x %08x %d\n", obj,
2408 obj->read_domains, obj->write_domain,
2409 obj_priv->last_rendering_seqno);
2412 if (len > request + offset)
2415 return len - offset;
2418 static int i915_gem_request_info(char *buf, char **start, off_t offset,
2419 int request, int *eof, void *data)
2421 struct drm_minor *minor = (struct drm_minor *) data;
2422 struct drm_device *dev = minor->dev;
2423 drm_i915_private_t *dev_priv = dev->dev_private;
2424 struct drm_i915_gem_request *gem_request;
2427 if (offset > DRM_PROC_LIMIT) {
2432 *start = &buf[offset];
2434 DRM_PROC_PRINT("Request:\n");
2435 list_for_each_entry(gem_request, &dev_priv->mm.request_list,
2438 DRM_PROC_PRINT (" %d @ %d %08x\n",
2440 (int) (jiffies - gem_request->emitted_jiffies),
2441 gem_request->flush_domains);
2443 if (len > request + offset)
2446 return len - offset;
2449 static int i915_gem_seqno_info(char *buf, char **start, off_t offset,
2450 int request, int *eof, void *data)
2452 struct drm_minor *minor = (struct drm_minor *) data;
2453 struct drm_device *dev = minor->dev;
2454 drm_i915_private_t *dev_priv = dev->dev_private;
2457 if (offset > DRM_PROC_LIMIT) {
2462 *start = &buf[offset];
2464 DRM_PROC_PRINT("Current sequence: %d\n", i915_get_gem_seqno(dev));
2465 DRM_PROC_PRINT("Waiter sequence: %d\n", dev_priv->mm.waiting_gem_seqno);
2466 DRM_PROC_PRINT("IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno);
2467 if (len > request + offset)
2470 return len - offset;
2474 static struct drm_proc_list {
2475 const char *name; /**< file name */
2476 int (*f) (char *, char **, off_t, int, int *, void *); /**< proc callback*/
2477 } i915_gem_proc_list[] = {
2478 {"gem_active", i915_gem_active_info},
2479 {"gem_flushing", i915_gem_flushing_info},
2480 {"gem_inactive", i915_gem_inactive_info},
2481 {"gem_request", i915_gem_request_info},
2482 {"gem_seqno", i915_gem_seqno_info},
2485 #define I915_GEM_PROC_ENTRIES ARRAY_SIZE(i915_gem_proc_list)
2487 int i915_gem_proc_init(struct drm_minor *minor)
2489 struct proc_dir_entry *ent;
2492 for (i = 0; i < I915_GEM_PROC_ENTRIES; i++) {
2493 ent = create_proc_entry(i915_gem_proc_list[i].name,
2494 S_IFREG | S_IRUGO, minor->dev_root);
2496 DRM_ERROR("Cannot create /proc/dri/.../%s\n",
2497 i915_gem_proc_list[i].name);
2498 for (j = 0; j < i; j++)
2499 remove_proc_entry(i915_gem_proc_list[i].name,
2503 ent->read_proc = i915_gem_proc_list[i].f;
2509 void i915_gem_proc_cleanup(struct drm_minor *minor)
2513 if (!minor->dev_root)
2516 for (i = 0; i < I915_GEM_PROC_ENTRIES; i++)
2517 remove_proc_entry(i915_gem_proc_list[i].name, minor->dev_root);
2521 i915_gem_lastclose(struct drm_device *dev)
2525 mutex_lock(&dev->struct_mutex);
2527 ret = i915_gem_idle(dev);
2529 DRM_ERROR("failed to idle hardware: %d\n", ret);
2531 i915_gem_cleanup_ringbuffer(dev);
2533 mutex_unlock(&dev->struct_mutex);