linux-core/nv50_display.c

   1 /*
   2  * Copyright (C) 2008 Maarten Maathuis.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining
   6  * a copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sublicense, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the
  14  * next paragraph) shall be included in all copies or substantial
  15  * portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24  *
  25  */
  26
  27 #include "nv50_display.h"
  28 #include "nv50_crtc.h"
  29 #include "nv50_output.h"
  30 #include "nv50_connector.h"
  31
  32 static int nv50_display_pre_init(struct nv50_display *display)
  33 {
  34         struct drm_device *dev = display->dev;
  35         struct drm_nouveau_private *dev_priv = dev->dev_private;
  36         int i;
  37         uint32_t ram_amount;
  38
  39         NV50_DEBUG("\n");
  40
  41         NV_WRITE(0x00610184, NV_READ(0x00614004));
  42         /*
  43          * I think the 0x006101XX range is some kind of main control area that enables things.
  44          */
  45         /* CRTC? */
  46         NV_WRITE(0x00610190 + 0 * 0x10, NV_READ(0x00616100 + 0 * 0x800));
  47         NV_WRITE(0x00610190 + 1 * 0x10, NV_READ(0x00616100 + 1 * 0x800));
  48         NV_WRITE(0x00610194 + 0 * 0x10, NV_READ(0x00616104 + 0 * 0x800));
  49         NV_WRITE(0x00610194 + 1 * 0x10, NV_READ(0x00616104 + 1 * 0x800));
  50         NV_WRITE(0x00610198 + 0 * 0x10, NV_READ(0x00616108 + 0 * 0x800));
  51         NV_WRITE(0x00610198 + 1 * 0x10, NV_READ(0x00616108 + 1 * 0x800));
  52         NV_WRITE(0x0061019c + 0 * 0x10, NV_READ(0x0061610c + 0 * 0x800));
  53         NV_WRITE(0x0061019c + 1 * 0x10, NV_READ(0x0061610c + 1 * 0x800));
  54         /* DAC */
  55         NV_WRITE(0x006101d0 + 0 * 0x4, NV_READ(0x0061a000 + 0 * 0x800));
  56         NV_WRITE(0x006101d0 + 1 * 0x4, NV_READ(0x0061a000 + 1 * 0x800));
  57         NV_WRITE(0x006101d0 + 2 * 0x4, NV_READ(0x0061a000 + 2 * 0x800));
  58         /* SOR */
  59         NV_WRITE(0x006101e0 + 0 * 0x4, NV_READ(0x0061c000 + 0 * 0x800));
  60         NV_WRITE(0x006101e0 + 1 * 0x4, NV_READ(0x0061c000 + 1 * 0x800));
  61         /* Something not yet in use, tv-out maybe. */
  62         NV_WRITE(0x006101f0 + 0 * 0x4, NV_READ(0x0061e000 + 0 * 0x800));
  63         NV_WRITE(0x006101f0 + 1 * 0x4, NV_READ(0x0061e000 + 1 * 0x800));
  64         NV_WRITE(0x006101f0 + 2 * 0x4, NV_READ(0x0061e000 + 2 * 0x800));
  65
  66         for (i = 0; i < 3; i++) {
  67                 NV_WRITE(NV50_PDISPLAY_DAC_REGS_DPMS_CTRL(i), 0x00550000 | NV50_PDISPLAY_DAC_REGS_DPMS_CTRL_PENDING);
  68                 NV_WRITE(NV50_PDISPLAY_DAC_REGS_CLK_CTRL1(i), 0x00000001);
  69         }
  70
  71         /* This used to be in crtc unblank, but seems out of place there. */
  72         NV_WRITE(NV50_PDISPLAY_UNK_380, 0);
  73         /* RAM is clamped to 256 MiB. */
  74         ram_amount = nouveau_mem_fb_amount(display->dev);
  75         NV50_DEBUG("ram_amount %d\n", ram_amount);
  76         if (ram_amount > 256*1024*1024)
  77                 ram_amount = 256*1024*1024;
  78         NV_WRITE(NV50_PDISPLAY_RAM_AMOUNT, ram_amount - 1);
  79         NV_WRITE(NV50_PDISPLAY_UNK_388, 0x150000);
  80         NV_WRITE(NV50_PDISPLAY_UNK_38C, 0);
  81
  82         display->preinit_done = true;
  83
  84         return 0;
  85 }
  86
  87 static int nv50_display_init(struct nv50_display *display)
  88 {
  89         struct drm_device *dev = display->dev;
  90         struct drm_nouveau_private *dev_priv = dev->dev_private;
  91         uint32_t val;
  92
  93         NV50_DEBUG("\n");
  94
  95         /* The precise purpose is unknown, i suspect it has something to do with text mode. */
  96         if (NV_READ(NV50_PDISPLAY_SUPERVISOR) & 0x100) {
  97                 NV_WRITE(NV50_PDISPLAY_SUPERVISOR, 0x100);
  98                 NV_WRITE(0x006194e8, NV_READ(0x006194e8) & ~1);
  99                 while (NV_READ(0x006194e8) & 2);
 100         }
 101
 102         /* taken from nv bug #12637 */
 103         NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0x2b00);
 104         do {
 105                 val = NV_READ(NV50_PDISPLAY_UNK200_CTRL);
 106                 if ((val & 0x9f0000) == 0x20000)
 107                         NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, val | 0x800000);
 108
 109                 if ((val & 0x3f0000) == 0x30000)
 110                         NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, val | 0x200000);
 111         } while (val & 0x1e0000);
 112
 113         NV_WRITE(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_ENABLE);
 114         NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0x1000b03);
 115         while (!(NV_READ(NV50_PDISPLAY_UNK200_CTRL) & 0x40000000));
 116
 117         /* For the moment this is just a wrapper, which should be replaced with a real fifo at some point. */
 118         OUT_MODE(NV50_UNK84, 0);
 119         OUT_MODE(NV50_UNK88, 0);
 120         OUT_MODE(NV50_CRTC0_BLANK_CTRL, NV50_CRTC0_BLANK_CTRL_BLANK);
 121         OUT_MODE(NV50_CRTC0_UNK800, 0);
 122         OUT_MODE(NV50_CRTC0_DISPLAY_START, 0);
 123         OUT_MODE(NV50_CRTC0_UNK82C, 0);
 124
 125         /* enable clock change interrupts. */
 126         NV_WRITE(NV50_PDISPLAY_SUPERVISOR_INTR, NV_READ(NV50_PDISPLAY_SUPERVISOR_INTR) | 0x70);
 127
 128         /* enable hotplug interrupts */
 129         NV_WRITE(NV50_PCONNECTOR_HOTPLUG_INTR, 0x7FFF7FFF);
 130
 131         display->init_done = true;
 132
 133         return 0;
 134 }
 135
 136 static int nv50_display_disable(struct nv50_display *display)
 137 {
 138         struct drm_device *dev = display->dev;
 139         struct drm_nouveau_private *dev_priv = dev->dev_private;
 140         struct nv50_crtc *crtc = NULL;
 141         int i;
 142
 143         NV50_DEBUG("\n");
 144
 145         list_for_each_entry(crtc, &display->crtcs, item) {
 146                 crtc->blank(crtc, true);
 147         }
 148
 149         display->update(display);
 150
 151         /* Almost like ack'ing a vblank interrupt, maybe in the spirit of cleaning up? */
 152         list_for_each_entry(crtc, &display->crtcs, item) {
 153                 if (crtc->enabled) {
 154                         uint32_t mask;
 155
 156                         if (crtc->index == 1)
 157                                 mask = NV50_PDISPLAY_SUPERVISOR_CRTC1;
 158                         else
 159                                 mask = NV50_PDISPLAY_SUPERVISOR_CRTC0;
 160
 161                         NV_WRITE(NV50_PDISPLAY_SUPERVISOR, mask);
 162                         while (!(NV_READ(NV50_PDISPLAY_SUPERVISOR) & mask));
 163                 }
 164         }
 165
 166         NV_WRITE(NV50_PDISPLAY_UNK200_CTRL, 0);
 167         NV_WRITE(NV50_PDISPLAY_CTRL_STATE, 0);
 168         while ((NV_READ(NV50_PDISPLAY_UNK200_CTRL) & 0x1e0000) != 0);
 169
 170         for (i = 0; i < 2; i++) {
 171                 while (NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_STATE(i)) & NV50_PDISPLAY_SOR_REGS_DPMS_STATE_WAIT);
 172         }
 173
 174         /* disable clock change interrupts. */
 175         NV_WRITE(NV50_PDISPLAY_SUPERVISOR_INTR, NV_READ(NV50_PDISPLAY_SUPERVISOR_INTR) & ~0x70);
 176
 177         /* disable hotplug interrupts */
 178         NV_WRITE(NV50_PCONNECTOR_HOTPLUG_INTR, 0);
 179
 180         display->init_done = false;
 181
 182         return 0;
 183 }
 184
 185 static int nv50_display_update(struct nv50_display *display)
 186 {
 187         struct drm_device *dev = display->dev;
 188         struct drm_nouveau_private *dev_priv = dev->dev_private;
 189
 190         NV50_DEBUG("\n");
 191
 192         OUT_MODE(NV50_UPDATE_DISPLAY, 0);
 193
 194         return 0;
 195 }
 196
 197 int nv50_display_create(struct drm_device *dev)
 198 {
 199         struct drm_nouveau_private *dev_priv = dev->dev_private;
 200         struct nv50_display *display = kzalloc(sizeof(struct nv50_display), GFP_KERNEL);
 201         int i, type, output_index, bus;
 202         /* DAC0, DAC1, DAC2, SOR0, SOR1*/
 203         int or_counter[5] = {0, 0, 0, 0, 0};
 204         int i2c_index[5] = {0, 0, 0, 0, 0};
 205         uint32_t bus_mask = 0;
 206         uint32_t bus_digital = 0, bus_analog = 0;
 207
 208         NV50_DEBUG("\n");
 209
 210         if (!display)
 211                 return -ENOMEM;
 212
 213         INIT_LIST_HEAD(&display->crtcs);
 214         INIT_LIST_HEAD(&display->outputs);
 215         INIT_LIST_HEAD(&display->connectors);
 216
 217         dev_priv->display_priv = display;
 218
 219         for (i = 0; i < 2; i++) {
 220                 nv50_crtc_create(dev, i);
 221         }
 222
 223         /* we setup the outputs up from the BIOS table */
 224         for (i = 0 ; i < dev_priv->dcb_table.entries; i++) {
 225                 type = dev_priv->dcb_table.entry[i].type;
 226                 output_index = ffs(dev_priv->dcb_table.entry[i].or) - 1;
 227                 bus = dev_priv->dcb_table.entry[i].bus;
 228
 229                 switch (type) {
 230                         case DCB_OUTPUT_TMDS:
 231                         case DCB_OUTPUT_LVDS:
 232                                 or_counter[output_index + 3] += 1;
 233                                 i2c_index[output_index + 3] = dev_priv->dcb_table.entry[i].i2c_index;
 234                                 bus_digital |= (1 << bus);
 235                                 nv50_sor_create(dev, i);
 236                                 break;
 237                         case DCB_OUTPUT_ANALOG:
 238                                 or_counter[output_index] += 1;
 239                                 i2c_index[output_index] = dev_priv->dcb_table.entry[i].i2c_index;
 240                                 bus_analog |= (1 << bus);
 241                                 nv50_dac_create(dev, i);
 242                                 break;
 243                         default:
 244                                 break;
 245                 }
 246
 247         }
 248
 249         /* setup the connectors based on the output tables. */
 250         for (i = 0 ; i < dev_priv->dcb_table.entries; i++) {
 251                 int connector_type = 0;
 252                 type = dev_priv->dcb_table.entry[i].type;
 253                 bus = dev_priv->dcb_table.entry[i].bus;
 254
 255                 /* already done? */
 256                 if (bus_mask & (1 << bus))
 257                         continue;
 258
 259                 /* only do it for supported outputs */
 260                 if (type != DCB_OUTPUT_ANALOG && type != DCB_OUTPUT_TMDS
 261                         && type != DCB_OUTPUT_LVDS)
 262                         continue;
 263
 264                 switch (type) {
 265                         case DCB_OUTPUT_TMDS:
 266                         case DCB_OUTPUT_ANALOG:
 267                                 if ((bus_digital & (1 << bus)) && (bus_analog & (1 << bus)))
 268                                         connector_type = CONNECTOR_DVI_I;
 269                                 else if (bus_digital & (1 << bus))
 270                                         connector_type = CONNECTOR_DVI_D;
 271                                 else if (bus_analog & (1 << bus))
 272                                         connector_type = CONNECTOR_VGA;
 273                                 break;
 274                         case DCB_OUTPUT_LVDS:
 275                                 connector_type = CONNECTOR_LVDS;
 276                                 break;
 277                         default:
 278                                 connector_type = CONNECTOR_UNKNOWN;
 279                                 break;
 280                 }
 281
 282                 if (connector_type == CONNECTOR_UNKNOWN)
 283                         continue;
 284
 285                 nv50_connector_create(dev, bus, dev_priv->dcb_table.entry[i].i2c_index, connector_type);
 286
 287                 bus_mask |= (1 << bus);
 288         }
 289
 290         display->dev = dev;
 291
 292         /* function pointers */
 293         display->init = nv50_display_init;
 294         display->pre_init = nv50_display_pre_init;
 295         display->disable = nv50_display_disable;
 296         display->update = nv50_display_update;
 297
 298         return 0;
 299 }
 300
 301 int nv50_display_destroy(struct drm_device *dev)
 302 {
 303         struct drm_nouveau_private *dev_priv = dev->dev_private;
 304         struct nv50_display *display = nv50_get_display(dev);
 305         struct nv50_crtc *crtc = NULL;
 306         struct nv50_output *output = NULL;
 307         struct nv50_connector *connector = NULL;
 308
 309         NV50_DEBUG("\n");
 310
 311         if (display->init_done)
 312                 display->disable(display);
 313
 314         list_for_each_entry(connector, &display->connectors, item) {
 315                 connector->destroy(connector);
 316         }
 317
 318         list_for_each_entry(output, &display->outputs, item) {
 319                 output->destroy(output);
 320         }
 321
 322         list_for_each_entry(crtc, &display->crtcs, item) {
 323                 crtc->destroy(crtc);
 324         }
 325
 326         kfree(display);
 327         dev_priv->display_priv = NULL;
 328
 329         return 0;
 330 }
 331
 332 /* This can be replaced with a real fifo in the future. */
 333 void nv50_display_command(struct drm_nouveau_private *dev_priv, uint32_t mthd, uint32_t val)
 334 {
 335         uint32_t counter = 0;
 336
 337 #if 1
 338         DRM_INFO("mthd 0x%03X val 0x%08X\n", mthd, val);
 339 #endif
 340
 341         NV_WRITE(NV50_PDISPLAY_CTRL_VAL, val);
 342         NV_WRITE(NV50_PDISPLAY_CTRL_STATE, NV50_PDISPLAY_CTRL_STATE_PENDING | 0x10000 | mthd | NV50_PDISPLAY_CTRL_STATE_ENABLE);
 343
 344         while (NV_READ(NV50_PDISPLAY_CTRL_STATE) & NV50_PDISPLAY_CTRL_STATE_PENDING) {
 345                 counter++;
 346                 if (counter > 1000000) {
 347                         DRM_ERROR("You probably need a reboot now\n");
 348                         break;
 349                 }
 350                 udelay(1);
 351         }
 352 }
 353
 354 struct nv50_display *nv50_get_display(struct drm_device *dev)
 355 {
 356         struct drm_nouveau_private *dev_priv = dev->dev_private;
 357
 358         return (struct nv50_display *) dev_priv->display_priv;
 359 }