linux-core/radeon_legacy_crtc.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "radeon_drm.h"
  28 #include "radeon_drv.h"
  29
  30 #include "drm_crtc_helper.h"
  31
  32 void radeon_restore_common_regs(struct drm_device *dev)
  33 {
  34         /* don't need this yet */
  35 }
  36
  37 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
  38 {
  39         struct drm_radeon_private *dev_priv = dev->dev_private;
  40         int i = 0;
  41
  42         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
  43            the cause yet, but this workaround will mask the problem for now.
  44            Other chips usually will pass at the very first test, so the
  45            workaround shouldn't have any effect on them. */
  46         for (i = 0;
  47              (i < 10000 &&
  48               RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
  49              i++);
  50 }
  51
  52 static void radeon_pll_write_update(struct drm_device *dev)
  53 {
  54         struct drm_radeon_private *dev_priv = dev->dev_private;
  55
  56         while (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
  57
  58         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
  59                            RADEON_PPLL_ATOMIC_UPDATE_W,
  60                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
  61 }
  62
  63 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
  64 {
  65         struct drm_radeon_private *dev_priv = dev->dev_private;
  66         int i = 0;
  67
  68
  69         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
  70            the cause yet, but this workaround will mask the problem for now.
  71            Other chips usually will pass at the very first test, so the
  72            workaround shouldn't have any effect on them. */
  73         for (i = 0;
  74              (i < 10000 &&
  75               RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
  76              i++);
  77 }
  78
  79 static void radeon_pll2_write_update(struct drm_device *dev)
  80 {
  81         struct drm_radeon_private *dev_priv = dev->dev_private;
  82
  83         while (RADEON_READ_PLL(dev_priv, RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
  84
  85         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
  86                            RADEON_P2PLL_ATOMIC_UPDATE_W,
  87                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
  88 }
  89
  90 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
  91                                        uint16_t fb_div)
  92 {
  93         unsigned int vcoFreq;
  94
  95         if (!ref_div)
  96                 return 1;
  97
  98         vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
  99
 100         /*
 101          * This is horribly crude: the VCO frequency range is divided into
 102          * 3 parts, each part having a fixed PLL gain value.
 103          */
 104         if (vcoFreq >= 30000)
 105                 /*
 106                  * [300..max] MHz : 7
 107                  */
 108                 return 7;
 109         else if (vcoFreq >= 18000)
 110                 /*
 111                  * [180..300) MHz : 4
 112                  */
 113                 return 4;
 114         else
 115                 /*
 116                  * [0..180) MHz : 1
 117                  */
 118                 return 1;
 119 }
 120
 121 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
 122 {
 123         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 124         struct drm_device *dev = crtc->dev;
 125         struct drm_radeon_private *dev_priv = dev->dev_private;
 126         uint32_t mask;
 127
 128         DRM_DEBUG("\n");
 129
 130         mask = radeon_crtc->crtc_id ?
 131                 (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) :
 132                 (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS);
 133
 134         switch(mode) {
 135         case DRM_MODE_DPMS_ON:
 136                 if (radeon_crtc->crtc_id)
 137                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, 0, ~mask);
 138                 else {
 139                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 140                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
 141                 }
 142                 break;
 143         case DRM_MODE_DPMS_STANDBY:
 144                 if (radeon_crtc->crtc_id)
 145                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), ~mask);
 146                 else {
 147                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 148                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS), ~mask);
 149                 }
 150                 break;
 151         case DRM_MODE_DPMS_SUSPEND:
 152                 if (radeon_crtc->crtc_id)
 153                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), ~mask);
 154                 else {
 155                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
 156                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_VSYNC_DIS), ~mask);
 157                 }
 158                 break;
 159         case DRM_MODE_DPMS_OFF:
 160                 if (radeon_crtc->crtc_id)
 161                         RADEON_WRITE_P(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
 162                 else {
 163                         RADEON_WRITE_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~RADEON_CRTC_DISP_REQ_EN_B);
 164                         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
 165                 }
 166                 break;
 167         }
 168
 169         if (mode != DRM_MODE_DPMS_OFF) {
 170                 radeon_crtc_load_lut(crtc);
 171         }
 172 }
 173
 174 /* properly set crtc bpp when using atombios */
 175 static void radeon_legacy_atom_set_surface(struct drm_crtc *crtc)
 176 {
 177         struct drm_device *dev = crtc->dev;
 178         struct drm_radeon_private *dev_priv = dev->dev_private;
 179         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 180         int format;
 181         uint32_t crtc_gen_cntl, crtc2_gen_cntl;
 182
 183         switch (crtc->fb->bits_per_pixel) {
 184         case 15:      /*  555 */
 185                 format = 3;
 186                 break;
 187         case 16:      /*  565 */
 188                 format = 4;
 189                 break;
 190         case 24:      /*  RGB */
 191                 format = 5;
 192                 break;
 193         case 32:      /* xRGB */
 194                 format = 6;
 195                 break;
 196         default:
 197                 return;
 198         }
 199
 200         switch (radeon_crtc->crtc_id) {
 201         case 0:
 202                 crtc_gen_cntl = RADEON_READ(RADEON_CRTC_GEN_CNTL) & 0xfffff0ff;
 203                 crtc_gen_cntl |= (format << 8);
 204                 crtc_gen_cntl |= RADEON_CRTC_EXT_DISP_EN;
 205                 RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 206                 break;
 207         case 1:
 208                 crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL) & 0xfffff0ff;
 209                 crtc2_gen_cntl |= (format << 8);
 210                 RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 211                 // not sure we need these...
 212                 RADEON_WRITE(RADEON_FP_H2_SYNC_STRT_WID,   RADEON_READ(RADEON_CRTC2_H_SYNC_STRT_WID));
 213                 RADEON_WRITE(RADEON_FP_V2_SYNC_STRT_WID,   RADEON_READ(RADEON_CRTC2_V_SYNC_STRT_WID));
 214                 break;
 215         }
 216 }
 217
 218 static bool radeon_set_crtc1_base(struct drm_crtc *crtc, int x, int y)
 219 {
 220         struct drm_device *dev = crtc->dev;
 221         struct drm_radeon_private *dev_priv = dev->dev_private;
 222         struct radeon_framebuffer *radeon_fb;
 223         struct drm_gem_object *obj;
 224         struct drm_radeon_gem_object *obj_priv;
 225         uint32_t base;
 226         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
 227         uint32_t crtc_pitch;
 228         uint32_t disp_merge_cntl;
 229
 230         DRM_DEBUG("\n");
 231
 232         radeon_fb = to_radeon_framebuffer(crtc->fb);
 233
 234         obj = radeon_fb->base.mm_private;
 235         obj_priv = obj->driver_private;
 236
 237         crtc_offset = obj_priv->bo->offset;
 238
 239         crtc_offset_cntl = 0;
 240
 241         /* TODO tiling */
 242         if (0) {
 243                 if (radeon_is_r300(dev_priv))
 244                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 245                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
 246                                              R300_CRTC_MACRO_TILE_EN);
 247                 else
 248                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
 249         } else {
 250                 if (radeon_is_r300(dev_priv))
 251                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 252                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 253                                               R300_CRTC_MACRO_TILE_EN);
 254                 else
 255                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 256         }
 257
 258         base = obj_priv->bo->offset;
 259
 260         /* TODO more tiling */
 261         if (0) {
 262                 if (radeon_is_r300(dev_priv)) {
 263                         crtc_tile_x0_y0 = x | (y << 16);
 264                         base &= ~0x7ff;
 265                 } else {
 266                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 267                         int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
 268                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 269                         crtc_offset_cntl |= (y % 16);
 270                 }
 271         } else {
 272                 int offset = y * crtc->fb->pitch + x;
 273                 switch (crtc->fb->bits_per_pixel) {
 274                 case 15:
 275                 case 16:
 276                         offset *= 2;
 277                         break;
 278                 case 24:
 279                         offset *= 3;
 280                         break;
 281                 case 32:
 282                         offset *= 4;
 283                         break;
 284                 default:
 285                         return false;
 286                 }
 287                 base += offset;
 288         }
 289
 290         base &= ~7;
 291
 292         /* update sarea TODO */
 293
 294         crtc_offset = base;
 295
 296         crtc_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
 297                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 298                        (crtc->fb->bits_per_pixel * 8));
 299         crtc_pitch |= crtc_pitch << 16;
 300
 301         DRM_DEBUG("mc_fb_location: 0x%x\n", dev_priv->fb_location);
 302
 303         RADEON_WRITE(RADEON_DISPLAY_BASE_ADDR, dev_priv->fb_location);
 304
 305         if (radeon_is_r300(dev_priv))
 306                 RADEON_WRITE(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
 307         RADEON_WRITE(RADEON_CRTC_OFFSET_CNTL, crtc_offset_cntl);
 308         RADEON_WRITE(RADEON_CRTC_OFFSET, crtc_offset);
 309         RADEON_WRITE(RADEON_CRTC_PITCH, crtc_pitch);
 310
 311         disp_merge_cntl = RADEON_READ(RADEON_DISP_MERGE_CNTL);
 312         disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
 313         RADEON_WRITE(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
 314
 315         if (dev_priv->is_atom_bios)
 316                 radeon_legacy_atom_set_surface(crtc);
 317
 318         return true;
 319 }
 320
 321 static bool radeon_set_crtc1_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 322 {
 323         struct drm_device *dev = crtc->dev;
 324         struct drm_radeon_private *dev_priv = dev->dev_private;
 325         int format;
 326         int hsync_start;
 327         int hsync_wid;
 328         int vsync_wid;
 329         uint32_t crtc_gen_cntl;
 330         uint32_t crtc_ext_cntl;
 331         uint32_t crtc_h_total_disp;
 332         uint32_t crtc_h_sync_strt_wid;
 333         uint32_t crtc_v_total_disp;
 334         uint32_t crtc_v_sync_strt_wid;
 335
 336         DRM_DEBUG("\n");
 337
 338         switch (crtc->fb->bits_per_pixel) {
 339         case 15:      /*  555 */
 340                 format = 3;
 341                 break;
 342         case 16:      /*  565 */
 343                 format = 4;
 344                 break;
 345         case 24:      /*  RGB */
 346                 format = 5;
 347                 break;
 348         case 32:      /* xRGB */
 349                 format = 6;
 350                 break;
 351         default:
 352                 return false;
 353         }
 354
 355         crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
 356                          | RADEON_CRTC_EN
 357                          | (format << 8)
 358                          | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 359                             ? RADEON_CRTC_DBL_SCAN_EN
 360                             : 0)
 361                          | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 362                             ? RADEON_CRTC_CSYNC_EN
 363                             : 0)
 364                          | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 365                             ? RADEON_CRTC_INTERLACE_EN
 366                             : 0));
 367
 368         crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
 369         crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
 370                           RADEON_CRTC_VSYNC_DIS |
 371                           RADEON_CRTC_HSYNC_DIS |
 372                           RADEON_CRTC_DISPLAY_DIS);
 373
 374         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 375                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 376
 377         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 378         if (!hsync_wid)
 379                 hsync_wid = 1;
 380         hsync_start = mode->crtc_hsync_start - 8;
 381
 382         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
 383                                 | ((hsync_wid & 0x3f) << 16)
 384                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 385                                    ? RADEON_CRTC_H_SYNC_POL
 386                                    : 0));
 387
 388         /* This works for double scan mode. */
 389         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 390                              | ((mode->crtc_vdisplay - 1) << 16));
 391
 392         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 393         if (!vsync_wid)
 394                 vsync_wid = 1;
 395
 396         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 397                                 | ((vsync_wid & 0x1f) << 16)
 398                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 399                                    ? RADEON_CRTC_V_SYNC_POL
 400                                    : 0));
 401
 402         /* TODO -> Dell Server */
 403         if (0) {
 404                 uint32_t disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
 405                 uint32_t tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
 406                 uint32_t dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2);
 407                 uint32_t crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
 408
 409                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
 410                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
 411
 412                 /* For CRT on DAC2, don't turn it on if BIOS didn't
 413                    enable it, even it's detected.
 414                 */
 415                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
 416                 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
 417                 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
 418
 419                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
 420                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 421                 RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 422                 RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
 423         }
 424
 425         RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl |
 426                      RADEON_CRTC_DISP_REQ_EN_B);
 427
 428         RADEON_WRITE_P(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl,
 429                        RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_DISPLAY_DIS);
 430
 431         RADEON_WRITE(RADEON_CRTC_H_TOTAL_DISP, crtc_h_total_disp);
 432         RADEON_WRITE(RADEON_CRTC_H_SYNC_STRT_WID, crtc_h_sync_strt_wid);
 433         RADEON_WRITE(RADEON_CRTC_V_TOTAL_DISP, crtc_v_total_disp);
 434         RADEON_WRITE(RADEON_CRTC_V_SYNC_STRT_WID, crtc_v_sync_strt_wid);
 435
 436         RADEON_WRITE(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
 437
 438         return true;
 439 }
 440
 441 static void radeon_set_pll1(struct drm_crtc *crtc, struct drm_display_mode *mode)
 442 {
 443         struct drm_device *dev = crtc->dev;
 444         struct drm_radeon_private *dev_priv = dev->dev_private;
 445         struct drm_encoder *encoder;
 446         uint32_t feedback_div = 0;
 447         uint32_t reference_div = 0;
 448         uint32_t post_divider = 0;
 449         uint32_t freq = 0;
 450         uint8_t pll_gain;
 451         int pll_flags = RADEON_PLL_LEGACY;
 452         bool use_bios_divs = false;
 453         /* PLL registers */
 454         uint32_t ppll_ref_div = 0;
 455         uint32_t ppll_div_3 = 0;
 456         uint32_t htotal_cntl = 0;
 457         uint32_t vclk_ecp_cntl;
 458
 459         struct radeon_pll *pll = &dev_priv->mode_info.p1pll;
 460
 461         struct {
 462                 int divider;
 463                 int bitvalue;
 464         } *post_div, post_divs[]   = {
 465                 /* From RAGE 128 VR/RAGE 128 GL Register
 466                  * Reference Manual (Technical Reference
 467                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 468                  * 3-17 (PLL_DIV_[3:0]).
 469                  */
 470                 {  1, 0 },              /* VCLK_SRC                 */
 471                 {  2, 1 },              /* VCLK_SRC/2               */
 472                 {  4, 2 },              /* VCLK_SRC/4               */
 473                 {  8, 3 },              /* VCLK_SRC/8               */
 474                 {  3, 4 },              /* VCLK_SRC/3               */
 475                 { 16, 5 },              /* VCLK_SRC/16              */
 476                 {  6, 6 },              /* VCLK_SRC/6               */
 477                 { 12, 7 },              /* VCLK_SRC/12              */
 478                 {  0, 0 }
 479         };
 480
 481         if (mode->clock > 200000) /* range limits??? */
 482                 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 483         else
 484                 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 485
 486         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 487                 if (encoder->crtc == crtc) {
 488                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 489                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 490                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 491                                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 492
 493                                 if (radeon_encoder->use_bios_dividers) {
 494                                         ppll_ref_div = radeon_encoder->panel_ref_divider;
 495                                         ppll_div_3   = (radeon_encoder->panel_fb_divider |
 496                                                         (radeon_encoder->panel_post_divider << 16));
 497                                         htotal_cntl  = 0;
 498                                         use_bios_divs = true;
 499                                 } else
 500                                         pll_flags |= RADEON_PLL_USE_REF_DIV;
 501                         }
 502                 }
 503         }
 504
 505         DRM_DEBUG("\n");
 506
 507         if (!use_bios_divs) {
 508                 radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, pll_flags);
 509
 510                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 511                         if (post_div->divider == post_divider)
 512                                 break;
 513                 }
 514
 515                 if (!post_div->divider) {
 516                         post_div = &post_divs[0];
 517                 }
 518
 519                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 520                           (unsigned)freq,
 521                           feedback_div,
 522                           reference_div,
 523                           post_divider);
 524
 525                 ppll_ref_div   = reference_div;
 526 #if defined(__powerpc__) && (0) /* TODO */
 527                 /* apparently programming this otherwise causes a hang??? */
 528                 if (info->MacModel == RADEON_MAC_IBOOK)
 529                         state->ppll_div_3 = 0x000600ad;
 530                 else
 531 #endif
 532                         ppll_div_3     = (feedback_div | (post_div->bitvalue << 16));
 533                 htotal_cntl    = mode->htotal & 0x7;
 534
 535         }
 536
 537         vclk_ecp_cntl = (RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL) &
 538                          ~RADEON_VCLK_SRC_SEL_MASK) | RADEON_VCLK_SRC_SEL_PPLLCLK;
 539
 540         pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.p1pll.reference_freq,
 541                                            ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 542                                            ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK);
 543
 544         if (dev_priv->flags & RADEON_IS_MOBILITY) {
 545                 /* A temporal workaround for the occational blanking on certain laptop panels.
 546                    This appears to related to the PLL divider registers (fail to lock?).
 547                    It occurs even when all dividers are the same with their old settings.
 548                    In this case we really don't need to fiddle with PLL registers.
 549                    By doing this we can avoid the blanking problem with some panels.
 550                 */
 551                 if ((ppll_ref_div == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
 552                     (ppll_div_3 == (RADEON_READ_PLL(dev_priv, RADEON_PPLL_DIV_3) &
 553                                            (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
 554                         RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
 555                                        RADEON_PLL_DIV_SEL,
 556                                        ~(RADEON_PLL_DIV_SEL));
 557                         radeon_pll_errata_after_index(dev_priv);
 558                         return;
 559                 }
 560         }
 561
 562         RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
 563                            RADEON_VCLK_SRC_SEL_CPUCLK,
 564                            ~(RADEON_VCLK_SRC_SEL_MASK));
 565         RADEON_WRITE_PLL_P(dev_priv,
 566                            RADEON_PPLL_CNTL,
 567                            RADEON_PPLL_RESET
 568                            | RADEON_PPLL_ATOMIC_UPDATE_EN
 569                            | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 570                            | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
 571                            ~(RADEON_PPLL_RESET
 572                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 573                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
 574                              | RADEON_PPLL_PVG_MASK));
 575
 576         RADEON_WRITE_P(RADEON_CLOCK_CNTL_INDEX,
 577                        RADEON_PLL_DIV_SEL,
 578                        ~(RADEON_PLL_DIV_SEL));
 579         radeon_pll_errata_after_index(dev_priv);
 580
 581         if (radeon_is_r300(dev_priv) ||
 582             (dev_priv->chip_family == CHIP_RS300) ||
 583             (dev_priv->chip_family == CHIP_RS400) ||
 584             (dev_priv->chip_family == CHIP_RS480)) {
 585                 if (ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
 586                         /* When restoring console mode, use saved PPLL_REF_DIV
 587                          * setting.
 588                          */
 589                         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 590                                            ppll_ref_div,
 591                                            0);
 592                 } else {
 593                         /* R300 uses ref_div_acc field as real ref divider */
 594                         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 595                                            (ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
 596                                            ~R300_PPLL_REF_DIV_ACC_MASK);
 597                 }
 598         } else {
 599                 RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_REF_DIV,
 600                                    ppll_ref_div,
 601                                    ~RADEON_PPLL_REF_DIV_MASK);
 602         }
 603
 604         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
 605                            ppll_div_3,
 606                            ~RADEON_PPLL_FB3_DIV_MASK);
 607
 608         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_DIV_3,
 609                            ppll_div_3,
 610                            ~RADEON_PPLL_POST3_DIV_MASK);
 611
 612         radeon_pll_write_update(dev);
 613         radeon_pll_wait_for_read_update_complete(dev);
 614
 615         RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL_CNTL, htotal_cntl);
 616
 617         RADEON_WRITE_PLL_P(dev_priv, RADEON_PPLL_CNTL,
 618                            0,
 619                            ~(RADEON_PPLL_RESET
 620                              | RADEON_PPLL_SLEEP
 621                              | RADEON_PPLL_ATOMIC_UPDATE_EN
 622                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
 623
 624         DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 625                   ppll_ref_div,
 626                   ppll_div_3,
 627                   (unsigned)htotal_cntl,
 628                   RADEON_READ_PLL(dev_priv, RADEON_PPLL_CNTL));
 629         DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
 630                   ppll_ref_div & RADEON_PPLL_REF_DIV_MASK,
 631                   ppll_div_3 & RADEON_PPLL_FB3_DIV_MASK,
 632                   (ppll_div_3 & RADEON_PPLL_POST3_DIV_MASK) >> 16);
 633
 634         mdelay(50); /* Let the clock to lock */
 635
 636         RADEON_WRITE_PLL_P(dev_priv, RADEON_VCLK_ECP_CNTL,
 637                            RADEON_VCLK_SRC_SEL_PPLLCLK,
 638                            ~(RADEON_VCLK_SRC_SEL_MASK));
 639
 640         /*RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);*/
 641
 642 }
 643
 644 static bool radeon_set_crtc2_base(struct drm_crtc *crtc, int x, int y)
 645 {
 646         struct drm_device *dev = crtc->dev;
 647         struct drm_radeon_private *dev_priv = dev->dev_private;
 648         struct radeon_framebuffer *radeon_fb;
 649         struct drm_gem_object *obj;
 650         struct drm_radeon_gem_object *obj_priv;
 651         uint32_t base;
 652         uint32_t crtc2_offset, crtc2_offset_cntl, crtc2_tile_x0_y0 = 0;
 653         uint32_t crtc2_pitch;
 654         uint32_t disp2_merge_cntl;
 655
 656         DRM_DEBUG("\n");
 657
 658         radeon_fb = to_radeon_framebuffer(crtc->fb);
 659
 660         obj = radeon_fb->base.mm_private;
 661         obj_priv = obj->driver_private;
 662
 663         crtc2_offset = obj_priv->bo->offset;
 664
 665         crtc2_offset_cntl = 0;
 666
 667         /* TODO tiling */
 668         if (0) {
 669                 if (radeon_is_r300(dev_priv))
 670                         crtc2_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
 671                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
 672                                               R300_CRTC_MACRO_TILE_EN);
 673                 else
 674                         crtc2_offset_cntl |= RADEON_CRTC_TILE_EN;
 675         } else {
 676                 if (radeon_is_r300(dev_priv))
 677                         crtc2_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
 678                                                R300_CRTC_MICRO_TILE_BUFFER_DIS |
 679                                                R300_CRTC_MACRO_TILE_EN);
 680                 else
 681                         crtc2_offset_cntl &= ~RADEON_CRTC_TILE_EN;
 682         }
 683
 684         base = obj_priv->bo->offset;
 685
 686         /* TODO more tiling */
 687         if (0) {
 688                 if (radeon_is_r300(dev_priv)) {
 689                         crtc2_tile_x0_y0 = x | (y << 16);
 690                         base &= ~0x7ff;
 691                 } else {
 692                         int byteshift = crtc->fb->bits_per_pixel >> 4;
 693                         int tile_addr = (((y >> 3) * crtc->fb->width + x) >> (8 - byteshift)) << 11;
 694                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
 695                         crtc2_offset_cntl |= (y % 16);
 696                 }
 697         } else {
 698                 int offset = y * crtc->fb->pitch + x;
 699                 switch (crtc->fb->bits_per_pixel) {
 700                 case 15:
 701                 case 16:
 702                         offset *= 2;
 703                         break;
 704                 case 24:
 705                         offset *= 3;
 706                         break;
 707                 case 32:
 708                         offset *= 4;
 709                         break;
 710                 default:
 711                         return false;
 712                 }
 713                 base += offset;
 714         }
 715
 716         base &= ~7;
 717
 718         /* update sarea TODO */
 719
 720         crtc2_offset = base;
 721
 722         crtc2_pitch  = ((((crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8)) * crtc->fb->bits_per_pixel) +
 723                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
 724                        (crtc->fb->bits_per_pixel * 8));
 725         crtc2_pitch |= crtc2_pitch << 16;
 726
 727         RADEON_WRITE(RADEON_DISPLAY2_BASE_ADDR, dev_priv->fb_location);
 728
 729         if (radeon_is_r300(dev_priv))
 730                 RADEON_WRITE(R300_CRTC2_TILE_X0_Y0, crtc2_tile_x0_y0);
 731         RADEON_WRITE(RADEON_CRTC2_OFFSET_CNTL, crtc2_offset_cntl);
 732         RADEON_WRITE(RADEON_CRTC2_OFFSET, crtc2_offset);
 733         RADEON_WRITE(RADEON_CRTC2_PITCH, crtc2_pitch);
 734
 735         disp2_merge_cntl = RADEON_READ(RADEON_DISP2_MERGE_CNTL);
 736         disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
 737         RADEON_WRITE(RADEON_DISP2_MERGE_CNTL,      disp2_merge_cntl);
 738
 739         if (dev_priv->is_atom_bios)
 740                 radeon_legacy_atom_set_surface(crtc);
 741
 742         return true;
 743 }
 744
 745 static bool radeon_set_crtc2_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
 746 {
 747         struct drm_device *dev = crtc->dev;
 748         struct drm_radeon_private *dev_priv = dev->dev_private;
 749         int format;
 750         int hsync_start;
 751         int hsync_wid;
 752         int vsync_wid;
 753         uint32_t crtc2_gen_cntl;
 754         uint32_t crtc2_h_total_disp;
 755         uint32_t crtc2_h_sync_strt_wid;
 756         uint32_t crtc2_v_total_disp;
 757         uint32_t crtc2_v_sync_strt_wid;
 758         uint32_t fp_h2_sync_strt_wid;
 759         uint32_t fp_v2_sync_strt_wid;
 760
 761         DRM_DEBUG("\n");
 762
 763         switch (crtc->fb->bits_per_pixel) {
 764
 765         case 15:      /*  555 */
 766                 format = 3;
 767                 break;
 768         case 16:      /*  565 */
 769                 format = 4;
 770                 break;
 771         case 24:      /*  RGB */
 772                 format = 5;
 773                 break;
 774         case 32:      /* xRGB */
 775                 format = 6;
 776                 break;
 777         default:
 778                 return false;
 779         }
 780
 781         crtc2_h_total_disp =
 782                 ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
 783                  | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 784
 785         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 786         if (!hsync_wid)
 787                 hsync_wid = 1;
 788         hsync_start = mode->crtc_hsync_start - 8;
 789
 790         crtc2_h_sync_strt_wid = ((hsync_start & 0x1fff)
 791                                  | ((hsync_wid & 0x3f) << 16)
 792                                  | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 793                                     ? RADEON_CRTC_H_SYNC_POL
 794                                     : 0));
 795
 796         /* This works for double scan mode. */
 797         crtc2_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
 798                               | ((mode->crtc_vdisplay - 1) << 16));
 799
 800         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 801         if (!vsync_wid)
 802                 vsync_wid = 1;
 803
 804         crtc2_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
 805                                  | ((vsync_wid & 0x1f) << 16)
 806                                  | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 807                                     ? RADEON_CRTC2_V_SYNC_POL
 808                                     : 0));
 809
 810         /* check to see if TV DAC is enabled for another crtc and keep it enabled */
 811         if (RADEON_READ(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_CRT2_ON)
 812                 crtc2_gen_cntl = RADEON_CRTC2_CRT2_ON;
 813         else
 814                 crtc2_gen_cntl = 0;
 815
 816         crtc2_gen_cntl |= (RADEON_CRTC2_EN
 817                            | (format << 8)
 818                            | RADEON_CRTC2_VSYNC_DIS
 819                            | RADEON_CRTC2_HSYNC_DIS
 820                            | RADEON_CRTC2_DISP_DIS
 821                            | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
 822                               ? RADEON_CRTC2_DBL_SCAN_EN
 823                               : 0)
 824                            | ((mode->flags & DRM_MODE_FLAG_CSYNC)
 825                               ? RADEON_CRTC2_CSYNC_EN
 826                               : 0)
 827                            | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 828                               ? RADEON_CRTC2_INTERLACE_EN
 829                               : 0));
 830
 831         fp_h2_sync_strt_wid = crtc2_h_sync_strt_wid;
 832         fp_v2_sync_strt_wid = crtc2_v_sync_strt_wid;
 833
 834         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,
 835                      crtc2_gen_cntl | RADEON_CRTC2_VSYNC_DIS |
 836                      RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_DIS |
 837                      RADEON_CRTC2_DISP_REQ_EN_B);
 838
 839         RADEON_WRITE(RADEON_CRTC2_H_TOTAL_DISP,    crtc2_h_total_disp);
 840         RADEON_WRITE(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid);
 841         RADEON_WRITE(RADEON_CRTC2_V_TOTAL_DISP,    crtc2_v_total_disp);
 842         RADEON_WRITE(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid);
 843
 844         RADEON_WRITE(RADEON_FP_H2_SYNC_STRT_WID,   fp_h2_sync_strt_wid);
 845         RADEON_WRITE(RADEON_FP_V2_SYNC_STRT_WID,   fp_v2_sync_strt_wid);
 846
 847         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL,        crtc2_gen_cntl);
 848
 849         return true;
 850
 851 }
 852
 853 static void radeon_set_pll2(struct drm_crtc *crtc, struct drm_display_mode *mode)
 854 {
 855         struct drm_device *dev = crtc->dev;
 856         struct drm_radeon_private *dev_priv = dev->dev_private;
 857         struct drm_encoder *encoder;
 858         uint32_t feedback_div = 0;
 859         uint32_t reference_div = 0;
 860         uint32_t post_divider = 0;
 861         uint32_t freq = 0;
 862         uint8_t pll_gain;
 863         int pll_flags = RADEON_PLL_LEGACY;
 864         bool use_bios_divs = false;
 865         /* PLL2 registers */
 866         uint32_t p2pll_ref_div = 0;
 867         uint32_t p2pll_div_0 = 0;
 868         uint32_t htotal_cntl2 = 0;
 869         uint32_t pixclks_cntl;
 870
 871         struct radeon_pll *pll = &dev_priv->mode_info.p2pll;
 872
 873         struct {
 874                 int divider;
 875                 int bitvalue;
 876         } *post_div, post_divs[]   = {
 877                 /* From RAGE 128 VR/RAGE 128 GL Register
 878                  * Reference Manual (Technical Reference
 879                  * Manual P/N RRG-G04100-C Rev. 0.04), page
 880                  * 3-17 (PLL_DIV_[3:0]).
 881                  */
 882                 {  1, 0 },              /* VCLK_SRC                 */
 883                 {  2, 1 },              /* VCLK_SRC/2               */
 884                 {  4, 2 },              /* VCLK_SRC/4               */
 885                 {  8, 3 },              /* VCLK_SRC/8               */
 886                 {  3, 4 },              /* VCLK_SRC/3               */
 887                 {  6, 6 },              /* VCLK_SRC/6               */
 888                 { 12, 7 },              /* VCLK_SRC/12              */
 889                 {  0, 0 }
 890         };
 891
 892         if (mode->clock > 200000) /* range limits??? */
 893                 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
 894         else
 895                 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
 896
 897         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 898                 if (encoder->crtc == crtc) {
 899                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
 900                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
 901                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
 902                                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 903
 904                                 if (radeon_encoder->use_bios_dividers) {
 905                                         p2pll_ref_div = radeon_encoder->panel_ref_divider;
 906                                         p2pll_div_0   = (radeon_encoder->panel_fb_divider |
 907                                                         (radeon_encoder->panel_post_divider << 16));
 908                                         htotal_cntl2  = 0;
 909                                         use_bios_divs = true;
 910                                 } else
 911                                         pll_flags |= RADEON_PLL_USE_REF_DIV;
 912                         }
 913                 }
 914         }
 915
 916         DRM_DEBUG("\n");
 917
 918         if (!use_bios_divs) {
 919                 radeon_compute_pll(pll, mode->clock, &freq, &feedback_div, &reference_div, &post_divider, pll_flags);
 920
 921                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
 922                         if (post_div->divider == post_divider)
 923                                 break;
 924                 }
 925
 926                 if (!post_div->divider) {
 927                         post_div = &post_divs[0];
 928                 }
 929
 930                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
 931                           (unsigned)freq,
 932                           feedback_div,
 933                           reference_div,
 934                           post_divider);
 935
 936                 p2pll_ref_div    = reference_div;
 937                 p2pll_div_0      = (feedback_div | (post_div->bitvalue << 16));
 938                 htotal_cntl2     = mode->htotal & 0x7;
 939
 940         }
 941
 942         pixclks_cntl     = ((RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL) &
 943                              ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
 944                             RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
 945
 946         pll_gain = radeon_compute_pll_gain(dev_priv->mode_info.p2pll.reference_freq,
 947                                            p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 948                                            p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK);
 949
 950
 951         RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
 952                            RADEON_PIX2CLK_SRC_SEL_CPUCLK,
 953                            ~(RADEON_PIX2CLK_SRC_SEL_MASK));
 954
 955         RADEON_WRITE_PLL_P(dev_priv,
 956                            RADEON_P2PLL_CNTL,
 957                            RADEON_P2PLL_RESET
 958                            | RADEON_P2PLL_ATOMIC_UPDATE_EN
 959                            | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
 960                            ~(RADEON_P2PLL_RESET
 961                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
 962                              | RADEON_P2PLL_PVG_MASK));
 963
 964
 965         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_REF_DIV,
 966                            p2pll_ref_div,
 967                            ~RADEON_P2PLL_REF_DIV_MASK);
 968
 969         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
 970                            p2pll_div_0,
 971                            ~RADEON_P2PLL_FB0_DIV_MASK);
 972
 973         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_DIV_0,
 974                            p2pll_div_0,
 975                            ~RADEON_P2PLL_POST0_DIV_MASK);
 976
 977         radeon_pll2_write_update(dev);
 978         radeon_pll2_wait_for_read_update_complete(dev);
 979
 980         RADEON_WRITE_PLL(dev_priv, RADEON_HTOTAL2_CNTL, htotal_cntl2);
 981
 982         RADEON_WRITE_PLL_P(dev_priv, RADEON_P2PLL_CNTL,
 983                            0,
 984                            ~(RADEON_P2PLL_RESET
 985                              | RADEON_P2PLL_SLEEP
 986                              | RADEON_P2PLL_ATOMIC_UPDATE_EN));
 987
 988         DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
 989                   (unsigned)p2pll_ref_div,
 990                   (unsigned)p2pll_div_0,
 991                   (unsigned)htotal_cntl2,
 992                   RADEON_READ_PLL(dev_priv, RADEON_P2PLL_CNTL));
 993         DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
 994                   (unsigned)p2pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
 995                   (unsigned)p2pll_div_0 & RADEON_P2PLL_FB0_DIV_MASK,
 996                   (unsigned)((p2pll_div_0 &
 997                               RADEON_P2PLL_POST0_DIV_MASK) >>16));
 998
 999         mdelay(50); /* Let the clock to lock */
1000
1001         RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL,
1002                            RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
1003                            ~(RADEON_PIX2CLK_SRC_SEL_MASK));
1004
1005         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
1006
1007 }
1008
1009 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
1010                                    struct drm_display_mode *mode,
1011                                    struct drm_display_mode *adjusted_mode)
1012 {
1013         return true;
1014 }
1015
1016 void radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y)
1017 {
1018         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1019
1020         switch(radeon_crtc->crtc_id) {
1021         case 0:
1022                 radeon_set_crtc1_base(crtc, x, y);
1023                 break;
1024         case 1:
1025                 radeon_set_crtc2_base(crtc, x, y);
1026                 break;
1027
1028         }
1029 }
1030
1031 static void radeon_crtc_mode_set(struct drm_crtc *crtc,
1032                                  struct drm_display_mode *mode,
1033                                  struct drm_display_mode *adjusted_mode,
1034                                  int x, int y)
1035 {
1036         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1037
1038         DRM_DEBUG("\n");
1039
1040         /* TODO TV */
1041
1042         radeon_crtc_set_base(crtc, x, y);
1043
1044         switch(radeon_crtc->crtc_id) {
1045         case 0:
1046                 radeon_set_crtc1_timing(crtc, adjusted_mode);
1047                 radeon_set_pll1(crtc, adjusted_mode);
1048                 break;
1049         case 1:
1050                 radeon_set_crtc2_timing(crtc, adjusted_mode);
1051                 radeon_set_pll2(crtc, adjusted_mode);
1052                 break;
1053
1054         }
1055 }
1056
1057 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1058 {
1059         radeon_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1060 }
1061
1062 static void radeon_crtc_commit(struct drm_crtc *crtc)
1063 {
1064         radeon_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1065 }
1066
1067 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1068         .dpms = radeon_crtc_dpms,
1069         .mode_fixup = radeon_crtc_mode_fixup,
1070         .mode_set = radeon_crtc_mode_set,
1071         .mode_set_base = radeon_crtc_set_base,
1072         .prepare = radeon_crtc_prepare,
1073         .commit = radeon_crtc_commit,
1074 };
1075
1076
1077 void radeon_legacy_init_crtc(struct drm_device *dev,
1078                                struct radeon_crtc *radeon_crtc)
1079 {
1080         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1081 }