linux-core/radeon_legacy_encoders.c

   1 /*
   2  * Copyright 2007-8 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include "drmP.h"
  27 #include "drm_crtc_helper.h"
  28 #include "radeon_drm.h"
  29 #include "radeon_drv.h"
  30
  31
  32 static void radeon_legacy_rmx_mode_set(struct drm_encoder *encoder,
  33                                        struct drm_display_mode *mode,
  34                                        struct drm_display_mode *adjusted_mode)
  35 {
  36         struct drm_device *dev = encoder->dev;
  37         struct drm_radeon_private *dev_priv = dev->dev_private;
  38         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  39         int    xres = mode->hdisplay;
  40         int    yres = mode->vdisplay;
  41         bool   hscale = true, vscale = true;
  42         int    hsync_wid;
  43         int    vsync_wid;
  44         int    hsync_start;
  45         uint32_t scale, inc;
  46         uint32_t fp_horz_stretch, fp_vert_stretch, crtc_more_cntl, fp_horz_vert_active;
  47         uint32_t fp_h_sync_strt_wid, fp_v_sync_strt_wid, fp_crtc_h_total_disp, fp_crtc_v_total_disp;
  48
  49         DRM_DEBUG("\n");
  50
  51         fp_vert_stretch = RADEON_READ(RADEON_FP_VERT_STRETCH) &
  52                 (RADEON_VERT_STRETCH_RESERVED |
  53                  RADEON_VERT_AUTO_RATIO_INC);
  54         fp_horz_stretch = RADEON_READ(RADEON_FP_HORZ_STRETCH) &
  55                 (RADEON_HORZ_FP_LOOP_STRETCH |
  56                  RADEON_HORZ_AUTO_RATIO_INC);
  57
  58         crtc_more_cntl = 0;
  59         if ((dev_priv->chip_family == CHIP_RS100) ||
  60             (dev_priv->chip_family == CHIP_RS200)) {
  61                 /* This is to workaround the asic bug for RMX, some versions
  62                    of BIOS dosen't have this register initialized correctly. */
  63                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
  64         }
  65
  66
  67         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
  68                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
  69
  70         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
  71         if (!hsync_wid)
  72                 hsync_wid = 1;
  73         hsync_start = mode->crtc_hsync_start - 8;
  74
  75         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
  76                               | ((hsync_wid & 0x3f) << 16)
  77                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
  78                                  ? RADEON_CRTC_H_SYNC_POL
  79                                  : 0));
  80
  81         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
  82                                 | ((mode->crtc_vdisplay - 1) << 16));
  83
  84         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
  85         if (!vsync_wid)
  86                 vsync_wid = 1;
  87
  88         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
  89                               | ((vsync_wid & 0x1f) << 16)
  90                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
  91                                  ? RADEON_CRTC_V_SYNC_POL
  92                                  : 0));
  93
  94         fp_horz_vert_active = 0;
  95
  96         if (radeon_encoder->panel_xres == 0 ||
  97             radeon_encoder->panel_yres == 0) {
  98                 hscale = false;
  99                 vscale = false;
 100         } else {
 101                 if (xres > radeon_encoder->panel_xres)
 102                         xres = radeon_encoder->panel_xres;
 103                 if (yres > radeon_encoder->panel_yres)
 104                         yres = radeon_encoder->panel_yres;
 105
 106                 if (xres == radeon_encoder->panel_xres)
 107                         hscale = false;
 108                 if (yres == radeon_encoder->panel_yres)
 109                         vscale = false;
 110         }
 111
 112         if (radeon_encoder->flags & RADEON_USE_RMX) {
 113                 if (radeon_encoder->rmx_type != RMX_CENTER) {
 114                         if (!hscale)
 115                                 fp_horz_stretch |= ((xres/8-1) << 16);
 116                         else {
 117                                 inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
 118                                 scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
 119                                         / radeon_encoder->panel_xres + 1;
 120                                 fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
 121                                                     RADEON_HORZ_STRETCH_BLEND |
 122                                                     RADEON_HORZ_STRETCH_ENABLE |
 123                                                     ((radeon_encoder->panel_xres/8-1) << 16));
 124                         }
 125
 126                         if (!vscale)
 127                                 fp_vert_stretch |= ((yres-1) << 12);
 128                         else {
 129                                 inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
 130                                 scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
 131                                         / radeon_encoder->panel_yres + 1;
 132                                 fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
 133                                                     RADEON_VERT_STRETCH_ENABLE |
 134                                                     RADEON_VERT_STRETCH_BLEND |
 135                                                     ((radeon_encoder->panel_yres-1) << 12));
 136                         }
 137                 } else if (radeon_encoder->rmx_type == RMX_CENTER) {
 138                         int    blank_width;
 139
 140                         fp_horz_stretch |= ((xres/8-1) << 16);
 141                         fp_vert_stretch |= ((yres-1) << 12);
 142
 143                         crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
 144                                            RADEON_CRTC_AUTO_VERT_CENTER_EN);
 145
 146                         blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
 147                         if (blank_width > 110)
 148                                 blank_width = 110;
 149
 150                         fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
 151                                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
 152
 153                         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
 154                         if (!hsync_wid)
 155                                 hsync_wid = 1;
 156
 157                         fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
 158                                               | ((hsync_wid & 0x3f) << 16)
 159                                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
 160                                                  ? RADEON_CRTC_H_SYNC_POL
 161                                                  : 0));
 162
 163                         fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
 164                                                 | ((mode->crtc_vdisplay - 1) << 16));
 165
 166                         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
 167                         if (!vsync_wid)
 168                                 vsync_wid = 1;
 169
 170                         fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
 171                                                | ((vsync_wid & 0x1f) << 16)
 172                                                | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
 173                                                   ? RADEON_CRTC_V_SYNC_POL
 174                                                   : 0)));
 175
 176                         fp_horz_vert_active = (((radeon_encoder->panel_yres) & 0xfff) |
 177                                                (((radeon_encoder->panel_xres / 8) & 0x1ff) << 16));
 178                 }
 179         } else {
 180                 fp_horz_stretch |= ((xres/8-1) << 16);
 181                 fp_vert_stretch |= ((yres-1) << 12);
 182         }
 183
 184         RADEON_WRITE(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
 185         RADEON_WRITE(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
 186         RADEON_WRITE(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
 187         RADEON_WRITE(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
 188         RADEON_WRITE(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
 189         RADEON_WRITE(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
 190         RADEON_WRITE(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
 191         RADEON_WRITE(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
 192
 193 }
 194
 195 static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 196 {
 197         struct drm_device *dev = encoder->dev;
 198         struct drm_radeon_private *dev_priv = dev->dev_private;
 199         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 200         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 201         uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
 202         uint32_t bios_5_scratch, bios_6_scratch;
 203
 204         DRM_DEBUG("\n");
 205
 206         // FIXME atom/legacy cards like r4xx
 207         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 208         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 209
 210         bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;
 211         bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_LCD1_CRTC_SHIFT);
 212
 213         switch (mode) {
 214         case DRM_MODE_DPMS_ON:
 215                 disp_pwr_man = RADEON_READ(RADEON_DISP_PWR_MAN);
 216                 disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
 217                 RADEON_WRITE(RADEON_DISP_PWR_MAN, disp_pwr_man);
 218                 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 219                 lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
 220                 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 221                 udelay(1000);
 222                 lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 223                 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
 224                 RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 225
 226                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 227                 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | RADEON_LVDS_DIGON | RADEON_LVDS_BLON);
 228                 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS);
 229                 udelay(radeon_encoder->panel_pwr_delay);
 230                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 231
 232                 /* update bios scratch regs */
 233                 bios_5_scratch |= RADEON_LCD1_ON;
 234                 bios_6_scratch |= RADEON_LCD_DPMS_ON;
 235
 236                 break;
 237         case DRM_MODE_DPMS_STANDBY:
 238         case DRM_MODE_DPMS_SUSPEND:
 239         case DRM_MODE_DPMS_OFF:
 240                 pixclks_cntl = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
 241                 RADEON_WRITE_PLL_P(dev_priv, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
 242                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 243                 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 244                 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
 245                 udelay(radeon_encoder->panel_pwr_delay);
 246                 RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 247                 RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
 248
 249                 bios_5_scratch &= ~RADEON_LCD1_ON;
 250                 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;
 251                 break;
 252         }
 253         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 254         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 255 }
 256
 257 static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 258 {
 259         // fix me: atom/legacy r4xx
 260         radeon_combios_output_lock(encoder, true);
 261         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 262 }
 263
 264 static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 265 {
 266         radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 267         // fix me: atom/legacy r4xx
 268         radeon_combios_output_lock(encoder, false);
 269 }
 270
 271 static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 272                                         struct drm_display_mode *mode,
 273                                         struct drm_display_mode *adjusted_mode)
 274 {
 275         struct drm_device *dev = encoder->dev;
 276         struct drm_radeon_private *dev_priv = dev->dev_private;
 277         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 278         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 279         uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
 280
 281         DRM_DEBUG("\n");
 282
 283         if (radeon_crtc->crtc_id == 0)
 284                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 285
 286         lvds_pll_cntl = RADEON_READ(RADEON_LVDS_PLL_CNTL);
 287         lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 288         if (radeon_encoder->lvds_gen_cntl)
 289                 lvds_gen_cntl = radeon_encoder->lvds_gen_cntl;
 290         else
 291                 lvds_gen_cntl = RADEON_READ(RADEON_LVDS_GEN_CNTL);
 292         lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 293         lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 294                            RADEON_LVDS_BLON |
 295                            RADEON_LVDS_EN |
 296                            RADEON_LVDS_RST_FM);
 297
 298         if (radeon_is_r300(dev_priv))
 299                 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 300
 301         if (radeon_crtc->crtc_id == 0) {
 302                 if (radeon_is_r300(dev_priv)) {
 303                         if (radeon_encoder->flags & RADEON_USE_RMX)
 304                                 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 305                 } else
 306                         lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 307         } else {
 308                 if (radeon_is_r300(dev_priv)) {
 309                         lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 310                 } else
 311                         lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 312         }
 313
 314         RADEON_WRITE(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 315         RADEON_WRITE(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 316
 317         lvds_ss_gen_cntl = RADEON_READ(RADEON_LVDS_SS_GEN_CNTL);
 318         if (radeon_encoder->panel_digon_delay &&
 319             radeon_encoder->panel_blon_delay) {
 320                 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 321                                       (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 322                 lvds_ss_gen_cntl |= ((radeon_encoder->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 323                                      (radeon_encoder->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 324         }
 325
 326         if (dev_priv->chip_family == CHIP_RV410)
 327                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, 0);
 328 }
 329
 330 static bool radeon_legacy_lvds_mode_fixup(struct drm_encoder *encoder,
 331                                           struct drm_display_mode *mode,
 332                                           struct drm_display_mode *adjusted_mode)
 333 {
 334         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 335
 336         radeon_encoder->flags &= ~RADEON_USE_RMX;
 337
 338         if (radeon_encoder->rmx_type != RMX_OFF)
 339                 radeon_rmx_mode_fixup(encoder, mode, adjusted_mode);
 340
 341         return true;
 342 }
 343
 344 static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 345         .dpms = radeon_legacy_lvds_dpms,
 346         .mode_fixup = radeon_legacy_lvds_mode_fixup,
 347         .prepare = radeon_legacy_lvds_prepare,
 348         .mode_set = radeon_legacy_lvds_mode_set,
 349         .commit = radeon_legacy_lvds_commit,
 350 };
 351
 352
 353 static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 354         .destroy = radeon_enc_destroy,
 355 };
 356
 357
 358 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index)
 359 {
 360         struct radeon_encoder *radeon_encoder;
 361         struct drm_encoder *encoder;
 362
 363         DRM_DEBUG("\n");
 364
 365         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 366         if (!radeon_encoder) {
 367                 return NULL;
 368         }
 369
 370         encoder = &radeon_encoder->base;
 371
 372         encoder->possible_crtcs = 0x3;
 373         encoder->possible_clones = 0;
 374         drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs,
 375                          DRM_MODE_ENCODER_LVDS);
 376
 377         drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
 378
 379         /* get the lvds info from the bios */
 380         radeon_combios_get_lvds_info(radeon_encoder);
 381
 382         /* LVDS gets default RMX full scaling */
 383         radeon_encoder->rmx_type = RMX_FULL;
 384
 385         return encoder;
 386 }
 387
 388 static bool radeon_legacy_primary_dac_mode_fixup(struct drm_encoder *encoder,
 389                                                  struct drm_display_mode *mode,
 390                                                  struct drm_display_mode *adjusted_mode)
 391 {
 392         return true;
 393 }
 394
 395 static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 396 {
 397         struct drm_device *dev = encoder->dev;
 398         struct drm_radeon_private *dev_priv = dev->dev_private;
 399         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 400         uint32_t crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
 401         uint32_t dac_cntl = RADEON_READ(RADEON_DAC_CNTL);
 402         uint32_t dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 403         uint32_t bios_5_scratch, bios_6_scratch;
 404
 405         DRM_DEBUG("\n");
 406
 407         // FIXME atom/legacy cards like r4xx
 408         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 409         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 410
 411         bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;
 412         bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT1_CRTC_SHIFT);
 413
 414         DRM_DEBUG("\n");
 415
 416         switch(mode) {
 417         case DRM_MODE_DPMS_ON:
 418                 crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 419                 dac_cntl &= ~RADEON_DAC_PDWN;
 420                 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 421                                     RADEON_DAC_PDWN_G |
 422                                     RADEON_DAC_PDWN_B);
 423                 bios_5_scratch |= RADEON_CRT1_ON;
 424                 bios_6_scratch |= RADEON_CRT_DPMS_ON;
 425                 break;
 426         case DRM_MODE_DPMS_STANDBY:
 427         case DRM_MODE_DPMS_SUSPEND:
 428         case DRM_MODE_DPMS_OFF:
 429                 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 430                 dac_cntl |= RADEON_DAC_PDWN;
 431                 dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 432                                    RADEON_DAC_PDWN_G |
 433                                    RADEON_DAC_PDWN_B);
 434                 bios_5_scratch &= ~RADEON_CRT1_ON;
 435                 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
 436                 break;
 437         }
 438
 439         RADEON_WRITE(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 440         RADEON_WRITE(RADEON_DAC_CNTL, dac_cntl);
 441         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 442
 443         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 444         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 445 }
 446
 447 static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 448 {
 449         // fix me: atom/legacy r4xx
 450         radeon_combios_output_lock(encoder, true);
 451         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 452 }
 453
 454 static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 455 {
 456         radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 457         // fix me: atom/legacy r4xx
 458         radeon_combios_output_lock(encoder, false);
 459 }
 460
 461 static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 462                                                struct drm_display_mode *mode,
 463                                                struct drm_display_mode *adjusted_mode)
 464 {
 465         struct drm_device *dev = encoder->dev;
 466         struct drm_radeon_private *dev_priv = dev->dev_private;
 467         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 468         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 469         uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 470
 471         DRM_DEBUG("\n");
 472
 473         if (radeon_crtc->crtc_id == 0)
 474                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 475
 476         if (radeon_crtc->crtc_id == 0) {
 477                 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
 478                         disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
 479                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 480                         RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 481                 } else {
 482                         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 483                         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 484                 }
 485         } else {
 486                 if (dev_priv->chip_family == CHIP_R200 || radeon_is_r300(dev_priv)) {
 487                         disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL) &
 488                                 ~(RADEON_DISP_DAC_SOURCE_MASK);
 489                         disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 490                         RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 491                 } else {
 492                         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 493                         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
 494                 }
 495         }
 496
 497         dac_cntl = (RADEON_DAC_MASK_ALL |
 498                     RADEON_DAC_VGA_ADR_EN |
 499                     /* TODO 6-bits */
 500                     RADEON_DAC_8BIT_EN);
 501
 502         RADEON_WRITE_P(RADEON_DAC_CNTL,
 503                        dac_cntl,
 504                        RADEON_DAC_RANGE_CNTL |
 505                        RADEON_DAC_BLANKING);
 506
 507         if (radeon_encoder->ps2_pdac_adj)
 508                 dac_macro_cntl = radeon_encoder->ps2_pdac_adj;
 509         else
 510                 dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 511         dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
 512         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 513 }
 514
 515 static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
 516                                                                   struct drm_connector *connector)
 517 {
 518         struct drm_device *dev = encoder->dev;
 519         struct drm_radeon_private *dev_priv = dev->dev_private;
 520         uint32_t vclk_ecp_cntl, crtc_ext_cntl;
 521         uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
 522         enum drm_connector_status found = connector_status_disconnected;
 523         bool color = true;
 524
 525         /* save the regs we need */
 526         vclk_ecp_cntl = RADEON_READ_PLL(dev_priv, RADEON_VCLK_ECP_CNTL);
 527         crtc_ext_cntl = RADEON_READ(RADEON_CRTC_EXT_CNTL);
 528         dac_ext_cntl = RADEON_READ(RADEON_DAC_EXT_CNTL);
 529         dac_cntl = RADEON_READ(RADEON_DAC_CNTL);
 530         dac_macro_cntl = RADEON_READ(RADEON_DAC_MACRO_CNTL);
 531
 532         tmp = vclk_ecp_cntl &
 533                 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
 534         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, tmp);
 535
 536         tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
 537         RADEON_WRITE(RADEON_CRTC_EXT_CNTL, tmp);
 538
 539         tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
 540                 RADEON_DAC_FORCE_DATA_EN;
 541
 542         if (color)
 543                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
 544         else
 545                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
 546
 547         if (radeon_is_r300(dev_priv))
 548                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
 549         else
 550                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
 551
 552         RADEON_WRITE(RADEON_DAC_EXT_CNTL, tmp);
 553
 554         tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
 555         tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
 556         RADEON_WRITE(RADEON_DAC_CNTL, tmp);
 557
 558         tmp &= ~(RADEON_DAC_PDWN_R |
 559                  RADEON_DAC_PDWN_G |
 560                  RADEON_DAC_PDWN_B);
 561
 562         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, tmp);
 563
 564         udelay(2000);
 565
 566         if (RADEON_READ(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
 567                 found = connector_status_connected;
 568
 569         /* restore the regs we used */
 570         RADEON_WRITE(RADEON_DAC_CNTL, dac_cntl);
 571         RADEON_WRITE(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 572         RADEON_WRITE(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
 573         RADEON_WRITE(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 574         RADEON_WRITE_PLL(dev_priv, RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
 575
 576         return found;
 577 }
 578
 579 static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 580         .dpms = radeon_legacy_primary_dac_dpms,
 581         .mode_fixup = radeon_legacy_primary_dac_mode_fixup,
 582         .prepare = radeon_legacy_primary_dac_prepare,
 583         .mode_set = radeon_legacy_primary_dac_mode_set,
 584         .commit = radeon_legacy_primary_dac_commit,
 585         .detect = radeon_legacy_primary_dac_detect,
 586 };
 587
 588
 589 static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 590         .destroy = radeon_enc_destroy,
 591 };
 592
 593 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int has_tv)
 594 {
 595         struct radeon_encoder *radeon_encoder;
 596         struct drm_encoder *encoder;
 597
 598         DRM_DEBUG("\n");
 599
 600         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 601         if (!radeon_encoder) {
 602                 return NULL;
 603         }
 604
 605         encoder = &radeon_encoder->base;
 606
 607         encoder->possible_crtcs = 0x3;
 608         encoder->possible_clones = 0;
 609         drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs,
 610                          DRM_MODE_ENCODER_DAC);
 611
 612         drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
 613
 614         /* get the primary dac bg/adj vals from bios tables */
 615         radeon_combios_get_primary_dac_info(radeon_encoder);
 616
 617         return encoder;
 618 }
 619
 620
 621 static bool radeon_legacy_tmds_int_mode_fixup(struct drm_encoder *encoder,
 622                                               struct drm_display_mode *mode,
 623                                               struct drm_display_mode *adjusted_mode)
 624 {
 625         return true;
 626 }
 627
 628 static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 629 {
 630         struct drm_device *dev = encoder->dev;
 631         struct drm_radeon_private *dev_priv = dev->dev_private;
 632         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 633         uint32_t fp_gen_cntl = RADEON_READ(RADEON_FP_GEN_CNTL);
 634         uint32_t bios_5_scratch, bios_6_scratch;
 635
 636         DRM_DEBUG("\n");
 637
 638         // FIXME atom/legacy cards like r4xx
 639         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 640         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 641
 642         bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;
 643         bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP1_CRTC_SHIFT);
 644
 645         switch(mode) {
 646         case DRM_MODE_DPMS_ON:
 647                 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 648                 bios_5_scratch |= RADEON_DFP1_ON;
 649                 bios_6_scratch |= RADEON_DFP_DPMS_ON;
 650                 break;
 651         case DRM_MODE_DPMS_STANDBY:
 652         case DRM_MODE_DPMS_SUSPEND:
 653         case DRM_MODE_DPMS_OFF:
 654                 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 655                 bios_5_scratch &= ~RADEON_DFP1_ON;
 656                 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
 657                 break;
 658         }
 659
 660         RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 661
 662         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 663         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 664 }
 665
 666 static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 667 {
 668         // fix me: atom/legacy r4xx
 669         radeon_combios_output_lock(encoder, true);
 670         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 671 }
 672
 673 static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 674 {
 675         radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 676         // fix me: atom/legacy r4xx
 677         radeon_combios_output_lock(encoder, true);
 678 }
 679
 680 static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 681                                             struct drm_display_mode *mode,
 682                                             struct drm_display_mode *adjusted_mode)
 683 {
 684         struct drm_device *dev = encoder->dev;
 685         struct drm_radeon_private *dev_priv = dev->dev_private;
 686         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 687         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 688         uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 689         int i;
 690
 691         DRM_DEBUG("\n");
 692
 693         if (radeon_crtc->crtc_id == 0)
 694                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 695
 696         tmp = tmds_pll_cntl = RADEON_READ(RADEON_TMDS_PLL_CNTL);
 697         tmp &= 0xfffff;
 698         if (dev_priv->chip_family == CHIP_RV280) {
 699                 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 700                 tmp ^= (1 << 22);
 701                 tmds_pll_cntl ^= (1 << 22);
 702         }
 703
 704         for (i = 0; i < 4; i++) {
 705                 if (radeon_encoder->tmds_pll[i].freq == 0)
 706                         break;
 707                 if ((uint32_t)(mode->clock / 10) < radeon_encoder->tmds_pll[i].freq) {
 708                         tmp = radeon_encoder->tmds_pll[i].value ;
 709                         break;
 710                 }
 711         }
 712
 713         if (radeon_is_r300(dev_priv) || (dev_priv->chip_family == CHIP_RV280)) {
 714                 if (tmp & 0xfff00000)
 715                         tmds_pll_cntl = tmp;
 716                 else {
 717                         tmds_pll_cntl &= 0xfff00000;
 718                         tmds_pll_cntl |= tmp;
 719                 }
 720         } else
 721                 tmds_pll_cntl = tmp;
 722
 723         tmds_transmitter_cntl = RADEON_READ(RADEON_TMDS_TRANSMITTER_CNTL) &
 724                 ~(RADEON_TMDS_TRANSMITTER_PLLRST);
 725
 726     if (dev_priv->chip_family == CHIP_R200 ||
 727         dev_priv->chip_family == CHIP_R100 ||
 728         radeon_is_r300(dev_priv))
 729             tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 730     else /* RV chips got this bit reversed */
 731             tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 732
 733     fp_gen_cntl = (RADEON_READ(RADEON_FP_GEN_CNTL) |
 734                    (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 735                     RADEON_FP_CRTC_DONT_SHADOW_HEND));
 736
 737     fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 738
 739     if (1) // FIXME rgbBits == 8
 740             fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 741     else
 742             fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 743
 744     if (radeon_crtc->crtc_id == 0) {
 745             if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
 746                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 747                     if (radeon_encoder->flags & RADEON_USE_RMX)
 748                             fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 749                     else
 750                             fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 751             } else
 752                     fp_gen_cntl |= RADEON_FP_SEL_CRTC1;
 753     } else {
 754             if (radeon_is_r300(dev_priv) || dev_priv->chip_family == CHIP_R200) {
 755                     fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 756                     fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 757             } else
 758                     fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 759     }
 760
 761     RADEON_WRITE(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 762     RADEON_WRITE(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 763     RADEON_WRITE(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 764 }
 765
 766 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 767         .dpms = radeon_legacy_tmds_int_dpms,
 768         .mode_fixup = radeon_legacy_tmds_int_mode_fixup,
 769         .prepare = radeon_legacy_tmds_int_prepare,
 770         .mode_set = radeon_legacy_tmds_int_mode_set,
 771         .commit = radeon_legacy_tmds_int_commit,
 772 };
 773
 774
 775 static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 776         .destroy = radeon_enc_destroy,
 777 };
 778
 779 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index)
 780 {
 781         struct radeon_encoder *radeon_encoder;
 782         struct drm_encoder *encoder;
 783
 784         DRM_DEBUG("\n");
 785
 786         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 787         if (!radeon_encoder) {
 788                 return NULL;
 789         }
 790
 791         encoder = &radeon_encoder->base;
 792
 793         encoder->possible_crtcs = 0x3;
 794         encoder->possible_clones = 0;
 795         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs,
 796                          DRM_MODE_ENCODER_TMDS);
 797
 798         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
 799
 800         radeon_combios_get_tmds_info(radeon_encoder);
 801
 802         return encoder;
 803 }
 804
 805 static bool radeon_legacy_tmds_ext_mode_fixup(struct drm_encoder *encoder,
 806                                               struct drm_display_mode *mode,
 807                                               struct drm_display_mode *adjusted_mode)
 808 {
 809         return true;
 810 }
 811
 812 static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 813 {
 814         struct drm_device *dev = encoder->dev;
 815         struct drm_radeon_private *dev_priv = dev->dev_private;
 816         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 817         uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 818         uint32_t bios_5_scratch, bios_6_scratch;
 819
 820         DRM_DEBUG("\n");
 821
 822         // FIXME atom/legacy cards like r4xx
 823         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 824         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 825
 826         bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;
 827         bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_DFP2_CRTC_SHIFT);
 828
 829         switch(mode) {
 830         case DRM_MODE_DPMS_ON:
 831                 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 832                 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 833                 bios_5_scratch |= RADEON_DFP2_ON;
 834                 bios_6_scratch |= RADEON_DFP_DPMS_ON;
 835                 break;
 836         case DRM_MODE_DPMS_STANDBY:
 837         case DRM_MODE_DPMS_SUSPEND:
 838         case DRM_MODE_DPMS_OFF:
 839                 fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 840                 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 841                 bios_5_scratch &= ~RADEON_DFP2_ON;
 842                 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;
 843                 break;
 844         }
 845
 846         RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 847
 848         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
 849         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
 850 }
 851
 852 static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 853 {
 854         // fix me: atom/legacy r4xx
 855         radeon_combios_output_lock(encoder, true);
 856         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 857 }
 858
 859 static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 860 {
 861         radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 862         // fix me: atom/legacy r4xx
 863         radeon_combios_output_lock(encoder, false);
 864 }
 865
 866 static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 867                                             struct drm_display_mode *mode,
 868                                             struct drm_display_mode *adjusted_mode)
 869 {
 870         struct drm_device *dev = encoder->dev;
 871         struct drm_radeon_private *dev_priv = dev->dev_private;
 872         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 873         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 874         uint32_t fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 875
 876         DRM_DEBUG("\n");
 877
 878         if (radeon_crtc->crtc_id == 0)
 879                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
 880
 881         if (1) // FIXME rgbBits == 8
 882                 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 883         else
 884                 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 885
 886         fp2_gen_cntl &= ~(RADEON_FP2_ON |
 887                           RADEON_FP2_DVO_EN |
 888                           RADEON_FP2_DVO_RATE_SEL_SDR);
 889
 890         /* XXX: these are oem specific */
 891         if (radeon_is_r300(dev_priv)) {
 892                 if ((dev->pdev->device == 0x4850) &&
 893                     (dev->pdev->subsystem_vendor == 0x1028) &&
 894                     (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 895                         fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 896                 else
 897                         fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 898
 899                 /*if (mode->clock > 165000)
 900                         fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 901         }
 902
 903         if (radeon_crtc->crtc_id == 0) {
 904                 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
 905                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 906                         if (radeon_encoder->flags & RADEON_USE_RMX)
 907                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 908                         else
 909                                 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 910                 } else
 911                         fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 912         } else {
 913                 if ((dev_priv->chip_family == CHIP_R200) || radeon_is_r300(dev_priv)) {
 914                         fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 915                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 916                 } else
 917                         fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 918         }
 919
 920         RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 921 }
 922
 923 static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 924         .dpms = radeon_legacy_tmds_ext_dpms,
 925         .mode_fixup = radeon_legacy_tmds_ext_mode_fixup,
 926         .prepare = radeon_legacy_tmds_ext_prepare,
 927         .mode_set = radeon_legacy_tmds_ext_mode_set,
 928         .commit = radeon_legacy_tmds_ext_commit,
 929 };
 930
 931
 932 static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 933         .destroy = radeon_enc_destroy,
 934 };
 935
 936 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index)
 937 {
 938         struct radeon_encoder *radeon_encoder;
 939         struct drm_encoder *encoder;
 940
 941         DRM_DEBUG("\n");
 942
 943         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
 944         if (!radeon_encoder) {
 945                 return NULL;
 946         }
 947
 948         encoder = &radeon_encoder->base;
 949
 950         encoder->possible_crtcs = 0x3;
 951         encoder->possible_clones = 0;
 952         drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs,
 953                          DRM_MODE_ENCODER_TMDS);
 954
 955         drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
 956
 957         //radeon_combios_get_tmds_info(radeon_encoder);
 958         return encoder;
 959 }
 960
 961 static bool radeon_legacy_tv_dac_mode_fixup(struct drm_encoder *encoder,
 962                                             struct drm_display_mode *mode,
 963                                             struct drm_display_mode *adjusted_mode)
 964 {
 965         return true;
 966 }
 967
 968 static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
 969 {
 970         struct drm_device *dev = encoder->dev;
 971         struct drm_radeon_private *dev_priv = dev->dev_private;
 972         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 973         uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
 974         //uint32_t tv_master_cntl = 0;
 975         uint32_t bios_5_scratch, bios_6_scratch;
 976
 977         DRM_DEBUG("\n");
 978
 979         // FIXME atom/legacy cards like r4xx
 980         bios_5_scratch = RADEON_READ(RADEON_BIOS_5_SCRATCH);
 981         bios_6_scratch = RADEON_READ(RADEON_BIOS_6_SCRATCH);
 982
 983         bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;
 984         bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_CRT2_CRTC_SHIFT);
 985         // FIXME TV
 986         //bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;
 987         //bios_5_scratch |= (radeon_crtc->crtc_id << RADEON_TV1_CRTC_SHIFT);
 988
 989         if (dev_priv->chip_family == CHIP_R200)
 990                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
 991         else {
 992                 crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
 993                 // FIXME TV
 994                 //tv_master_cntl = RADEON_READ(RADEON_TV_MASTER_CNTL);
 995                 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
 996         }
 997
 998         switch(mode) {
 999         case DRM_MODE_DPMS_ON:
1000                 if (dev_priv->chip_family == CHIP_R200)
1001                         fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1002                 else {
1003                         crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1004                         //tv_master_cntl |= RADEON_TV_ON;
1005                         if (dev_priv->chip_family == CHIP_R420 ||
1006                             dev_priv->chip_family == CHIP_RV410)
1007                                 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1008                                                  R420_TV_DAC_GDACPD |
1009                                                  R420_TV_DAC_BDACPD |
1010                                                  RADEON_TV_DAC_BGSLEEP);
1011                         else
1012                                 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1013                                                  RADEON_TV_DAC_GDACPD |
1014                                                  RADEON_TV_DAC_BDACPD |
1015                                                  RADEON_TV_DAC_BGSLEEP);
1016                 }
1017                 //bios_5_scratch |= RADEON_TV1_ON;
1018                 //bios_6_scratch |= RADEON_TV_DPMS_ON;
1019                 bios_5_scratch |= RADEON_CRT2_ON;
1020                 bios_6_scratch |= RADEON_CRT_DPMS_ON;
1021                 break;
1022         case DRM_MODE_DPMS_STANDBY:
1023         case DRM_MODE_DPMS_SUSPEND:
1024         case DRM_MODE_DPMS_OFF:
1025                 if (dev_priv->chip_family == CHIP_R200)
1026                         fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1027                 else {
1028                         crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1029                         //tv_master_cntl &= ~RADEON_TV_ON;
1030                         if (dev_priv->chip_family == CHIP_R420 ||
1031                             dev_priv->chip_family == CHIP_RV410)
1032                                 tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1033                                                 R420_TV_DAC_GDACPD |
1034                                                 R420_TV_DAC_BDACPD |
1035                                                 RADEON_TV_DAC_BGSLEEP);
1036                         else
1037                                 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1038                                                 RADEON_TV_DAC_GDACPD |
1039                                                 RADEON_TV_DAC_BDACPD |
1040                                                 RADEON_TV_DAC_BGSLEEP);
1041                 }
1042                 //bios_5_scratch &= ~RADEON_TV1_ON;
1043                 //bios_6_scratch &= ~RADEON_TV_DPMS_ON;
1044                 bios_5_scratch &= ~RADEON_CRT2_ON;
1045                 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;
1046                 break;
1047         }
1048
1049         if (dev_priv->chip_family == CHIP_R200)
1050                 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1051         else {
1052                 RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1053                 //RADEON_WRITE(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1054                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1055         }
1056
1057         RADEON_WRITE(RADEON_BIOS_5_SCRATCH, bios_5_scratch);
1058         RADEON_WRITE(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1059 }
1060
1061 static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1062 {
1063         // fix me: atom/legacy r4xx
1064         radeon_combios_output_lock(encoder, true);
1065         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1066 }
1067
1068 static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1069 {
1070         radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1071         // fix me: atom/legacy r4xx
1072         radeon_combios_output_lock(encoder, false);
1073 }
1074
1075 static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1076                                           struct drm_display_mode *mode,
1077                                           struct drm_display_mode *adjusted_mode)
1078 {
1079         struct drm_device *dev = encoder->dev;
1080         struct drm_radeon_private *dev_priv = dev->dev_private;
1081         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1082         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1083         uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1084         uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0;
1085
1086         DRM_DEBUG("\n");
1087
1088         if (radeon_crtc->crtc_id == 0)
1089                 radeon_legacy_rmx_mode_set(encoder, mode, adjusted_mode);
1090
1091         if (dev_priv->chip_family != CHIP_R200) {
1092                 tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
1093                 if (dev_priv->chip_family == CHIP_R420 ||
1094                     dev_priv->chip_family == CHIP_RV410) {
1095                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1096                                          RADEON_TV_DAC_BGADJ_MASK |
1097                                          R420_TV_DAC_DACADJ_MASK |
1098                                          R420_TV_DAC_RDACPD |
1099                                          R420_TV_DAC_GDACPD |
1100                                          R420_TV_DAC_GDACPD |
1101                                          R420_TV_DAC_TVENABLE);
1102                 } else {
1103                         tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1104                                          RADEON_TV_DAC_BGADJ_MASK |
1105                                          RADEON_TV_DAC_DACADJ_MASK |
1106                                          RADEON_TV_DAC_RDACPD |
1107                                          RADEON_TV_DAC_GDACPD |
1108                                          RADEON_TV_DAC_GDACPD);
1109                 }
1110
1111                 // FIXME TV
1112                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1113                                 RADEON_TV_DAC_NHOLD |
1114                                 RADEON_TV_DAC_STD_PS2 |
1115                                 radeon_encoder->ps2_tvdac_adj);
1116
1117                 RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1118         }
1119
1120         if (radeon_is_r300(dev_priv)) {
1121                 gpiopad_a = RADEON_READ(RADEON_GPIOPAD_A) | 1;
1122                 disp_output_cntl = RADEON_READ(RADEON_DISP_OUTPUT_CNTL);
1123         } else if (dev_priv->chip_family == CHIP_R200)
1124                 fp2_gen_cntl = RADEON_READ(RADEON_FP2_GEN_CNTL);
1125         else
1126                 disp_hw_debug = RADEON_READ(RADEON_DISP_HW_DEBUG);
1127
1128         dac2_cntl = RADEON_READ(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1129
1130         if (radeon_crtc->crtc_id == 0) {
1131                 if (radeon_is_r300(dev_priv)) {
1132                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1133                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1134                 } else if (dev_priv->chip_family == CHIP_R200) {
1135                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1136                                           RADEON_FP2_DVO_RATE_SEL_SDR);
1137                 } else
1138                         disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1139         } else {
1140                 if (radeon_is_r300(dev_priv)) {
1141                         disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1142                         disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1143                 } else if (dev_priv->chip_family == CHIP_R200) {
1144                         fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1145                                           RADEON_FP2_DVO_RATE_SEL_SDR);
1146                         fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1147                 } else
1148                         disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1149         }
1150
1151         RADEON_WRITE(RADEON_DAC_CNTL2, dac2_cntl);
1152
1153         if (radeon_is_r300(dev_priv)) {
1154                 RADEON_WRITE_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1155                 RADEON_WRITE(RADEON_DISP_TV_OUT_CNTL, disp_output_cntl);
1156         } else if (dev_priv->chip_family == CHIP_R200)
1157                 RADEON_WRITE(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1158         else
1159                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1160
1161 }
1162
1163 static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1164                                                              struct drm_connector *connector)
1165 {
1166         struct drm_device *dev = encoder->dev;
1167         struct drm_radeon_private *dev_priv = dev->dev_private;
1168         uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1169         uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
1170         enum drm_connector_status found = connector_status_disconnected;
1171         bool color = true;
1172
1173         // FIXME tv
1174
1175         /* save the regs we need */
1176         pixclks_cntl = RADEON_READ_PLL(dev_priv, RADEON_PIXCLKS_CNTL);
1177         gpiopad_a = radeon_is_r300(dev_priv) ? RADEON_READ(RADEON_GPIOPAD_A) : 0;
1178         disp_output_cntl = radeon_is_r300(dev_priv) ? RADEON_READ(RADEON_DISP_OUTPUT_CNTL) : 0;
1179         disp_hw_debug = radeon_is_r300(dev_priv) ? 0 : RADEON_READ(RADEON_DISP_HW_DEBUG);
1180         crtc2_gen_cntl = RADEON_READ(RADEON_CRTC2_GEN_CNTL);
1181         tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
1182         dac_ext_cntl = RADEON_READ(RADEON_DAC_EXT_CNTL);
1183         dac_cntl2 = RADEON_READ(RADEON_DAC_CNTL2);
1184
1185         tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1186                                | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1187         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, tmp);
1188
1189         if (radeon_is_r300(dev_priv))
1190                 RADEON_WRITE_P(RADEON_GPIOPAD_A, 1, ~1);
1191
1192         tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1193         tmp |= RADEON_CRTC2_CRT2_ON |
1194                 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1195
1196         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, tmp);
1197
1198         if (radeon_is_r300(dev_priv)) {
1199                 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1200                 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1201                 RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, tmp);
1202         } else {
1203                 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1204                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, tmp);
1205         }
1206
1207         tmp = RADEON_TV_DAC_NBLANK |
1208                 RADEON_TV_DAC_NHOLD |
1209                 RADEON_TV_MONITOR_DETECT_EN |
1210                 RADEON_TV_DAC_STD_PS2;
1211
1212         RADEON_WRITE(RADEON_TV_DAC_CNTL, tmp);
1213
1214         tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1215                 RADEON_DAC2_FORCE_DATA_EN;
1216
1217         if (color)
1218                 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1219         else
1220                 tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1221
1222         if (radeon_is_r300(dev_priv))
1223                 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1224         else
1225                 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1226
1227         RADEON_WRITE(RADEON_DAC_EXT_CNTL, tmp);
1228
1229         tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1230         RADEON_WRITE(RADEON_DAC_CNTL2, tmp);
1231
1232         udelay(10000);
1233
1234         if (radeon_is_r300(dev_priv)) {
1235                 if (RADEON_READ(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1236                         found = connector_status_connected;
1237         } else {
1238                 if (RADEON_READ(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1239                         found = connector_status_connected;
1240         }
1241
1242         /* restore regs we used */
1243         RADEON_WRITE(RADEON_DAC_CNTL2, dac_cntl2);
1244         RADEON_WRITE(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1245         RADEON_WRITE(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1246         RADEON_WRITE(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1247
1248         if (radeon_is_r300(dev_priv)) {
1249                 RADEON_WRITE(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1250                 RADEON_WRITE_P(RADEON_GPIOPAD_A, gpiopad_a, ~1 );
1251         } else {
1252                 RADEON_WRITE(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1253         }
1254         RADEON_WRITE_PLL(dev_priv, RADEON_PIXCLKS_CNTL, pixclks_cntl);
1255
1256         //return found;
1257         return connector_status_disconnected;
1258
1259 }
1260
1261 static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1262         .dpms = radeon_legacy_tv_dac_dpms,
1263         .mode_fixup = radeon_legacy_tv_dac_mode_fixup,
1264         .prepare = radeon_legacy_tv_dac_prepare,
1265         .mode_set = radeon_legacy_tv_dac_mode_set,
1266         .commit = radeon_legacy_tv_dac_commit,
1267         .detect = radeon_legacy_tv_dac_detect,
1268 };
1269
1270
1271 static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1272         .destroy = radeon_enc_destroy,
1273 };
1274
1275 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int has_tv)
1276 {
1277         struct radeon_encoder *radeon_encoder;
1278         struct drm_encoder *encoder;
1279
1280         DRM_DEBUG("\n");
1281
1282         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1283         if (!radeon_encoder) {
1284                 return NULL;
1285         }
1286
1287         encoder = &radeon_encoder->base;
1288
1289         encoder->possible_crtcs = 0x3;
1290         encoder->possible_clones = 0;
1291         drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs,
1292                          DRM_MODE_ENCODER_DAC);
1293
1294         drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1295
1296         /* get the tv dac vals from bios tables */
1297         radeon_combios_get_tv_info(radeon_encoder);
1298         radeon_combios_get_tv_dac_info(radeon_encoder);
1299
1300         return encoder;
1301 }