1 //===- FastISel.h - Definition of the FastISel class ------------*- C++ -*-===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/ADT/StringRef.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 #include "llvm/IR/Attributes.h"
23 #include "llvm/IR/CallingConv.h"
24 #include "llvm/IR/DebugLoc.h"
25 #include "llvm/IR/DerivedTypes.h"
26 #include "llvm/IR/InstrTypes.h"
27 #include "llvm/IR/IntrinsicInst.h"
28 #include "llvm/Support/MachineValueType.h"
41 class FunctionLoweringInfo;
43 class MachineConstantPool;
44 class MachineFrameInfo;
45 class MachineFunction;
47 class MachineMemOperand;
49 class MachineRegisterInfo;
53 class TargetInstrInfo;
54 class TargetLibraryInfo;
56 class TargetRegisterClass;
57 class TargetRegisterInfo;
62 /// This is a fast-path instruction selection class that generates poor
63 /// code and doesn't support illegal types or non-trivial lowering, but runs
67 using ArgListEntry = TargetLoweringBase::ArgListEntry;
68 using ArgListTy = TargetLoweringBase::ArgListTy;
69 struct CallLoweringInfo {
70 Type *RetTy = nullptr;
75 bool DoesNotReturn : 1;
76 bool IsReturnValueUsed : 1;
77 bool IsPatchPoint : 1;
79 // IsTailCall Should be modified by implementations of FastLowerCall
80 // that perform tail call conversions.
81 bool IsTailCall = false;
83 unsigned NumFixedArgs = -1;
84 CallingConv::ID CallConv = CallingConv::C;
85 const Value *Callee = nullptr;
86 MCSymbol *Symbol = nullptr;
88 const CallBase *CB = nullptr;
89 MachineInstr *Call = nullptr;
91 unsigned NumResultRegs = 0;
93 SmallVector<Value *, 16> OutVals;
94 SmallVector<ISD::ArgFlagsTy, 16> OutFlags;
95 SmallVector<Register, 16> OutRegs;
96 SmallVector<ISD::InputArg, 4> Ins;
97 SmallVector<Register, 4> InRegs;
100 : RetSExt(false), RetZExt(false), IsVarArg(false), IsInReg(false),
101 DoesNotReturn(false), IsReturnValueUsed(true), IsPatchPoint(false) {}
103 CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
104 const Value *Target, ArgListTy &&ArgsList,
105 const CallBase &Call) {
109 IsInReg = Call.hasRetAttr(Attribute::InReg);
110 DoesNotReturn = Call.doesNotReturn();
111 IsVarArg = FuncTy->isVarArg();
112 IsReturnValueUsed = !Call.use_empty();
113 RetSExt = Call.hasRetAttr(Attribute::SExt);
114 RetZExt = Call.hasRetAttr(Attribute::ZExt);
116 CallConv = Call.getCallingConv();
117 Args = std::move(ArgsList);
118 NumFixedArgs = FuncTy->getNumParams();
125 CallLoweringInfo &setCallee(Type *ResultTy, FunctionType *FuncTy,
126 MCSymbol *Target, ArgListTy &&ArgsList,
127 const CallBase &Call,
128 unsigned FixedArgs = ~0U) {
130 Callee = Call.getCalledOperand();
133 IsInReg = Call.hasRetAttr(Attribute::InReg);
134 DoesNotReturn = Call.doesNotReturn();
135 IsVarArg = FuncTy->isVarArg();
136 IsReturnValueUsed = !Call.use_empty();
137 RetSExt = Call.hasRetAttr(Attribute::SExt);
138 RetZExt = Call.hasRetAttr(Attribute::ZExt);
140 CallConv = Call.getCallingConv();
141 Args = std::move(ArgsList);
142 NumFixedArgs = (FixedArgs == ~0U) ? FuncTy->getNumParams() : FixedArgs;
149 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
150 const Value *Target, ArgListTy &&ArgsList,
151 unsigned FixedArgs = ~0U) {
155 Args = std::move(ArgsList);
156 NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
160 CallLoweringInfo &setCallee(const DataLayout &DL, MCContext &Ctx,
161 CallingConv::ID CC, Type *ResultTy,
162 StringRef Target, ArgListTy &&ArgsList,
163 unsigned FixedArgs = ~0U);
165 CallLoweringInfo &setCallee(CallingConv::ID CC, Type *ResultTy,
166 MCSymbol *Target, ArgListTy &&ArgsList,
167 unsigned FixedArgs = ~0U) {
171 Args = std::move(ArgsList);
172 NumFixedArgs = (FixedArgs == ~0U) ? Args.size() : FixedArgs;
176 CallLoweringInfo &setTailCall(bool Value = true) {
181 CallLoweringInfo &setIsPatchPoint(bool Value = true) {
182 IsPatchPoint = Value;
186 ArgListTy &getArgs() { return Args; }
201 DenseMap<const Value *, Register> LocalValueMap;
202 FunctionLoweringInfo &FuncInfo;
204 MachineRegisterInfo &MRI;
205 MachineFrameInfo &MFI;
206 MachineConstantPool &MCP;
208 const TargetMachine &TM;
209 const DataLayout &DL;
210 const TargetInstrInfo &TII;
211 const TargetLowering &TLI;
212 const TargetRegisterInfo &TRI;
213 const TargetLibraryInfo *LibInfo;
214 bool SkipTargetIndependentISel;
216 /// The position of the last instruction for materializing constants
217 /// for use in the current block. It resets to EmitStartPt when it makes sense
218 /// (for example, it's usually profitable to avoid function calls between the
219 /// definition and the use)
220 MachineInstr *LastLocalValue;
222 /// The top most instruction in the current block that is allowed for
223 /// emitting local variables. LastLocalValue resets to EmitStartPt when it
224 /// makes sense (for example, on function calls)
225 MachineInstr *EmitStartPt;
230 /// Return the position of the last instruction emitted for
231 /// materializing constants for use in the current block.
232 MachineInstr *getLastLocalValue() { return LastLocalValue; }
234 /// Update the position of the last instruction emitted for
235 /// materializing constants for use in the current block.
236 void setLastLocalValue(MachineInstr *I) {
241 /// Set the current block to which generated machine instructions will
243 void startNewBlock();
245 /// Flush the local value map.
246 void finishBasicBlock();
248 /// Return current debug location information.
249 DebugLoc getCurDebugLoc() const { return DbgLoc; }
251 /// Do "fast" instruction selection for function arguments and append
252 /// the machine instructions to the current block. Returns true when
254 bool lowerArguments();
256 /// Do "fast" instruction selection for the given LLVM IR instruction
257 /// and append the generated machine instructions to the current block.
258 /// Returns true if selection was successful.
259 bool selectInstruction(const Instruction *I);
261 /// Do "fast" instruction selection for the given LLVM IR operator
262 /// (Instruction or ConstantExpr), and append generated machine instructions
263 /// to the current block. Return true if selection was successful.
264 bool selectOperator(const User *I, unsigned Opcode);
266 /// Create a virtual register and arrange for it to be assigned the
267 /// value for the given LLVM value.
268 Register getRegForValue(const Value *V);
270 /// Look up the value to see if its value is already cached in a
271 /// register. It may be defined by instructions across blocks or defined
273 Register lookUpRegForValue(const Value *V);
275 /// This is a wrapper around getRegForValue that also takes care of
276 /// truncating or sign-extending the given getelementptr index value.
277 std::pair<Register, bool> getRegForGEPIndex(const Value *Idx);
279 /// We're checking to see if we can fold \p LI into \p FoldInst. Note
280 /// that we could have a sequence where multiple LLVM IR instructions are
281 /// folded into the same machineinstr. For example we could have:
283 /// A: x = load i32 *P
284 /// B: y = icmp A, 42
287 /// In this scenario, \p LI is "A", and \p FoldInst is "C". We know about "B"
288 /// (and any other folded instructions) because it is between A and C.
290 /// If we succeed folding, return true.
291 bool tryToFoldLoad(const LoadInst *LI, const Instruction *FoldInst);
293 /// The specified machine instr operand is a vreg, and that vreg is
294 /// being provided by the specified load instruction. If possible, try to
295 /// fold the load as an operand to the instruction, returning true if
298 /// This method should be implemented by targets.
299 virtual bool tryToFoldLoadIntoMI(MachineInstr * /*MI*/, unsigned /*OpNo*/,
300 const LoadInst * /*LI*/) {
304 /// Reset InsertPt to prepare for inserting instructions into the
306 void recomputeInsertPt();
308 /// Remove all dead instructions between the I and E.
309 void removeDeadCode(MachineBasicBlock::iterator I,
310 MachineBasicBlock::iterator E);
312 using SavePoint = MachineBasicBlock::iterator;
314 /// Prepare InsertPt to begin inserting instructions into the local
315 /// value area and return the old insert position.
316 SavePoint enterLocalValueArea();
318 /// Reset InsertPt to the given old insert position.
319 void leaveLocalValueArea(SavePoint Old);
322 explicit FastISel(FunctionLoweringInfo &FuncInfo,
323 const TargetLibraryInfo *LibInfo,
324 bool SkipTargetIndependentISel = false);
326 /// This method is called by target-independent code when the normal
327 /// FastISel process fails to select an instruction. This gives targets a
328 /// chance to emit code for anything that doesn't fit into FastISel's
329 /// framework. It returns true if it was successful.
330 virtual bool fastSelectInstruction(const Instruction *I) = 0;
332 /// This method is called by target-independent code to do target-
333 /// specific argument lowering. It returns true if it was successful.
334 virtual bool fastLowerArguments();
336 /// This method is called by target-independent code to do target-
337 /// specific call lowering. It returns true if it was successful.
338 virtual bool fastLowerCall(CallLoweringInfo &CLI);
340 /// This method is called by target-independent code to do target-
341 /// specific intrinsic lowering. It returns true if it was successful.
342 virtual bool fastLowerIntrinsicCall(const IntrinsicInst *II);
344 /// This method is called by target-independent code to request that an
345 /// instruction with the given type and opcode be emitted.
346 virtual unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode);
348 /// This method is called by target-independent code to request that an
349 /// instruction with the given type, opcode, and register operand be emitted.
350 virtual unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
353 /// This method is called by target-independent code to request that an
354 /// instruction with the given type, opcode, and register operands be emitted.
355 virtual unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
356 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
358 /// This method is called by target-independent code to request that an
359 /// instruction with the given type, opcode, and register and immediate
360 /// operands be emitted.
361 virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
362 bool Op0IsKill, uint64_t Imm);
364 /// This method is a wrapper of fastEmit_ri.
366 /// It first tries to emit an instruction with an immediate operand using
367 /// fastEmit_ri. If that fails, it materializes the immediate into a register
368 /// and try fastEmit_rr instead.
369 Register fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
370 uint64_t Imm, MVT ImmType);
372 /// This method is called by target-independent code to request that an
373 /// instruction with the given type, opcode, and immediate operand be emitted.
374 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
376 /// This method is called by target-independent code to request that an
377 /// instruction with the given type, opcode, and floating-point immediate
378 /// operand be emitted.
379 virtual unsigned fastEmit_f(MVT VT, MVT RetVT, unsigned Opcode,
380 const ConstantFP *FPImm);
382 /// Emit a MachineInstr with no operands and a result register in the
383 /// given register class.
384 Register fastEmitInst_(unsigned MachineInstOpcode,
385 const TargetRegisterClass *RC);
387 /// Emit a MachineInstr with one register operand and a result register
388 /// in the given register class.
389 Register fastEmitInst_r(unsigned MachineInstOpcode,
390 const TargetRegisterClass *RC, unsigned Op0,
393 /// Emit a MachineInstr with two register operands and a result
394 /// register in the given register class.
395 Register fastEmitInst_rr(unsigned MachineInstOpcode,
396 const TargetRegisterClass *RC, unsigned Op0,
397 bool Op0IsKill, unsigned Op1, bool Op1IsKill);
399 /// Emit a MachineInstr with three register operands and a result
400 /// register in the given register class.
401 Register fastEmitInst_rrr(unsigned MachineInstOpcode,
402 const TargetRegisterClass *RC, unsigned Op0,
403 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
404 unsigned Op2, bool Op2IsKill);
406 /// Emit a MachineInstr with a register operand, an immediate, and a
407 /// result register in the given register class.
408 Register fastEmitInst_ri(unsigned MachineInstOpcode,
409 const TargetRegisterClass *RC, unsigned Op0,
410 bool Op0IsKill, uint64_t Imm);
412 /// Emit a MachineInstr with one register operand and two immediate
414 Register fastEmitInst_rii(unsigned MachineInstOpcode,
415 const TargetRegisterClass *RC, unsigned Op0,
416 bool Op0IsKill, uint64_t Imm1, uint64_t Imm2);
418 /// Emit a MachineInstr with a floating point immediate, and a result
419 /// register in the given register class.
420 Register fastEmitInst_f(unsigned MachineInstOpcode,
421 const TargetRegisterClass *RC,
422 const ConstantFP *FPImm);
424 /// Emit a MachineInstr with two register operands, an immediate, and a
425 /// result register in the given register class.
426 Register fastEmitInst_rri(unsigned MachineInstOpcode,
427 const TargetRegisterClass *RC, unsigned Op0,
428 bool Op0IsKill, unsigned Op1, bool Op1IsKill,
431 /// Emit a MachineInstr with a single immediate operand, and a result
432 /// register in the given register class.
433 Register fastEmitInst_i(unsigned MachineInstOpcode,
434 const TargetRegisterClass *RC, uint64_t Imm);
436 /// Emit a MachineInstr for an extract_subreg from a specified index of
437 /// a superregister to a specified type.
438 Register fastEmitInst_extractsubreg(MVT RetVT, unsigned Op0, bool Op0IsKill,
441 /// Emit MachineInstrs to compute the value of Op with all but the
442 /// least significant bit set to zero.
443 Register fastEmitZExtFromI1(MVT VT, unsigned Op0, bool Op0IsKill);
445 /// Emit an unconditional branch to the given block, unless it is the
446 /// immediate (fall-through) successor, and update the CFG.
447 void fastEmitBranch(MachineBasicBlock *MSucc, const DebugLoc &DbgLoc);
449 /// Emit an unconditional branch to \p FalseMBB, obtains the branch weight
450 /// and adds TrueMBB and FalseMBB to the successor list.
451 void finishCondBranch(const BasicBlock *BranchBB, MachineBasicBlock *TrueMBB,
452 MachineBasicBlock *FalseMBB);
454 /// Update the value map to include the new mapping for this
455 /// instruction, or insert an extra copy to get the result in a previous
456 /// determined register.
458 /// NOTE: This is only necessary because we might select a block that uses a
459 /// value before we select the block that defines the value. It might be
460 /// possible to fix this by selecting blocks in reverse postorder.
461 void updateValueMap(const Value *I, Register Reg, unsigned NumRegs = 1);
463 Register createResultReg(const TargetRegisterClass *RC);
465 /// Try to constrain Op so that it is usable by argument OpNum of the
466 /// provided MCInstrDesc. If this fails, create a new virtual register in the
467 /// correct class and COPY the value there.
468 Register constrainOperandRegClass(const MCInstrDesc &II, Register Op,
471 /// Emit a constant in a register using target-specific logic, such as
472 /// constant pool loads.
473 virtual unsigned fastMaterializeConstant(const Constant *C) { return 0; }
475 /// Emit an alloca address in a register using target-specific logic.
476 virtual unsigned fastMaterializeAlloca(const AllocaInst *C) { return 0; }
478 /// Emit the floating-point constant +0.0 in a register using target-
480 virtual unsigned fastMaterializeFloatZero(const ConstantFP *CF) {
484 /// Check if \c Add is an add that can be safely folded into \c GEP.
486 /// \c Add can be folded into \c GEP if:
487 /// - \c Add is an add,
488 /// - \c Add's size matches \c GEP's,
489 /// - \c Add is in the same basic block as \c GEP, and
490 /// - \c Add has a constant operand.
491 bool canFoldAddIntoGEP(const User *GEP, const Value *Add);
493 /// Test whether the register associated with this value has exactly one use,
494 /// in which case that single use is killing. Note that multiple IR values
495 /// may map onto the same register, in which case this is not the same as
496 /// checking that an IR value has one use.
497 bool hasTrivialKill(const Value *V);
499 /// Create a machine mem operand from the given instruction.
500 MachineMemOperand *createMachineMemOperandFor(const Instruction *I) const;
502 CmpInst::Predicate optimizeCmpPredicate(const CmpInst *CI) const;
504 bool lowerCallTo(const CallInst *CI, MCSymbol *Symbol, unsigned NumArgs);
505 bool lowerCallTo(const CallInst *CI, const char *SymName,
507 bool lowerCallTo(CallLoweringInfo &CLI);
509 bool lowerCall(const CallInst *I);
510 /// Select and emit code for a binary operator instruction, which has
511 /// an opcode which directly corresponds to the given ISD opcode.
512 bool selectBinaryOp(const User *I, unsigned ISDOpcode);
513 bool selectFNeg(const User *I, const Value *In);
514 bool selectGetElementPtr(const User *I);
515 bool selectStackmap(const CallInst *I);
516 bool selectPatchpoint(const CallInst *I);
517 bool selectCall(const User *I);
518 bool selectIntrinsicCall(const IntrinsicInst *II);
519 bool selectBitCast(const User *I);
520 bool selectFreeze(const User *I);
521 bool selectCast(const User *I, unsigned Opcode);
522 bool selectExtractValue(const User *U);
523 bool selectXRayCustomEvent(const CallInst *II);
524 bool selectXRayTypedEvent(const CallInst *II);
526 bool shouldOptForSize(const MachineFunction *MF) const {
527 // TODO: Implement PGSO.
528 return MF->getFunction().hasOptSize();
532 /// Handle PHI nodes in successor blocks.
534 /// Emit code to ensure constants are copied into registers when needed.
535 /// Remember the virtual registers that need to be added to the Machine PHI
536 /// nodes as input. We cannot just directly add them, because expansion might
537 /// result in multiple MBB's for one BB. As such, the start of the BB might
538 /// correspond to a different MBB than the end.
539 bool handlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
541 /// Helper for materializeRegForValue to materialize a constant in a
542 /// target-independent way.
543 Register materializeConstant(const Value *V, MVT VT);
545 /// Helper for getRegForVale. This function is called when the value
546 /// isn't already available in a register and must be materialized with new
548 Register materializeRegForValue(const Value *V, MVT VT);
550 /// Clears LocalValueMap and moves the area for the new local variables
551 /// to the beginning of the block. It helps to avoid spilling cached variables
552 /// across heavy instructions like calls.
553 void flushLocalValueMap();
555 /// Removes dead local value instructions after SavedLastLocalvalue.
556 void removeDeadLocalValueCode(MachineInstr *SavedLastLocalValue);
558 /// Insertion point before trying to select the current instruction.
559 MachineBasicBlock::iterator SavedInsertPt;
561 /// Add a stackmap or patchpoint intrinsic call's live variable
562 /// operands to a stackmap or patchpoint machine instruction.
563 bool addStackMapLiveVars(SmallVectorImpl<MachineOperand> &Ops,
564 const CallInst *CI, unsigned StartIdx);
565 bool lowerCallOperands(const CallInst *CI, unsigned ArgIdx, unsigned NumArgs,
566 const Value *Callee, bool ForceRetVoidTy,
567 CallLoweringInfo &CLI);
570 } // end namespace llvm
572 #endif // LLVM_CODEGEN_FASTISEL_H