1 ###########################################################
2 ## Commands for running tblgen to compile a td file
3 ##########################################################
4 define transform-td-to-out
5 $(if $(LOCAL_IS_HOST_MODULE), \
6 $(call transform-host-td-to-out,$(1)), \
7 $(call transform-device-td-to-out,$(1)))
10 ###########################################################
11 ## TableGen: Compile .td files to .inc.
12 ###########################################################
14 # Set LOCAL_MODULE_CLASS to STATIC_LIBRARIES default (require
15 # for macro local-intermediates-dir)
16 ifeq ($(LOCAL_MODULE_CLASS),)
17 LOCAL_MODULE_CLASS := STATIC_LIBRARIES
20 ifneq ($(strip $(TBLGEN_TABLES)),)
22 intermediates := $(call local-intermediates-dir)
23 tblgen_gen_tables := $(addprefix $(intermediates)/,$(TBLGEN_TABLES))
24 LOCAL_GENERATED_SOURCES += $(tblgen_gen_tables)
26 tblgen_source_dir := $(LOCAL_PATH)
27 ifneq ($(TBLGEN_TD_DIR),)
28 tblgen_source_dir := $(TBLGEN_TD_DIR)
31 ifneq ($(filter %GenRegisterInfo.inc,$(tblgen_gen_tables)),)
32 $(intermediates)/%GenRegisterInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
33 $(call transform-td-to-out,register-info)
36 ifneq ($(filter %GenInstrInfo.inc,$(tblgen_gen_tables)),)
37 $(intermediates)/%GenInstrInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
38 $(call transform-td-to-out,instr-info)
41 ifneq ($(filter %GenAsmWriter.inc,$(tblgen_gen_tables)),)
42 $(intermediates)/%GenAsmWriter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
43 $(call transform-td-to-out,asm-writer)
46 ifneq ($(filter %GenAsmWriter1.inc,$(tblgen_gen_tables)),)
47 $(intermediates)/%GenAsmWriter1.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
48 $(call transform-td-to-out,asm-writer -asmwriternum=1)
51 ifneq ($(filter %GenAsmMatcher.inc,$(tblgen_gen_tables)),)
52 $(intermediates)/%GenAsmMatcher.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
53 $(call transform-td-to-out,asm-matcher)
56 ifneq ($(filter %GenCodeEmitter.inc,$(tblgen_gen_tables)),)
57 $(intermediates)/%GenCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
58 $(call transform-td-to-out,emitter)
61 ifneq ($(filter %GenMCCodeEmitter.inc,$(tblgen_gen_tables)),)
62 $(intermediates)/%GenMCCodeEmitter.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
63 $(call transform-td-to-out,emitter -mc-emitter)
66 ifneq ($(filter %GenDAGISel.inc,$(tblgen_gen_tables)),)
67 $(intermediates)/%GenDAGISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
68 $(call transform-td-to-out,dag-isel)
71 ifneq ($(filter %GenDisassemblerTables.inc,$(tblgen_gen_tables)),)
72 $(intermediates)/%GenDisassemblerTables.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
73 $(call transform-td-to-out,disassembler)
76 ifneq ($(filter %GenEDInfo.inc,$(tblgen_gen_tables)),)
77 $(intermediates)/%GenEDInfo.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
78 $(call transform-td-to-out,enhanced-disassembly-info)
81 ifneq ($(filter %GenFastISel.inc,$(tblgen_gen_tables)),)
82 $(intermediates)/%GenFastISel.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
83 $(call transform-td-to-out,fast-isel)
86 ifneq ($(filter %GenSubtarget.inc,$(tblgen_gen_tables)),)
87 $(intermediates)/%GenSubtarget.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
88 $(call transform-td-to-out,subtarget)
91 ifneq ($(filter %GenCallingConv.inc,$(tblgen_gen_tables)),)
92 $(intermediates)/%GenCallingConv.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
93 $(call transform-td-to-out,callingconv)
96 ifneq ($(filter %GenIntrinsics.inc,$(tblgen_gen_tables)),)
97 $(intermediates)/%GenIntrinsics.inc: $(tblgen_source_dir)/%.td $(TBLGEN)
98 $(call transform-td-to-out,tgt_intrinsics)
101 ifneq ($(findstring ARMGenDecoderTables.inc,$(tblgen_gen_tables)),)
102 $(intermediates)/ARMGenDecoderTables.inc: $(tblgen_source_dir)/ARM.td $(TBLGEN)
103 $(call transform-td-to-out,arm-decoder)