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minigbm: Add AMDGPU minigbm driver
[android-x86/external-minigbm.git] / mediatek.c
1 /*
2  * Copyright 2015 The Chromium OS Authors. All rights reserved.
3  * Use of this source code is governed by a BSD-style license that can be
4  * found in the LICENSE file.
5  */
6
7 #ifdef DRV_MEDIATEK
8
9 #include <stdio.h>
10 #include <string.h>
11 #include <sys/mman.h>
12 #include <xf86drm.h>
13 #include <mediatek_drm.h>
14
15 #include "drv_priv.h"
16 #include "helpers.h"
17
18 static int mediatek_bo_create(struct bo *bo, uint32_t width, uint32_t height,
19                               uint32_t format, uint32_t flags)
20 {
21         int ret;
22         size_t plane;
23         struct drm_mtk_gem_create gem_create;
24
25         drv_bo_from_format(bo, width, height, format);
26
27         memset(&gem_create, 0, sizeof(gem_create));
28         gem_create.size = bo->total_size;
29
30         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MTK_GEM_CREATE, &gem_create);
31         if (ret) {
32                 fprintf(stderr, "drv: DRM_IOCTL_MTK_GEM_CREATE failed "
33                                 "(size=%llu)\n", gem_create.size);
34                 return ret;
35         }
36
37         for (plane = 0; plane < bo->num_planes; plane++)
38                 bo->handles[plane].u32 = gem_create.handle;
39
40         return 0;
41 }
42
43 static void *mediatek_bo_map(struct bo *bo)
44 {
45         int ret;
46         struct drm_mtk_gem_map_off gem_map;
47
48         memset(&gem_map, 0, sizeof(gem_map));
49         gem_map.handle = bo->handles[0].u32;
50
51         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_MTK_GEM_MAP_OFFSET, &gem_map);
52         if (ret) {
53                 fprintf(stderr,"drv: DRM_IOCTL_MTK_GEM_MAP_OFFSET failed\n");
54                 return MAP_FAILED;
55         }
56
57         return mmap(0, bo->total_size, PROT_READ | PROT_WRITE, MAP_SHARED,
58                     bo->drv->fd, gem_map.offset);
59 }
60
61 static drv_format_t mediatek_resolve_format(drv_format_t format)
62 {
63         switch (format) {
64         case DRV_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
65                 /*HACK: See b/28671744 */
66                 return DRV_FORMAT_XBGR8888;
67         case DRV_FORMAT_FLEX_YCbCr_420_888:
68                 return DRV_FORMAT_YVU420;
69         default:
70                 return format;
71         }
72 }
73
74 const struct backend backend_mediatek =
75 {
76         .name = "mediatek",
77         .bo_create = mediatek_bo_create,
78         .bo_destroy = drv_gem_bo_destroy,
79         .bo_map = mediatek_bo_map,
80         .resolve_format = mediatek_resolve_format,
81         .format_list = {
82                 {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
83                                       DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
84                                       DRV_BO_USE_HW_RENDER | DRV_BO_USE_HW_2D |
85                                       DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
86                 {DRV_FORMAT_XRGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
87                                       DRV_BO_USE_LINEAR | DRV_BO_USE_SW_READ_OFTEN |
88                                       DRV_BO_USE_SW_WRITE_OFTEN},
89                 {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
90                                       DRV_BO_USE_RENDERING | DRV_BO_USE_HW_TEXTURE |
91                                       DRV_BO_USE_HW_RENDER | DRV_BO_USE_HW_2D |
92                                       DRV_BO_USE_SW_READ_RARELY | DRV_BO_USE_SW_WRITE_RARELY},
93                 {DRV_FORMAT_ARGB8888, DRV_BO_USE_SCANOUT | DRV_BO_USE_CURSOR |
94                                       DRV_BO_USE_LINEAR | DRV_BO_USE_SW_READ_OFTEN |
95                                       DRV_BO_USE_SW_WRITE_OFTEN},
96                 {DRV_FORMAT_YVU420,   DRV_BO_USE_LINEAR | DRV_BO_USE_SW_READ_OFTEN |
97                                       DRV_BO_USE_SW_WRITE_OFTEN},
98         }
99 };
100
101 #endif