1 /* Instruction printing code for the MAXQ
3 Copyright 2004, 2005, 2007, 2009, 2010 Free Software Foundation, Inc.
5 Written by Vineet Sharma(vineets@noida.hcltech.com) Inderpreet
6 S.(inderpreetb@noida.hcltech.com)
8 This file is part of the GNU opcodes library.
10 This library is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
26 #include "opcode/maxq.h"
30 unsigned char group_no;
31 unsigned char sub_opcode;
40 typedef struct _group_info group_info;
48 #define MASK_LOW_BYTE 0x0f
49 #define MASK_HIGH_BYTE 0xf0
51 /* Flags for retrieving the bits from the op-code. */
52 #define _DECODE_LOWNIB_LOWBYTE 0x000f
53 #define _DECODE_HIGHNIB_LOWBYTE 0x00f0
54 #define _DECODE_LOWNIB_HIGHBYTE 0x0f00
55 #define _DECODE_HIGHNIB_HIGHBYTE 0xf000
56 #define _DECODE_HIGHBYTE 0xff00
57 #define _DECODE_LOWBYTE 0x00ff
58 #define _DECODE_4TO6_HIGHBYTE 0x7000
59 #define _DECODE_4TO6_LOWBYTE 0x0070
60 #define _DECODE_0TO6_HIGHBYTE 0x7f00
61 #define _DECODE_0TO2_HIGHBYTE 0x0700
62 #define _DECODE_GET_F_HIGHBYTE 0x8000
63 #define _DECODE_BIT7_HIGHBYTE 0x8000
64 #define _DECODE_BIT7_LOWBYTE 0x0080
65 #define _DECODE_GET_CARRY 0x10000
66 #define _DECODE_BIT0_LOWBYTE 0x1
67 #define _DECODE_BIT6AND7_HIGHBYTE 0xc000
69 /* Module and Register Indexed of System Registers. */
70 #define _CURR_ACC_MODINDEX 0xa
71 #define _CURR_ACC_REGINDEX 0x0
72 #define _PSF_REG_MODINDEX 0x8
73 #define _PSF_REG_REGINDEX 0x4
74 #define _PFX_REG_MODINDEX 0xb
75 #define _PFX0_REG_REGINDEX 0x0
76 #define _PFX2_REG_REGINDEX 0x2
77 #define _DP_REG_MODINDEX 0xf
78 #define _DP0_REG_REGINDEX 0x3
79 #define _DP1_REG_REGINDEX 0x7
80 #define _IP_REG_MODINDEX 0xc
81 #define _IP_REG_REGINDEX 0x0
82 #define _IIR_REG_MODINDEX 0x8
83 #define _IIR_REG_REGINDEX 0xb
84 #define _SP_REG_MODINDEX 0xd
85 #define _SP_REG_REGINDEX 0x1
86 #define _IC_REG_MODINDEX 0x8
87 #define _IC_REG_REGINDEX 0x5
88 #define _LC_REG_MODINDEX 0xe
89 #define _LC0_REG_REGINDEX 0x0
90 #define _LC1_REG_REGINDEX 0x1
91 #define _LC2_REG_REGINDEX 0x2
92 #define _LC3_REG_REGINDEX 0x3
94 /* Flags for finding the bits in PSF Register. */
95 #define SIM_ALU_DECODE_CARRY_BIT_POS 0x2
96 #define SIM_ALU_DECODE_SIGN_BIT_POS 0x40
97 #define SIM_ALU_DECODE_ZERO_BIT_POS 0x80
98 #define SIM_ALU_DECODE_EQUAL_BIT_POS 0x1
99 #define SIM_ALU_DECODE_IGE_BIT_POS 0x1
101 /* Number Of Op-code Groups. */
102 unsigned char const SIM_ALU_DECODE_OPCODE_GROUPS = 11;
104 /* Op-code Groups. */
105 unsigned char const SIM_ALU_DECODE_LOGICAL_XCHG_OP_GROUP = 1;
107 /* Group1: AND/OR/XOR/ADD/SUB Operations: fxxx 1010 ssss ssss. */
108 unsigned char const SIM_ALU_DECODE_AND_OR_ADD_SUB_OP_GROUP = 2;
110 /* Group2: Logical Operations: 1000 1010 xxxx 1010. */
111 unsigned char const SIM_ALU_DECODE_BIT_OP_GROUP = 3;
113 /* XCHG/Bit Operations: 1xxx 1010 xxxx 1010. */
114 unsigned char const SIM_ALU_DECODE_SET_DEST_BIT_GROUP = 4;
116 /* Move value in bit of destination register: 1ddd dddd xbbb 0111. */
117 unsigned char const SIM_ALU_DECODE_JUMP_OP_GROUP = 5;
119 #define JUMP_CHECK(insn) \
120 ( ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000) \
121 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x2000) \
122 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x6000) \
123 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x1000) \
124 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000) \
125 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000) \
126 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x7000) \
127 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000) )
129 /* JUMP operations: fxxx 1100 ssss ssss */
130 unsigned char const SIM_ALU_DECODE_RET_OP_GROUP = 6;
132 /* RET Operations: 1xxx 1100 0000 1101 */
133 unsigned char const SIM_ALU_DECODE_MOVE_SRC_DST_GROUP = 7;
135 /* Move src into dest register: fddd dddd ssss ssss */
136 unsigned char const SIM_ALU_DECODE_SET_SRC_BIT_GROUP = 8;
138 /* Move value in bit of source register: fbbb 0111 ssss ssss */
139 unsigned char const SIM_ALU_DECODE_DJNZ_CALL_PUSH_OP_GROUP = 9;
141 /* PUSH, DJNZ and CALL operations: fxxx 1101 ssss ssss */
142 unsigned char const SIM_ALU_DECODE_POP_OP_GROUP = 10;
144 /* POP operation: 1ddd dddd 0000 1101 */
145 unsigned char const SIM_ALU_DECODE_CMP_SRC_OP_GROUP = 11;
148 char unres_reg_name[20];
151 get_reg_name (unsigned char reg_code, type1 arg_pos)
153 unsigned char module;
154 unsigned char r_index;
156 reg_entry const *reg_x;
157 mem_access_syntax const *syntax;
162 module = (reg_code & MASK_LOW_BYTE);
163 r_index = (reg_code & MASK_HIGH_BYTE);
164 r_index = r_index >> 4;
166 /* Search the system register table. */
167 for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL; ++reg_x)
168 if ((reg_x->Mod_name == module) && (reg_x->Mod_index == r_index))
169 return reg_x->reg_name;
171 /* Serch pheripheral table. */
172 for (ix = 0; ix < num_of_reg; ix++)
174 reg_x = &new_reg_table[ix];
176 if ((reg_x->Mod_name == module) && (reg_x->Mod_index == r_index))
177 return reg_x->reg_name;
180 for (mem_acc = &mem_table[0]; mem_acc->name != NULL || !mem_acc; ++mem_acc)
182 if (reg_code == mem_acc->opcode)
184 for (syntax = mem_access_syntax_table;
185 syntax != NULL && syntax->name;
187 if (!strcmp (mem_acc->name, syntax->name))
189 if ((arg_pos == syntax->type) || (syntax->type == BOTH))
190 return mem_acc->name;
197 memset (unres_reg_name, 0, 20);
198 sprintf (unres_reg_name, "%01x%01xh", r_index, module);
200 return unres_reg_name;
204 check_move (unsigned char insn0, unsigned char insn8)
206 bfd_boolean first = FALSE;
207 bfd_boolean second = FALSE;
208 reg_entry const *reg_x;
209 const unsigned char module1 = insn0 & MASK_LOW_BYTE;
210 const unsigned char index1 = ((insn0 & 0x70) >> 4);
211 const unsigned char module2 = insn8 & MASK_LOW_BYTE;
212 const unsigned char index2 = ((insn8 & MASK_HIGH_BYTE) >> 4);
215 if (((insn0 & MASK_LOW_BYTE) == MASK_LOW_BYTE)
216 && ((index1 == 0) || (index1 == 1) || (index1 == 2) || (index1 == 5)
217 || (index1 == 4) || (index1 == 6)))
220 else if (((insn0 & MASK_LOW_BYTE) == 0x0D) && (index1 == 0))
223 else if ((module1 == 0x0E)
224 && ((index1 == 0) || (index1 == 1) || (index1 == 2)))
229 for (reg_x = &system_reg_table[0]; reg_x->reg_name != NULL && reg_x;
232 if ((reg_x->Mod_name == module1) && (reg_x->Mod_index == index1)
233 && ((reg_x->rtype == Reg_16W) || (reg_x->rtype == Reg_8W)))
235 /* IP not allowed. */
236 if ((reg_x->Mod_name == 0x0C) && (reg_x->Mod_index == 0x00))
239 /* A[AP] not allowed. */
240 if ((reg_x->Mod_name == 0x0A) && (reg_x->Mod_index == 0x01))
249 /* No need to check further. */
255 if (((insn8 & MASK_LOW_BYTE) == MASK_LOW_BYTE)
256 && ((index2 == 0) || (index2 == 1) || (index2 == 2) || (index2 == 4)
257 || (index2 == 5) || (index2 == 6)))
260 else if (((insn8 & MASK_LOW_BYTE) == 0x0D) && (index2 == 0))
263 else if ((module2 == 0x0E)
264 && ((index2 == 0) || (index2 == 1) || (index2 == 2)))
269 for (reg_x = &system_reg_table[0];
270 reg_x->reg_name != NULL && reg_x;
273 if ((reg_x->Mod_name == (insn8 & MASK_LOW_BYTE))
274 && (reg_x->Mod_index == (((insn8 & 0xf0) >> 4))))
284 if ((module1 == 0x0A && index1 == 0x0)
285 && (module2 == 0x0A && index2 == 0x01))
298 maxq_print_arg (MAX_ARG_TYPE arg,
299 struct disassemble_info * info,
305 info->fprintf_func (info->stream, "C");
308 info->fprintf_func (info->stream, "NC");
312 info->fprintf_func (info->stream, "Z");
316 info->fprintf_func (info->stream, "NZ");
320 info->fprintf_func (info->stream, "S");
324 info->fprintf_func (info->stream, "E");
328 info->fprintf_func (info->stream, "NE");
332 info->fprintf_func (info->stream, "Acc");
333 if ((grp.flag & BIT_NO) == BIT_NO)
334 info->fprintf_func (info->stream, ".%d", grp.bit_no);
338 info->fprintf_func (info->stream, "#0");
341 info->fprintf_func (info->stream, "#1");
350 get_group (const unsigned int insn)
352 if (check_move ((insn >> 8), (insn & _DECODE_LOWBYTE)))
355 if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0A00)
357 /* && condition with sec part added on 26 May for resolving 2 & 3 grp
359 if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x000A)
360 && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
362 if ((insn & _DECODE_HIGHNIB_HIGHBYTE) == 0x8000)
370 else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0C00)
372 if (((insn & _DECODE_LOWBYTE) == 0x000D) && JUMP_CHECK (insn)
373 && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
375 else if ((insn & _DECODE_LOWBYTE) == 0x008D)
380 else if (((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0D00)
381 && (((insn & _DECODE_4TO6_HIGHBYTE) == 0x3000)
382 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x4000)
383 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x5000)
384 || ((insn & _DECODE_4TO6_HIGHBYTE) == 0x0000)))
387 else if ((insn & _DECODE_LOWBYTE) == 0x000D)
390 else if ((insn & _DECODE_LOWBYTE) == 0x008D)
393 else if ((insn & _DECODE_0TO6_HIGHBYTE) == 0x7800)
396 else if ((insn & _DECODE_LOWNIB_HIGHBYTE) == 0x0700)
399 else if (((insn & _DECODE_LOWNIB_LOWBYTE) == 0x0007)
400 && ((insn & _DECODE_GET_F_HIGHBYTE) == 0x8000))
407 get_insn_opcode (const unsigned int insn, group_info *i)
409 static unsigned char pfx_flag = 0;
410 static unsigned char count_for_pfx = 0;
413 i->bit_no ^= i->bit_no;
416 i->group_no ^= i->group_no;
418 i->sub_opcode ^= i->sub_opcode;
420 if (count_for_pfx > 0)
423 if (((insn >> 8) == 0x0b) || ((insn >> 8) == 0x2b))
429 i->group_no = get_group (insn);
431 if (pfx_flag && (i->group_no == 0x0D) && (count_for_pfx == 2)
432 && ((insn & _DECODE_0TO6_HIGHBYTE) == 0x7800))
436 pfx_flag ^= pfx_flag;
442 i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
444 i->src = ((insn & _DECODE_LOWBYTE));
446 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
451 i->sub_opcode = ((insn & _DECODE_HIGHNIB_LOWBYTE) >> 4);
456 i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
458 i->bit_no = ((insn & _DECODE_HIGHNIB_LOWBYTE) >> 4);
463 i->sub_opcode = ((insn & _DECODE_BIT7_LOWBYTE) >> 7);
465 i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
467 i->bit_no = ((insn & _DECODE_4TO6_LOWBYTE) >> 4);
472 i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
474 i->src = ((insn & _DECODE_LOWBYTE));
476 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
481 i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
486 i->sub_opcode = ((insn & _DECODE_HIGHNIB_HIGHBYTE) >> 12);
491 i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
493 i->src = ((insn & _DECODE_LOWBYTE));
495 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
500 i->sub_opcode = ((insn & _DECODE_0TO2_HIGHBYTE) >> 8);
502 i->bit_no = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
504 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
506 i->src = ((insn & _DECODE_LOWBYTE));
511 i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
513 i->src = ((insn & _DECODE_LOWBYTE));
515 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
520 i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
525 i->dst = ((insn & _DECODE_0TO6_HIGHBYTE) >> 8);
530 i->sub_opcode = ((insn & _DECODE_4TO6_HIGHBYTE) >> 12);
532 i->src = ((insn & _DECODE_LOWBYTE));
534 i->fbit = ((insn & _DECODE_GET_F_HIGHBYTE) >> 15);
543 /* Print one instruction from MEMADDR on INFO->STREAM. Return the size of the
544 instruction (always 2 on MAXQ20). */
547 print_insn (bfd_vma memaddr, struct disassemble_info *info,
548 enum bfd_endian endianess)
550 /* The raw instruction. */
551 unsigned char insn[2], derived_code;
553 unsigned int actual_operands;
555 /* The group_info collected/decoded. */
557 MAXQ20_OPCODE_INFO const *opcode;
562 status = info->read_memory_func (memaddr, (bfd_byte *) & insn[0], 2, info);
566 info->memory_error_func (status, memaddr, info);
570 /* FIXME: Endianness always little. */
571 if (endianess == BFD_ENDIAN_BIG)
572 get_insn_opcode (((insn[0] << 8) | (insn[1])), &grp);
574 get_insn_opcode (((insn[1] << 8) | (insn[0])), &grp);
576 derived_code = ((grp.group_no << 4) | grp.sub_opcode);
578 if (insn[0] == 0 && insn[1] == 0)
580 info->fprintf_func (info->stream, "00 00");
584 /* The opcode is always in insn[0]. */
585 for (opcode = &op_table[0]; opcode->name != NULL; ++opcode)
587 if (opcode->instr_id == derived_code)
589 if (opcode->instr_id == 0x3D)
591 if ((grp.bit_no == 0) && (opcode->arg[1] != A_BIT_0))
593 if ((grp.bit_no == 1) && (opcode->arg[1] != A_BIT_1))
595 if ((grp.bit_no == 3) && (opcode->arg[0] != 0))
599 info->fprintf_func (info->stream, "%s ", opcode->name);
603 if ((grp.flag & SRC) == SRC)
606 if ((grp.flag & DST) == DST)
609 /* If Implict FLAG in the Instruction. */
610 if ((opcode->op_number > actual_operands)
611 && !((grp.flag & SRC) == SRC) && !((grp.flag & DST) == DST))
613 for (i = 0; i < opcode->op_number; i++)
615 if (i == 1 && (opcode->arg[1] != NO_ARG))
616 info->fprintf_func (info->stream, ",");
617 maxq_print_arg (opcode->arg[i], info, grp);
621 /* DST is ABSENT in the grp. */
622 if ((opcode->op_number > actual_operands)
623 && ((grp.flag & SRC) == SRC))
625 maxq_print_arg (opcode->arg[0], info, grp);
626 info->fprintf_func (info->stream, " ");
628 if (opcode->instr_id == 0xA4)
629 info->fprintf_func (info->stream, "LC[0]");
631 if (opcode->instr_id == 0xA5)
632 info->fprintf_func (info->stream, "LC[1]");
634 if ((grp.flag & SRC) == SRC)
635 info->fprintf_func (info->stream, ",");
638 if ((grp.flag & DST) == DST)
640 if ((grp.flag & BIT_NO) == BIT_NO)
642 info->fprintf_func (info->stream, " %s.%d",
643 get_reg_name (grp.dst,
648 info->fprintf_func (info->stream, " %s",
649 get_reg_name (grp.dst, (type1) 0));
652 /* SRC is ABSENT in the grp. */
653 if ((opcode->op_number > actual_operands)
654 && ((grp.flag & DST) == DST))
656 info->fprintf_func (info->stream, ",");
657 maxq_print_arg (opcode->arg[1], info, grp);
658 info->fprintf_func (info->stream, " ");
661 if ((grp.flag & SRC) == SRC)
663 if ((grp.flag & DST) == DST)
664 info->fprintf_func (info->stream, ",");
666 if ((grp.flag & BIT_NO) == BIT_NO)
668 format = opcode->format;
670 if ((grp.flag & FORMAT) == FORMAT)
673 info->fprintf_func (info->stream, " %s.%d",
674 get_reg_name (grp.src,
678 info->fprintf_func (info->stream, " #%02xh.%d",
679 grp.src, grp.bit_no);
683 format = opcode->format;
685 if ((grp.flag & FORMAT) == FORMAT)
688 info->fprintf_func (info->stream, " %s",
689 get_reg_name (grp.src,
692 info->fprintf_func (info->stream, " #%02xh",
701 info->fprintf_func (info->stream, "Unable to Decode : %02x %02x",
707 print_insn_maxq_little (bfd_vma memaddr, struct disassemble_info *info)
709 return print_insn (memaddr, info, BFD_ENDIAN_LITTLE);