1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2005
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
7 This file is part of GDB, GAS, and the GNU binutils.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "libiberty.h"
27 #include "opcode/mips.h"
30 /* FIXME: These are needed to figure out if the code is mips16 or
31 not. The low bit of the address is often a good indicator. No
32 symbol table is available when this code runs out in an embedded
33 system as when it is used for disassembler support in a monitor. */
35 #if !defined(EMBEDDED_ENV)
36 #define SYMTAB_AVAILABLE 1
41 /* Mips instructions are at maximum this many bytes long. */
45 /* FIXME: These should be shared with gdb somehow. */
47 struct mips_cp0sel_name
51 const char * const name;
54 /* The mips16 registers. */
55 static const unsigned int mips16_to_32_reg_map[] =
57 16, 17, 2, 3, 4, 5, 6, 7
60 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
63 static const char * const mips_gpr_names_numeric[32] =
65 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
66 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
67 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
68 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
71 static const char * const mips_gpr_names_oldabi[32] =
73 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
74 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
75 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
76 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
79 static const char * const mips_gpr_names_newabi[32] =
81 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
82 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
83 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
84 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
87 static const char * const mips_fpr_names_numeric[32] =
89 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
90 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
91 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
92 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
95 static const char * const mips_fpr_names_32[32] =
97 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
98 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
99 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
100 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
103 static const char * const mips_fpr_names_n32[32] =
105 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
106 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
107 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
108 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
111 static const char * const mips_fpr_names_64[32] =
113 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
114 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
115 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
116 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
119 static const char * const mips_cp0_names_numeric[32] =
121 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
122 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
123 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
124 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
127 static const char * const mips_cp0_names_mips3264[32] =
129 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
130 "c0_context", "c0_pagemask", "c0_wired", "$7",
131 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
132 "c0_status", "c0_cause", "c0_epc", "c0_prid",
133 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
134 "c0_xcontext", "$21", "$22", "c0_debug",
135 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
136 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
139 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
141 { 16, 1, "c0_config1" },
142 { 16, 2, "c0_config2" },
143 { 16, 3, "c0_config3" },
144 { 18, 1, "c0_watchlo,1" },
145 { 18, 2, "c0_watchlo,2" },
146 { 18, 3, "c0_watchlo,3" },
147 { 18, 4, "c0_watchlo,4" },
148 { 18, 5, "c0_watchlo,5" },
149 { 18, 6, "c0_watchlo,6" },
150 { 18, 7, "c0_watchlo,7" },
151 { 19, 1, "c0_watchhi,1" },
152 { 19, 2, "c0_watchhi,2" },
153 { 19, 3, "c0_watchhi,3" },
154 { 19, 4, "c0_watchhi,4" },
155 { 19, 5, "c0_watchhi,5" },
156 { 19, 6, "c0_watchhi,6" },
157 { 19, 7, "c0_watchhi,7" },
158 { 25, 1, "c0_perfcnt,1" },
159 { 25, 2, "c0_perfcnt,2" },
160 { 25, 3, "c0_perfcnt,3" },
161 { 25, 4, "c0_perfcnt,4" },
162 { 25, 5, "c0_perfcnt,5" },
163 { 25, 6, "c0_perfcnt,6" },
164 { 25, 7, "c0_perfcnt,7" },
165 { 27, 1, "c0_cacheerr,1" },
166 { 27, 2, "c0_cacheerr,2" },
167 { 27, 3, "c0_cacheerr,3" },
168 { 28, 1, "c0_datalo" },
169 { 29, 1, "c0_datahi" }
172 static const char * const mips_cp0_names_mips3264r2[32] =
174 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
175 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
176 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
177 "c0_status", "c0_cause", "c0_epc", "c0_prid",
178 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
179 "c0_xcontext", "$21", "$22", "c0_debug",
180 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
181 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
184 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
186 { 4, 1, "c0_contextconfig" },
187 { 5, 1, "c0_pagegrain" },
188 { 12, 1, "c0_intctl" },
189 { 12, 2, "c0_srsctl" },
190 { 12, 3, "c0_srsmap" },
191 { 15, 1, "c0_ebase" },
192 { 16, 1, "c0_config1" },
193 { 16, 2, "c0_config2" },
194 { 16, 3, "c0_config3" },
195 { 18, 1, "c0_watchlo,1" },
196 { 18, 2, "c0_watchlo,2" },
197 { 18, 3, "c0_watchlo,3" },
198 { 18, 4, "c0_watchlo,4" },
199 { 18, 5, "c0_watchlo,5" },
200 { 18, 6, "c0_watchlo,6" },
201 { 18, 7, "c0_watchlo,7" },
202 { 19, 1, "c0_watchhi,1" },
203 { 19, 2, "c0_watchhi,2" },
204 { 19, 3, "c0_watchhi,3" },
205 { 19, 4, "c0_watchhi,4" },
206 { 19, 5, "c0_watchhi,5" },
207 { 19, 6, "c0_watchhi,6" },
208 { 19, 7, "c0_watchhi,7" },
209 { 23, 1, "c0_tracecontrol" },
210 { 23, 2, "c0_tracecontrol2" },
211 { 23, 3, "c0_usertracedata" },
212 { 23, 4, "c0_tracebpc" },
213 { 25, 1, "c0_perfcnt,1" },
214 { 25, 2, "c0_perfcnt,2" },
215 { 25, 3, "c0_perfcnt,3" },
216 { 25, 4, "c0_perfcnt,4" },
217 { 25, 5, "c0_perfcnt,5" },
218 { 25, 6, "c0_perfcnt,6" },
219 { 25, 7, "c0_perfcnt,7" },
220 { 27, 1, "c0_cacheerr,1" },
221 { 27, 2, "c0_cacheerr,2" },
222 { 27, 3, "c0_cacheerr,3" },
223 { 28, 1, "c0_datalo" },
224 { 28, 2, "c0_taglo1" },
225 { 28, 3, "c0_datalo1" },
226 { 28, 4, "c0_taglo2" },
227 { 28, 5, "c0_datalo2" },
228 { 28, 6, "c0_taglo3" },
229 { 28, 7, "c0_datalo3" },
230 { 29, 1, "c0_datahi" },
231 { 29, 2, "c0_taghi1" },
232 { 29, 3, "c0_datahi1" },
233 { 29, 4, "c0_taghi2" },
234 { 29, 5, "c0_datahi2" },
235 { 29, 6, "c0_taghi3" },
236 { 29, 7, "c0_datahi3" },
239 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
240 static const char * const mips_cp0_names_sb1[32] =
242 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
243 "c0_context", "c0_pagemask", "c0_wired", "$7",
244 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
245 "c0_status", "c0_cause", "c0_epc", "c0_prid",
246 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
247 "c0_xcontext", "$21", "$22", "c0_debug",
248 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
249 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
252 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
254 { 16, 1, "c0_config1" },
255 { 18, 1, "c0_watchlo,1" },
256 { 19, 1, "c0_watchhi,1" },
257 { 22, 0, "c0_perftrace" },
258 { 23, 3, "c0_edebug" },
259 { 25, 1, "c0_perfcnt,1" },
260 { 25, 2, "c0_perfcnt,2" },
261 { 25, 3, "c0_perfcnt,3" },
262 { 25, 4, "c0_perfcnt,4" },
263 { 25, 5, "c0_perfcnt,5" },
264 { 25, 6, "c0_perfcnt,6" },
265 { 25, 7, "c0_perfcnt,7" },
266 { 26, 1, "c0_buserr_pa" },
267 { 27, 1, "c0_cacheerr_d" },
268 { 27, 3, "c0_cacheerr_d_pa" },
269 { 28, 1, "c0_datalo_i" },
270 { 28, 2, "c0_taglo_d" },
271 { 28, 3, "c0_datalo_d" },
272 { 29, 1, "c0_datahi_i" },
273 { 29, 2, "c0_taghi_d" },
274 { 29, 3, "c0_datahi_d" },
277 static const char * const mips_hwr_names_numeric[32] =
279 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
280 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
281 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
282 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
285 static const char * const mips_hwr_names_mips3264r2[32] =
287 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
288 "$4", "$5", "$6", "$7",
289 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
290 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
291 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
294 struct mips_abi_choice
297 const char * const *gpr_names;
298 const char * const *fpr_names;
301 struct mips_abi_choice mips_abi_choices[] =
303 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
304 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
305 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
306 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
309 struct mips_arch_choice
313 unsigned long bfd_mach;
316 const char * const *cp0_names;
317 const struct mips_cp0sel_name *cp0sel_names;
318 unsigned int cp0sel_names_len;
319 const char * const *hwr_names;
322 const struct mips_arch_choice mips_arch_choices[] =
324 { "numeric", 0, 0, 0, 0,
325 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
327 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
328 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
329 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
330 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
331 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
332 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
333 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
334 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
335 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
336 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
337 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
338 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
339 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
340 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
341 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
342 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
343 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
344 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
345 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
346 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
347 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
348 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
349 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
350 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
351 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
352 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
353 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
354 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
355 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
356 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
357 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
358 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
359 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
360 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
361 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
362 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
363 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
364 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
365 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
366 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
367 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
368 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
370 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
371 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
372 _MIPS32 Architecture For Programmers Volume I: Introduction to the
373 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
375 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
376 ISA_MIPS32 | INSN_MIPS16 | INSN_DSP,
377 mips_cp0_names_mips3264,
378 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
379 mips_hwr_names_numeric },
381 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
382 ISA_MIPS32R2 | INSN_MIPS16 | INSN_DSP | INSN_MT,
383 mips_cp0_names_mips3264r2,
384 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
385 mips_hwr_names_mips3264r2 },
387 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
388 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
389 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
390 mips_cp0_names_mips3264,
391 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
392 mips_hwr_names_numeric },
394 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
395 ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX | INSN_DSP,
396 mips_cp0_names_mips3264r2,
397 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
398 mips_hwr_names_mips3264r2 },
400 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
401 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
403 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
404 mips_hwr_names_numeric },
406 /* This entry, mips16, is here only for ISA/processor selection; do
407 not print its name. */
408 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
409 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
412 /* ISA and processor type to disassemble for, and register names to use.
413 set_default_mips_dis_options and parse_mips_dis_options fill in these
415 static int mips_processor;
417 static const char * const *mips_gpr_names;
418 static const char * const *mips_fpr_names;
419 static const char * const *mips_cp0_names;
420 static const struct mips_cp0sel_name *mips_cp0sel_names;
421 static int mips_cp0sel_names_len;
422 static const char * const *mips_hwr_names;
425 static int no_aliases; /* If set disassemble as most general inst. */
427 static const struct mips_abi_choice *
428 choose_abi_by_name (const char *name, unsigned int namelen)
430 const struct mips_abi_choice *c;
433 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
434 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
435 && strlen (mips_abi_choices[i].name) == namelen)
436 c = &mips_abi_choices[i];
441 static const struct mips_arch_choice *
442 choose_arch_by_name (const char *name, unsigned int namelen)
444 const struct mips_arch_choice *c = NULL;
447 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
448 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
449 && strlen (mips_arch_choices[i].name) == namelen)
450 c = &mips_arch_choices[i];
455 static const struct mips_arch_choice *
456 choose_arch_by_number (unsigned long mach)
458 static unsigned long hint_bfd_mach;
459 static const struct mips_arch_choice *hint_arch_choice;
460 const struct mips_arch_choice *c;
463 /* We optimize this because even if the user specifies no
464 flags, this will be done for every instruction! */
465 if (hint_bfd_mach == mach
466 && hint_arch_choice != NULL
467 && hint_arch_choice->bfd_mach == hint_bfd_mach)
468 return hint_arch_choice;
470 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
472 if (mips_arch_choices[i].bfd_mach_valid
473 && mips_arch_choices[i].bfd_mach == mach)
475 c = &mips_arch_choices[i];
476 hint_bfd_mach = mach;
477 hint_arch_choice = c;
483 /* Check if the object uses NewABI conventions. */
486 is_newabi (Elf_Internal_Ehdr *header)
488 /* There are no old-style ABIs which use 64-bit ELF. */
489 if (header->e_ident[EI_CLASS] == ELFCLASS64)
492 /* If a 32-bit ELF file, n32 is a new-style ABI. */
493 if ((header->e_flags & EF_MIPS_ABI2) != 0)
500 set_default_mips_dis_options (struct disassemble_info *info)
502 const struct mips_arch_choice *chosen_arch;
504 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
505 and numeric FPR, CP0 register, and HWR names. */
506 mips_isa = ISA_MIPS3;
507 mips_processor = CPU_R3000;
508 mips_gpr_names = mips_gpr_names_oldabi;
509 mips_fpr_names = mips_fpr_names_numeric;
510 mips_cp0_names = mips_cp0_names_numeric;
511 mips_cp0sel_names = NULL;
512 mips_cp0sel_names_len = 0;
513 mips_hwr_names = mips_hwr_names_numeric;
516 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
517 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
519 Elf_Internal_Ehdr *header;
521 header = elf_elfheader (info->section->owner);
522 if (is_newabi (header))
523 mips_gpr_names = mips_gpr_names_newabi;
526 /* Set ISA, architecture, and cp0 register names as best we can. */
527 #if ! SYMTAB_AVAILABLE
528 /* This is running out on a target machine, not in a host tool.
529 FIXME: Where does mips_target_info come from? */
530 target_processor = mips_target_info.processor;
531 mips_isa = mips_target_info.isa;
533 chosen_arch = choose_arch_by_number (info->mach);
534 if (chosen_arch != NULL)
536 mips_processor = chosen_arch->processor;
537 mips_isa = chosen_arch->isa;
538 mips_cp0_names = chosen_arch->cp0_names;
539 mips_cp0sel_names = chosen_arch->cp0sel_names;
540 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
541 mips_hwr_names = chosen_arch->hwr_names;
547 parse_mips_dis_option (const char *option, unsigned int len)
549 unsigned int i, optionlen, vallen;
551 const struct mips_abi_choice *chosen_abi;
552 const struct mips_arch_choice *chosen_arch;
554 /* Try to match options that are simple flags */
555 if (strncmp (option, "no-aliases", 10) == 0)
561 /* Look for the = that delimits the end of the option name. */
562 for (i = 0; i < len; i++)
563 if (option[i] == '=')
566 if (i == 0) /* Invalid option: no name before '='. */
568 if (i == len) /* Invalid option: no '='. */
570 if (i == (len - 1)) /* Invalid option: no value after '='. */
574 val = option + (optionlen + 1);
575 vallen = len - (optionlen + 1);
577 if (strncmp ("gpr-names", option, optionlen) == 0
578 && strlen ("gpr-names") == optionlen)
580 chosen_abi = choose_abi_by_name (val, vallen);
581 if (chosen_abi != NULL)
582 mips_gpr_names = chosen_abi->gpr_names;
586 if (strncmp ("fpr-names", option, optionlen) == 0
587 && strlen ("fpr-names") == optionlen)
589 chosen_abi = choose_abi_by_name (val, vallen);
590 if (chosen_abi != NULL)
591 mips_fpr_names = chosen_abi->fpr_names;
595 if (strncmp ("cp0-names", option, optionlen) == 0
596 && strlen ("cp0-names") == optionlen)
598 chosen_arch = choose_arch_by_name (val, vallen);
599 if (chosen_arch != NULL)
601 mips_cp0_names = chosen_arch->cp0_names;
602 mips_cp0sel_names = chosen_arch->cp0sel_names;
603 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
608 if (strncmp ("hwr-names", option, optionlen) == 0
609 && strlen ("hwr-names") == optionlen)
611 chosen_arch = choose_arch_by_name (val, vallen);
612 if (chosen_arch != NULL)
613 mips_hwr_names = chosen_arch->hwr_names;
617 if (strncmp ("reg-names", option, optionlen) == 0
618 && strlen ("reg-names") == optionlen)
620 /* We check both ABI and ARCH here unconditionally, so
621 that "numeric" will do the desirable thing: select
622 numeric register names for all registers. Other than
623 that, a given name probably won't match both. */
624 chosen_abi = choose_abi_by_name (val, vallen);
625 if (chosen_abi != NULL)
627 mips_gpr_names = chosen_abi->gpr_names;
628 mips_fpr_names = chosen_abi->fpr_names;
630 chosen_arch = choose_arch_by_name (val, vallen);
631 if (chosen_arch != NULL)
633 mips_cp0_names = chosen_arch->cp0_names;
634 mips_cp0sel_names = chosen_arch->cp0sel_names;
635 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
636 mips_hwr_names = chosen_arch->hwr_names;
641 /* Invalid option. */
645 parse_mips_dis_options (const char *options)
647 const char *option_end;
652 while (*options != '\0')
654 /* Skip empty options. */
661 /* We know that *options is neither NUL or a comma. */
662 option_end = options + 1;
663 while (*option_end != ',' && *option_end != '\0')
666 parse_mips_dis_option (options, option_end - options);
668 /* Go on to the next one. If option_end points to a comma, it
669 will be skipped above. */
670 options = option_end;
674 static const struct mips_cp0sel_name *
675 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
682 for (i = 0; i < len; i++)
683 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
688 /* Print insn arguments for 32/64-bit code. */
691 print_insn_args (const char *d,
692 register unsigned long int l,
694 struct disassemble_info *info)
697 unsigned int lsb, msb, msbd;
701 for (; *d != '\0'; d++)
710 (*info->fprintf_func) (info->stream, "%c", *d);
714 /* Extension character; switch for second char. */
719 /* xgettext:c-format */
720 (*info->fprintf_func) (info->stream,
721 _("# internal error, incomplete extension sequence (+)"));
725 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
726 (*info->fprintf_func) (info->stream, "0x%x", lsb);
730 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
731 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
736 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
737 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
742 const struct mips_cp0sel_name *n;
743 unsigned int cp0reg, sel;
745 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
746 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
748 /* CP0 register including 'sel' code for mtcN (et al.), to be
749 printed textually if known. If not known, print both
750 CP0 register name and sel numerically since CP0 register
751 with sel 0 may have a name unrelated to register being
753 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
754 mips_cp0sel_names_len, cp0reg, sel);
756 (*info->fprintf_func) (info->stream, "%s", n->name);
758 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
763 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
764 (*info->fprintf_func) (info->stream, "0x%x", lsb);
768 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
769 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
773 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
774 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
777 case 't': /* Coprocessor 0 reg name */
778 (*info->fprintf_func) (info->stream, "%s",
779 mips_cp0_names[(l >> OP_SH_RT) &
783 case 'T': /* Coprocessor 0 reg name */
785 const struct mips_cp0sel_name *n;
786 unsigned int cp0reg, sel;
788 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
789 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
791 /* CP0 register including 'sel' code for mftc0, to be
792 printed textually if known. If not known, print both
793 CP0 register name and sel numerically since CP0 register
794 with sel 0 may have a name unrelated to register being
796 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
797 mips_cp0sel_names_len, cp0reg, sel);
799 (*info->fprintf_func) (info->stream, "%s", n->name);
801 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
806 /* xgettext:c-format */
807 (*info->fprintf_func) (info->stream,
808 _("# internal error, undefined extension sequence (+%c)"),
815 (*info->fprintf_func) (info->stream, "0x%lx",
816 (l >> OP_SH_SA3) & OP_MASK_SA3);
820 (*info->fprintf_func) (info->stream, "0x%lx",
821 (l >> OP_SH_SA4) & OP_MASK_SA4);
825 (*info->fprintf_func) (info->stream, "0x%lx",
826 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
830 (*info->fprintf_func) (info->stream, "0x%lx",
831 (l >> OP_SH_RS) & OP_MASK_RS);
835 (*info->fprintf_func) (info->stream, "$ac%ld",
836 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
840 (*info->fprintf_func) (info->stream, "0x%lx",
841 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
845 (*info->fprintf_func) (info->stream, "$ac%ld",
846 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
849 case '0': /* dsp 6-bit signed immediate in bit 20 */
850 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
851 if (delta & 0x20) /* test sign bit */
852 delta |= ~OP_MASK_DSPSFT;
853 (*info->fprintf_func) (info->stream, "%d", delta);
856 case ':': /* dsp 7-bit signed immediate in bit 19 */
857 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
858 if (delta & 0x40) /* test sign bit */
859 delta |= ~OP_MASK_DSPSFT_7;
860 (*info->fprintf_func) (info->stream, "%d", delta);
864 (*info->fprintf_func) (info->stream, "0x%lx",
865 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
868 case '@': /* dsp 10-bit signed immediate in bit 16 */
869 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
870 if (delta & 0x200) /* test sign bit */
871 delta |= ~OP_MASK_IMM10;
872 (*info->fprintf_func) (info->stream, "%d", delta);
876 (*info->fprintf_func) (info->stream, "%ld",
877 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
881 (*info->fprintf_func) (info->stream, "%ld",
882 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
886 (*info->fprintf_func) (info->stream, "$ac%ld",
887 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
891 (*info->fprintf_func) (info->stream, "$ac%ld",
892 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
896 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
897 (*info->fprintf_func) (info->stream, "$%ld",
898 (l >> OP_SH_RD) & OP_MASK_RD);
905 (*info->fprintf_func) (info->stream, "%s",
906 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
911 (*info->fprintf_func) (info->stream, "%s",
912 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
917 (*info->fprintf_func) (info->stream, "0x%lx",
918 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
921 case 'j': /* Same as i, but sign-extended. */
923 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
926 (*info->fprintf_func) (info->stream, "%d",
931 (*info->fprintf_func) (info->stream, "0x%x",
932 (unsigned int) ((l >> OP_SH_PREFX)
937 (*info->fprintf_func) (info->stream, "0x%x",
938 (unsigned int) ((l >> OP_SH_CACHE)
943 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
944 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
945 (*info->print_address_func) (info->target, info);
949 /* Sign extend the displacement. */
950 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
953 info->target = (delta << 2) + pc + INSNLEN;
954 (*info->print_address_func) (info->target, info);
958 (*info->fprintf_func) (info->stream, "%s",
959 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
964 /* First check for both rd and rt being equal. */
965 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
966 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
967 (*info->fprintf_func) (info->stream, "%s",
968 mips_gpr_names[reg]);
971 /* If one is zero use the other. */
973 (*info->fprintf_func) (info->stream, "%s",
974 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
975 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
976 (*info->fprintf_func) (info->stream, "%s",
977 mips_gpr_names[reg]);
978 else /* Bogus, result depends on processor. */
979 (*info->fprintf_func) (info->stream, "%s or %s",
981 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
987 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
991 (*info->fprintf_func) (info->stream, "0x%lx",
992 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
996 (*info->fprintf_func) (info->stream, "0x%lx",
997 (l >> OP_SH_CODE) & OP_MASK_CODE);
1001 (*info->fprintf_func) (info->stream, "0x%lx",
1002 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
1006 (*info->fprintf_func) (info->stream, "0x%lx",
1007 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
1011 (*info->fprintf_func) (info->stream, "0x%lx",
1013 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
1017 (*info->fprintf_func) (info->stream, "0x%lx",
1018 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
1023 (*info->fprintf_func) (info->stream, "%s",
1024 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
1029 (*info->fprintf_func) (info->stream, "%s",
1030 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
1034 (*info->fprintf_func) (info->stream, "%s",
1035 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
1039 (*info->fprintf_func) (info->stream, "%s",
1040 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
1044 /* Coprocessor register for lwcN instructions, et al.
1046 Note that there is no load/store cp0 instructions, and
1047 that FPU (cp1) instructions disassemble this field using
1048 'T' format. Therefore, until we gain understanding of
1049 cp2 register names, we can simply print the register
1051 (*info->fprintf_func) (info->stream, "$%ld",
1052 (l >> OP_SH_RT) & OP_MASK_RT);
1056 /* Coprocessor register for mtcN instructions, et al. Note
1057 that FPU (cp1) instructions disassemble this field using
1058 'S' format. Therefore, we only need to worry about cp0,
1060 op = (l >> OP_SH_OP) & OP_MASK_OP;
1061 if (op == OP_OP_COP0)
1062 (*info->fprintf_func) (info->stream, "%s",
1063 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1065 (*info->fprintf_func) (info->stream, "$%ld",
1066 (l >> OP_SH_RD) & OP_MASK_RD);
1070 (*info->fprintf_func) (info->stream, "%s",
1071 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
1075 (*info->fprintf_func) (info->stream, "$fcc%ld",
1076 (l >> OP_SH_BCC) & OP_MASK_BCC);
1080 (*info->fprintf_func) (info->stream, "$fcc%ld",
1081 (l >> OP_SH_CCC) & OP_MASK_CCC);
1085 (*info->fprintf_func) (info->stream, "%ld",
1086 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
1090 (*info->fprintf_func) (info->stream, "%ld",
1091 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
1095 (*info->fprintf_func) (info->stream, "%ld",
1096 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
1100 (*info->fprintf_func) (info->stream, "%ld",
1101 (l >> OP_SH_SEL) & OP_MASK_SEL);
1105 (*info->fprintf_func) (info->stream, "%ld",
1106 (l >> OP_SH_ALN) & OP_MASK_ALN);
1111 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
1113 if ((vsel & 0x10) == 0)
1118 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
1119 if ((vsel & 1) == 0)
1121 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
1122 (l >> OP_SH_FT) & OP_MASK_FT,
1125 else if ((vsel & 0x08) == 0)
1127 (*info->fprintf_func) (info->stream, "$v%ld",
1128 (l >> OP_SH_FT) & OP_MASK_FT);
1132 (*info->fprintf_func) (info->stream, "0x%lx",
1133 (l >> OP_SH_FT) & OP_MASK_FT);
1139 (*info->fprintf_func) (info->stream, "$v%ld",
1140 (l >> OP_SH_FD) & OP_MASK_FD);
1144 (*info->fprintf_func) (info->stream, "$v%ld",
1145 (l >> OP_SH_FS) & OP_MASK_FS);
1149 (*info->fprintf_func) (info->stream, "$v%ld",
1150 (l >> OP_SH_FT) & OP_MASK_FT);
1154 /* xgettext:c-format */
1155 (*info->fprintf_func) (info->stream,
1156 _("# internal error, undefined modifier(%c)"),
1163 /* Print the mips instruction at address MEMADDR in debugged memory,
1164 on using INFO. Returns length of the instruction, in bytes, which is
1165 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
1166 this is little-endian code. */
1169 print_insn_mips (bfd_vma memaddr,
1170 unsigned long int word,
1171 struct disassemble_info *info)
1173 const struct mips_opcode *op;
1174 static bfd_boolean init = 0;
1175 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
1177 /* Build a hash table to shorten the search time. */
1182 for (i = 0; i <= OP_MASK_OP; i++)
1184 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
1186 if (op->pinfo == INSN_MACRO
1187 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
1189 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
1200 info->bytes_per_chunk = INSNLEN;
1201 info->display_endian = info->endian;
1202 info->insn_info_valid = 1;
1203 info->branch_delay_insns = 0;
1204 info->data_size = 0;
1205 info->insn_type = dis_nonbranch;
1209 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
1212 for (; op < &mips_opcodes[NUMOPCODES]; op++)
1214 if (op->pinfo != INSN_MACRO
1215 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1216 && (word & op->mask) == op->match)
1220 /* We always allow to disassemble the jalx instruction. */
1221 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
1222 && strcmp (op->name, "jalx"))
1225 /* Figure out instruction type and branch delay information. */
1226 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1228 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1229 info->insn_type = dis_jsr;
1231 info->insn_type = dis_branch;
1232 info->branch_delay_insns = 1;
1234 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
1235 | INSN_COND_BRANCH_LIKELY)) != 0)
1237 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
1238 info->insn_type = dis_condjsr;
1240 info->insn_type = dis_condbranch;
1241 info->branch_delay_insns = 1;
1243 else if ((op->pinfo & (INSN_STORE_MEMORY
1244 | INSN_LOAD_MEMORY_DELAY)) != 0)
1245 info->insn_type = dis_dref;
1247 (*info->fprintf_func) (info->stream, "%s", op->name);
1250 if (d != NULL && *d != '\0')
1252 (*info->fprintf_func) (info->stream, "\t");
1253 print_insn_args (d, word, memaddr, info);
1261 /* Handle undefined instructions. */
1262 info->insn_type = dis_noninsn;
1263 (*info->fprintf_func) (info->stream, "0x%lx", word);
1267 /* Disassemble an operand for a mips16 instruction. */
1270 print_mips16_insn_arg (char type,
1271 const struct mips_opcode *op,
1273 bfd_boolean use_extend,
1276 struct disassemble_info *info)
1283 (*info->fprintf_func) (info->stream, "%c", type);
1288 (*info->fprintf_func) (info->stream, "%s",
1289 mips16_reg_names(((l >> MIPS16OP_SH_RY)
1290 & MIPS16OP_MASK_RY)));
1295 (*info->fprintf_func) (info->stream, "%s",
1296 mips16_reg_names(((l >> MIPS16OP_SH_RX)
1297 & MIPS16OP_MASK_RX)));
1301 (*info->fprintf_func) (info->stream, "%s",
1302 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
1303 & MIPS16OP_MASK_RZ)));
1307 (*info->fprintf_func) (info->stream, "%s",
1308 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
1309 & MIPS16OP_MASK_MOVE32Z)));
1313 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
1317 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
1321 (*info->fprintf_func) (info->stream, "$pc");
1325 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
1329 (*info->fprintf_func) (info->stream, "%s",
1330 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
1331 & MIPS16OP_MASK_REGR32)]);
1335 (*info->fprintf_func) (info->stream, "%s",
1336 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
1362 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
1374 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1380 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1386 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
1392 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
1398 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
1404 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1405 info->insn_type = dis_dref;
1406 info->data_size = 1;
1411 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1412 info->insn_type = dis_dref;
1413 info->data_size = 2;
1418 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1419 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
1420 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
1422 info->insn_type = dis_dref;
1423 info->data_size = 4;
1429 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1430 info->insn_type = dis_dref;
1431 info->data_size = 8;
1435 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1440 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1444 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1449 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1450 /* FIXME: This might be lw, or it might be addiu to $sp or
1451 $pc. We assume it's load. */
1452 info->insn_type = dis_dref;
1453 info->data_size = 4;
1458 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1459 info->insn_type = dis_dref;
1460 info->data_size = 8;
1464 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1469 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1475 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1480 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1484 info->insn_type = dis_condbranch;
1488 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
1492 info->insn_type = dis_branch;
1497 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
1499 /* FIXME: This can be lw or la. We assume it is lw. */
1500 info->insn_type = dis_dref;
1501 info->data_size = 4;
1506 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1508 info->insn_type = dis_dref;
1509 info->data_size = 8;
1514 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
1523 if (signedp && immed >= (1 << (nbits - 1)))
1524 immed -= 1 << nbits;
1526 if ((type == '<' || type == '>' || type == '[' || type == ']')
1533 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
1534 else if (extbits == 15)
1535 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
1537 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
1538 immed &= (1 << extbits) - 1;
1539 if (! extu && immed >= (1 << (extbits - 1)))
1540 immed -= 1 << extbits;
1544 (*info->fprintf_func) (info->stream, "%d", immed);
1552 baseaddr = memaddr + 2;
1554 else if (use_extend)
1555 baseaddr = memaddr - 2;
1563 /* If this instruction is in the delay slot of a jr
1564 instruction, the base address is the address of the
1565 jr instruction. If it is in the delay slot of jalr
1566 instruction, the base address is the address of the
1567 jalr instruction. This test is unreliable: we have
1568 no way of knowing whether the previous word is
1569 instruction or data. */
1570 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
1573 && (((info->endian == BFD_ENDIAN_BIG
1574 ? bfd_getb16 (buffer)
1575 : bfd_getl16 (buffer))
1576 & 0xf800) == 0x1800))
1577 baseaddr = memaddr - 4;
1580 status = (*info->read_memory_func) (memaddr - 2, buffer,
1583 && (((info->endian == BFD_ENDIAN_BIG
1584 ? bfd_getb16 (buffer)
1585 : bfd_getl16 (buffer))
1586 & 0xf81f) == 0xe800))
1587 baseaddr = memaddr - 2;
1590 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
1591 (*info->print_address_func) (info->target, info);
1599 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
1600 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
1601 (*info->print_address_func) (info->target, info);
1602 info->insn_type = dis_jsr;
1603 info->branch_delay_insns = 1;
1609 int need_comma, amask, smask;
1613 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
1615 amask = (l >> 3) & 7;
1617 if (amask > 0 && amask < 5)
1619 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1621 (*info->fprintf_func) (info->stream, "-%s",
1622 mips_gpr_names[amask + 3]);
1626 smask = (l >> 1) & 3;
1629 (*info->fprintf_func) (info->stream, "%s??",
1630 need_comma ? "," : "");
1635 (*info->fprintf_func) (info->stream, "%s%s",
1636 need_comma ? "," : "",
1637 mips_gpr_names[16]);
1639 (*info->fprintf_func) (info->stream, "-%s",
1640 mips_gpr_names[smask + 15]);
1646 (*info->fprintf_func) (info->stream, "%s%s",
1647 need_comma ? "," : "",
1648 mips_gpr_names[31]);
1652 if (amask == 5 || amask == 6)
1654 (*info->fprintf_func) (info->stream, "%s$f0",
1655 need_comma ? "," : "");
1657 (*info->fprintf_func) (info->stream, "-$f1");
1664 /* MIPS16e save/restore. */
1667 int amask, args, statics;
1676 amask = (l >> 16) & 0xf;
1677 if (amask == MIPS16_ALL_ARGS)
1682 else if (amask == MIPS16_ALL_STATICS)
1690 statics = amask & 3;
1694 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
1696 (*info->fprintf_func) (info->stream, "-%s",
1697 mips_gpr_names[4 + args - 1]);
1701 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
1702 if (framesz == 0 && !use_extend)
1705 (*info->fprintf_func) (info->stream, "%s%d",
1706 need_comma ? "," : "",
1709 if (l & 0x40) /* $ra */
1710 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
1712 nsreg = (l >> 24) & 0x7;
1714 if (l & 0x20) /* $s0 */
1716 if (l & 0x10) /* $s1 */
1718 if (nsreg > 0) /* $s2-$s8 */
1719 smask |= ((1 << nsreg) - 1) << 2;
1721 /* Find first set static reg bit. */
1722 for (i = 0; i < 9; i++)
1724 if (smask & (1 << i))
1726 (*info->fprintf_func) (info->stream, ",%s",
1727 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
1728 /* Skip over string of set bits. */
1729 for (j = i; smask & (2 << j); j++)
1732 (*info->fprintf_func) (info->stream, "-%s",
1733 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
1738 /* Statics $ax - $a3. */
1740 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
1741 else if (statics > 0)
1742 (*info->fprintf_func) (info->stream, ",%s-%s",
1743 mips_gpr_names[7 - statics + 1],
1749 /* xgettext:c-format */
1750 (*info->fprintf_func)
1752 _("# internal disassembler error, unrecognised modifier (%c)"),
1758 /* Disassemble mips16 instructions. */
1761 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
1767 bfd_boolean use_extend;
1769 const struct mips_opcode *op, *opend;
1771 info->bytes_per_chunk = 2;
1772 info->display_endian = info->endian;
1773 info->insn_info_valid = 1;
1774 info->branch_delay_insns = 0;
1775 info->data_size = 0;
1776 info->insn_type = dis_nonbranch;
1780 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1783 (*info->memory_error_func) (status, memaddr, info);
1789 if (info->endian == BFD_ENDIAN_BIG)
1790 insn = bfd_getb16 (buffer);
1792 insn = bfd_getl16 (buffer);
1794 /* Handle the extend opcode specially. */
1796 if ((insn & 0xf800) == 0xf000)
1799 extend = insn & 0x7ff;
1803 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
1806 (*info->fprintf_func) (info->stream, "extend 0x%x",
1807 (unsigned int) extend);
1808 (*info->memory_error_func) (status, memaddr, info);
1812 if (info->endian == BFD_ENDIAN_BIG)
1813 insn = bfd_getb16 (buffer);
1815 insn = bfd_getl16 (buffer);
1817 /* Check for an extend opcode followed by an extend opcode. */
1818 if ((insn & 0xf800) == 0xf000)
1820 (*info->fprintf_func) (info->stream, "extend 0x%x",
1821 (unsigned int) extend);
1822 info->insn_type = dis_noninsn;
1829 /* FIXME: Should probably use a hash table on the major opcode here. */
1831 opend = mips16_opcodes + bfd_mips16_num_opcodes;
1832 for (op = mips16_opcodes; op < opend; op++)
1834 if (op->pinfo != INSN_MACRO
1835 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
1836 && (insn & op->mask) == op->match)
1840 if (strchr (op->args, 'a') != NULL)
1844 (*info->fprintf_func) (info->stream, "extend 0x%x",
1845 (unsigned int) extend);
1846 info->insn_type = dis_noninsn;
1854 status = (*info->read_memory_func) (memaddr, buffer, 2,
1859 if (info->endian == BFD_ENDIAN_BIG)
1860 extend = bfd_getb16 (buffer);
1862 extend = bfd_getl16 (buffer);
1867 (*info->fprintf_func) (info->stream, "%s", op->name);
1868 if (op->args[0] != '\0')
1869 (*info->fprintf_func) (info->stream, "\t");
1871 for (s = op->args; *s != '\0'; s++)
1875 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
1876 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
1878 /* Skip the register and the comma. */
1884 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
1885 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
1887 /* Skip the register and the comma. */
1891 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
1895 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
1897 info->branch_delay_insns = 1;
1898 if (info->insn_type != dis_jsr)
1899 info->insn_type = dis_branch;
1907 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
1908 (*info->fprintf_func) (info->stream, "0x%x", insn);
1909 info->insn_type = dis_noninsn;
1914 /* In an environment where we do not know the symbol type of the
1915 instruction we are forced to assume that the low order bit of the
1916 instructions' address may mark it as a mips16 instruction. If we
1917 are single stepping, or the pc is within the disassembled function,
1918 this works. Otherwise, we need a clue. Sometimes. */
1921 _print_insn_mips (bfd_vma memaddr,
1922 struct disassemble_info *info,
1923 enum bfd_endian endianness)
1925 bfd_byte buffer[INSNLEN];
1928 set_default_mips_dis_options (info);
1929 parse_mips_dis_options (info->disassembler_options);
1932 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
1933 /* Only a few tools will work this way. */
1935 return print_insn_mips16 (memaddr, info);
1938 #if SYMTAB_AVAILABLE
1939 if (info->mach == bfd_mach_mips16
1940 || (info->flavour == bfd_target_elf_flavour
1941 && info->symbols != NULL
1942 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
1944 return print_insn_mips16 (memaddr, info);
1947 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
1952 if (endianness == BFD_ENDIAN_BIG)
1953 insn = (unsigned long) bfd_getb32 (buffer);
1955 insn = (unsigned long) bfd_getl32 (buffer);
1957 return print_insn_mips (memaddr, insn, info);
1961 (*info->memory_error_func) (status, memaddr, info);
1967 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
1969 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
1973 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
1975 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
1979 print_mips_disassembler_options (FILE *stream)
1983 fprintf (stream, _("\n\
1984 The following MIPS specific disassembler options are supported for use\n\
1985 with the -M switch (multiple options should be separated by commas):\n"));
1987 fprintf (stream, _("\n\
1988 gpr-names=ABI Print GPR names according to specified ABI.\n\
1989 Default: based on binary being disassembled.\n"));
1991 fprintf (stream, _("\n\
1992 fpr-names=ABI Print FPR names according to specified ABI.\n\
1993 Default: numeric.\n"));
1995 fprintf (stream, _("\n\
1996 cp0-names=ARCH Print CP0 register names according to\n\
1997 specified architecture.\n\
1998 Default: based on binary being disassembled.\n"));
2000 fprintf (stream, _("\n\
2001 hwr-names=ARCH Print HWR names according to specified \n\
2003 Default: based on binary being disassembled.\n"));
2005 fprintf (stream, _("\n\
2006 reg-names=ABI Print GPR and FPR names according to\n\
2007 specified ABI.\n"));
2009 fprintf (stream, _("\n\
2010 reg-names=ARCH Print CP0 register and HWR names according to\n\
2011 specified architecture.\n"));
2013 fprintf (stream, _("\n\
2014 For the options above, the following values are supported for \"ABI\":\n\
2016 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
2017 fprintf (stream, " %s", mips_abi_choices[i].name);
2018 fprintf (stream, _("\n"));
2020 fprintf (stream, _("\n\
2021 For the options above, The following values are supported for \"ARCH\":\n\
2023 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
2024 if (*mips_arch_choices[i].name != '\0')
2025 fprintf (stream, " %s", mips_arch_choices[i].name);
2026 fprintf (stream, _("\n"));
2028 fprintf (stream, _("\n"));