1 /* Disassembly routines for TMS320C30 architecture
2 Copyright 1998, 1999, 2000, 2002, 2005 Free Software Foundation, Inc.
3 Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
24 #include "opcode/tic30.h"
27 #define PARALLEL_INSN 2
29 /* Gets the type of instruction based on the top 2 or 3 bits of the
31 #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
33 /* Instruction types. */
34 #define TWO_OPERAND_1 0x00000000
35 #define TWO_OPERAND_2 0x40000000
36 #define THREE_OPERAND 0x20000000
37 #define PAR_STORE 0xC0000000
38 #define MUL_ADDS 0x80000000
39 #define BRANCHES 0x60000000
41 /* Specific instruction id bits. */
42 #define NORMAL_IDEN 0x1F800000
43 #define PAR_STORE_IDEN 0x3E000000
44 #define MUL_ADD_IDEN 0x2C000000
45 #define BR_IMM_IDEN 0x1F000000
46 #define BR_COND_IDEN 0x1C3F0000
48 /* Addressing modes. */
49 #define AM_REGISTER 0x00000000
50 #define AM_DIRECT 0x00200000
51 #define AM_INDIRECT 0x00400000
52 #define AM_IMM 0x00600000
54 #define P_FIELD 0x03000000
57 #define LDP_INSN 0x08700000
59 /* TMS320C30 program counter for current instruction. */
60 static unsigned int _pc;
70 get_tic30_instruction (unsigned long insn_word, struct instruction *insn)
72 switch (GET_TYPE (insn_word))
77 insn->type = NORMAL_INSN;
79 template *current_optab = (template *) tic30_optab;
81 for (; current_optab < tic30_optab_end; current_optab++)
83 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
85 if (current_optab->operands == 0)
87 if (current_optab->base_opcode == insn_word)
89 insn->tm = current_optab;
93 else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN))
95 insn->tm = current_optab;
104 insn->type = PARALLEL_INSN;
106 partemplate *current_optab = (partemplate *) tic30_paroptab;
108 for (; current_optab < tic30_paroptab_end; current_optab++)
110 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
112 if ((current_optab->base_opcode & PAR_STORE_IDEN)
113 == (insn_word & PAR_STORE_IDEN))
115 insn->ptm = current_optab;
124 insn->type = PARALLEL_INSN;
126 partemplate *current_optab = (partemplate *) tic30_paroptab;
128 for (; current_optab < tic30_paroptab_end; current_optab++)
130 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
132 if ((current_optab->base_opcode & MUL_ADD_IDEN)
133 == (insn_word & MUL_ADD_IDEN))
135 insn->ptm = current_optab;
144 insn->type = NORMAL_INSN;
146 template *current_optab = (template *) tic30_optab;
148 for (; current_optab < tic30_optab_end; current_optab++)
150 if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
152 if (current_optab->operand_types[0] & Imm24)
154 if ((current_optab->base_opcode & BR_IMM_IDEN)
155 == (insn_word & BR_IMM_IDEN))
157 insn->tm = current_optab;
161 else if (current_optab->operands > 0)
163 if ((current_optab->base_opcode & BR_COND_IDEN)
164 == (insn_word & BR_COND_IDEN))
166 insn->tm = current_optab;
172 if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000))
173 == (insn_word & (BR_COND_IDEN | 0x00800000)))
175 insn->tm = current_optab;
190 get_register_operand (unsigned char fragment, char *buffer)
192 const reg *current_reg = tic30_regtab;
196 for (; current_reg < tic30_regtab_end; current_reg++)
198 if ((fragment & 0x1F) == current_reg->opcode)
200 strcpy (buffer, current_reg->name);
208 get_indirect_operand (unsigned short fragment,
218 /* Determine which bits identify the sections of the indirect
219 operand based on the size in bytes. */
223 mod = (fragment & 0x00F8) >> 3;
224 arnum = (fragment & 0x0007);
228 mod = (fragment & 0xF800) >> 11;
229 arnum = (fragment & 0x0700) >> 8;
230 disp = (fragment & 0x00FF);
236 const ind_addr_type *current_ind = tic30_indaddr_tab;
238 for (; current_ind < tic30_indaddrtab_end; current_ind++)
240 if (current_ind->modfield == mod)
242 if (current_ind->displacement == IMPLIED_DISP && size == 2)
250 len = strlen (current_ind->syntax);
251 for (i = 0, bufcnt = 0; i < len; i++, bufcnt++)
253 buffer[bufcnt] = current_ind->syntax[i];
254 if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r')
255 buffer[++bufcnt] = arnum + '0';
256 if (buffer[bufcnt] == '('
257 && current_ind->displacement == DISP_REQUIRED)
259 sprintf (&buffer[bufcnt + 1], "%u", disp);
260 bufcnt += strlen (&buffer[bufcnt + 1]);
263 buffer[bufcnt + 1] = '\0';
273 cnvt_tmsfloat_ieee (unsigned long tmsfloat, int size, float *ieeefloat)
275 unsigned long exp, sign, mant;
284 if ((tmsfloat & 0x0000F000) == 0x00008000)
285 tmsfloat = 0x80000000;
289 tmsfloat = (long) tmsfloat >> 4;
292 exp = tmsfloat & 0xFF000000;
293 if (exp == 0x80000000)
299 sign = (tmsfloat & 0x00800000) << 8;
300 mant = tmsfloat & 0x007FFFFF;
301 if (exp == 0xFF000000)
306 *ieeefloat = 1.0 / 0.0;
308 *ieeefloat = -1.0 / 0.0;
314 mant = (~mant) & 0x007FFFFF;
316 exp += mant & 0x00800000;
320 if (tmsfloat == 0x80000000)
321 sign = mant = exp = 0;
322 tmsfloat = sign | exp | mant;
329 print_two_operand (disassemble_info *info,
330 unsigned long insn_word,
331 struct instruction *insn)
334 char operand[2][13] =
341 if (insn->tm == NULL)
343 strcpy (name, insn->tm->name);
344 if (insn->tm->opcode_modifier == AddressMode)
347 /* Determine whether instruction is a store or a normal instruction. */
348 if ((insn->tm->operand_types[1] & (Direct | Indirect))
349 == (Direct | Indirect))
359 /* Get the destination register. */
360 if (insn->tm->operands == 2)
361 get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]);
362 /* Get the source operand based on addressing mode. */
363 switch (insn_word & AddressMode)
366 /* Check for the NOP instruction before getting the operand. */
367 if ((insn->tm->operand_types[0] & NotReq) == 0)
368 get_register_operand ((insn_word & 0x0000001F), operand[src_op]);
371 sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF));
374 get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]);
377 /* Get the value of the immediate operand based on variable type. */
378 switch (insn->tm->imm_arg_type)
381 cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number);
382 sprintf (operand[src_op], "%2.2f", f_number);
385 sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF));
388 sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF));
393 /* Handle special case for LDP instruction. */
394 if ((insn_word & 0xFFFFFF00) == LDP_INSN)
396 strcpy (name, "ldp");
397 sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16);
398 operand[1][0] = '\0';
402 /* Handle case for stack and rotate instructions. */
403 else if (insn->tm->operands == 1)
405 if (insn->tm->opcode_modifier == StackOp)
406 get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]);
408 /* Output instruction to stream. */
409 info->fprintf_func (info->stream, " %s %s%c%s", name,
410 operand[0][0] ? operand[0] : "",
411 operand[1][0] ? ',' : ' ',
412 operand[1][0] ? operand[1] : "");
417 print_three_operand (disassemble_info *info,
418 unsigned long insn_word,
419 struct instruction *insn)
421 char operand[3][13] =
428 if (insn->tm == NULL)
430 switch (insn_word & AddressMode)
433 get_register_operand ((insn_word & 0x000000FF), operand[0]);
434 get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
437 get_register_operand ((insn_word & 0x000000FF), operand[0]);
438 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
441 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
442 get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
445 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
446 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
451 if (insn->tm->operands == 3)
452 get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]);
453 info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name,
454 operand[0], operand[1],
455 operand[2][0] ? ',' : ' ',
456 operand[2][0] ? operand[2] : "");
461 print_par_insn (disassemble_info *info,
462 unsigned long insn_word,
463 struct instruction *insn)
467 char operand[2][3][13] =
481 if (insn->ptm == NULL)
483 /* Parse out the names of each of the parallel instructions from the
484 q_insn1_insn2 format. */
485 name1 = (char *) strdup (insn->ptm->name + 2);
487 len = strlen (name1);
488 for (i = 0; i < len; i++)
492 name2 = &name1[i + 1];
497 /* Get the operands of the instruction based on the operand order. */
498 switch (insn->ptm->oporder)
501 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
502 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
503 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
504 get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
507 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
508 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
509 get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]);
510 get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
513 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
514 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
515 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
516 get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]);
519 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
520 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
521 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
522 get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
523 get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
526 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
527 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
528 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
529 get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
530 get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
533 if (insn_word & 0x00800000)
534 get_register_operand (0x01, operand[0][2]);
536 get_register_operand (0x00, operand[0][2]);
537 if (insn_word & 0x00400000)
538 get_register_operand (0x03, operand[1][2]);
540 get_register_operand (0x02, operand[1][2]);
541 switch (insn_word & P_FIELD)
544 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
545 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
546 get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
547 get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]);
550 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]);
551 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
552 get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
553 get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
556 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
557 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
558 get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]);
559 get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
562 get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
563 get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
564 get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
565 get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
572 info->fprintf_func (info->stream, " %s %s,%s%c%s", name1,
573 operand[0][0], operand[0][1],
574 operand[0][2][0] ? ',' : ' ',
575 operand[0][2][0] ? operand[0][2] : "");
576 info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2,
577 operand[1][0], operand[1][1],
578 operand[1][2][0] ? ',' : ' ',
579 operand[1][2][0] ? operand[1][2] : "");
585 print_branch (disassemble_info *info,
586 unsigned long insn_word,
587 struct instruction *insn)
589 char operand[2][13] =
594 unsigned long address;
597 if (insn->tm == NULL)
599 /* Get the operands for 24-bit immediate jumps. */
600 if (insn->tm->operand_types[0] & Imm24)
602 address = insn_word & 0x00FFFFFF;
603 sprintf (operand[0], "0x%lX", address);
606 /* Get the operand for the trap instruction. */
607 else if (insn->tm->operand_types[0] & IVector)
609 address = insn_word & 0x0000001F;
610 sprintf (operand[0], "0x%lX", address);
614 address = insn_word & 0x0000FFFF;
615 /* Get the operands for the DB instructions. */
616 if (insn->tm->operands == 2)
618 get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]);
619 if (insn_word & PCRel)
621 sprintf (operand[1], "%d", (short) address);
625 get_register_operand (insn_word & 0x0000001F, operand[1]);
627 /* Get the operands for the standard branches. */
628 else if (insn->tm->operands == 1)
630 if (insn_word & PCRel)
632 address = (short) address;
633 sprintf (operand[0], "%ld", address);
637 get_register_operand (insn_word & 0x0000001F, operand[0]);
640 info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name,
641 operand[0][0] ? operand[0] : "",
642 operand[1][0] ? ',' : ' ',
643 operand[1][0] ? operand[1] : "");
644 /* Print destination of branch in relation to current symbol. */
645 if (print_label && info->symbols)
647 asymbol *sym = *info->symbols;
649 if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel))
651 address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4);
652 /* Check for delayed instruction, if so adjust destination. */
653 if (insn_word & 0x00200000)
658 address -= ((sym->section->vma + sym->value) / 4);
661 info->fprintf_func (info->stream, " <%s>", sym->name);
663 info->fprintf_func (info->stream, " <%s %c %d>", sym->name,
664 ((short) address < 0) ? '-' : '+',
671 print_insn_tic30 (bfd_vma pc, disassemble_info *info)
673 unsigned long insn_word;
674 struct instruction insn = { 0, NULL, NULL };
675 bfd_vma bufaddr = pc - info->buffer_vma;
677 /* Obtain the current instruction word from the buffer. */
678 insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) |
679 (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3);
681 /* Get the instruction refered to by the current instruction word
682 and print it out based on its type. */
683 if (!get_tic30_instruction (insn_word, &insn))
685 switch (GET_TYPE (insn_word))
689 if (!print_two_operand (info, insn_word, &insn))
693 if (!print_three_operand (info, insn_word, &insn))
698 if (!print_par_insn (info, insn_word, &insn))
702 if (!print_branch (info, insn_word, &insn))