1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 //============================================================
23 //============================================================
24 #include "mp_precomp.h"
25 #include "phydm_precomp.h"
29 ODM_GetAutoChannelSelectResult(
34 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
35 PACS pACS = &pDM_Odm->DM_ACS;
37 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
38 if(Band == ODM_BAND_2_4G)
40 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_2G(%d)\n", pACS->CleanChannel_2G));
41 return (u1Byte)pACS->CleanChannel_2G;
45 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[ACS] ODM_GetAutoChannelSelectResult(): CleanChannel_5G(%d)\n", pACS->CleanChannel_5G));
46 return (u1Byte)pACS->CleanChannel_5G;
49 return (u1Byte)pACS->CleanChannel_2G;
55 odm_AutoChannelSelectSetting(
60 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
61 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
62 u2Byte period = 0x2710;// 40ms in default
65 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSetting()=========> \n"));
73 if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
75 //PHY parameters initialize for ac series
76 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, period); //0x990[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
77 //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, BIT8|BIT9|BIT10, NHMType); //0x994[9:8]=3 enable CCX
79 else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
81 //PHY parameters initialize for n series
82 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, period); //0x894[31:16]=0x2710 Time duration for NHM unit: 4us, 0x2710=40ms
83 //ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, BIT10|BIT9|BIT8, NHMType); //0x890[9:8]=3 enable CCX
89 odm_AutoChannelSelectInit(
93 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
94 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
95 PACS pACS = &pDM_Odm->DM_ACS;
98 if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
101 if(pACS->bForceACSResult)
104 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectInit()=========> \n"));
106 pACS->CleanChannel_2G = 1;
107 pACS->CleanChannel_5G = 36;
109 for (i = 0; i < ODM_MAX_CHANNEL_2G; ++i)
111 pACS->Channel_Info_2G[0][i] = 0;
112 pACS->Channel_Info_2G[1][i] = 0;
115 if(pDM_Odm->SupportICType & (ODM_IC_11AC_SERIES|ODM_RTL8192D))
117 for (i = 0; i < ODM_MAX_CHANNEL_5G; ++i)
119 pACS->Channel_Info_5G[0][i] = 0;
120 pACS->Channel_Info_5G[1][i] = 0;
127 odm_AutoChannelSelectReset(
131 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
132 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
133 PACS pACS = &pDM_Odm->DM_ACS;
135 if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
138 if(pACS->bForceACSResult)
141 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectReset()=========> \n"));
143 odm_AutoChannelSelectSetting(pDM_Odm,TRUE);// for 20ms measurement
144 Phydm_NHMCounterStatisticsReset(pDM_Odm);
149 odm_AutoChannelSelect(
154 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
155 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
156 PACS pACS = &pDM_Odm->DM_ACS;
157 u1Byte ChannelIDX = 0, SearchIDX = 0;
160 if(!(pDM_Odm->SupportAbility & ODM_BB_NHM_CNT))
162 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Return: SupportAbility ODM_BB_NHM_CNT is disabled\n"));
166 if(pACS->bForceACSResult)
168 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Force 2G clean channel = %d, 5G clean channel = %d\n",
169 pACS->CleanChannel_2G, pACS->CleanChannel_5G));
173 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel = %d=========> \n", Channel));
175 Phydm_GetNHMCounterStatistics(pDM_Odm);
176 odm_AutoChannelSelectSetting(pDM_Odm,FALSE);
178 if(Channel >=1 && Channel <=14)
180 ChannelIDX = Channel - 1;
181 pACS->Channel_Info_2G[1][ChannelIDX]++;
183 if(pACS->Channel_Info_2G[1][ChannelIDX] >= 2)
184 pACS->Channel_Info_2G[0][ChannelIDX] = (pACS->Channel_Info_2G[0][ChannelIDX] >> 1) +
185 (pACS->Channel_Info_2G[0][ChannelIDX] >> 2) + (pDM_Odm->NHM_cnt_0>>2);
187 pACS->Channel_Info_2G[0][ChannelIDX] = pDM_Odm->NHM_cnt_0;
189 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): NHM_cnt_0 = %d \n", pDM_Odm->NHM_cnt_0));
190 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelect(): Channel_Info[0][%d] = %d, Channel_Info[1][%d] = %d\n", ChannelIDX, pACS->Channel_Info_2G[0][ChannelIDX], ChannelIDX, pACS->Channel_Info_2G[1][ChannelIDX]));
192 for(SearchIDX = 0; SearchIDX < ODM_MAX_CHANNEL_2G; SearchIDX++)
194 if(pACS->Channel_Info_2G[1][SearchIDX] != 0)
196 if(pACS->Channel_Info_2G[0][SearchIDX] >= MaxScore)
198 MaxScore = pACS->Channel_Info_2G[0][SearchIDX];
199 pACS->CleanChannel_2G = SearchIDX+1;
203 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("(1)odm_AutoChannelSelect(): 2G: CleanChannel_2G = %d, MaxScore = %d \n",
204 pACS->CleanChannel_2G, MaxScore));
207 else if(Channel >= 36)
210 pACS->CleanChannel_5G = Channel;
215 #if ( DM_ODM_SUPPORT_TYPE & ODM_AP )
218 phydm_AutoChannelSelectSettingAP(
220 IN u4Byte setting, // 0: STORE_DEFAULT_NHM_SETTING; 1: RESTORE_DEFAULT_NHM_SETTING, 2: ACS_NHM_SETTING
224 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
225 prtl8192cd_priv priv = pDM_Odm->priv;
226 PACS pACS = &pDM_Odm->DM_ACS;
228 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("odm_AutoChannelSelectSettingAP()=========> \n"));
230 //3 Store Default Setting
231 if(setting == STORE_DEFAULT_NHM_SETTING)
233 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("STORE_DEFAULT_NHM_SETTING\n"));
235 if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0
237 pACS->Reg0x990 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC); // Reg0x990
238 pACS->Reg0x994 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC); // Reg0x994
239 pACS->Reg0x998 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC); // Reg0x998
240 pACS->Reg0x99C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC); // Reg0x99c
241 pACS->Reg0x9A0 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC); // Reg0x9a0, u1Byte
243 else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
245 pACS->Reg0x890 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N); // Reg0x890
246 pACS->Reg0x894 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N); // Reg0x894
247 pACS->Reg0x898 = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N); // Reg0x898
248 pACS->Reg0x89C = ODM_Read4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N); // Reg0x89c
249 pACS->Reg0xE28 = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N); // Reg0xe28, u1Byte
253 //3 Restore Default Setting
254 else if(setting == RESTORE_DEFAULT_NHM_SETTING)
256 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("RESTORE_DEFAULT_NHM_SETTING\n"));
258 if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) // store Reg0x990, Reg0x994, Reg0x998, Reg0x99C, Reg0x9a0
260 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC, pACS->Reg0x990);
261 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC, pACS->Reg0x994);
262 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, pACS->Reg0x998);
263 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, pACS->Reg0x99C);
264 ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, pACS->Reg0x9A0);
266 else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
268 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N, pACS->Reg0x890);
269 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N, pACS->Reg0x894);
270 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, pACS->Reg0x898);
271 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, pACS->Reg0x89C);
272 ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, pACS->Reg0xE28);
277 else if(setting == ACS_NHM_SETTING)
279 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("ACS_NHM_SETTING\n"));
282 pACS->ACS_Step = acs_step;
284 if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
286 //4 Set NHM period, 0x990[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms
287 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11AC+2, period);
288 //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0
289 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC,BIT8|BIT9|BIT10, 3);
291 if(pACS->ACS_Step == 0)
294 ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E);
295 if (get_rf_mimo_mode(priv) != MIMO_1T1R)
296 ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E);
298 //4 Set ACS NHM threshold
299 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x82786e64);
300 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff8c);
301 ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11AC, 0xff);
302 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11AC+2, 0xffff);
305 else if(pACS->ACS_Step == 1)
308 ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A);
309 if (get_rf_mimo_mode(priv) != MIMO_1T1R)
310 ODM_SetBBReg(pDM_Odm,0xe50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A);
312 //4 Set ACS NHM threshold
313 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0x5a50463c);
314 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffff64);
319 else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
321 //4 Set NHM period, 0x894[31:16]=0x61a8, Time duration for NHM unit: 4us, 0x61a8=100ms
322 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TIMER_11N+2, period);
323 //4 Set NHM ignore_cca=1, ignore_txon=1, ccx_en=0
324 ODM_SetBBReg(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N,BIT8|BIT9|BIT10, 3);
326 if(pACS->ACS_Step == 0)
329 ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E);
330 if (get_rf_mimo_mode(priv) != MIMO_1T1R)
331 ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x3E);
333 //4 Set ACS NHM threshold
334 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x82786e64);
335 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff8c);
336 ODM_Write1Byte(pDM_Odm, ODM_REG_NHM_TH8_11N, 0xff);
337 ODM_Write2Byte(pDM_Odm, ODM_REG_NHM_TH9_TH10_11N+2, 0xffff);
340 else if(pACS->ACS_Step == 1)
343 ODM_SetBBReg(pDM_Odm,0xc50,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A);
344 if (get_rf_mimo_mode(priv) != MIMO_1T1R)
345 ODM_SetBBReg(pDM_Odm,0xc58,BIT0|BIT1|BIT2|BIT3|BIT4|BIT5|BIT6,0x2A);
347 //4 Set ACS NHM threshold
348 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH3_TO_TH0_11N, 0x5a50463c);
349 ODM_Write4Byte(pDM_Odm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffff64);
358 phydm_GetNHMStatisticsAP(
360 IN u4Byte idx, // @ 2G, Real channel number = idx+1
364 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
365 prtl8192cd_priv priv = pDM_Odm->priv;
366 PACS pACS = &pDM_Odm->DM_ACS;
370 pACS->ACS_Step = acs_step;
372 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
374 //4 Check if NHM result is ready
375 for (i=0; i<20; i++) {
378 if ( ODM_GetBBReg(pDM_Odm,rFPGA0_PSDReport,BIT17) )
382 //4 Get NHM Statistics
383 if ( pACS->ACS_Step==1 ) {
385 value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11N);
387 pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8;
388 pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0);
390 value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N
392 pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24;
393 pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16;
394 pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8;
396 } else if (pACS->ACS_Step==2) {
398 value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11N); // ODM_REG_NHM_CNT3_TO_CNT0_11N
400 pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
401 pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24;
402 pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16;
403 pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8;
404 pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0);
407 else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
409 //4 Check if NHM result is ready
410 for (i=0; i<20; i++) {
413 if (ODM_GetBBReg(pDM_Odm,ODM_REG_NHM_DUR_READY_11AC,BIT17))
417 if ( pACS->ACS_Step==1 ) {
419 value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT7_TO_CNT4_11AC);
421 pACS->NHM_Cnt[idx][9] = (value32 & bMaskByte1) >> 8;
422 pACS->NHM_Cnt[idx][8] = (value32 & bMaskByte0);
424 value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC
426 pACS->NHM_Cnt[idx][7] = (value32 & bMaskByte3) >> 24;
427 pACS->NHM_Cnt[idx][6] = (value32 & bMaskByte2) >> 16;
428 pACS->NHM_Cnt[idx][5] = (value32 & bMaskByte1) >> 8;
430 } else if (pACS->ACS_Step==2) {
432 value32 = ODM_Read4Byte(pDM_Odm,ODM_REG_NHM_CNT_11AC); // ODM_REG_NHM_CNT3_TO_CNT0_11AC
434 pACS->NHM_Cnt[idx][4] = ODM_Read1Byte(pDM_Odm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
435 pACS->NHM_Cnt[idx][3] = (value32 & bMaskByte3) >> 24;
436 pACS->NHM_Cnt[idx][2] = (value32 & bMaskByte2) >> 16;
437 pACS->NHM_Cnt[idx][1] = (value32 & bMaskByte1) >> 8;
438 pACS->NHM_Cnt[idx][0] = (value32 & bMaskByte0);
445 //#define ACS_DEBUG_INFO //acs debug default off
447 int phydm_AutoChannelSelectAP(
449 IN u4Byte ACS_Type, // 0: RXCount_Type, 1:NHM_Type
450 IN u4Byte available_chnl_num // amount of all channels
453 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
454 PACS pACS = &pDM_Odm->DM_ACS;
455 prtl8192cd_priv priv = pDM_Odm->priv;
457 static u4Byte score2G[MAX_2G_CHANNEL_NUM], score5G[MAX_5G_CHANNEL_NUM];
458 u4Byte score[MAX_BSS_NUM], use_nhm = 0;
459 u4Byte minScore=0xffffffff;
460 u4Byte tmpScore, tmpIdx=0;
461 u4Byte traffic_check = 0;
462 u4Byte fa_count_weighting = 1;
463 int i, j, idx=0, idx_2G_end=-1, idx_5G_begin=-1, minChan=0;
464 struct bss_desc *pBss=NULL;
466 #ifdef _DEBUG_RTL8192CD_
471 memset(score2G, '\0', sizeof(score2G));
472 memset(score5G, '\0', sizeof(score5G));
474 for (i=0; i<priv->available_chnl_num; i++) {
475 if (priv->available_chnl[i] <= 14)
481 for (i=0; i<priv->available_chnl_num; i++) {
482 if (priv->available_chnl[i] > 14) {
489 #ifndef CONFIG_RTL_NEW_AUTOCH
490 for (i=0; i<priv->site_survey->count; i++) {
491 pBss = &priv->site_survey->bss[i];
492 for (idx=0; idx<priv->available_chnl_num; idx++) {
493 if (pBss->channel == priv->available_chnl[idx]) {
494 if (pBss->channel <= 14)
495 setChannelScore(idx, score2G, 0, MAX_2G_CHANNEL_NUM-1);
497 score5G[idx - idx_5G_begin] += 5;
505 for (i=0; i<=idx_2G_end; i++)
506 score[i] = score2G[i];
507 if (idx_5G_begin >= 0)
508 for (i=idx_5G_begin; i<priv->available_chnl_num; i++)
509 score[i] = score5G[i - idx_5G_begin];
511 #ifdef CONFIG_RTL_NEW_AUTOCH
513 u4Byte y, ch_begin=0, ch_end= priv->available_chnl_num;
515 u4Byte do_ap_check = 1, ap_ratio = 0;
518 ch_end = idx_2G_end+1;
519 if (idx_5G_begin >= 0)
520 ch_begin = idx_5G_begin;
522 #ifdef ACS_DEBUG_INFO//for debug
524 for (y=ch_begin; y<ch_end; y++)
525 printk("1. init: chnl[%d] 20M_rx[%d] 40M_rx[%d] fa_cnt[%d] score[%d]\n",
526 priv->available_chnl[y],
527 priv->chnl_ss_mac_rx_count[y],
528 priv->chnl_ss_mac_rx_count_40M[y],
529 priv->chnl_ss_fa_count[y],
534 #if defined(CONFIG_RTL_88E_SUPPORT) || defined(CONFIG_WLAN_HAL_8192EE)
535 if( pDM_Odm->SupportICType&(ODM_RTL8188E|ODM_RTL8192E)&& priv->pmib->dot11RFEntry.acs_type )
537 u4Byte tmp_score[MAX_BSS_NUM];
538 memcpy(tmp_score, score, sizeof(score));
539 if (find_clean_channel(priv, ch_begin, ch_end, tmp_score)) {
540 //memcpy(score, tmp_score, sizeof(score));
541 #ifdef _DEBUG_RTL8192CD_
542 printk("!! Found clean channel, select minimum FA channel\n");
546 #ifdef _DEBUG_RTL8192CD_
547 printk("!! Not found clean channel, use NHM algorithm\n");
551 for (y=ch_begin; y<ch_end; y++) {
552 for (i=0; i<=9; i++) {
553 u4Byte val32 = priv->nhm_cnt[y][i];
559 #ifdef _DEBUG_RTL8192CD_
560 printk("nhm_cnt_%d: H<-[ %3d %3d %3d %3d %3d %3d %3d %3d %3d %3d]->L, score: %d\n",
561 y+1, priv->nhm_cnt[y][9], priv->nhm_cnt[y][8], priv->nhm_cnt[y][7],
562 priv->nhm_cnt[y][6], priv->nhm_cnt[y][5], priv->nhm_cnt[y][4],
563 priv->nhm_cnt[y][3], priv->nhm_cnt[y][2], priv->nhm_cnt[y][1],
564 priv->nhm_cnt[y][0], score[y]);
569 memcpy(score, tmp_score, sizeof(score));
575 // For each channel, weighting behind channels with MAC RX counter
576 //For each channel, weighting the channel with FA counter
578 for (y=ch_begin; y<ch_end; y++) {
579 score[y] += 8 * priv->chnl_ss_mac_rx_count[y];
580 if (priv->chnl_ss_mac_rx_count[y] > 30)
582 if( priv->chnl_ss_mac_rx_count[y] > MAC_RX_COUNT_THRESHOLD )
585 #ifdef RTK_5G_SUPPORT
586 if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)
589 if ((int)(y-4) >= (int)ch_begin)
590 score[y-4] += 2 * priv->chnl_ss_mac_rx_count[y];
591 if ((int)(y-3) >= (int)ch_begin)
592 score[y-3] += 8 * priv->chnl_ss_mac_rx_count[y];
593 if ((int)(y-2) >= (int)ch_begin)
594 score[y-2] += 8 * priv->chnl_ss_mac_rx_count[y];
595 if ((int)(y-1) >= (int)ch_begin)
596 score[y-1] += 10 * priv->chnl_ss_mac_rx_count[y];
597 if ((int)(y+1) < (int)ch_end)
598 score[y+1] += 10 * priv->chnl_ss_mac_rx_count[y];
599 if ((int)(y+2) < (int)ch_end)
600 score[y+2] += 8 * priv->chnl_ss_mac_rx_count[y];
601 if ((int)(y+3) < (int)ch_end)
602 score[y+3] += 8 * priv->chnl_ss_mac_rx_count[y];
603 if ((int)(y+4) < (int)ch_end)
604 score[y+4] += 2 * priv->chnl_ss_mac_rx_count[y];
607 //this is for CH_LOAD caculation
608 if( priv->chnl_ss_cca_count[y] > priv->chnl_ss_fa_count[y])
609 priv->chnl_ss_cca_count[y]-= priv->chnl_ss_fa_count[y];
611 priv->chnl_ss_cca_count[y] = 0;
614 #ifdef ACS_DEBUG_INFO//for debug
616 for (y=ch_begin; y<ch_end; y++)
617 printk("2. after 20M check: chnl[%d] score[%d]\n",priv->available_chnl[y], score[y]);
621 for (y=ch_begin; y<ch_end; y++) {
622 if (priv->chnl_ss_mac_rx_count_40M[y]) {
623 score[y] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
624 if (priv->chnl_ss_mac_rx_count_40M[y] > 30)
626 if( priv->chnl_ss_mac_rx_count_40M[y] > MAC_RX_COUNT_THRESHOLD )
629 #ifdef RTK_5G_SUPPORT
630 if (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)
633 if ((int)(y-6) >= (int)ch_begin)
634 score[y-6] += 1 * priv->chnl_ss_mac_rx_count_40M[y];
635 if ((int)(y-5) >= (int)ch_begin)
636 score[y-5] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
637 if ((int)(y-4) >= (int)ch_begin)
638 score[y-4] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
639 if ((int)(y-3) >= (int)ch_begin)
640 score[y-3] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
641 if ((int)(y-2) >= (int)ch_begin)
642 score[y-2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2;
643 if ((int)(y-1) >= (int)ch_begin)
644 score[y-1] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
645 if ((int)(y+1) < (int)ch_end)
646 score[y+1] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
647 if ((int)(y+2) < (int)ch_end)
648 score[y+2] += (5 * priv->chnl_ss_mac_rx_count_40M[y])/2;
649 if ((int)(y+3) < (int)ch_end)
650 score[y+3] += 5 * priv->chnl_ss_mac_rx_count_40M[y];
651 if ((int)(y+4) < (int)ch_end)
652 score[y+4] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
653 if ((int)(y+5) < (int)ch_end)
654 score[y+5] += 4 * priv->chnl_ss_mac_rx_count_40M[y];
655 if ((int)(y+6) < (int)ch_end)
656 score[y+6] += 1 * priv->chnl_ss_mac_rx_count_40M[y];
661 #ifdef ACS_DEBUG_INFO//for debug
663 for (y=ch_begin; y<ch_end; y++)
664 printk("3. after 40M check: chnl[%d] score[%d]\n",priv->available_chnl[y], score[y]);
666 printk("4. do_ap_check=%d traffic_check=%d\n", do_ap_check, traffic_check);
670 if( traffic_check == 0)
671 fa_count_weighting = 5;
673 fa_count_weighting = 1;
675 for (y=ch_begin; y<ch_end; y++) {
676 score[y] += fa_count_weighting * priv->chnl_ss_fa_count[y];
679 #ifdef ACS_DEBUG_INFO//for debug
681 for (y=ch_begin; y<ch_end; y++)
682 printk("5. after fa check: chnl[%d] score[%d]\n",priv->available_chnl[y], score[y]);
687 for (i=0; i<priv->site_survey->count; i++) {
688 pBss = &priv->site_survey->bss[i];
689 for (y=ch_begin; y<ch_end; y++) {
690 if (pBss->channel == priv->available_chnl[y]) {
691 if (pBss->channel <= 14) {
692 #ifdef ACS_DEBUG_INFO//for debug
694 printk("chnl[%d] has ap rssi=%d bw[0x%02x]\n",
695 pBss->channel, pBss->rssi, pBss->t_stamp[1]);
700 else if (pBss->rssi > 35)
705 if ((pBss->t_stamp[1] & 0x6) == 0) {
706 score[y] += 50 * ap_ratio;
707 if ((int)(y-4) >= (int)ch_begin)
708 score[y-4] += 10 * ap_ratio;
709 if ((int)(y-3) >= (int)ch_begin)
710 score[y-3] += 20 * ap_ratio;
711 if ((int)(y-2) >= (int)ch_begin)
712 score[y-2] += 30 * ap_ratio;
713 if ((int)(y-1) >= (int)ch_begin)
714 score[y-1] += 40 * ap_ratio;
715 if ((int)(y+1) < (int)ch_end)
716 score[y+1] += 40 * ap_ratio;
717 if ((int)(y+2) < (int)ch_end)
718 score[y+2] += 30 * ap_ratio;
719 if ((int)(y+3) < (int)ch_end)
720 score[y+3] += 20 * ap_ratio;
721 if ((int)(y+4) < (int)ch_end)
722 score[y+4] += 10 * ap_ratio;
724 else if ((pBss->t_stamp[1] & 0x4) == 0) {
725 score[y] += 50 * ap_ratio;
726 if ((int)(y-3) >= (int)ch_begin)
727 score[y-3] += 20 * ap_ratio;
728 if ((int)(y-2) >= (int)ch_begin)
729 score[y-2] += 30 * ap_ratio;
730 if ((int)(y-1) >= (int)ch_begin)
731 score[y-1] += 40 * ap_ratio;
732 if ((int)(y+1) < (int)ch_end)
733 score[y+1] += 50 * ap_ratio;
734 if ((int)(y+2) < (int)ch_end)
735 score[y+2] += 50 * ap_ratio;
736 if ((int)(y+3) < (int)ch_end)
737 score[y+3] += 50 * ap_ratio;
738 if ((int)(y+4) < (int)ch_end)
739 score[y+4] += 50 * ap_ratio;
740 if ((int)(y+5) < (int)ch_end)
741 score[y+5] += 40 * ap_ratio;
742 if ((int)(y+6) < (int)ch_end)
743 score[y+6] += 30 * ap_ratio;
744 if ((int)(y+7) < (int)ch_end)
745 score[y+7] += 20 * ap_ratio;
748 score[y] += 50 * ap_ratio;
749 if ((int)(y-7) >= (int)ch_begin)
750 score[y-7] += 20 * ap_ratio;
751 if ((int)(y-6) >= (int)ch_begin)
752 score[y-6] += 30 * ap_ratio;
753 if ((int)(y-5) >= (int)ch_begin)
754 score[y-5] += 40 * ap_ratio;
755 if ((int)(y-4) >= (int)ch_begin)
756 score[y-4] += 50 * ap_ratio;
757 if ((int)(y-3) >= (int)ch_begin)
758 score[y-3] += 50 * ap_ratio;
759 if ((int)(y-2) >= (int)ch_begin)
760 score[y-2] += 50 * ap_ratio;
761 if ((int)(y-1) >= (int)ch_begin)
762 score[y-1] += 50 * ap_ratio;
763 if ((int)(y+1) < (int)ch_end)
764 score[y+1] += 40 * ap_ratio;
765 if ((int)(y+2) < (int)ch_end)
766 score[y+2] += 30 * ap_ratio;
767 if ((int)(y+3) < (int)ch_end)
768 score[y+3] += 20 * ap_ratio;
772 if ((pBss->t_stamp[1] & 0x6) == 0) {
775 else if ((pBss->t_stamp[1] & 0x4) == 0) {
777 if ((int)(y+1) < (int)ch_end)
782 if ((int)(y-1) >= (int)ch_begin)
792 #ifdef ACS_DEBUG_INFO//for debug
794 for (y=ch_begin; y<ch_end; y++)
795 printk("6. after ap check: chnl[%d]:%d\n", priv->available_chnl[y],score[y]);
799 #ifdef SS_CH_LOAD_PROC
801 // caculate noise level -- suggested by wilson
802 for (y=ch_begin; y<ch_end; y++) {
803 int fa_lv=0, cca_lv=0;
804 if (priv->chnl_ss_fa_count[y]>1000) {
806 } else if (priv->chnl_ss_fa_count[y]>500) {
807 fa_lv = 34 * (priv->chnl_ss_fa_count[y]-500) / 500 + 66;
808 } else if (priv->chnl_ss_fa_count[y]>200) {
809 fa_lv = 33 * (priv->chnl_ss_fa_count[y] - 200) / 300 + 33;
810 } else if (priv->chnl_ss_fa_count[y]>100) {
811 fa_lv = 18 * (priv->chnl_ss_fa_count[y] - 100) / 100 + 15;
813 fa_lv = 15 * priv->chnl_ss_fa_count[y] / 100;
815 if (priv->chnl_ss_cca_count[y]>400) {
817 } else if (priv->chnl_ss_cca_count[y]>200) {
818 cca_lv = 34 * (priv->chnl_ss_cca_count[y] - 200) / 200 + 66;
819 } else if (priv->chnl_ss_cca_count[y]>80) {
820 cca_lv = 33 * (priv->chnl_ss_cca_count[y] - 80) / 120 + 33;
821 } else if (priv->chnl_ss_cca_count[y]>40) {
822 cca_lv = 18 * (priv->chnl_ss_cca_count[y] - 40) / 40 + 15;
824 cca_lv = 15 * priv->chnl_ss_cca_count[y] / 40;
827 priv->chnl_ss_load[y] = (((fa_lv > cca_lv)? fa_lv : cca_lv)*75+((score[y]>100)?100:score[y])*25)/100;
829 DEBUG_INFO("ch:%d f=%d (%d), c=%d (%d), fl=%d, cl=%d, sc=%d, cu=%d\n",
830 priv->available_chnl[y],
831 priv->chnl_ss_fa_count[y], fa_thd,
832 priv->chnl_ss_cca_count[y], cca_thd,
836 priv->chnl_ss_load[y]);
846 // heavy weighted DFS channel
847 if (idx_5G_begin >= 0){
848 for (i=idx_5G_begin; i<priv->available_chnl_num; i++) {
849 if (!priv->pmib->dot11DFSEntry.disable_DFS && is_DFS_channel(priv->available_chnl[i])
850 && (score[i]!= 0xffffffff)){
858 //prevent Auto Channel selecting wrong channel in 40M mode-----------------
859 if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N)
860 && priv->pshare->is_40m_bw) {
862 if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 1) {
863 //Upper Primary Channel, cannot select the two lowest channels
864 if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) {
865 score[0] = 0xffffffff;
866 score[1] = 0xffffffff;
867 score[2] = 0xffffffff;
868 score[3] = 0xffffffff;
869 score[4] = 0xffffffff;
871 score[13] = 0xffffffff;
872 score[12] = 0xffffffff;
873 score[11] = 0xffffffff;
876 // if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) {
877 // score[idx_5G_begin] = 0xffffffff;
878 // score[idx_5G_begin + 1] = 0xffffffff;
881 else if (GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset == 2) {
882 //Lower Primary Channel, cannot select the two highest channels
883 if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) {
884 score[0] = 0xffffffff;
885 score[1] = 0xffffffff;
886 score[2] = 0xffffffff;
888 score[13] = 0xffffffff;
889 score[12] = 0xffffffff;
890 score[11] = 0xffffffff;
891 score[10] = 0xffffffff;
892 score[9] = 0xffffffff;
895 // if (priv->pmib->dot11BssType.net_work_type & WIRELESS_11A) {
896 // score[priv->available_chnl_num - 2] = 0xffffffff;
897 // score[priv->available_chnl_num - 1] = 0xffffffff;
901 for (i=0; i<=idx_2G_end; ++i)
902 if (priv->available_chnl[i] == 14)
903 score[i] = 0xffffffff; // mask chan14
905 #ifdef RTK_5G_SUPPORT
906 if (idx_5G_begin >= 0) {
907 for (i=idx_5G_begin; i<priv->available_chnl_num; i++) {
908 int ch = priv->available_chnl[i];
909 if(priv->available_chnl[i] > 144)
911 if((ch%4) || ch==140 || ch == 164 ) //mask ch 140, ch 165, ch 184...
912 score[i] = 0xffffffff;
920 if (priv->pmib->dot11RFEntry.disable_ch1213) {
921 for (i=0; i<=idx_2G_end; ++i) {
922 int ch = priv->available_chnl[i];
923 if ((ch == 12) || (ch == 13))
924 score[i] = 0xffffffff;
928 if (((priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_GLOBAL) ||
929 (priv->pmib->dot11StationConfigEntry.dot11RegDomain == DOMAIN_WORLD_WIDE)) &&
930 (idx_2G_end >= 11) && (idx_2G_end < 14)) {
931 score[13] = 0xffffffff; // mask chan14
932 score[12] = 0xffffffff; // mask chan13
933 score[11] = 0xffffffff; // mask chan12
936 //------------------------------------------------------------------
938 #ifdef _DEBUG_RTL8192CD_
939 for (i=0; i<priv->available_chnl_num; i++) {
940 len += sprintf(tmpbuf+len, "ch%d:%u ", priv->available_chnl[i], score[i]);
942 strcat(tmpbuf, "\n");
943 panic_printk("%s", tmpbuf);
947 if ( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G)
948 && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80))
950 for (i=0; i<priv->available_chnl_num; i++) {
951 if (is80MChannel(priv->available_chnl, priv->available_chnl_num, priv->available_chnl[i])) {
953 for (j=0; j<4; j++) {
954 if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff))
955 tmpScore += score[i+j];
957 tmpScore = 0xffffffff;
959 tmpScore = tmpScore / 4;
960 if (minScore > tmpScore) {
963 tmpScore = 0xffffffff;
964 for (j=0; j<4; j++) {
965 if (score[i+j] < tmpScore) {
966 tmpScore = score[i+j];
976 if (minScore == 0xffffffff) {
977 // there is no 80M channels
978 priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20;
979 for (i=0; i<priv->available_chnl_num; i++) {
980 if (score[i] < minScore) {
987 else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G)
988 && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40))
990 for (i=0; i<priv->available_chnl_num; i++) {
991 if(is40MChannel(priv->available_chnl,priv->available_chnl_num,priv->available_chnl[i])) {
994 if ((tmpScore != 0xffffffff) && (score[i+j] != 0xffffffff))
995 tmpScore += score[i+j];
997 tmpScore = 0xffffffff;
999 tmpScore = tmpScore / 2;
1000 if(minScore > tmpScore) {
1001 minScore = tmpScore;
1003 tmpScore = 0xffffffff;
1004 for (j=0; j<2; j++) {
1005 if (score[i+j] < tmpScore) {
1006 tmpScore = score[i+j];
1016 if (minScore == 0xffffffff) {
1017 // there is no 40M channels
1018 priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20;
1019 for (i=0; i<priv->available_chnl_num; i++) {
1020 if (score[i] < minScore) {
1021 minScore = score[i];
1027 else if( (priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_2G)
1028 && (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)
1029 && (priv->available_chnl_num >= 8) )
1031 u4Byte groupScore[14];
1033 memset(groupScore, 0xff , sizeof(groupScore));
1034 for (i=0; i<priv->available_chnl_num-4; i++) {
1035 if (score[i] != 0xffffffff && score[i+4] != 0xffffffff) {
1036 groupScore[i] = score[i] + score[i+4];
1037 DEBUG_INFO("groupScore, ch %d,%d: %d\n", i+1, i+5, groupScore[i]);
1038 if (groupScore[i] < minScore) {
1039 #ifdef AUTOCH_SS_SPEEDUP
1040 if(priv->pmib->miscEntry.autoch_1611_enable)
1042 if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11)
1044 minScore = groupScore[i];
1051 minScore = groupScore[i];
1058 if (score[idx] < score[idx+4]) {
1059 GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE;
1060 priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE;
1063 GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW;
1064 priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW;
1069 for (i=0; i<priv->available_chnl_num; i++) {
1070 if (score[i] < minScore) {
1071 #ifdef AUTOCH_SS_SPEEDUP
1072 if(priv->pmib->miscEntry.autoch_1611_enable)
1074 if(priv->available_chnl[i]==1 || priv->available_chnl[i]==6 || priv->available_chnl[i]==11)
1076 minScore = score[i];
1083 minScore = score[i];
1090 if (IS_A_CUT_8881A(priv) &&
1091 (priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)) {
1092 if ((priv->available_chnl[idx] == 36) ||
1093 (priv->available_chnl[idx] == 52) ||
1094 (priv->available_chnl[idx] == 100) ||
1095 (priv->available_chnl[idx] == 116) ||
1096 (priv->available_chnl[idx] == 132) ||
1097 (priv->available_chnl[idx] == 149) ||
1098 (priv->available_chnl[idx] == 165))
1100 else if ((priv->available_chnl[idx] == 48) ||
1101 (priv->available_chnl[idx] == 64) ||
1102 (priv->available_chnl[idx] == 112) ||
1103 (priv->available_chnl[idx] == 128) ||
1104 (priv->available_chnl[idx] == 144) ||
1105 (priv->available_chnl[idx] == 161) ||
1106 (priv->available_chnl[idx] == 177))
1110 minChan = priv->available_chnl[idx];
1112 // skip channel 14 if don't support ofdm
1113 if ((priv->pmib->dot11RFEntry.disable_ch14_ofdm) &&
1115 score[idx] = 0xffffffff;
1117 minScore = 0xffffffff;
1118 for (i=0; i<priv->available_chnl_num; i++) {
1119 if (score[i] < minScore) {
1120 minScore = score[i];
1124 minChan = priv->available_chnl[idx];
1128 //Check if selected channel available for 80M/40M BW or NOT ?
1129 if(priv->pmib->dot11RFEntry.phyBandSelect == PHY_BAND_5G)
1131 if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_80)
1133 if(!is80MChannel(priv->available_chnl,priv->available_chnl_num,minChan))
1135 //printk("BW=80M, selected channel = %d is unavaliable! reduce to 40M\n", minChan);
1136 //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20_40;
1137 priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20_40;
1141 if(priv->pmib->dot11nConfigEntry.dot11nUse40M == HT_CHANNEL_WIDTH_20_40)
1143 if(!is40MChannel(priv->available_chnl,priv->available_chnl_num,minChan))
1145 //printk("BW=40M, selected channel = %d is unavaliable! reduce to 20M\n", minChan);
1146 //priv->pmib->dot11nConfigEntry.dot11nUse40M = HT_CHANNEL_WIDTH_20;
1147 priv->pshare->is_40m_bw = HT_CHANNEL_WIDTH_20;
1153 #ifdef CONFIG_RTL_NEW_AUTOCH
1154 RTL_W32(RXERR_RPT, RXERR_RPT_RST);
1157 // auto adjust contro-sideband
1158 if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N)
1159 && (priv->pshare->is_40m_bw ==1 || priv->pshare->is_40m_bw ==2)) {
1161 #ifdef RTK_5G_SUPPORT
1162 if (priv->pmib->dot11RFEntry.phyBandSelect & PHY_BAND_5G) {
1163 if( (minChan>144) ? ((minChan-1)%8) : (minChan%8)) {
1164 GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE;
1165 priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE;
1167 GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW;
1168 priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW;
1175 #ifdef CONFIG_RTL_NEW_AUTOCH
1176 unsigned int ch_max;
1178 if (priv->available_chnl[idx_2G_end] >= 13)
1181 ch_max = priv->available_chnl[idx_2G_end];
1183 if ((minChan >= 5) && (minChan <= (ch_max-5))) {
1184 if (score[minChan+4] > score[minChan-4]) { // what if some channels were cancelled?
1185 GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW;
1186 priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW;
1188 GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE;
1189 priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE;
1195 GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_ABOVE;
1196 priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_ABOVE;
1198 else if (minChan > 7) {
1199 GET_MIB(priv)->dot11nConfigEntry.dot11n2ndChOffset = HT_2NDCH_OFFSET_BELOW;
1200 priv->pshare->offset_2nd_chan = HT_2NDCH_OFFSET_BELOW;
1206 //-----------------------
1208 #if defined(__ECOS) && defined(CONFIG_SDIO_HCI)
1209 panic_printk("Auto channel choose ch:%d\n", minChan);
1211 #ifdef _DEBUG_RTL8192CD_
1212 panic_printk("Auto channel choose ch:%d\n", minChan);
1215 #ifdef ACS_DEBUG_INFO//for debug
1216 printk("7. minChan:%d 2nd_offset:%d\n", minChan, priv->pshare->offset_2nd_chan);
1228 IN u2Byte sampleNum /*unit : 4us*/
1231 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
1233 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
1234 ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_TIME_PERIOD_11AC, bMaskLWord, sampleNum); /*4us sample 1 time*/
1235 ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT8, 0x1); /*Enable CCX for CLM*/
1236 } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
1237 ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_TIME_PERIOD_11N, bMaskLWord, sampleNum); /*4us sample 1 time*/
1238 ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT8, 0x1); /*Enable CCX for CLM*/
1241 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[%s] : CLM sampleNum = %d\n", __func__, sampleNum));
1250 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
1252 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) {
1253 ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x0); /*Trigger CLM*/
1254 ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11AC, BIT0, 0x1);
1255 } else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES) {
1256 ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x0); /*Trigger CLM*/
1257 ODM_SetBBReg(pDM_Odm, ODM_REG_CLM_11N, BIT0, 0x1);
1262 phydm_checkCLMready(
1266 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
1268 BOOLEAN ret = FALSE;
1270 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
1271 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*make sure CLM calc is ready*/
1272 else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
1273 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_READY_11N, bMaskDWord); /*make sure CLM calc is ready*/
1275 if (value32 & BIT16)
1280 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[%s] : CLM ready = %d\n", __func__, ret));
1290 PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;
1294 if (pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
1295 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11AC, bMaskDWord); /*read CLM calc result*/
1296 else if (pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
1297 value32 = ODM_GetBBReg(pDM_Odm, ODM_REG_CLM_RESULT_11N, bMaskDWord); /*read CLM calc result*/
1299 results = (u2Byte)(value32 & bMaskLWord);
1301 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ACS, ODM_DBG_LOUD, ("[%s] : CLM result = %d\n", __func__, results));
1304 /*results are number of CCA times in sampleNum*/