rtl8821ce/core/rtw_mp.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2017 Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  *****************************************************************************/
  15 #define _RTW_MP_C_
  16 #include <drv_types.h>
  17 #ifdef PLATFORM_FREEBSD
  18         #include <sys/unistd.h>         /* for RFHIGHPID */
  19 #endif
  20
  21 #include "../hal/phydm/phydm_precomp.h"
  22 #if defined(CONFIG_RTL8723B) || defined(CONFIG_RTL8821A)
  23         #include <rtw_bt_mp.h>
  24 #endif
  25
  26 #ifdef CONFIG_MP_VHT_HW_TX_MODE
  27 #define CEILING_POS(X) ((X - (int)(X)) > 0 ? (int)(X + 1) : (int)(X))
  28 #define CEILING_NEG(X) ((X - (int)(X)) < 0 ? (int)(X - 1) : (int)(X))
  29 #define ceil(X) (((X) > 0) ? CEILING_POS(X) : CEILING_NEG(X))
  30
  31 int rtfloor(float x)
  32 {
  33         int i = x - 2;
  34         while
  35         (++i <= x - 1)
  36                 ;
  37         return i;
  38 }
  39 #endif
  40
  41 #ifdef CONFIG_MP_INCLUDED
  42 u32 read_macreg(_adapter *padapter, u32 addr, u32 sz)
  43 {
  44         u32 val = 0;
  45
  46         switch (sz) {
  47         case 1:
  48                 val = rtw_read8(padapter, addr);
  49                 break;
  50         case 2:
  51                 val = rtw_read16(padapter, addr);
  52                 break;
  53         case 4:
  54                 val = rtw_read32(padapter, addr);
  55                 break;
  56         default:
  57                 val = 0xffffffff;
  58                 break;
  59         }
  60
  61         return val;
  62
  63 }
  64
  65 void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz)
  66 {
  67         switch (sz) {
  68         case 1:
  69                 rtw_write8(padapter, addr, (u8)val);
  70                 break;
  71         case 2:
  72                 rtw_write16(padapter, addr, (u16)val);
  73                 break;
  74         case 4:
  75                 rtw_write32(padapter, addr, val);
  76                 break;
  77         default:
  78                 break;
  79         }
  80
  81 }
  82
  83 u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask)
  84 {
  85         return rtw_hal_read_bbreg(padapter, addr, bitmask);
  86 }
  87
  88 void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val)
  89 {
  90         rtw_hal_write_bbreg(padapter, addr, bitmask, val);
  91 }
  92
  93 u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask)
  94 {
  95         return rtw_hal_read_rfreg(padapter, rfpath, addr, bitmask);
  96 }
  97
  98 void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val)
  99 {
 100         rtw_hal_write_rfreg(padapter, rfpath, addr, bitmask, val);
 101 }
 102
 103 u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr)
 104 {
 105         return _read_rfreg(padapter, rfpath, addr, bRFRegOffsetMask);
 106 }
 107
 108 void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val)
 109 {
 110         _write_rfreg(padapter, rfpath, addr, bRFRegOffsetMask, val);
 111 }
 112
 113 static void _init_mp_priv_(struct mp_priv *pmp_priv)
 114 {
 115         WLAN_BSSID_EX *pnetwork;
 116
 117         _rtw_memset(pmp_priv, 0, sizeof(struct mp_priv));
 118
 119         pmp_priv->mode = MP_OFF;
 120
 121         pmp_priv->channel = 1;
 122         pmp_priv->bandwidth = CHANNEL_WIDTH_20;
 123         pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
 124         pmp_priv->rateidx = RATE_1M;
 125         pmp_priv->txpoweridx = 0x2A;
 126
 127         pmp_priv->antenna_tx = ANTENNA_A;
 128         pmp_priv->antenna_rx = ANTENNA_AB;
 129
 130         pmp_priv->check_mp_pkt = 0;
 131
 132         pmp_priv->tx_pktcount = 0;
 133
 134         pmp_priv->rx_bssidpktcount = 0;
 135         pmp_priv->rx_pktcount = 0;
 136         pmp_priv->rx_crcerrpktcount = 0;
 137
 138         pmp_priv->network_macaddr[0] = 0x00;
 139         pmp_priv->network_macaddr[1] = 0xE0;
 140         pmp_priv->network_macaddr[2] = 0x4C;
 141         pmp_priv->network_macaddr[3] = 0x87;
 142         pmp_priv->network_macaddr[4] = 0x66;
 143         pmp_priv->network_macaddr[5] = 0x55;
 144
 145         pmp_priv->bSetRxBssid = _FALSE;
 146         pmp_priv->bRTWSmbCfg = _FALSE;
 147         pmp_priv->bloopback = _FALSE;
 148
 149         pmp_priv->bloadefusemap = _FALSE;
 150         pmp_priv->brx_filter_beacon = _FALSE;
 151
 152         pnetwork = &pmp_priv->mp_network.network;
 153         _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN);
 154
 155         pnetwork->Ssid.SsidLength = 8;
 156         _rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength);
 157
 158         pmp_priv->tx.payload = 2;
 159 #ifdef CONFIG_80211N_HT
 160         pmp_priv->tx.attrib.ht_en = 1;
 161 #endif
 162
 163         pmp_priv->mpt_ctx.mpt_rate_index = 1;
 164
 165 }
 166
 167 #ifdef PLATFORM_WINDOWS
 168 #if 0
 169 void mp_wi_callback(
 170         IN NDIS_WORK_ITEM       *pwk_item,
 171         IN PVOID                        cntx
 172 )
 173 {
 174         _adapter *padapter = (_adapter *)cntx;
 175         struct mp_priv *pmppriv = &padapter->mppriv;
 176         struct mp_wi_cntx       *pmp_wi_cntx = &pmppriv->wi_cntx;
 177
 178         /*  Execute specified action. */
 179         if (pmp_wi_cntx->curractfunc != NULL) {
 180                 LARGE_INTEGER   cur_time;
 181                 ULONGLONG start_time, end_time;
 182                 NdisGetCurrentSystemTime(&cur_time);    /*  driver version */
 183                 start_time = cur_time.QuadPart / 10; /*  The return value is in microsecond */
 184
 185                 pmp_wi_cntx->curractfunc(padapter);
 186
 187                 NdisGetCurrentSystemTime(&cur_time);    /*  driver version */
 188                 end_time = cur_time.QuadPart / 10; /*  The return value is in microsecond */
 189
 190         }
 191
 192         NdisAcquireSpinLock(&(pmp_wi_cntx->mp_wi_lock));
 193         pmp_wi_cntx->bmp_wi_progress = _FALSE;
 194         NdisReleaseSpinLock(&(pmp_wi_cntx->mp_wi_lock));
 195
 196         if (pmp_wi_cntx->bmpdrv_unload)
 197                 NdisSetEvent(&(pmp_wi_cntx->mp_wi_evt));
 198
 199 }
 200 #endif
 201
 202 static int init_mp_priv_by_os(struct mp_priv *pmp_priv)
 203 {
 204         struct mp_wi_cntx *pmp_wi_cntx;
 205
 206         if (pmp_priv == NULL)
 207                 return _FAIL;
 208
 209         pmp_priv->rx_testcnt = 0;
 210         pmp_priv->rx_testcnt1 = 0;
 211         pmp_priv->rx_testcnt2 = 0;
 212
 213         pmp_priv->tx_testcnt = 0;
 214         pmp_priv->tx_testcnt1 = 0;
 215
 216         pmp_wi_cntx = &pmp_priv->wi_cntx
 217                       pmp_wi_cntx->bmpdrv_unload = _FALSE;
 218         pmp_wi_cntx->bmp_wi_progress = _FALSE;
 219         pmp_wi_cntx->curractfunc = NULL;
 220
 221         return _SUCCESS;
 222 }
 223 #endif
 224
 225 #ifdef PLATFORM_LINUX
 226 #if 0
 227 static int init_mp_priv_by_os(struct mp_priv *pmp_priv)
 228 {
 229         int i, res;
 230         struct mp_xmit_frame *pmp_xmitframe;
 231
 232         if (pmp_priv == NULL)
 233                 return _FAIL;
 234
 235         _rtw_init_queue(&pmp_priv->free_mp_xmitqueue);
 236
 237         pmp_priv->pallocated_mp_xmitframe_buf = NULL;
 238         pmp_priv->pallocated_mp_xmitframe_buf = rtw_zmalloc(NR_MP_XMITFRAME * sizeof(struct mp_xmit_frame) + 4);
 239         if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) {
 240                 res = _FAIL;
 241                 goto _exit_init_mp_priv;
 242         }
 243
 244         pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf + 4 - ((SIZE_PTR)(pmp_priv->pallocated_mp_xmitframe_buf) & 3);
 245
 246         pmp_xmitframe = (struct mp_xmit_frame *)pmp_priv->pmp_xmtframe_buf;
 247
 248         for (i = 0; i < NR_MP_XMITFRAME; i++) {
 249                 _rtw_init_listhead(&pmp_xmitframe->list);
 250                 rtw_list_insert_tail(&pmp_xmitframe->list, &pmp_priv->free_mp_xmitqueue.queue);
 251
 252                 pmp_xmitframe->pkt = NULL;
 253                 pmp_xmitframe->frame_tag = MP_FRAMETAG;
 254                 pmp_xmitframe->padapter = pmp_priv->papdater;
 255
 256                 pmp_xmitframe++;
 257         }
 258
 259         pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME;
 260
 261         res = _SUCCESS;
 262
 263 _exit_init_mp_priv:
 264
 265         return res;
 266 }
 267 #endif
 268 #endif
 269
 270 static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter)
 271 {
 272         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
 273
 274         struct pkt_attrib *pattrib;
 275
 276         /* init xmitframe attribute */
 277         pattrib = &pmptx->attrib;
 278         _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib));
 279         _rtw_memset(pmptx->desc, 0, TXDESC_SIZE);
 280
 281         pattrib->ether_type = 0x8712;
 282 #if 0
 283         _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
 284         _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
 285 #endif
 286         _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN);
 287
 288         /*      pattrib->dhcp_pkt = 0;
 289          *      pattrib->pktlen = 0; */
 290         pattrib->ack_policy = 0;
 291         /*      pattrib->pkt_hdrlen = ETH_HLEN; */
 292         pattrib->hdrlen = WLAN_HDR_A3_LEN;
 293         pattrib->subtype = WIFI_DATA;
 294         pattrib->priority = 0;
 295         pattrib->qsel = pattrib->priority;
 296         /*      do_queue_select(padapter, pattrib); */
 297         pattrib->nr_frags = 1;
 298         pattrib->encrypt = 0;
 299         pattrib->bswenc = _FALSE;
 300         pattrib->qos_en = _FALSE;
 301
 302         pattrib->pktlen = 1500;
 303
 304         if (pHalData->rf_type == RF_2T2R)
 305                 pattrib->raid = RATEID_IDX_BGN_40M_2SS;
 306         else
 307                 pattrib->raid = RATEID_IDX_BGN_40M_1SS;
 308
 309 #ifdef CONFIG_80211AC_VHT
 310         if (pHalData->rf_type == RF_1T1R)
 311                 pattrib->raid = RATEID_IDX_VHT_1SS;
 312         else if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_2T4R)
 313                 pattrib->raid = RATEID_IDX_VHT_2SS;
 314         else if (pHalData->rf_type == RF_3T3R)
 315                 pattrib->raid = RATEID_IDX_VHT_3SS;
 316         else
 317                 pattrib->raid = RATEID_IDX_BGN_40M_1SS;
 318 #endif
 319 }
 320
 321 s32 init_mp_priv(PADAPTER padapter)
 322 {
 323         struct mp_priv *pmppriv = &padapter->mppriv;
 324         PHAL_DATA_TYPE pHalData;
 325
 326         pHalData = GET_HAL_DATA(padapter);
 327
 328         _init_mp_priv_(pmppriv);
 329         pmppriv->papdater = padapter;
 330         pmppriv->mp_dm = 0;
 331         pmppriv->tx.stop = 1;
 332         pmppriv->bSetTxPower = 0;               /*for  manually set tx power*/
 333         pmppriv->bTxBufCkFail = _FALSE;
 334         pmppriv->pktInterval = 0;
 335         pmppriv->pktLength = 1000;
 336
 337         mp_init_xmit_attrib(&pmppriv->tx, padapter);
 338
 339         switch (padapter->registrypriv.rf_config) {
 340         case RF_1T1R:
 341                 pmppriv->antenna_tx = ANTENNA_A;
 342                 pmppriv->antenna_rx = ANTENNA_A;
 343                 break;
 344         case RF_1T2R:
 345         default:
 346                 pmppriv->antenna_tx = ANTENNA_A;
 347                 pmppriv->antenna_rx = ANTENNA_AB;
 348                 break;
 349         case RF_2T2R:
 350                 pmppriv->antenna_tx = ANTENNA_AB;
 351                 pmppriv->antenna_rx = ANTENNA_AB;
 352                 break;
 353         case RF_2T4R:
 354                 pmppriv->antenna_tx = ANTENNA_BC;
 355                 pmppriv->antenna_rx = ANTENNA_ABCD;
 356                 break;
 357         }
 358
 359         pHalData->AntennaRxPath = pmppriv->antenna_rx;
 360         pHalData->antenna_tx_path = pmppriv->antenna_tx;
 361
 362         return _SUCCESS;
 363 }
 364
 365 void free_mp_priv(struct mp_priv *pmp_priv)
 366 {
 367         if (pmp_priv->pallocated_mp_xmitframe_buf) {
 368                 rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0);
 369                 pmp_priv->pallocated_mp_xmitframe_buf = NULL;
 370         }
 371         pmp_priv->pmp_xmtframe_buf = NULL;
 372 }
 373
 374 #if 0
 375 static VOID PHY_IQCalibrate_default(
 376         IN      PADAPTER        pAdapter,
 377         IN      BOOLEAN bReCovery
 378 )
 379 {
 380         RTW_INFO("%s\n", __func__);
 381 }
 382
 383 static VOID PHY_LCCalibrate_default(
 384         IN      PADAPTER        pAdapter
 385 )
 386 {
 387         RTW_INFO("%s\n", __func__);
 388 }
 389
 390 static VOID PHY_SetRFPathSwitch_default(
 391         IN      PADAPTER        pAdapter,
 392         IN      BOOLEAN         bMain
 393 )
 394 {
 395         RTW_INFO("%s\n", __func__);
 396 }
 397 #endif
 398
 399 void mpt_InitHWConfig(PADAPTER Adapter)
 400 {
 401         PHAL_DATA_TYPE hal;
 402
 403         hal = GET_HAL_DATA(Adapter);
 404
 405         if (IS_HARDWARE_TYPE_8723B(Adapter)) {
 406                 /* TODO: <20130114, Kordan> The following setting is only for DPDT and Fixed board type. */
 407                 /* TODO:  A better solution is configure it according EFUSE during the run-time. */
 408
 409                 phy_set_mac_reg(Adapter, 0x64, BIT20, 0x0);             /* 0x66[4]=0             */
 410                 phy_set_mac_reg(Adapter, 0x64, BIT24, 0x0);             /* 0x66[8]=0 */
 411                 phy_set_mac_reg(Adapter, 0x40, BIT4, 0x0);              /* 0x40[4]=0             */
 412                 phy_set_mac_reg(Adapter, 0x40, BIT3, 0x1);              /* 0x40[3]=1             */
 413                 phy_set_mac_reg(Adapter, 0x4C, BIT24, 0x1);             /* 0x4C[24:23]=10 */
 414                 phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0);             /* 0x4C[24:23]=10 */
 415                 phy_set_bb_reg(Adapter, 0x944, BIT1 | BIT0, 0x3);       /* 0x944[1:0]=11         */
 416                 phy_set_bb_reg(Adapter, 0x930, bMaskByte0, 0x77);/* 0x930[7:0]=77         */
 417                 phy_set_mac_reg(Adapter, 0x38, BIT11, 0x1);/* 0x38[11]=1 */
 418
 419                 /* TODO: <20130206, Kordan> The default setting is wrong, hard-coded here. */
 420                 phy_set_mac_reg(Adapter, 0x778, 0x3, 0x3);                                      /* Turn off hardware PTA control (Asked by Scott) */
 421                 phy_set_mac_reg(Adapter, 0x64, bMaskDWord, 0x36000000);/* Fix BT S0/S1 */
 422                 phy_set_mac_reg(Adapter, 0x948, bMaskDWord, 0x0);               /* Fix BT can't Tx */
 423
 424                 /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou) */
 425                 phy_set_bb_reg(Adapter, 0xA00, BIT8, 0x0);                      /*0xA01[0] = 0*/
 426         } else if (IS_HARDWARE_TYPE_8821(Adapter)) {
 427                 /* <20131121, VincentL> Add for 8821AU DPDT setting and fix switching antenna issue (Asked by Rock)
 428                 <20131122, VincentL> Enable for all 8821A/8811AU  (Asked by Alex)*/
 429                 phy_set_mac_reg(Adapter, 0x4C, BIT23, 0x0);             /*0x4C[23:22]=01*/
 430                 phy_set_mac_reg(Adapter, 0x4C, BIT22, 0x1);             /*0x4C[23:22]=01*/
 431         } else if (IS_HARDWARE_TYPE_8188ES(Adapter))
 432                 phy_set_mac_reg(Adapter, 0x4C , BIT23, 0);              /*select DPDT_P and DPDT_N as output pin*/
 433 #ifdef CONFIG_RTL8814A
 434         else if (IS_HARDWARE_TYPE_8814A(Adapter))
 435                 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8814A, 0x2000);
 436 #endif
 437
 438 #ifdef CONFIG_RTL8812A
 439         else if (IS_HARDWARE_TYPE_8812(Adapter)) {
 440                 rtw_write32(Adapter, 0x520, rtw_read32(Adapter, 0x520) | 0x8000);
 441                 rtw_write32(Adapter, 0x524, rtw_read32(Adapter, 0x524) & (~0x800));
 442         }
 443 #endif
 444
 445
 446 #ifdef CONFIG_RTL8822B
 447         else if (IS_HARDWARE_TYPE_8822B(Adapter)) {
 448                 u32 tmp_reg = 0;
 449
 450                 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8822B, 0x2000);
 451                 /* fixed wifi can't 2.4g tx suggest by Szuyitasi 20160504 */
 452                 phy_set_bb_reg(Adapter, 0x70, bMaskByte3, 0x0e);
 453                 RTW_INFO(" 0x73 = 0x%x\n", phy_query_bb_reg(Adapter, 0x70, bMaskByte3));
 454                 phy_set_bb_reg(Adapter, 0x1704, bMaskDWord, 0x0000ff00);
 455                 RTW_INFO(" 0x1704 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1704, bMaskDWord));
 456                 phy_set_bb_reg(Adapter, 0x1700, bMaskDWord, 0xc00f0038);
 457                 RTW_INFO(" 0x1700 = 0x%x\n", phy_query_bb_reg(Adapter, 0x1700, bMaskDWord));
 458         }
 459 #endif /* CONFIG_RTL8822B */
 460 #ifdef CONFIG_RTL8821C
 461         else if (IS_HARDWARE_TYPE_8821C(Adapter))
 462                 PlatformEFIOWrite2Byte(Adapter, REG_RXFLTMAP1_8821C, 0x2000);
 463 #endif /* CONFIG_RTL8821C */
 464 #if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
 465         else if (IS_HARDWARE_TYPE_8188F(Adapter) || IS_HARDWARE_TYPE_8188GTV(Adapter)) {
 466                 if (IS_A_CUT(hal->version_id) || IS_B_CUT(hal->version_id)) {
 467                         RTW_INFO("%s() Active large power detection\n", __func__);
 468                         phy_active_large_power_detection_8188f(&(GET_HAL_DATA(Adapter)->odmpriv));
 469                 }
 470         }
 471 #endif
 472 }
 473
 474 static void PHY_IQCalibrate(PADAPTER padapter, u8 bReCovery)
 475 {
 476         halrf_iqk_trigger(&(GET_HAL_DATA(padapter)->odmpriv), bReCovery);
 477 }
 478
 479 static void PHY_LCCalibrate(PADAPTER padapter)
 480 {
 481         halrf_lck_trigger(&(GET_HAL_DATA(padapter)->odmpriv));
 482 }
 483
 484 static u8 PHY_QueryRFPathSwitch(PADAPTER padapter)
 485 {
 486         u8 bmain = 0;
 487 /*
 488         if (IS_HARDWARE_TYPE_8723B(padapter)) {
 489 #ifdef CONFIG_RTL8723B
 490                 bmain = PHY_QueryRFPathSwitch_8723B(padapter);
 491 #endif
 492         } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
 493 #ifdef CONFIG_RTL8188E
 494                 bmain = PHY_QueryRFPathSwitch_8188E(padapter);
 495 #endif
 496         } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
 497 #ifdef CONFIG_RTL8814A
 498                 bmain = PHY_QueryRFPathSwitch_8814A(padapter);
 499 #endif
 500         } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
 501 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
 502                 bmain = PHY_QueryRFPathSwitch_8812A(padapter);
 503 #endif
 504         } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
 505 #ifdef CONFIG_RTL8192E
 506                 bmain = PHY_QueryRFPathSwitch_8192E(padapter);
 507 #endif
 508         } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
 509 #ifdef CONFIG_RTL8703B
 510                 bmain = PHY_QueryRFPathSwitch_8703B(padapter);
 511 #endif
 512         } else if (IS_HARDWARE_TYPE_8188F(padapter)) {
 513 #ifdef CONFIG_RTL8188F
 514                 bmain = PHY_QueryRFPathSwitch_8188F(padapter);
 515 #endif
 516         } else if (IS_HARDWARE_TYPE_8188GTV(padapter)) {
 517 #ifdef CONFIG_RTL8188GTV
 518                 bmain = PHY_QueryRFPathSwitch_8188GTV(padapter);
 519 #endif
 520         } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
 521 #ifdef CONFIG_RTL8822B
 522                 bmain = PHY_QueryRFPathSwitch_8822B(padapter);
 523 #endif
 524         } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
 525 #ifdef CONFIG_RTL8723D
 526                 bmain = PHY_QueryRFPathSwitch_8723D(padapter);
 527 #endif
 528         } else
 529 */
 530
 531         if (IS_HARDWARE_TYPE_8821C(padapter)) {
 532 #ifdef CONFIG_RTL8821C
 533                 bmain = phy_query_rf_path_switch_8821c(padapter);
 534 #endif
 535         }
 536
 537         return bmain;
 538 }
 539
 540 static void  PHY_SetRFPathSwitch(PADAPTER padapter , BOOLEAN bMain) {
 541
 542         PHAL_DATA_TYPE hal = GET_HAL_DATA(padapter);
 543         struct dm_struct *phydm = &hal->odmpriv;
 544
 545         if (IS_HARDWARE_TYPE_8723B(padapter)) {
 546 #ifdef CONFIG_RTL8723B
 547                 phy_set_rf_path_switch_8723b(phydm, bMain);
 548 #endif
 549         } else if (IS_HARDWARE_TYPE_8188E(padapter)) {
 550 #ifdef CONFIG_RTL8188E
 551                 phy_set_rf_path_switch_8188e(phydm, bMain);
 552 #endif
 553         } else if (IS_HARDWARE_TYPE_8814A(padapter)) {
 554 #ifdef CONFIG_RTL8814A
 555                 phy_set_rf_path_switch_8814a(phydm, bMain);
 556 #endif
 557         } else if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter)) {
 558 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
 559                 phy_set_rf_path_switch_8812a(phydm, bMain);
 560 #endif
 561         } else if (IS_HARDWARE_TYPE_8192E(padapter)) {
 562 #ifdef CONFIG_RTL8192E
 563                 phy_set_rf_path_switch_8192e(phydm, bMain);
 564 #endif
 565         } else if (IS_HARDWARE_TYPE_8703B(padapter)) {
 566 #ifdef CONFIG_RTL8703B
 567                 phy_set_rf_path_switch_8703b(phydm, bMain);
 568 #endif
 569         } else if (IS_HARDWARE_TYPE_8188F(padapter) || IS_HARDWARE_TYPE_8188GTV(padapter)) {
 570 #if defined(CONFIG_RTL8188F) || defined(CONFIG_RTL8188GTV)
 571                 phy_set_rf_path_switch_8188f(phydm, bMain);
 572 #endif
 573         } else if (IS_HARDWARE_TYPE_8192F(padapter)) {
 574 #ifdef CONFIG_RTL8192F
 575                 phy_set_rf_path_switch_8192f(padapter, bMain);
 576 #endif
 577         } else if (IS_HARDWARE_TYPE_8822B(padapter)) {
 578 #ifdef CONFIG_RTL8822B
 579                 phy_set_rf_path_switch_8822b(phydm, bMain);
 580 #endif
 581         } else if (IS_HARDWARE_TYPE_8723D(padapter)) {
 582 #ifdef CONFIG_RTL8723D
 583                 phy_set_rf_path_switch_8723d(phydm, bMain);
 584 #endif
 585         } else if (IS_HARDWARE_TYPE_8821C(padapter)) {
 586 #ifdef CONFIG_RTL8821C
 587                 phy_set_rf_path_switch_8821c(phydm, bMain);
 588 #endif
 589         }
 590 }
 591
 592
 593 static void phy_switch_rf_path_set(PADAPTER padapter , u8 *prf_set_State) {
 594 #ifdef CONFIG_RTL8821C
 595         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
 596         struct dm_struct *p_dm = &pHalData->odmpriv;
 597
 598         if (IS_HARDWARE_TYPE_8821C(padapter)) {
 599                 config_phydm_set_ant_path(p_dm, *prf_set_State, p_dm->current_ant_num_8821c);
 600                 /* Do IQK when switching to BTG/WLG, requested by RF Binson */
 601                 if (*prf_set_State == SWITCH_TO_BTG || *prf_set_State == SWITCH_TO_WLG)
 602                         PHY_IQCalibrate(padapter, FALSE);
 603         }
 604 #endif
 605
 606 }
 607
 608
 609 #ifdef CONFIG_ANTENNA_DIVERSITY
 610 u8 rtw_mp_set_antdiv(PADAPTER padapter, BOOLEAN bMain)
 611 {
 612         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter);
 613         u8 cur_ant, change_ant;
 614
 615         if (!pHalData->AntDivCfg)
 616                 return _FALSE;
 617         /*rtw_hal_get_odm_var(padapter, HAL_ODM_ANTDIV_SELECT, &cur_ant, NULL);*/
 618         change_ant = (bMain == MAIN_ANT) ? MAIN_ANT : AUX_ANT;
 619
 620         RTW_INFO("%s: config %s\n", __func__, (bMain == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
 621         rtw_antenna_select_cmd(padapter, change_ant, _FALSE);
 622
 623         return _TRUE;
 624 }
 625 #endif
 626
 627 s32
 628 MPT_InitializeAdapter(
 629         IN      PADAPTER                        pAdapter,
 630         IN      u8                              Channel
 631 )
 632 {
 633         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
 634         s32             rtStatus = _SUCCESS;
 635         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.mpt_ctx;
 636         u32             ledsetting;
 637
 638         pMptCtx->bMptDrvUnload = _FALSE;
 639         pMptCtx->bMassProdTest = _FALSE;
 640         pMptCtx->bMptIndexEven = _TRUE; /* default gain index is -6.0db */
 641         pMptCtx->h2cReqNum = 0x0;
 642         /* init for BT MP */
 643 #if defined(CONFIG_RTL8723B)
 644         pMptCtx->bMPh2c_timeout = _FALSE;
 645         pMptCtx->MptH2cRspEvent = _FALSE;
 646         pMptCtx->MptBtC2hEvent = _FALSE;
 647         _rtw_init_sema(&pMptCtx->MPh2c_Sema, 0);
 648         rtw_init_timer(&pMptCtx->MPh2c_timeout_timer, pAdapter, MPh2c_timeout_handle, pAdapter);
 649 #endif
 650
 651         mpt_InitHWConfig(pAdapter);
 652
 653 #ifdef CONFIG_RTL8723B
 654         rtl8723b_InitAntenna_Selection(pAdapter);
 655         if (IS_HARDWARE_TYPE_8723B(pAdapter)) {
 656
 657                 /* <20130522, Kordan> Turn off equalizer to improve Rx sensitivity. (Asked by EEChou)*/
 658                 phy_set_bb_reg(pAdapter, 0xA00, BIT8, 0x0);
 659                 PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /*default use Main*/
 660
 661                 if (pHalData->PackageType == PACKAGE_DEFAULT)
 662                         phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6B04E);
 663                 else
 664                         phy_set_rf_reg(pAdapter, RF_PATH_A, 0x51, bRFRegOffsetMask, 0x6F10E);
 665
 666         }
 667         /*set ant to wifi side in mp mode*/
 668         rtw_write16(pAdapter, 0x870, 0x300);
 669         rtw_write16(pAdapter, 0x860, 0x110);
 670 #endif
 671
 672         pMptCtx->bMptWorkItemInProgress = _FALSE;
 673         pMptCtx->CurrMptAct = NULL;
 674         pMptCtx->mpt_rf_path = RF_PATH_A;
 675         /* ------------------------------------------------------------------------- */
 676         /* Don't accept any packets */
 677         rtw_write32(pAdapter, REG_RCR, 0);
 678
 679         /* ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); */
 680         /* rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); */
 681
 682         /* rtw_write32(pAdapter, REG_LEDCFG0, 0x08080); */
 683         ledsetting = rtw_read32(pAdapter, REG_LEDCFG0);
 684
 685
 686         PHY_LCCalibrate(pAdapter);
 687         PHY_IQCalibrate(pAdapter, _FALSE);
 688         /* dm_check_txpowertracking(&pHalData->odmpriv);        */ /* trigger thermal meter */
 689
 690         PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); /* default use Main */
 691
 692         pMptCtx->backup0xc50 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);
 693         pMptCtx->backup0xc58 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);
 694         pMptCtx->backup0xc30 = (u1Byte)phy_query_bb_reg(pAdapter, rOFDM0_RxDetector1, bMaskByte0);
 695         pMptCtx->backup0x52_RF_A = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_A, RF_0x52, 0x000F0);
 696         pMptCtx->backup0x52_RF_B = (u1Byte)phy_query_rf_reg(pAdapter, RF_PATH_B, RF_0x52, 0x000F0);
 697 #ifdef CONFIG_RTL8188E
 698         rtw_write32(pAdapter, REG_MACID_NO_LINK_0, 0x0);
 699         rtw_write32(pAdapter, REG_MACID_NO_LINK_1, 0x0);
 700 #endif
 701 #ifdef CONFIG_RTL8814A
 702         if (IS_HARDWARE_TYPE_8814A(pAdapter)) {
 703                 pHalData->BackUp_IG_REG_4_Chnl_Section[0] = (u1Byte)phy_query_bb_reg(pAdapter, rA_IGI_Jaguar, bMaskByte0);
 704                 pHalData->BackUp_IG_REG_4_Chnl_Section[1] = (u1Byte)phy_query_bb_reg(pAdapter, rB_IGI_Jaguar, bMaskByte0);
 705                 pHalData->BackUp_IG_REG_4_Chnl_Section[2] = (u1Byte)phy_query_bb_reg(pAdapter, rC_IGI_Jaguar2, bMaskByte0);
 706                 pHalData->BackUp_IG_REG_4_Chnl_Section[3] = (u1Byte)phy_query_bb_reg(pAdapter, rD_IGI_Jaguar2, bMaskByte0);
 707         }
 708 #endif
 709         return  rtStatus;
 710 }
 711
 712 /*-----------------------------------------------------------------------------
 713  * Function:    MPT_DeInitAdapter()
 714  *
 715  * Overview:    Extra DeInitialization for Mass Production Test.
 716  *
 717  * Input:               PADAPTER        pAdapter
 718  *
 719  * Output:              NONE
 720  *
 721  * Return:              NONE
 722  *
 723  * Revised History:
 724  *      When            Who             Remark
 725  *      05/08/2007      MHC             Create Version 0.
 726  *      05/18/2007      MHC             Add normal driver MPHalt code.
 727  *
 728  *---------------------------------------------------------------------------*/
 729 VOID
 730 MPT_DeInitAdapter(
 731         IN      PADAPTER        pAdapter
 732 )
 733 {
 734         PMPT_CONTEXT            pMptCtx = &pAdapter->mppriv.mpt_ctx;
 735
 736         pMptCtx->bMptDrvUnload = _TRUE;
 737 #if defined(CONFIG_RTL8723B)
 738         _rtw_free_sema(&(pMptCtx->MPh2c_Sema));
 739         _cancel_timer_ex(&pMptCtx->MPh2c_timeout_timer);
 740 #endif
 741 #if     defined(CONFIG_RTL8723B)
 742         phy_set_bb_reg(pAdapter, 0xA01, BIT0, 1); /* /suggestion  by jerry for MP Rx. */
 743 #endif
 744 #if 0 /* for Windows */
 745         PlatformFreeWorkItem(&(pMptCtx->MptWorkItem));
 746
 747         while (pMptCtx->bMptWorkItemInProgress) {
 748                 if (NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50))
 749                         break;
 750         }
 751         NdisFreeSpinLock(&(pMptCtx->MptWorkItemSpinLock));
 752 #endif
 753 }
 754
 755 static u8 mpt_ProStartTest(PADAPTER padapter)
 756 {
 757         PMPT_CONTEXT pMptCtx = &padapter->mppriv.mpt_ctx;
 758
 759         pMptCtx->bMassProdTest = _TRUE;
 760         pMptCtx->is_start_cont_tx = _FALSE;
 761         pMptCtx->bCckContTx = _FALSE;
 762         pMptCtx->bOfdmContTx = _FALSE;
 763         pMptCtx->bSingleCarrier = _FALSE;
 764         pMptCtx->is_carrier_suppression = _FALSE;
 765         pMptCtx->is_single_tone = _FALSE;
 766         pMptCtx->HWTxmode = PACKETS_TX;
 767
 768         return _SUCCESS;
 769 }
 770
 771 /*
 772  * General use
 773  */
 774 s32 SetPowerTracking(PADAPTER padapter, u8 enable)
 775 {
 776
 777         hal_mpt_SetPowerTracking(padapter, enable);
 778         return 0;
 779 }
 780
 781 void GetPowerTracking(PADAPTER padapter, u8 *enable)
 782 {
 783         hal_mpt_GetPowerTracking(padapter, enable);
 784 }
 785
 786 void rtw_mp_trigger_iqk(PADAPTER padapter)
 787 {
 788         PHY_IQCalibrate(padapter, _FALSE);
 789 }
 790
 791 void rtw_mp_trigger_lck(PADAPTER padapter)
 792 {
 793         PHY_LCCalibrate(padapter);
 794 }
 795
 796 static void init_mp_data(PADAPTER padapter)
 797 {
 798         u8 v8;
 799         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
 800         struct dm_struct                *pDM_Odm = &pHalData->odmpriv;
 801
 802         /*disable BCN*/
 803         v8 = rtw_read8(padapter, REG_BCN_CTRL);
 804         v8 &= ~EN_BCN_FUNCTION;
 805         rtw_write8(padapter, REG_BCN_CTRL, v8);
 806
 807         pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
 808 }
 809
 810 void MPT_PwrCtlDM(PADAPTER padapter, u32 bstart)
 811 {
 812         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(padapter);
 813         struct dm_struct                *pDM_Odm = &pHalData->odmpriv;
 814         u32     rf_ability;
 815
 816         if (bstart == 1) {
 817                 RTW_INFO("in MPT_PwrCtlDM start\n");
 818
 819                 rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) | HAL_RF_TX_PWR_TRACK;
 820                 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
 821
 822                 pDM_Odm->rf_calibrate_info.txpowertrack_control = _TRUE;
 823                 padapter->mppriv.mp_dm = 1;
 824
 825         } else {
 826                 RTW_INFO("in MPT_PwrCtlDM stop\n");
 827                 rf_ability = ((u32)halrf_cmn_info_get(pDM_Odm, HALRF_CMNINFO_ABILITY)) & ~HAL_RF_TX_PWR_TRACK;
 828                 halrf_cmn_info_set(pDM_Odm, HALRF_CMNINFO_ABILITY, rf_ability);
 829                 pDM_Odm->rf_calibrate_info.txpowertrack_control = _FALSE;
 830                 padapter->mppriv.mp_dm = 0;
 831                 {
 832                         struct txpwrtrack_cfg c;
 833                         u1Byte  chnl = 0 ;
 834                         _rtw_memset(&c, 0, sizeof(struct txpwrtrack_cfg));
 835                         configure_txpower_track(pDM_Odm, &c);
 836                         odm_clear_txpowertracking_state(pDM_Odm);
 837                         if (*c.odm_tx_pwr_track_set_pwr) {
 838                                 if (pDM_Odm->support_ic_type == ODM_RTL8188F)
 839                                         (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
 840                                 else if (pDM_Odm->support_ic_type == ODM_RTL8723D) {
 841                                         (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
 842                                         SetTxPower(padapter);
 843                                 } else if (pDM_Odm->support_ic_type == ODM_RTL8192F) {
 844                                         (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_A, chnl);
 845                                         (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, MIX_MODE, RF_PATH_B, chnl);
 846                                 } else {
 847                                         (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_A, chnl);
 848                                         (*c.odm_tx_pwr_track_set_pwr)(pDM_Odm, BBSWING, RF_PATH_B, chnl);
 849                                 }
 850                         }
 851                 }
 852         }
 853
 854 }
 855
 856
 857 u32 mp_join(PADAPTER padapter, u8 mode)
 858 {
 859         WLAN_BSSID_EX bssid;
 860         struct sta_info *psta;
 861         u32 length;
 862         _irqL irqL;
 863         s32 res = _SUCCESS;
 864
 865         struct mp_priv *pmppriv = &padapter->mppriv;
 866         struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
 867         struct wlan_network *tgt_network = &pmlmepriv->cur_network;
 868         struct mlme_ext_priv    *pmlmeext = &padapter->mlmeextpriv;
 869         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
 870         WLAN_BSSID_EX           *pnetwork = (WLAN_BSSID_EX *)(&(pmlmeinfo->network));
 871
 872         /* 1. initialize a new WLAN_BSSID_EX */
 873         _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX));
 874         RTW_INFO("%s ,pmppriv->network_macaddr=%x %x %x %x %x %x\n", __func__,
 875                 pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
 876                  pmppriv->network_macaddr[5]);
 877         _rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN);
 878
 879         if (mode == WIFI_FW_ADHOC_STATE) {
 880                 bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc");
 881                 _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_adhoc", bssid.Ssid.SsidLength);
 882                 bssid.InfrastructureMode = Ndis802_11IBSS;
 883                 bssid.NetworkTypeInUse = Ndis802_11DS;
 884                 bssid.IELength = 0;
 885                 bssid.Configuration.DSConfig = pmppriv->channel;
 886
 887         } else if (mode == WIFI_FW_STATION_STATE) {
 888                 bssid.Ssid.SsidLength = strlen("mp_pseudo_STATION");
 889                 _rtw_memcpy(bssid.Ssid.Ssid, (u8 *)"mp_pseudo_STATION", bssid.Ssid.SsidLength);
 890                 bssid.InfrastructureMode = Ndis802_11Infrastructure;
 891                 bssid.NetworkTypeInUse = Ndis802_11DS;
 892                 bssid.IELength = 0;
 893         }
 894
 895         length = get_WLAN_BSSID_EX_sz(&bssid);
 896         if (length % 4)
 897                 bssid.Length = ((length >> 2) + 1) << 2; /* round up to multiple of 4 bytes. */
 898         else
 899                 bssid.Length = length;
 900
 901         _enter_critical_bh(&pmlmepriv->lock, &irqL);
 902
 903         if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)
 904                 goto end_of_mp_start_test;
 905
 906         /* init mp_start_test status */
 907         if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) {
 908                 rtw_disassoc_cmd(padapter, 500, 0);
 909                 rtw_indicate_disconnect(padapter, 0, _FALSE);
 910                 rtw_free_assoc_resources_cmd(padapter, _TRUE, 0);
 911         }
 912         pmppriv->prev_fw_state = get_fwstate(pmlmepriv);
 913         /*pmlmepriv->fw_state = WIFI_MP_STATE;*/
 914         init_fwstate(pmlmepriv, WIFI_MP_STATE);
 915
 916         set_fwstate(pmlmepriv, _FW_UNDER_LINKING);
 917
 918         /* 3 2. create a new psta for mp driver */
 919         /* clear psta in the cur_network, if any */
 920         psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
 921         if (psta)
 922                 rtw_free_stainfo(padapter, psta);
 923
 924         psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress);
 925         if (psta == NULL) {
 926                 /*pmlmepriv->fw_state = pmppriv->prev_fw_state;*/
 927                 init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
 928                 res = _FAIL;
 929                 goto end_of_mp_start_test;
 930         }
 931         if (mode == WIFI_FW_ADHOC_STATE)
 932         set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE);
 933         else
 934                 set_fwstate(pmlmepriv, WIFI_STATION_STATE);
 935         /* 3 3. join psudo AdHoc */
 936         tgt_network->join_res = 1;
 937         tgt_network->aid = psta->cmn.aid = 1;
 938
 939         _rtw_memcpy(&padapter->registrypriv.dev_network, &bssid, length);
 940         rtw_update_registrypriv_dev_network(padapter);
 941         _rtw_memcpy(&tgt_network->network, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
 942         _rtw_memcpy(pnetwork, &padapter->registrypriv.dev_network, padapter->registrypriv.dev_network.Length);
 943
 944         rtw_indicate_connect(padapter);
 945         _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING);
 946         set_fwstate(pmlmepriv, _FW_LINKED);
 947
 948 end_of_mp_start_test:
 949
 950         _exit_critical_bh(&pmlmepriv->lock, &irqL);
 951
 952         if (1) { /* (res == _SUCCESS) */
 953                 /* set MSR to WIFI_FW_ADHOC_STATE */
 954                 if (mode == WIFI_FW_ADHOC_STATE) {
 955                         /* set msr to WIFI_FW_ADHOC_STATE */
 956                         pmlmeinfo->state = WIFI_FW_ADHOC_STATE;
 957                         Set_MSR(padapter, (pmlmeinfo->state & 0x3));
 958                         rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress);
 959                         rtw_hal_rcr_set_chk_bssid(padapter, MLME_ADHOC_STARTED);
 960                         pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS;
 961                 } else {
 962                         Set_MSR(padapter, WIFI_FW_STATION_STATE);
 963
 964                         RTW_INFO("%s , pmppriv->network_macaddr =%x %x %x %x %x %x\n", __func__,
 965                                 pmppriv->network_macaddr[0], pmppriv->network_macaddr[1], pmppriv->network_macaddr[2], pmppriv->network_macaddr[3], pmppriv->network_macaddr[4],
 966                                  pmppriv->network_macaddr[5]);
 967
 968                         rtw_hal_set_hwreg(padapter, HW_VAR_BSSID, pmppriv->network_macaddr);
 969                 }
 970         }
 971
 972         return res;
 973 }
 974 /* This function initializes the DUT to the MP test mode */
 975 s32 mp_start_test(PADAPTER padapter)
 976 {
 977         struct mp_priv *pmppriv = &padapter->mppriv;
 978         s32 res = _SUCCESS;
 979
 980         padapter->registrypriv.mp_mode = 1;
 981
 982         init_mp_data(padapter);
 983 #ifdef CONFIG_RTL8814A
 984         rtl8814_InitHalDm(padapter);
 985 #endif /* CONFIG_RTL8814A */
 986 #ifdef CONFIG_RTL8812A
 987         rtl8812_InitHalDm(padapter);
 988 #endif /* CONFIG_RTL8812A */
 989 #ifdef CONFIG_RTL8723B
 990         rtl8723b_InitHalDm(padapter);
 991 #endif /* CONFIG_RTL8723B */
 992 #ifdef CONFIG_RTL8703B
 993         rtl8703b_InitHalDm(padapter);
 994 #endif /* CONFIG_RTL8703B */
 995 #ifdef CONFIG_RTL8192E
 996         rtl8192e_InitHalDm(padapter);
 997 #endif
 998 #ifdef CONFIG_RTL8188F
 999         rtl8188f_InitHalDm(padapter);
1000 #endif
1001 #ifdef CONFIG_RTL8188GTV
1002         rtl8188gtv_InitHalDm(padapter);
1003 #endif
1004 #ifdef CONFIG_RTL8188E
1005         rtl8188e_InitHalDm(padapter);
1006 #endif
1007 #ifdef CONFIG_RTL8723D
1008         rtl8723d_InitHalDm(padapter);
1009 #endif /* CONFIG_RTL8723D */
1010
1011         /* 3 0. update mp_priv */
1012
1013         if (!RF_TYPE_VALID(padapter->registrypriv.rf_config)) {
1014                 /*              switch (phal->rf_type) { */
1015                 switch (GET_RF_TYPE(padapter)) {
1016                 case RF_1T1R:
1017                         pmppriv->antenna_tx = ANTENNA_A;
1018                         pmppriv->antenna_rx = ANTENNA_A;
1019                         break;
1020                 case RF_1T2R:
1021                 default:
1022                         pmppriv->antenna_tx = ANTENNA_A;
1023                         pmppriv->antenna_rx = ANTENNA_AB;
1024                         break;
1025                 case RF_2T2R:
1026                         pmppriv->antenna_tx = ANTENNA_AB;
1027                         pmppriv->antenna_rx = ANTENNA_AB;
1028                         break;
1029                 case RF_2T4R:
1030                         pmppriv->antenna_tx = ANTENNA_AB;
1031                         pmppriv->antenna_rx = ANTENNA_ABCD;
1032                         break;
1033                 }
1034         }
1035
1036         mpt_ProStartTest(padapter);
1037
1038         mp_join(padapter, WIFI_FW_ADHOC_STATE);
1039
1040         return res;
1041 }
1042 /* ------------------------------------------------------------------------------
1043  * This function change the DUT from the MP test mode into normal mode */
1044 void mp_stop_test(PADAPTER padapter)
1045 {
1046         struct mp_priv *pmppriv = &padapter->mppriv;
1047         struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
1048         struct wlan_network *tgt_network = &pmlmepriv->cur_network;
1049         struct sta_info *psta;
1050
1051         _irqL irqL;
1052
1053         if (pmppriv->mode == MP_ON) {
1054                 pmppriv->bSetTxPower = 0;
1055                 _enter_critical_bh(&pmlmepriv->lock, &irqL);
1056                 if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)
1057                         goto end_of_mp_stop_test;
1058
1059                 /* 3 1. disconnect psudo AdHoc */
1060                 rtw_indicate_disconnect(padapter, 0, _FALSE);
1061
1062                 /* 3 2. clear psta used in mp test mode.
1063                 *       rtw_free_assoc_resources(padapter, _TRUE); */
1064                 psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress);
1065                 if (psta)
1066                         rtw_free_stainfo(padapter, psta);
1067
1068                 /* 3 3. return to normal state (default:station mode) */
1069                 /*pmlmepriv->fw_state = pmppriv->prev_fw_state; */ /* WIFI_STATION_STATE;*/
1070                 init_fwstate(pmlmepriv, pmppriv->prev_fw_state);
1071
1072                 /* flush the cur_network */
1073                 _rtw_memset(tgt_network, 0, sizeof(struct wlan_network));
1074
1075                 _clr_fwstate_(pmlmepriv, WIFI_MP_STATE);
1076
1077 end_of_mp_stop_test:
1078
1079                 _exit_critical_bh(&pmlmepriv->lock, &irqL);
1080
1081 #ifdef CONFIG_RTL8812A
1082                 rtl8812_InitHalDm(padapter);
1083 #endif
1084 #ifdef CONFIG_RTL8723B
1085                 rtl8723b_InitHalDm(padapter);
1086 #endif
1087 #ifdef CONFIG_RTL8703B
1088                 rtl8703b_InitHalDm(padapter);
1089 #endif
1090 #ifdef CONFIG_RTL8192E
1091                 rtl8192e_InitHalDm(padapter);
1092 #endif
1093 #ifdef CONFIG_RTL8188F
1094                 rtl8188f_InitHalDm(padapter);
1095 #endif
1096 #ifdef CONFIG_RTL8188GTV
1097                 rtl8188gtv_InitHalDm(padapter);
1098 #endif
1099 #ifdef CONFIG_RTL8723D
1100                 rtl8723d_InitHalDm(padapter);
1101 #endif
1102         }
1103 }
1104 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
1105 #if 0
1106 /* #ifdef CONFIG_USB_HCI */
1107 static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID)
1108 {
1109         u8              eRFPath;
1110         u32             rfReg0x26;
1111         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
1112
1113
1114         if (RateIdx < MPT_RATE_6M)      /* CCK rate,for 88cu */
1115                 rfReg0x26 = 0xf400;
1116         else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {/* OFDM rate,for 88cu */
1117                 if ((4 == Channel) || (8 == Channel) || (12 == Channel))
1118                         rfReg0x26 = 0xf000;
1119                 else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
1120                         rfReg0x26 = 0xf400;
1121                 else
1122                         rfReg0x26 = 0x4f200;
1123         } else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {
1124                 /* MCS 20M ,for 88cu */ /* MCS40M rate,for 88cu */
1125
1126                 if (CHANNEL_WIDTH_20 == BandWidthID) {
1127                         if ((4 == Channel) || (8 == Channel))
1128                                 rfReg0x26 = 0xf000;
1129                         else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel))
1130                                 rfReg0x26 = 0xf400;
1131                         else
1132                                 rfReg0x26 = 0x4f200;
1133                 } else {
1134                         if ((4 == Channel) || (8 == Channel))
1135                                 rfReg0x26 = 0xf000;
1136                         else if ((5 == Channel) || (7 == Channel))
1137                                 rfReg0x26 = 0xf400;
1138                         else
1139                                 rfReg0x26 = 0x4f200;
1140                 }
1141         }
1142
1143         for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++)
1144                 write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26);
1145 }
1146 #endif
1147 /*-----------------------------------------------------------------------------
1148  * Function:    mpt_SwitchRfSetting
1149  *
1150  * Overview:    Change RF Setting when we siwthc channel/rate/BW for MP.
1151  *
1152  * Input:       IN      PADAPTER                                pAdapter
1153  *
1154  * Output:      NONE
1155  *
1156  * Return:      NONE
1157  *
1158  * Revised History:
1159  * When                 Who             Remark
1160  * 01/08/2009   MHC             Suggestion from SD3 Willis for 92S series.
1161  * 01/09/2009   MHC             Add CCK modification for 40MHZ. Suggestion from SD3.
1162  *
1163  *---------------------------------------------------------------------------*/
1164 #if 0
1165 static void mpt_SwitchRfSetting(PADAPTER pAdapter)
1166 {
1167         hal_mpt_SwitchRfSetting(pAdapter);
1168 }
1169
1170 /*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/
1171 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
1172 static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14)
1173 {
1174         hal_mpt_CCKTxPowerAdjust(Adapter, bInCH14);
1175 }
1176 #endif
1177
1178 /*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/
1179
1180 /*
1181  * SetChannel
1182  * Description
1183  *      Use H2C command to change channel,
1184  *      not only modify rf register, but also other setting need to be done.
1185  */
1186 void SetChannel(PADAPTER pAdapter)
1187 {
1188         hal_mpt_SetChannel(pAdapter);
1189 }
1190
1191 /*
1192  * Notice
1193  *      Switch bandwitdth may change center frequency(channel)
1194  */
1195 void SetBandwidth(PADAPTER pAdapter)
1196 {
1197         hal_mpt_SetBandwidth(pAdapter);
1198
1199 }
1200
1201 void SetAntenna(PADAPTER pAdapter)
1202 {
1203         hal_mpt_SetAntenna(pAdapter);
1204 }
1205
1206 int SetTxPower(PADAPTER pAdapter)
1207 {
1208
1209         hal_mpt_SetTxPower(pAdapter);
1210         return _TRUE;
1211 }
1212
1213 void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset)
1214 {
1215         u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D, tmpAGC;
1216
1217         TxAGCOffset_B = (ulTxAGCOffset & 0x000000ff);
1218         TxAGCOffset_C = ((ulTxAGCOffset & 0x0000ff00) >> 8);
1219         TxAGCOffset_D = ((ulTxAGCOffset & 0x00ff0000) >> 16);
1220
1221         tmpAGC = (TxAGCOffset_D << 8 | TxAGCOffset_C << 4 | TxAGCOffset_B);
1222         write_bbreg(pAdapter, rFPGA0_TxGainStage,
1223                     (bXBTxAGC | bXCTxAGC | bXDTxAGC), tmpAGC);
1224 }
1225
1226 void SetDataRate(PADAPTER pAdapter)
1227 {
1228         hal_mpt_SetDataRate(pAdapter);
1229 }
1230
1231 void MP_PHY_SetRFPathSwitch(PADAPTER pAdapter , BOOLEAN bMain)
1232 {
1233
1234         PHY_SetRFPathSwitch(pAdapter, bMain);
1235
1236 }
1237
1238 void mp_phy_switch_rf_path_set(PADAPTER pAdapter , u8 *pstate)
1239 {
1240
1241         phy_switch_rf_path_set(pAdapter, pstate);
1242
1243 }
1244
1245 u8 MP_PHY_QueryRFPathSwitch(PADAPTER pAdapter)
1246 {
1247         return PHY_QueryRFPathSwitch(pAdapter);
1248 }
1249
1250 s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther)
1251 {
1252         return hal_mpt_SetThermalMeter(pAdapter, target_ther);
1253 }
1254
1255 #if 0
1256 static void TriggerRFThermalMeter(PADAPTER pAdapter)
1257 {
1258         hal_mpt_TriggerRFThermalMeter(pAdapter);
1259 }
1260
1261 static u8 ReadRFThermalMeter(PADAPTER pAdapter)
1262 {
1263         return hal_mpt_ReadRFThermalMeter(pAdapter);
1264 }
1265 #endif
1266
1267 void GetThermalMeter(PADAPTER pAdapter, u8 *value)
1268 {
1269         hal_mpt_GetThermalMeter(pAdapter, value);
1270 }
1271
1272 void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart)
1273 {
1274         PhySetTxPowerLevel(pAdapter);
1275         hal_mpt_SetSingleCarrierTx(pAdapter, bStart);
1276 }
1277
1278 void SetSingleToneTx(PADAPTER pAdapter, u8 bStart)
1279 {
1280         PhySetTxPowerLevel(pAdapter);
1281         hal_mpt_SetSingleToneTx(pAdapter, bStart);
1282 }
1283
1284 void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart)
1285 {
1286         PhySetTxPowerLevel(pAdapter);
1287         hal_mpt_SetCarrierSuppressionTx(pAdapter, bStart);
1288 }
1289
1290 void SetContinuousTx(PADAPTER pAdapter, u8 bStart)
1291 {
1292         PhySetTxPowerLevel(pAdapter);
1293         hal_mpt_SetContinuousTx(pAdapter, bStart);
1294 }
1295
1296
1297 void PhySetTxPowerLevel(PADAPTER pAdapter)
1298 {
1299         struct mp_priv *pmp_priv = &pAdapter->mppriv;
1300
1301
1302         if (pmp_priv->bSetTxPower == 0) /* for NO manually set power index */
1303                 rtw_hal_set_tx_power_level(pAdapter, pmp_priv->channel);
1304 }
1305
1306 /* ------------------------------------------------------------------------------ */
1307 static void dump_mpframe(PADAPTER padapter, struct xmit_frame *pmpframe)
1308 {
1309         rtw_hal_mgnt_xmit(padapter, pmpframe);
1310 }
1311
1312 static struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv)
1313 {
1314         struct xmit_frame       *pmpframe;
1315         struct xmit_buf *pxmitbuf;
1316
1317         pmpframe = rtw_alloc_xmitframe(pxmitpriv);
1318         if (pmpframe == NULL)
1319                 return NULL;
1320
1321         pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv);
1322         if (pxmitbuf == NULL) {
1323                 rtw_free_xmitframe(pxmitpriv, pmpframe);
1324                 return NULL;
1325         }
1326
1327         pmpframe->frame_tag = MP_FRAMETAG;
1328
1329         pmpframe->pxmitbuf = pxmitbuf;
1330
1331         pmpframe->buf_addr = pxmitbuf->pbuf;
1332
1333         pxmitbuf->priv_data = pmpframe;
1334
1335         return pmpframe;
1336
1337 }
1338
1339 #ifdef CONFIG_PCI_HCI
1340 static u8 check_nic_enough_desc(_adapter *padapter, struct pkt_attrib *pattrib)
1341 {
1342         u32 prio;
1343         struct xmit_priv        *pxmitpriv = &padapter->xmitpriv;
1344         struct rtw_tx_ring      *ring;
1345
1346         switch (pattrib->qsel) {
1347         case 0:
1348         case 3:
1349                 prio = BE_QUEUE_INX;
1350                 break;
1351         case 1:
1352         case 2:
1353                 prio = BK_QUEUE_INX;
1354                 break;
1355         case 4:
1356         case 5:
1357                 prio = VI_QUEUE_INX;
1358                 break;
1359         case 6:
1360         case 7:
1361                 prio = VO_QUEUE_INX;
1362                 break;
1363         default:
1364                 prio = BE_QUEUE_INX;
1365                 break;
1366         }
1367
1368         ring = &pxmitpriv->tx_ring[prio];
1369
1370         /*
1371          * for now we reserve two free descriptor as a safety boundary
1372          * between the tail and the head
1373          */
1374         if ((ring->entries - ring->qlen) >= 2)
1375                 return _TRUE;
1376         else
1377                 return _FALSE;
1378 }
1379 #endif
1380
1381 static thread_return mp_xmit_packet_thread(thread_context context)
1382 {
1383         struct xmit_frame       *pxmitframe;
1384         struct mp_tx            *pmptx;
1385         struct mp_priv  *pmp_priv;
1386         struct xmit_priv        *pxmitpriv;
1387         PADAPTER padapter;
1388
1389         pmp_priv = (struct mp_priv *)context;
1390         pmptx = &pmp_priv->tx;
1391         padapter = pmp_priv->papdater;
1392         pxmitpriv = &(padapter->xmitpriv);
1393
1394         thread_enter("RTW_MP_THREAD");
1395
1396         RTW_INFO("%s:pkTx Start\n", __func__);
1397         while (1) {
1398                 pxmitframe = alloc_mp_xmitframe(pxmitpriv);
1399 #ifdef CONFIG_PCI_HCI
1400                 if(check_nic_enough_desc(padapter, &pmptx->attrib) == _FALSE) {
1401                         rtw_usleep_os(1000);
1402                         continue;
1403                 }
1404 #endif
1405                 if (pxmitframe == NULL) {
1406                         if (pmptx->stop ||
1407                             RTW_CANNOT_RUN(padapter))
1408                                 goto exit;
1409                         else {
1410                                 rtw_usleep_os(10);
1411                                 continue;
1412                         }
1413                 }
1414                 _rtw_memcpy((u8 *)(pxmitframe->buf_addr + TXDESC_OFFSET), pmptx->buf, pmptx->write_size);
1415                 _rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib));
1416
1417
1418                 rtw_usleep_os(padapter->mppriv.pktInterval);
1419                 dump_mpframe(padapter, pxmitframe);
1420
1421                 pmptx->sended++;
1422                 pmp_priv->tx_pktcount++;
1423
1424                 if (pmptx->stop ||
1425                     RTW_CANNOT_RUN(padapter))
1426                         goto exit;
1427                 if ((pmptx->count != 0) &&
1428                     (pmptx->count == pmptx->sended))
1429                         goto exit;
1430
1431                 flush_signals_thread();
1432         }
1433
1434 exit:
1435         /* RTW_INFO("%s:pkTx Exit\n", __func__); */
1436         rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size);
1437         pmptx->pallocated_buf = NULL;
1438         pmptx->stop = 1;
1439
1440         thread_exit(NULL);
1441         return 0;
1442 }
1443
1444 void fill_txdesc_for_mp(PADAPTER padapter, u8 *ptxdesc)
1445 {
1446         struct mp_priv *pmp_priv = &padapter->mppriv;
1447         _rtw_memcpy(ptxdesc, pmp_priv->tx.desc, TXDESC_SIZE);
1448 }
1449
1450 #if defined(CONFIG_RTL8188E)
1451 void fill_tx_desc_8188e(PADAPTER padapter)
1452 {
1453         struct mp_priv *pmp_priv = &padapter->mppriv;
1454         struct tx_desc *desc   = (struct tx_desc *)&(pmp_priv->tx.desc);
1455         struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1456         u32     pkt_size = pattrib->last_txcmdsz;
1457         s32 bmcast = IS_MCAST(pattrib->ra);
1458         /* offset 0 */
1459 #if !defined(CONFIG_RTL8188E_SDIO) && !defined(CONFIG_PCI_HCI)
1460         desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG);
1461         desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); /* packet size */
1462         desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); /* 32 bytes for TX Desc */
1463         if (bmcast)
1464                 desc->txdw0 |= cpu_to_le32(BMC); /* broadcast packet */
1465
1466         desc->txdw1 |= cpu_to_le32((0x01 << 26) & 0xff000000);
1467 #endif
1468
1469         desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x3F); /* CAM_ID(MAC_ID) */
1470         desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); /* Queue Select, TID */
1471         desc->txdw1 |= cpu_to_le32((pattrib->raid << RATE_ID_SHT) & 0x000F0000); /* Rate Adaptive ID */
1472         /* offset 8 */
1473         /* desc->txdw2 |= cpu_to_le32(AGG_BK); */ /* AGG BK */
1474
1475         desc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0x0fff0000);
1476         desc->txdw4 |= cpu_to_le32(HW_SSN);
1477
1478         desc->txdw4 |= cpu_to_le32(USERATE);
1479         desc->txdw4 |= cpu_to_le32(DISDATAFB);
1480
1481         if (pmp_priv->preamble) {
1482                 if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
1483                         desc->txdw4 |= cpu_to_le32(DATA_SHORT); /* CCK Short Preamble */
1484         }
1485
1486         if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1487                 desc->txdw4 |= cpu_to_le32(DATA_BW);
1488
1489         /* offset 20 */
1490         desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F);
1491
1492         if (pmp_priv->preamble) {
1493                 if (HwRateToMPTRate(pmp_priv->rateidx) > MPT_RATE_54M)
1494                         desc->txdw5 |= cpu_to_le32(SGI); /* MCS Short Guard Interval */
1495         }
1496
1497         desc->txdw5 |= cpu_to_le32(RTY_LMT_EN); /* retry limit enable */
1498         desc->txdw5 |= cpu_to_le32(0x00180000); /* DATA/RTS Rate Fallback Limit  */
1499
1500
1501 }
1502 #endif
1503
1504 #if defined(CONFIG_RTL8814A)
1505 void fill_tx_desc_8814a(PADAPTER padapter)
1506 {
1507         struct mp_priv *pmp_priv = &padapter->mppriv;
1508         u8 *pDesc   = (u8 *)&(pmp_priv->tx.desc);
1509         struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1510
1511         u32     pkt_size = pattrib->last_txcmdsz;
1512         s32 bmcast = IS_MCAST(pattrib->ra);
1513         u8 offset;
1514
1515         /* SET_TX_DESC_FIRST_SEG_8814A(pDesc, 1); */
1516         SET_TX_DESC_LAST_SEG_8814A(pDesc, 1);
1517         /* SET_TX_DESC_OWN_(pDesc, 1); */
1518
1519         SET_TX_DESC_PKT_SIZE_8814A(pDesc, pkt_size);
1520
1521         offset = TXDESC_SIZE + OFFSET_SZ;
1522
1523         SET_TX_DESC_OFFSET_8814A(pDesc, offset);
1524 #if defined(CONFIG_PCI_HCI)
1525         SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 0); /* 8814AE pkt_offset is 0 */
1526 #else
1527         SET_TX_DESC_PKT_OFFSET_8814A(pDesc, 1);
1528 #endif
1529
1530         if (bmcast)
1531                 SET_TX_DESC_BMC_8814A(pDesc, 1);
1532
1533         SET_TX_DESC_MACID_8814A(pDesc, pattrib->mac_id);
1534         SET_TX_DESC_RATE_ID_8814A(pDesc, pattrib->raid);
1535
1536         /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
1537         SET_TX_DESC_QUEUE_SEL_8814A(pDesc,  pattrib->qsel);
1538         /* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
1539
1540         if (pmp_priv->preamble)
1541                 SET_TX_DESC_DATA_SHORT_8814A(pDesc, 1);
1542
1543         if (!pattrib->qos_en) {
1544                 SET_TX_DESC_HWSEQ_EN_8814A(pDesc, 1); /* Hw set sequence number */
1545         } else
1546                 SET_TX_DESC_SEQ_8814A(pDesc, pattrib->seqnum);
1547
1548         if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
1549                 SET_TX_DESC_DATA_BW_8814A(pDesc, pmp_priv->bandwidth);
1550         else {
1551                 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1552                 SET_TX_DESC_DATA_BW_8814A(pDesc, CHANNEL_WIDTH_20);
1553         }
1554
1555         SET_TX_DESC_DISABLE_FB_8814A(pDesc, 1);
1556         SET_TX_DESC_USE_RATE_8814A(pDesc, 1);
1557         SET_TX_DESC_TX_RATE_8814A(pDesc, pmp_priv->rateidx);
1558
1559 }
1560 #endif
1561
1562 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1563 void fill_tx_desc_8812a(PADAPTER padapter)
1564 {
1565         struct mp_priv *pmp_priv = &padapter->mppriv;
1566         u8 *pDesc   = (u8 *)&(pmp_priv->tx.desc);
1567         struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1568
1569         u32     pkt_size = pattrib->last_txcmdsz;
1570         s32 bmcast = IS_MCAST(pattrib->ra);
1571         u8 data_rate, pwr_status, offset;
1572
1573         SET_TX_DESC_FIRST_SEG_8812(pDesc, 1);
1574         SET_TX_DESC_LAST_SEG_8812(pDesc, 1);
1575         SET_TX_DESC_OWN_8812(pDesc, 1);
1576
1577         SET_TX_DESC_PKT_SIZE_8812(pDesc, pkt_size);
1578
1579         offset = TXDESC_SIZE + OFFSET_SZ;
1580
1581         SET_TX_DESC_OFFSET_8812(pDesc, offset);
1582
1583 #if defined(CONFIG_PCI_HCI)
1584         SET_TX_DESC_PKT_OFFSET_8812(pDesc, 0);
1585 #else
1586         SET_TX_DESC_PKT_OFFSET_8812(pDesc, 1);
1587 #endif
1588         if (bmcast)
1589                 SET_TX_DESC_BMC_8812(pDesc, 1);
1590
1591         SET_TX_DESC_MACID_8812(pDesc, pattrib->mac_id);
1592         SET_TX_DESC_RATE_ID_8812(pDesc, pattrib->raid);
1593
1594         /* SET_TX_DESC_RATE_ID_8812(pDesc, RATEID_IDX_G); */
1595         SET_TX_DESC_QUEUE_SEL_8812(pDesc,  pattrib->qsel);
1596         /* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
1597
1598         if (!pattrib->qos_en) {
1599                 SET_TX_DESC_HWSEQ_EN_8812(pDesc, 1); /* Hw set sequence number */
1600         } else
1601                 SET_TX_DESC_SEQ_8812(pDesc, pattrib->seqnum);
1602
1603         if (pmp_priv->bandwidth <= CHANNEL_WIDTH_160)
1604                 SET_TX_DESC_DATA_BW_8812(pDesc, pmp_priv->bandwidth);
1605         else {
1606                 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1607                 SET_TX_DESC_DATA_BW_8812(pDesc, CHANNEL_WIDTH_20);
1608         }
1609
1610         SET_TX_DESC_DISABLE_FB_8812(pDesc, 1);
1611         SET_TX_DESC_USE_RATE_8812(pDesc, 1);
1612         SET_TX_DESC_TX_RATE_8812(pDesc, pmp_priv->rateidx);
1613
1614 }
1615 #endif
1616 #if defined(CONFIG_RTL8192E)
1617 void fill_tx_desc_8192e(PADAPTER padapter)
1618 {
1619         struct mp_priv *pmp_priv = &padapter->mppriv;
1620         u8 *pDesc       = (u8 *)&(pmp_priv->tx.desc);
1621         struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1622
1623         u32 pkt_size = pattrib->last_txcmdsz;
1624         s32 bmcast = IS_MCAST(pattrib->ra);
1625         u8 data_rate, pwr_status, offset;
1626
1627
1628         SET_TX_DESC_PKT_SIZE_92E(pDesc, pkt_size);
1629
1630         offset = TXDESC_SIZE + OFFSET_SZ;
1631
1632         SET_TX_DESC_OFFSET_92E(pDesc, offset);
1633 #if defined(CONFIG_PCI_HCI) /* 8192EE */
1634
1635         SET_TX_DESC_PKT_OFFSET_92E(pDesc, 0); /* 8192EE pkt_offset is 0 */
1636 #else /* 8192EU 8192ES */
1637         SET_TX_DESC_PKT_OFFSET_92E(pDesc, 1);
1638 #endif
1639
1640         if (bmcast)
1641                 SET_TX_DESC_BMC_92E(pDesc, 1);
1642
1643         SET_TX_DESC_MACID_92E(pDesc, pattrib->mac_id);
1644         SET_TX_DESC_RATE_ID_92E(pDesc, pattrib->raid);
1645
1646
1647         SET_TX_DESC_QUEUE_SEL_92E(pDesc,  pattrib->qsel);
1648         /* SET_TX_DESC_QUEUE_SEL_8812(pDesc,  QSLT_MGNT); */
1649
1650         if (!pattrib->qos_en) {
1651                 SET_TX_DESC_EN_HWSEQ_92E(pDesc, 1);/* Hw set sequence number */
1652                 SET_TX_DESC_HWSEQ_SEL_92E(pDesc, pattrib->hw_ssn_sel);
1653         } else
1654                 SET_TX_DESC_SEQ_92E(pDesc, pattrib->seqnum);
1655
1656         if ((pmp_priv->bandwidth == CHANNEL_WIDTH_20) || (pmp_priv->bandwidth == CHANNEL_WIDTH_40))
1657                 SET_TX_DESC_DATA_BW_92E(pDesc, pmp_priv->bandwidth);
1658         else {
1659                 RTW_INFO("%s:Err: unknown bandwidth %d, use 20M\n", __func__, pmp_priv->bandwidth);
1660                 SET_TX_DESC_DATA_BW_92E(pDesc, CHANNEL_WIDTH_20);
1661         }
1662
1663         /* SET_TX_DESC_DATA_SC_92E(pDesc, SCMapping_92E(padapter,pattrib)); */
1664
1665         SET_TX_DESC_DISABLE_FB_92E(pDesc, 1);
1666         SET_TX_DESC_USE_RATE_92E(pDesc, 1);
1667         SET_TX_DESC_TX_RATE_92E(pDesc, pmp_priv->rateidx);
1668
1669 }
1670 #endif
1671
1672 #if defined(CONFIG_RTL8723B)
1673 void fill_tx_desc_8723b(PADAPTER padapter)
1674 {
1675         struct mp_priv *pmp_priv = &padapter->mppriv;
1676         struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1677         u8 *ptxdesc = pmp_priv->tx.desc;
1678
1679         SET_TX_DESC_AGG_BREAK_8723B(ptxdesc, 1);
1680         SET_TX_DESC_MACID_8723B(ptxdesc, pattrib->mac_id);
1681         SET_TX_DESC_QUEUE_SEL_8723B(ptxdesc, pattrib->qsel);
1682
1683         SET_TX_DESC_RATE_ID_8723B(ptxdesc, pattrib->raid);
1684         SET_TX_DESC_SEQ_8723B(ptxdesc, pattrib->seqnum);
1685         SET_TX_DESC_HWSEQ_EN_8723B(ptxdesc, 1);
1686         SET_TX_DESC_USE_RATE_8723B(ptxdesc, 1);
1687         SET_TX_DESC_DISABLE_FB_8723B(ptxdesc, 1);
1688
1689         if (pmp_priv->preamble) {
1690                 if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
1691                         SET_TX_DESC_DATA_SHORT_8723B(ptxdesc, 1);
1692         }
1693
1694         if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1695                 SET_TX_DESC_DATA_BW_8723B(ptxdesc, 1);
1696
1697         SET_TX_DESC_TX_RATE_8723B(ptxdesc, pmp_priv->rateidx);
1698
1699         SET_TX_DESC_DATA_RATE_FB_LIMIT_8723B(ptxdesc, 0x1F);
1700         SET_TX_DESC_RTS_RATE_FB_LIMIT_8723B(ptxdesc, 0xF);
1701 }
1702 #endif
1703
1704 #if defined(CONFIG_RTL8703B)
1705 void fill_tx_desc_8703b(PADAPTER padapter)
1706 {
1707         struct mp_priv *pmp_priv = &padapter->mppriv;
1708         struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1709         u8 *ptxdesc = pmp_priv->tx.desc;
1710
1711         SET_TX_DESC_AGG_BREAK_8703B(ptxdesc, 1);
1712         SET_TX_DESC_MACID_8703B(ptxdesc, pattrib->mac_id);
1713         SET_TX_DESC_QUEUE_SEL_8703B(ptxdesc, pattrib->qsel);
1714
1715         SET_TX_DESC_RATE_ID_8703B(ptxdesc, pattrib->raid);
1716         SET_TX_DESC_SEQ_8703B(ptxdesc, pattrib->seqnum);
1717         SET_TX_DESC_HWSEQ_EN_8703B(ptxdesc, 1);
1718         SET_TX_DESC_USE_RATE_8703B(ptxdesc, 1);
1719         SET_TX_DESC_DISABLE_FB_8703B(ptxdesc, 1);
1720
1721         if (pmp_priv->preamble) {
1722                 if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
1723                         SET_TX_DESC_DATA_SHORT_8703B(ptxdesc, 1);
1724         }
1725
1726         if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1727                 SET_TX_DESC_DATA_BW_8703B(ptxdesc, 1);
1728
1729         SET_TX_DESC_TX_RATE_8703B(ptxdesc, pmp_priv->rateidx);
1730
1731         SET_TX_DESC_DATA_RATE_FB_LIMIT_8703B(ptxdesc, 0x1F);
1732         SET_TX_DESC_RTS_RATE_FB_LIMIT_8703B(ptxdesc, 0xF);
1733 }
1734 #endif
1735
1736 #if defined(CONFIG_RTL8188F)
1737 void fill_tx_desc_8188f(PADAPTER padapter)
1738 {
1739         struct mp_priv *pmp_priv = &padapter->mppriv;
1740         struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1741         u8 *ptxdesc = pmp_priv->tx.desc;
1742
1743         SET_TX_DESC_AGG_BREAK_8188F(ptxdesc, 1);
1744         SET_TX_DESC_MACID_8188F(ptxdesc, pattrib->mac_id);
1745         SET_TX_DESC_QUEUE_SEL_8188F(ptxdesc, pattrib->qsel);
1746
1747         SET_TX_DESC_RATE_ID_8188F(ptxdesc, pattrib->raid);
1748         SET_TX_DESC_SEQ_8188F(ptxdesc, pattrib->seqnum);
1749         SET_TX_DESC_HWSEQ_EN_8188F(ptxdesc, 1);
1750         SET_TX_DESC_USE_RATE_8188F(ptxdesc, 1);
1751         SET_TX_DESC_DISABLE_FB_8188F(ptxdesc, 1);
1752
1753         if (pmp_priv->preamble)
1754                 if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
1755                         SET_TX_DESC_DATA_SHORT_8188F(ptxdesc, 1);
1756
1757         if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1758                 SET_TX_DESC_DATA_BW_8188F(ptxdesc, 1);
1759
1760         SET_TX_DESC_TX_RATE_8188F(ptxdesc, pmp_priv->rateidx);
1761
1762         SET_TX_DESC_DATA_RATE_FB_LIMIT_8188F(ptxdesc, 0x1F);
1763         SET_TX_DESC_RTS_RATE_FB_LIMIT_8188F(ptxdesc, 0xF);
1764 }
1765 #endif
1766
1767 #if defined(CONFIG_RTL8188GTV)
1768 void fill_tx_desc_8188gtv(PADAPTER padapter)
1769 {
1770         struct mp_priv *pmp_priv = &padapter->mppriv;
1771         struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1772         u8 *ptxdesc = pmp_priv->tx.desc;
1773
1774         SET_TX_DESC_AGG_BREAK_8188GTV(ptxdesc, 1);
1775         SET_TX_DESC_MACID_8188GTV(ptxdesc, pattrib->mac_id);
1776         SET_TX_DESC_QUEUE_SEL_8188GTV(ptxdesc, pattrib->qsel);
1777
1778         SET_TX_DESC_RATE_ID_8188GTV(ptxdesc, pattrib->raid);
1779         SET_TX_DESC_SEQ_8188GTV(ptxdesc, pattrib->seqnum);
1780         SET_TX_DESC_HWSEQ_EN_8188GTV(ptxdesc, 1);
1781         SET_TX_DESC_USE_RATE_8188GTV(ptxdesc, 1);
1782         SET_TX_DESC_DISABLE_FB_8188GTV(ptxdesc, 1);
1783
1784         if (pmp_priv->preamble)
1785                 if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
1786                         SET_TX_DESC_DATA_SHORT_8188GTV(ptxdesc, 1);
1787
1788         if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1789                 SET_TX_DESC_DATA_BW_8188GTV(ptxdesc, 1);
1790
1791         SET_TX_DESC_TX_RATE_8188GTV(ptxdesc, pmp_priv->rateidx);
1792
1793         SET_TX_DESC_DATA_RATE_FB_LIMIT_8188GTV(ptxdesc, 0x1F);
1794         SET_TX_DESC_RTS_RATE_FB_LIMIT_8188GTV(ptxdesc, 0xF);
1795 }
1796 #endif
1797
1798 #if defined(CONFIG_RTL8723D)
1799 void fill_tx_desc_8723d(PADAPTER padapter)
1800 {
1801         struct mp_priv *pmp_priv = &padapter->mppriv;
1802         struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1803         u8 *ptxdesc = pmp_priv->tx.desc;
1804
1805         SET_TX_DESC_BK_8723D(ptxdesc, 1);
1806         SET_TX_DESC_MACID_8723D(ptxdesc, pattrib->mac_id);
1807         SET_TX_DESC_QUEUE_SEL_8723D(ptxdesc, pattrib->qsel);
1808
1809         SET_TX_DESC_RATE_ID_8723D(ptxdesc, pattrib->raid);
1810         SET_TX_DESC_SEQ_8723D(ptxdesc, pattrib->seqnum);
1811         SET_TX_DESC_HWSEQ_EN_8723D(ptxdesc, 1);
1812         SET_TX_DESC_USE_RATE_8723D(ptxdesc, 1);
1813         SET_TX_DESC_DISABLE_FB_8723D(ptxdesc, 1);
1814
1815         if (pmp_priv->preamble) {
1816                 if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
1817                         SET_TX_DESC_DATA_SHORT_8723D(ptxdesc, 1);
1818         }
1819
1820         if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1821                 SET_TX_DESC_DATA_BW_8723D(ptxdesc, 1);
1822
1823         SET_TX_DESC_TX_RATE_8723D(ptxdesc, pmp_priv->rateidx);
1824
1825         SET_TX_DESC_DATA_RATE_FB_LIMIT_8723D(ptxdesc, 0x1F);
1826         SET_TX_DESC_RTS_RATE_FB_LIMIT_8723D(ptxdesc, 0xF);
1827 }
1828 #endif
1829
1830 #if defined(CONFIG_RTL8710B)
1831 void fill_tx_desc_8710b(PADAPTER padapter)
1832 {
1833         struct mp_priv *pmp_priv = &padapter->mppriv;
1834         struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1835         u8 *ptxdesc = pmp_priv->tx.desc;
1836
1837         SET_TX_DESC_BK_8710B(ptxdesc, 1);
1838         SET_TX_DESC_MACID_8710B(ptxdesc, pattrib->mac_id);
1839         SET_TX_DESC_QUEUE_SEL_8710B(ptxdesc, pattrib->qsel);
1840
1841         SET_TX_DESC_RATE_ID_8710B(ptxdesc, pattrib->raid);
1842         SET_TX_DESC_SEQ_8710B(ptxdesc, pattrib->seqnum);
1843         SET_TX_DESC_HWSEQ_EN_8710B(ptxdesc, 1);
1844         SET_TX_DESC_USE_RATE_8710B(ptxdesc, 1);
1845         SET_TX_DESC_DISABLE_FB_8710B(ptxdesc, 1);
1846
1847         if (pmp_priv->preamble) {
1848                 if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
1849                         SET_TX_DESC_DATA_SHORT_8710B(ptxdesc, 1);
1850         }
1851
1852         if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1853                 SET_TX_DESC_DATA_BW_8710B(ptxdesc, 1);
1854
1855         SET_TX_DESC_TX_RATE_8710B(ptxdesc, pmp_priv->rateidx);
1856
1857         SET_TX_DESC_DATA_RATE_FB_LIMIT_8710B(ptxdesc, 0x1F);
1858         SET_TX_DESC_RTS_RATE_FB_LIMIT_8710B(ptxdesc, 0xF);
1859 }
1860 #endif
1861
1862 #if defined(CONFIG_RTL8192F)
1863 void fill_tx_desc_8192f(PADAPTER padapter)
1864 {
1865         struct mp_priv *pmp_priv = &padapter->mppriv;
1866         struct pkt_attrib *pattrib = &(pmp_priv->tx.attrib);
1867         u8 *ptxdesc = pmp_priv->tx.desc;
1868
1869         SET_TX_DESC_BK_8192F(ptxdesc, 1);
1870         SET_TX_DESC_MACID_8192F(ptxdesc, pattrib->mac_id);
1871         SET_TX_DESC_QUEUE_SEL_8192F(ptxdesc, pattrib->qsel);
1872
1873         SET_TX_DESC_RATE_ID_8192F(ptxdesc, pattrib->raid);
1874         SET_TX_DESC_SEQ_8192F(ptxdesc, pattrib->seqnum);
1875         SET_TX_DESC_HWSEQ_EN_8192F(ptxdesc, 1);
1876         SET_TX_DESC_USE_RATE_8192F(ptxdesc, 1);
1877         SET_TX_DESC_DISABLE_FB_8192F(ptxdesc, 1);
1878
1879         if (pmp_priv->preamble) {
1880                 if (HwRateToMPTRate(pmp_priv->rateidx) <=  MPT_RATE_54M)
1881                         SET_TX_DESC_DATA_SHORT_8192F(ptxdesc, 1);
1882         }
1883
1884         if (pmp_priv->bandwidth == CHANNEL_WIDTH_40)
1885                 SET_TX_DESC_DATA_BW_8192F(ptxdesc, 1);
1886
1887         SET_TX_DESC_TX_RATE_8192F(ptxdesc, pmp_priv->rateidx);
1888
1889         SET_TX_DESC_DATA_RATE_FB_LIMIT_8192F(ptxdesc, 0x1F);
1890         SET_TX_DESC_RTS_RATE_FB_LIMIT_8192F(ptxdesc, 0xF);
1891 }
1892
1893 #endif
1894 static void Rtw_MPSetMacTxEDCA(PADAPTER padapter)
1895 {
1896
1897         rtw_write32(padapter, 0x508 , 0x00a422); /* Disable EDCA BE Txop for MP pkt tx adjust Packet interval */
1898         /* RTW_INFO("%s:write 0x508~~~~~~ 0x%x\n", __func__,rtw_read32(padapter, 0x508)); */
1899         phy_set_mac_reg(padapter, 0x458 , bMaskDWord , 0x0);
1900         /*RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" ,__func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));*/
1901         phy_set_mac_reg(padapter, 0x460 , bMaskLWord , 0x0); /* fast EDCA queue packet interval & time out value*/
1902         /*phy_set_mac_reg(padapter, ODM_EDCA_VO_PARAM ,bMaskLWord , 0x431C);*/
1903         /*phy_set_mac_reg(padapter, ODM_EDCA_BE_PARAM ,bMaskLWord , 0x431C);*/
1904         /*phy_set_mac_reg(padapter, ODM_EDCA_BK_PARAM ,bMaskLWord , 0x431C);*/
1905         RTW_INFO("%s()!!!!! 0x460 = 0x%x\n" , __func__, phy_query_bb_reg(padapter, 0x460, bMaskDWord));
1906
1907 }
1908
1909 void SetPacketTx(PADAPTER padapter)
1910 {
1911         u8 *ptr, *pkt_start, *pkt_end;
1912         u32 pkt_size, i;
1913         struct rtw_ieee80211_hdr *hdr;
1914         u8 payload;
1915         s32 bmcast;
1916         struct pkt_attrib *pattrib;
1917         struct mp_priv *pmp_priv;
1918
1919         pmp_priv = &padapter->mppriv;
1920
1921         if (pmp_priv->tx.stop)
1922                 return;
1923         pmp_priv->tx.sended = 0;
1924         pmp_priv->tx.stop = 0;
1925         pmp_priv->tx_pktcount = 0;
1926
1927         /* 3 1. update_attrib() */
1928         pattrib = &pmp_priv->tx.attrib;
1929         _rtw_memcpy(pattrib->src, adapter_mac_addr(padapter), ETH_ALEN);
1930         _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN);
1931         _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN);
1932         bmcast = IS_MCAST(pattrib->ra);
1933         if (bmcast)
1934                 pattrib->psta = rtw_get_bcmc_stainfo(padapter);
1935         else
1936                 pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv));
1937
1938         pattrib->mac_id = pattrib->psta->cmn.mac_id;
1939         pattrib->mbssid = 0;
1940
1941         pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen;
1942
1943         /* 3 2. allocate xmit buffer */
1944         pkt_size = pattrib->last_txcmdsz;
1945
1946         if (pmp_priv->tx.pallocated_buf)
1947                 rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size);
1948         pmp_priv->tx.write_size = pkt_size;
1949         pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ;
1950         pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size);
1951         if (pmp_priv->tx.pallocated_buf == NULL) {
1952                 RTW_INFO("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size);
1953                 return;
1954         }
1955         pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ);
1956         ptr = pmp_priv->tx.buf;
1957
1958         _rtw_memset(pmp_priv->tx.desc, 0, TXDESC_SIZE);
1959         pkt_start = ptr;
1960         pkt_end = pkt_start + pkt_size;
1961
1962         /* 3 3. init TX descriptor */
1963 #if defined(CONFIG_RTL8188E)
1964         if (IS_HARDWARE_TYPE_8188E(padapter))
1965                 fill_tx_desc_8188e(padapter);
1966 #endif
1967
1968 #if defined(CONFIG_RTL8814A)
1969         if (IS_HARDWARE_TYPE_8814A(padapter))
1970                 fill_tx_desc_8814a(padapter);
1971 #endif /* defined(CONFIG_RTL8814A) */
1972
1973 #if defined(CONFIG_RTL8822B)
1974         if (IS_HARDWARE_TYPE_8822B(padapter))
1975                 rtl8822b_prepare_mp_txdesc(padapter, pmp_priv);
1976 #endif /* CONFIG_RTL8822B */
1977
1978 #if defined(CONFIG_RTL8821C)
1979         if (IS_HARDWARE_TYPE_8821C(padapter))
1980                 rtl8821c_prepare_mp_txdesc(padapter, pmp_priv);
1981 #endif /* CONFIG_RTL8821C */
1982
1983 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A)
1984         if (IS_HARDWARE_TYPE_8812(padapter) || IS_HARDWARE_TYPE_8821(padapter))
1985                 fill_tx_desc_8812a(padapter);
1986 #endif
1987
1988 #if defined(CONFIG_RTL8192E)
1989         if (IS_HARDWARE_TYPE_8192E(padapter))
1990                 fill_tx_desc_8192e(padapter);
1991 #endif
1992 #if defined(CONFIG_RTL8723B)
1993         if (IS_HARDWARE_TYPE_8723B(padapter))
1994                 fill_tx_desc_8723b(padapter);
1995 #endif
1996 #if defined(CONFIG_RTL8703B)
1997         if (IS_HARDWARE_TYPE_8703B(padapter))
1998                 fill_tx_desc_8703b(padapter);
1999 #endif
2000
2001 #if defined(CONFIG_RTL8188F)
2002         if (IS_HARDWARE_TYPE_8188F(padapter))
2003                 fill_tx_desc_8188f(padapter);
2004 #endif
2005
2006 #if defined(CONFIG_RTL8188GTV)
2007         if (IS_HARDWARE_TYPE_8188GTV(padapter))
2008                 fill_tx_desc_8188gtv(padapter);
2009 #endif
2010
2011 #if defined(CONFIG_RTL8723D)
2012         if (IS_HARDWARE_TYPE_8723D(padapter))
2013                 fill_tx_desc_8723d(padapter);
2014 #endif
2015 #if defined(CONFIG_RTL8192F)
2016                 if (IS_HARDWARE_TYPE_8192F(padapter))
2017                         fill_tx_desc_8192f(padapter);
2018 #endif
2019
2020 #if defined(CONFIG_RTL8710B)
2021         if (IS_HARDWARE_TYPE_8710B(padapter))
2022                 fill_tx_desc_8710b(padapter);
2023 #endif
2024
2025         /* 3 4. make wlan header, make_wlanhdr() */
2026         hdr = (struct rtw_ieee80211_hdr *)pkt_start;
2027         set_frame_sub_type(&hdr->frame_ctl, pattrib->subtype);
2028
2029         _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); /* DA */
2030         _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); /* SA */
2031         _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); /* RA, BSSID */
2032
2033         /* 3 5. make payload */
2034         ptr = pkt_start + pattrib->hdrlen;
2035
2036         switch (pmp_priv->tx.payload) {
2037         case 0:
2038                 payload = 0x00;
2039                 break;
2040         case 1:
2041                 payload = 0x5a;
2042                 break;
2043         case 2:
2044                 payload = 0xa5;
2045                 break;
2046         case 3:
2047                 payload = 0xff;
2048                 break;
2049         default:
2050                 payload = 0x00;
2051                 break;
2052         }
2053         pmp_priv->TXradomBuffer = rtw_zmalloc(4096);
2054         if (pmp_priv->TXradomBuffer == NULL) {
2055                 RTW_INFO("mp create random buffer fail!\n");
2056                 goto exit;
2057         }
2058
2059
2060         for (i = 0; i < 4096; i++)
2061                 pmp_priv->TXradomBuffer[i] = rtw_random32() % 0xFF;
2062
2063         /* startPlace = (u32)(rtw_random32() % 3450); */
2064         _rtw_memcpy(ptr, pmp_priv->TXradomBuffer, pkt_end - ptr);
2065         /* _rtw_memset(ptr, payload, pkt_end - ptr); */
2066         rtw_mfree(pmp_priv->TXradomBuffer, 4096);
2067
2068         /* 3 6. start thread */
2069 #ifdef PLATFORM_LINUX
2070         pmp_priv->tx.PktTxThread = kthread_run(mp_xmit_packet_thread, pmp_priv, "RTW_MP_THREAD");
2071         if (IS_ERR(pmp_priv->tx.PktTxThread)) {
2072                 RTW_ERR("Create PktTx Thread Fail !!!!!\n");
2073                 pmp_priv->tx.PktTxThread = NULL;
2074         }
2075 #endif
2076 #ifdef PLATFORM_FREEBSD
2077         {
2078                 struct proc *p;
2079                 struct thread *td;
2080                 pmp_priv->tx.PktTxThread = kproc_kthread_add(mp_xmit_packet_thread, pmp_priv,
2081                         &p, &td, RFHIGHPID, 0, "MPXmitThread", "MPXmitThread");
2082
2083                 if (pmp_priv->tx.PktTxThread < 0)
2084                         RTW_INFO("Create PktTx Thread Fail !!!!!\n");
2085         }
2086 #endif
2087
2088         Rtw_MPSetMacTxEDCA(padapter);
2089 exit:
2090         return;
2091 }
2092
2093 void SetPacketRx(PADAPTER pAdapter, u8 bStartRx, u8 bAB)
2094 {
2095         PHAL_DATA_TYPE pHalData = GET_HAL_DATA(pAdapter);
2096         struct mp_priv *pmppriv = &pAdapter->mppriv;
2097
2098
2099         if (bStartRx) {
2100 #ifdef CONFIG_RTL8723B
2101                 phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x3); /* Power on adc  (in RX_WAIT_CCA state) */
2102                 write_bbreg(pAdapter, 0xa01, BIT0, bDisable);/* improve Rx performance by jerry  */
2103 #endif
2104                 pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AMF | RCR_HTC_LOC_CTRL;
2105                 pHalData->ReceiveConfig |= RCR_ACRC32;
2106                 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
2107
2108                 if (pmppriv->bSetRxBssid == _TRUE) {
2109                         RTW_INFO("%s: pmppriv->network_macaddr=" MAC_FMT "\n", __func__,
2110                                  MAC_ARG(pmppriv->network_macaddr));
2111                         pHalData->ReceiveConfig = 0;
2112                         pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN |RCR_APM | RCR_AM | RCR_AB |RCR_AMF;
2113                         pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF;
2114
2115 #if defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
2116                         write_bbreg(pAdapter, 0x550, BIT3, bEnable);
2117 #endif
2118                         rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFEF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
2119                         pmppriv->brx_filter_beacon = _TRUE;
2120
2121                 } else {
2122                         pHalData->ReceiveConfig |= RCR_ADF;
2123                         /* Accept all data frames */
2124                         rtw_write16(pAdapter, REG_RXFLTMAP2, 0xFFFF);
2125                 }
2126
2127                 if (bAB)
2128                         pHalData->ReceiveConfig |= RCR_AB;
2129         } else {
2130 #ifdef CONFIG_RTL8723B
2131                 phy_set_mac_reg(pAdapter, 0xe70, BIT23 | BIT22, 0x00); /* Power off adc  (in RX_WAIT_CCA state)*/
2132                 write_bbreg(pAdapter, 0xa01, BIT0, bEnable);/* improve Rx performance by jerry   */
2133 #endif
2134                 pHalData->ReceiveConfig = 0;
2135                 rtw_write16(pAdapter, REG_RXFLTMAP0, 0xFFFF); /* REG_RXFLTMAP0 (RX Filter Map Group 0) */
2136         }
2137
2138         rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig);
2139 }
2140
2141 void ResetPhyRxPktCount(PADAPTER pAdapter)
2142 {
2143         u32 i, phyrx_set = 0;
2144
2145         for (i = 0; i <= 0xF; i++) {
2146                 phyrx_set = 0;
2147                 phyrx_set |= _RXERR_RPT_SEL(i); /* select */
2148                 phyrx_set |= RXERR_RPT_RST;     /* set counter to zero */
2149                 rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
2150         }
2151 }
2152
2153 static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit)
2154 {
2155         /* selection */
2156         u32 phyrx_set = 0, count = 0;
2157
2158         phyrx_set = _RXERR_RPT_SEL(selbit & 0xF);
2159         rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set);
2160
2161         /* Read packet count */
2162         count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK;
2163
2164         return count;
2165 }
2166
2167 u32 GetPhyRxPktReceived(PADAPTER pAdapter)
2168 {
2169         u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
2170
2171         OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK);
2172         CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK);
2173         HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK);
2174
2175         return OFDM_cnt + CCK_cnt + HT_cnt;
2176 }
2177
2178 u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter)
2179 {
2180         u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0;
2181
2182         OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL);
2183         CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL);
2184         HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL);
2185
2186         return OFDM_cnt + CCK_cnt + HT_cnt;
2187 }
2188
2189 struct psd_init_regs {
2190         /* 3 wire */
2191         int reg_88c;
2192         int reg_c00;
2193         int reg_e00;
2194         int reg_1800;
2195         int reg_1a00;
2196         /* cck */
2197         int reg_800;
2198         int reg_808;
2199 };
2200
2201 static int rtw_mp_psd_init(PADAPTER padapter, struct psd_init_regs *regs)
2202 {
2203         HAL_DATA_TYPE   *phal_data      = GET_HAL_DATA(padapter);
2204
2205         switch (phal_data->rf_type) {
2206         /* 1R */
2207         case RF_1T1R:
2208                 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2209                         /* 11AC 1R PSD Setting 3wire & cck off */
2210                         regs->reg_c00 = rtw_read32(padapter, 0xC00);
2211                         phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2212                         regs->reg_808 = rtw_read32(padapter, 0x808);
2213                         phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2214                 } else {
2215                         /* 11N 3-wire off 1 */
2216                         regs->reg_88c = rtw_read32(padapter, 0x88C);
2217                         phy_set_bb_reg(padapter, 0x88C, 0x300000, 0x3);
2218                         /* 11N CCK off */
2219                         regs->reg_800 = rtw_read32(padapter, 0x800);
2220                         phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
2221                 }
2222         break;
2223
2224         /* 2R */
2225         case RF_1T2R:
2226         case RF_2T2R:
2227                 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2228                         /* 11AC 2R PSD Setting 3wire & cck off */
2229                         regs->reg_c00 = rtw_read32(padapter, 0xC00);
2230                         regs->reg_e00 = rtw_read32(padapter, 0xE00);
2231                         phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2232                         phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2233                         regs->reg_808 = rtw_read32(padapter, 0x808);
2234                         phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2235                 } else {
2236                         /* 11N 3-wire off 2 */
2237                         regs->reg_88c = rtw_read32(padapter, 0x88C);
2238                         phy_set_bb_reg(padapter, 0x88C, 0xF00000, 0xF);
2239                         /* 11N CCK off */
2240                         regs->reg_800 = rtw_read32(padapter, 0x800);
2241                         phy_set_bb_reg(padapter, 0x800, 0x1000000, 0x0);
2242                 }
2243         break;
2244
2245         /* 3R */
2246         case RF_2T3R:
2247         case RF_3T3R:
2248                 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2249                         /* 11AC 3R PSD Setting 3wire & cck off */
2250                         regs->reg_c00 = rtw_read32(padapter, 0xC00);
2251                         regs->reg_e00 = rtw_read32(padapter, 0xE00);
2252                         regs->reg_1800 = rtw_read32(padapter, 0x1800);
2253                         phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2254                         phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2255                         phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
2256                         regs->reg_808 = rtw_read32(padapter, 0x808);
2257                         phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2258                 } else {
2259                         RTW_ERR("%s: 11n don't support 3R\n", __func__);
2260                         return -1;
2261                 }
2262                 break;
2263
2264         /* 4R */
2265         case RF_2T4R:
2266         case RF_3T4R:
2267         case RF_4T4R:
2268                 if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2269                         /* 11AC 4R PSD Setting 3wire & cck off */
2270                         regs->reg_c00 = rtw_read32(padapter, 0xC00);
2271                         regs->reg_e00 = rtw_read32(padapter, 0xE00);
2272                         regs->reg_1800 = rtw_read32(padapter, 0x1800);
2273                         regs->reg_1a00 = rtw_read32(padapter, 0x1A00);
2274                         phy_set_bb_reg(padapter, 0xC00, 0x3, 0x00);
2275                         phy_set_bb_reg(padapter, 0xE00, 0x3, 0x00);
2276                         phy_set_bb_reg(padapter, 0x1800, 0x3, 0x00);
2277                         phy_set_bb_reg(padapter, 0x1A00, 0x3, 0x00);
2278                         regs->reg_808 = rtw_read32(padapter, 0x808);
2279                         phy_set_bb_reg(padapter, 0x808, 0x10000000, 0x0);
2280                 } else {
2281                         RTW_ERR("%s: 11n don't support 4R\n", __func__);
2282                         return -1;
2283                 }
2284                 break;
2285
2286         default:
2287                 RTW_ERR("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
2288                 return -1;
2289         }
2290
2291         /* Set PSD points, 0=128, 1=256, 2=512, 3=1024 */
2292         if (hal_chk_proto_cap(padapter, PROTO_CAP_11AC))
2293                 phy_set_bb_reg(padapter, 0x910, 0xC000, 3);
2294         else
2295                 phy_set_bb_reg(padapter, 0x808, 0xC000, 3);
2296
2297         RTW_INFO("%s: set %d rf type done\n", __func__, phal_data->rf_type);
2298         return 0;
2299 }
2300
2301 static int rtw_mp_psd_close(PADAPTER padapter, struct psd_init_regs *regs)
2302 {
2303         HAL_DATA_TYPE   *phal_data      = GET_HAL_DATA(padapter);
2304
2305
2306         if (!hal_chk_proto_cap(padapter, PROTO_CAP_11AC)) {
2307                 /* 11n 3wire restore */
2308                 rtw_write32(padapter, 0x88C, regs->reg_88c);
2309                 /* 11n cck restore */
2310                 rtw_write32(padapter, 0x800, regs->reg_800);
2311                 RTW_INFO("%s: restore %d rf type\n", __func__, phal_data->rf_type);
2312                 return 0;
2313         }
2314
2315         /* 11ac 3wire restore */
2316         switch (phal_data->rf_type) {
2317         case RF_1T1R:
2318                 rtw_write32(padapter, 0xC00, regs->reg_c00);
2319                 break;
2320         case RF_1T2R:
2321         case RF_2T2R:
2322                 rtw_write32(padapter, 0xC00, regs->reg_c00);
2323                 rtw_write32(padapter, 0xE00, regs->reg_e00);
2324                 break;
2325         case RF_2T3R:
2326         case RF_3T3R:
2327                 rtw_write32(padapter, 0xC00, regs->reg_c00);
2328                 rtw_write32(padapter, 0xE00, regs->reg_e00);
2329                 rtw_write32(padapter, 0x1800, regs->reg_1800);
2330                 break;
2331         case RF_2T4R:
2332         case RF_3T4R:
2333         case RF_4T4R:
2334                 rtw_write32(padapter, 0xC00, regs->reg_c00);
2335                 rtw_write32(padapter, 0xE00, regs->reg_e00);
2336                 rtw_write32(padapter, 0x1800, regs->reg_1800);
2337                 rtw_write32(padapter, 0x1A00, regs->reg_1a00);
2338                 break;
2339         default:
2340                 RTW_WARN("%s: unknown %d rf type\n", __func__, phal_data->rf_type);
2341                 break;
2342         }
2343
2344         /* 11ac cck restore */
2345         rtw_write32(padapter, 0x808, regs->reg_808);
2346         RTW_INFO("%s: restore %d rf type done\n", __func__, phal_data->rf_type);
2347         return 0;
2348 }
2349
2350 /* reg 0x808[9:0]: FFT data x
2351  * reg 0x808[22]:  0  -->  1  to get 1 FFT data y
2352  * reg 0x8B4[15:0]: FFT data y report */
2353 static u32 rtw_GetPSDData(PADAPTER pAdapter, u32 point)
2354 {
2355         u32 psd_val = 0;
2356
2357 #if defined(CONFIG_RTL8812A) || defined(CONFIG_RTL8821A) || defined(CONFIG_RTL8814A) || defined(CONFIG_RTL8822B) || defined(CONFIG_RTL8821C)
2358         u16 psd_reg = 0x910;
2359         u16 psd_regL = 0xF44;
2360 #else
2361         u16 psd_reg = 0x808;
2362         u16 psd_regL = 0x8B4;
2363 #endif
2364
2365         psd_val = rtw_read32(pAdapter, psd_reg);
2366
2367         psd_val &= 0xFFBFFC00;
2368         psd_val |= point;
2369
2370         rtw_write32(pAdapter, psd_reg, psd_val);
2371         rtw_mdelay_os(1);
2372         psd_val |= 0x00400000;
2373
2374         rtw_write32(pAdapter, psd_reg, psd_val);
2375         rtw_mdelay_os(1);
2376
2377         psd_val = rtw_read32(pAdapter, psd_regL);
2378 #if defined(CONFIG_RTL8821C)
2379         psd_val = (psd_val & 0x00FFFFFF) / 32;
2380 #else
2381         psd_val &= 0x0000FFFF;
2382 #endif
2383
2384         return psd_val;
2385 }
2386
2387 /*
2388  * pts  start_point_min         stop_point_max
2389  * 128  64                      64 + 128 = 192
2390  * 256  128                     128 + 256 = 384
2391  * 512  256                     256 + 512 = 768
2392  * 1024 512                     512 + 1024 = 1536
2393  *
2394  */
2395 u32 mp_query_psd(PADAPTER pAdapter, u8 *data)
2396 {
2397         u32 i, psd_pts = 0, psd_start = 0, psd_stop = 0;
2398         u32 psd_data = 0;
2399         struct psd_init_regs regs = {};
2400         int psd_analysis = 0;
2401
2402 #ifdef PLATFORM_LINUX
2403         if (!netif_running(pAdapter->pnetdev)) {
2404                 return 0;
2405         }
2406 #endif
2407
2408         if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) {
2409                 return 0;
2410         }
2411
2412         if (strlen(data) == 0) { /* default value */
2413                 psd_pts = 128;
2414                 psd_start = 64;
2415                 psd_stop = 128;
2416         } else if (strncmp(data, "analysis,", 9) == 0) {
2417                 if (rtw_mp_psd_init(pAdapter, &regs) != 0)
2418                         return 0;
2419                 psd_analysis = 1;
2420                 sscanf(data + 9, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
2421         } else
2422                 sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop);
2423
2424         data[0] = '\0';
2425
2426         i = psd_start;
2427         while (i < psd_stop) {
2428                 if (i >= psd_pts)
2429                         psd_data = rtw_GetPSDData(pAdapter, i - psd_pts);
2430                 else
2431                         psd_data = rtw_GetPSDData(pAdapter, i);
2432                 sprintf(data, "%s%x ", data, psd_data);
2433                 i++;
2434         }
2435
2436 #ifdef CONFIG_LONG_DELAY_ISSUE
2437         rtw_msleep_os(100);
2438 #else
2439         rtw_mdelay_os(100);
2440 #endif
2441
2442         if (psd_analysis)
2443                 rtw_mp_psd_close(pAdapter, &regs);
2444
2445         return strlen(data) + 1;
2446 }
2447
2448
2449 #if 0
2450 void _rtw_mp_xmit_priv(struct xmit_priv *pxmitpriv)
2451 {
2452         int i, res;
2453         _adapter *padapter = pxmitpriv->adapter;
2454         struct xmit_frame       *pxmitframe = (struct xmit_frame *) pxmitpriv->pxmit_frame_buf;
2455         struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf;
2456
2457         u32 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2458         u32 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2459         if (padapter->registrypriv.mp_mode == 0) {
2460                 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2461                 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2462         } else {
2463                 max_xmit_extbuf_size = 6000;
2464                 num_xmit_extbuf = 8;
2465         }
2466
2467         pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
2468         for (i = 0; i < num_xmit_extbuf; i++) {
2469                 rtw_os_xmit_resource_free(padapter, pxmitbuf, (max_xmit_extbuf_size + XMITBUF_ALIGN_SZ), _FALSE);
2470
2471                 pxmitbuf++;
2472         }
2473
2474         if (pxmitpriv->pallocated_xmit_extbuf)
2475                 rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
2476
2477         if (padapter->registrypriv.mp_mode == 0) {
2478                 max_xmit_extbuf_size = 6000;
2479                 num_xmit_extbuf = 8;
2480         } else {
2481                 max_xmit_extbuf_size = MAX_XMIT_EXTBUF_SZ;
2482                 num_xmit_extbuf = NR_XMIT_EXTBUFF;
2483         }
2484
2485         /* Init xmit extension buff */
2486         _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue);
2487
2488         pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(num_xmit_extbuf * sizeof(struct xmit_buf) + 4);
2489
2490         if (pxmitpriv->pallocated_xmit_extbuf  == NULL) {
2491                 res = _FAIL;
2492                 goto exit;
2493         }
2494
2495         pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4);
2496
2497         pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf;
2498
2499         for (i = 0; i < num_xmit_extbuf; i++) {
2500                 _rtw_init_listhead(&pxmitbuf->list);
2501
2502                 pxmitbuf->priv_data = NULL;
2503                 pxmitbuf->padapter = padapter;
2504                 pxmitbuf->buf_tag = XMITBUF_MGNT;
2505
2506                 res = rtw_os_xmit_resource_alloc(padapter, pxmitbuf, max_xmit_extbuf_size + XMITBUF_ALIGN_SZ, _TRUE);
2507                 if (res == _FAIL) {
2508                         res = _FAIL;
2509                         goto exit;
2510                 }
2511
2512 #if defined(CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
2513                 pxmitbuf->phead = pxmitbuf->pbuf;
2514                 pxmitbuf->pend = pxmitbuf->pbuf + max_xmit_extbuf_size;
2515                 pxmitbuf->len = 0;
2516                 pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->phead;
2517 #endif
2518
2519                 rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue));
2520 #ifdef DBG_XMIT_BUF_EXT
2521                 pxmitbuf->no = i;
2522 #endif
2523                 pxmitbuf++;
2524
2525         }
2526
2527         pxmitpriv->free_xmit_extbuf_cnt = num_xmit_extbuf;
2528
2529 exit:
2530         ;
2531 }
2532 #endif
2533
2534 u8
2535 mpt_to_mgnt_rate(
2536         IN      ULONG   MptRateIdx
2537 )
2538 {
2539         /* Mapped to MGN_XXX defined in MgntGen.h */
2540         switch (MptRateIdx) {
2541         /* CCK rate. */
2542         case    MPT_RATE_1M:
2543                 return MGN_1M;
2544         case    MPT_RATE_2M:
2545                 return MGN_2M;
2546         case    MPT_RATE_55M:
2547                 return MGN_5_5M;
2548         case    MPT_RATE_11M:
2549                 return MGN_11M;
2550
2551         /* OFDM rate. */
2552         case    MPT_RATE_6M:
2553                 return MGN_6M;
2554         case    MPT_RATE_9M:
2555                 return MGN_9M;
2556         case    MPT_RATE_12M:
2557                 return MGN_12M;
2558         case    MPT_RATE_18M:
2559                 return MGN_18M;
2560         case    MPT_RATE_24M:
2561                 return MGN_24M;
2562         case    MPT_RATE_36M:
2563                 return MGN_36M;
2564         case    MPT_RATE_48M:
2565                 return MGN_48M;
2566         case    MPT_RATE_54M:
2567                 return MGN_54M;
2568
2569         /* HT rate. */
2570         case    MPT_RATE_MCS0:
2571                 return MGN_MCS0;
2572         case    MPT_RATE_MCS1:
2573                 return MGN_MCS1;
2574         case    MPT_RATE_MCS2:
2575                 return MGN_MCS2;
2576         case    MPT_RATE_MCS3:
2577                 return MGN_MCS3;
2578         case    MPT_RATE_MCS4:
2579                 return MGN_MCS4;
2580         case    MPT_RATE_MCS5:
2581                 return MGN_MCS5;
2582         case    MPT_RATE_MCS6:
2583                 return MGN_MCS6;
2584         case    MPT_RATE_MCS7:
2585                 return MGN_MCS7;
2586         case    MPT_RATE_MCS8:
2587                 return MGN_MCS8;
2588         case    MPT_RATE_MCS9:
2589                 return MGN_MCS9;
2590         case    MPT_RATE_MCS10:
2591                 return MGN_MCS10;
2592         case    MPT_RATE_MCS11:
2593                 return MGN_MCS11;
2594         case    MPT_RATE_MCS12:
2595                 return MGN_MCS12;
2596         case    MPT_RATE_MCS13:
2597                 return MGN_MCS13;
2598         case    MPT_RATE_MCS14:
2599                 return MGN_MCS14;
2600         case    MPT_RATE_MCS15:
2601                 return MGN_MCS15;
2602         case    MPT_RATE_MCS16:
2603                 return MGN_MCS16;
2604         case    MPT_RATE_MCS17:
2605                 return MGN_MCS17;
2606         case    MPT_RATE_MCS18:
2607                 return MGN_MCS18;
2608         case    MPT_RATE_MCS19:
2609                 return MGN_MCS19;
2610         case    MPT_RATE_MCS20:
2611                 return MGN_MCS20;
2612         case    MPT_RATE_MCS21:
2613                 return MGN_MCS21;
2614         case    MPT_RATE_MCS22:
2615                 return MGN_MCS22;
2616         case    MPT_RATE_MCS23:
2617                 return MGN_MCS23;
2618         case    MPT_RATE_MCS24:
2619                 return MGN_MCS24;
2620         case    MPT_RATE_MCS25:
2621                 return MGN_MCS25;
2622         case    MPT_RATE_MCS26:
2623                 return MGN_MCS26;
2624         case    MPT_RATE_MCS27:
2625                 return MGN_MCS27;
2626         case    MPT_RATE_MCS28:
2627                 return MGN_MCS28;
2628         case    MPT_RATE_MCS29:
2629                 return MGN_MCS29;
2630         case    MPT_RATE_MCS30:
2631                 return MGN_MCS30;
2632         case    MPT_RATE_MCS31:
2633                 return MGN_MCS31;
2634
2635         /* VHT rate. */
2636         case    MPT_RATE_VHT1SS_MCS0:
2637                 return MGN_VHT1SS_MCS0;
2638         case    MPT_RATE_VHT1SS_MCS1:
2639                 return MGN_VHT1SS_MCS1;
2640         case    MPT_RATE_VHT1SS_MCS2:
2641                 return MGN_VHT1SS_MCS2;
2642         case    MPT_RATE_VHT1SS_MCS3:
2643                 return MGN_VHT1SS_MCS3;
2644         case    MPT_RATE_VHT1SS_MCS4:
2645                 return MGN_VHT1SS_MCS4;
2646         case    MPT_RATE_VHT1SS_MCS5:
2647                 return MGN_VHT1SS_MCS5;
2648         case    MPT_RATE_VHT1SS_MCS6:
2649                 return MGN_VHT1SS_MCS6;
2650         case    MPT_RATE_VHT1SS_MCS7:
2651                 return MGN_VHT1SS_MCS7;
2652         case    MPT_RATE_VHT1SS_MCS8:
2653                 return MGN_VHT1SS_MCS8;
2654         case    MPT_RATE_VHT1SS_MCS9:
2655                 return MGN_VHT1SS_MCS9;
2656         case    MPT_RATE_VHT2SS_MCS0:
2657                 return MGN_VHT2SS_MCS0;
2658         case    MPT_RATE_VHT2SS_MCS1:
2659                 return MGN_VHT2SS_MCS1;
2660         case    MPT_RATE_VHT2SS_MCS2:
2661                 return MGN_VHT2SS_MCS2;
2662         case    MPT_RATE_VHT2SS_MCS3:
2663                 return MGN_VHT2SS_MCS3;
2664         case    MPT_RATE_VHT2SS_MCS4:
2665                 return MGN_VHT2SS_MCS4;
2666         case    MPT_RATE_VHT2SS_MCS5:
2667                 return MGN_VHT2SS_MCS5;
2668         case    MPT_RATE_VHT2SS_MCS6:
2669                 return MGN_VHT2SS_MCS6;
2670         case    MPT_RATE_VHT2SS_MCS7:
2671                 return MGN_VHT2SS_MCS7;
2672         case    MPT_RATE_VHT2SS_MCS8:
2673                 return MGN_VHT2SS_MCS8;
2674         case    MPT_RATE_VHT2SS_MCS9:
2675                 return MGN_VHT2SS_MCS9;
2676         case    MPT_RATE_VHT3SS_MCS0:
2677                 return MGN_VHT3SS_MCS0;
2678         case    MPT_RATE_VHT3SS_MCS1:
2679                 return MGN_VHT3SS_MCS1;
2680         case    MPT_RATE_VHT3SS_MCS2:
2681                 return MGN_VHT3SS_MCS2;
2682         case    MPT_RATE_VHT3SS_MCS3:
2683                 return MGN_VHT3SS_MCS3;
2684         case    MPT_RATE_VHT3SS_MCS4:
2685                 return MGN_VHT3SS_MCS4;
2686         case    MPT_RATE_VHT3SS_MCS5:
2687                 return MGN_VHT3SS_MCS5;
2688         case    MPT_RATE_VHT3SS_MCS6:
2689                 return MGN_VHT3SS_MCS6;
2690         case    MPT_RATE_VHT3SS_MCS7:
2691                 return MGN_VHT3SS_MCS7;
2692         case    MPT_RATE_VHT3SS_MCS8:
2693                 return MGN_VHT3SS_MCS8;
2694         case    MPT_RATE_VHT3SS_MCS9:
2695                 return MGN_VHT3SS_MCS9;
2696         case    MPT_RATE_VHT4SS_MCS0:
2697                 return MGN_VHT4SS_MCS0;
2698         case    MPT_RATE_VHT4SS_MCS1:
2699                 return MGN_VHT4SS_MCS1;
2700         case    MPT_RATE_VHT4SS_MCS2:
2701                 return MGN_VHT4SS_MCS2;
2702         case    MPT_RATE_VHT4SS_MCS3:
2703                 return MGN_VHT4SS_MCS3;
2704         case    MPT_RATE_VHT4SS_MCS4:
2705                 return MGN_VHT4SS_MCS4;
2706         case    MPT_RATE_VHT4SS_MCS5:
2707                 return MGN_VHT4SS_MCS5;
2708         case    MPT_RATE_VHT4SS_MCS6:
2709                 return MGN_VHT4SS_MCS6;
2710         case    MPT_RATE_VHT4SS_MCS7:
2711                 return MGN_VHT4SS_MCS7;
2712         case    MPT_RATE_VHT4SS_MCS8:
2713                 return MGN_VHT4SS_MCS8;
2714         case    MPT_RATE_VHT4SS_MCS9:
2715                 return MGN_VHT4SS_MCS9;
2716
2717         case    MPT_RATE_LAST:  /* fully automatiMGN_VHT2SS_MCS1;        */
2718         default:
2719                 RTW_INFO("<===mpt_to_mgnt_rate(), Invalid Rate: %d!!\n", MptRateIdx);
2720                 return 0x0;
2721         }
2722 }
2723
2724
2725 u8 HwRateToMPTRate(u8 rate)
2726 {
2727         u8      ret_rate = MGN_1M;
2728
2729         switch (rate) {
2730         case DESC_RATE1M:
2731                 ret_rate = MPT_RATE_1M;
2732                 break;
2733         case DESC_RATE2M:
2734                 ret_rate = MPT_RATE_2M;
2735                 break;
2736         case DESC_RATE5_5M:
2737                 ret_rate = MPT_RATE_55M;
2738                 break;
2739         case DESC_RATE11M:
2740                 ret_rate = MPT_RATE_11M;
2741                 break;
2742         case DESC_RATE6M:
2743                 ret_rate = MPT_RATE_6M;
2744                 break;
2745         case DESC_RATE9M:
2746                 ret_rate = MPT_RATE_9M;
2747                 break;
2748         case DESC_RATE12M:
2749                 ret_rate = MPT_RATE_12M;
2750                 break;
2751         case DESC_RATE18M:
2752                 ret_rate = MPT_RATE_18M;
2753                 break;
2754         case DESC_RATE24M:
2755                 ret_rate = MPT_RATE_24M;
2756                 break;
2757         case DESC_RATE36M:
2758                 ret_rate = MPT_RATE_36M;
2759                 break;
2760         case DESC_RATE48M:
2761                 ret_rate = MPT_RATE_48M;
2762                 break;
2763         case DESC_RATE54M:
2764                 ret_rate = MPT_RATE_54M;
2765                 break;
2766         case DESC_RATEMCS0:
2767                 ret_rate = MPT_RATE_MCS0;
2768                 break;
2769         case DESC_RATEMCS1:
2770                 ret_rate = MPT_RATE_MCS1;
2771                 break;
2772         case DESC_RATEMCS2:
2773                 ret_rate = MPT_RATE_MCS2;
2774                 break;
2775         case DESC_RATEMCS3:
2776                 ret_rate = MPT_RATE_MCS3;
2777                 break;
2778         case DESC_RATEMCS4:
2779                 ret_rate = MPT_RATE_MCS4;
2780                 break;
2781         case DESC_RATEMCS5:
2782                 ret_rate = MPT_RATE_MCS5;
2783                 break;
2784         case DESC_RATEMCS6:
2785                 ret_rate = MPT_RATE_MCS6;
2786                 break;
2787         case DESC_RATEMCS7:
2788                 ret_rate = MPT_RATE_MCS7;
2789                 break;
2790         case DESC_RATEMCS8:
2791                 ret_rate = MPT_RATE_MCS8;
2792                 break;
2793         case DESC_RATEMCS9:
2794                 ret_rate = MPT_RATE_MCS9;
2795                 break;
2796         case DESC_RATEMCS10:
2797                 ret_rate = MPT_RATE_MCS10;
2798                 break;
2799         case DESC_RATEMCS11:
2800                 ret_rate = MPT_RATE_MCS11;
2801                 break;
2802         case DESC_RATEMCS12:
2803                 ret_rate = MPT_RATE_MCS12;
2804                 break;
2805         case DESC_RATEMCS13:
2806                 ret_rate = MPT_RATE_MCS13;
2807                 break;
2808         case DESC_RATEMCS14:
2809                 ret_rate = MPT_RATE_MCS14;
2810                 break;
2811         case DESC_RATEMCS15:
2812                 ret_rate = MPT_RATE_MCS15;
2813                 break;
2814         case DESC_RATEMCS16:
2815                 ret_rate = MPT_RATE_MCS16;
2816                 break;
2817         case DESC_RATEMCS17:
2818                 ret_rate = MPT_RATE_MCS17;
2819                 break;
2820         case DESC_RATEMCS18:
2821                 ret_rate = MPT_RATE_MCS18;
2822                 break;
2823         case DESC_RATEMCS19:
2824                 ret_rate = MPT_RATE_MCS19;
2825                 break;
2826         case DESC_RATEMCS20:
2827                 ret_rate = MPT_RATE_MCS20;
2828                 break;
2829         case DESC_RATEMCS21:
2830                 ret_rate = MPT_RATE_MCS21;
2831                 break;
2832         case DESC_RATEMCS22:
2833                 ret_rate = MPT_RATE_MCS22;
2834                 break;
2835         case DESC_RATEMCS23:
2836                 ret_rate = MPT_RATE_MCS23;
2837                 break;
2838         case DESC_RATEMCS24:
2839                 ret_rate = MPT_RATE_MCS24;
2840                 break;
2841         case DESC_RATEMCS25:
2842                 ret_rate = MPT_RATE_MCS25;
2843                 break;
2844         case DESC_RATEMCS26:
2845                 ret_rate = MPT_RATE_MCS26;
2846                 break;
2847         case DESC_RATEMCS27:
2848                 ret_rate = MPT_RATE_MCS27;
2849                 break;
2850         case DESC_RATEMCS28:
2851                 ret_rate = MPT_RATE_MCS28;
2852                 break;
2853         case DESC_RATEMCS29:
2854                 ret_rate = MPT_RATE_MCS29;
2855                 break;
2856         case DESC_RATEMCS30:
2857                 ret_rate = MPT_RATE_MCS30;
2858                 break;
2859         case DESC_RATEMCS31:
2860                 ret_rate = MPT_RATE_MCS31;
2861                 break;
2862         case DESC_RATEVHTSS1MCS0:
2863                 ret_rate = MPT_RATE_VHT1SS_MCS0;
2864                 break;
2865         case DESC_RATEVHTSS1MCS1:
2866                 ret_rate = MPT_RATE_VHT1SS_MCS1;
2867                 break;
2868         case DESC_RATEVHTSS1MCS2:
2869                 ret_rate = MPT_RATE_VHT1SS_MCS2;
2870                 break;
2871         case DESC_RATEVHTSS1MCS3:
2872                 ret_rate = MPT_RATE_VHT1SS_MCS3;
2873                 break;
2874         case DESC_RATEVHTSS1MCS4:
2875                 ret_rate = MPT_RATE_VHT1SS_MCS4;
2876                 break;
2877         case DESC_RATEVHTSS1MCS5:
2878                 ret_rate = MPT_RATE_VHT1SS_MCS5;
2879                 break;
2880         case DESC_RATEVHTSS1MCS6:
2881                 ret_rate = MPT_RATE_VHT1SS_MCS6;
2882                 break;
2883         case DESC_RATEVHTSS1MCS7:
2884                 ret_rate = MPT_RATE_VHT1SS_MCS7;
2885                 break;
2886         case DESC_RATEVHTSS1MCS8:
2887                 ret_rate = MPT_RATE_VHT1SS_MCS8;
2888                 break;
2889         case DESC_RATEVHTSS1MCS9:
2890                 ret_rate = MPT_RATE_VHT1SS_MCS9;
2891                 break;
2892         case DESC_RATEVHTSS2MCS0:
2893                 ret_rate = MPT_RATE_VHT2SS_MCS0;
2894                 break;
2895         case DESC_RATEVHTSS2MCS1:
2896                 ret_rate = MPT_RATE_VHT2SS_MCS1;
2897                 break;
2898         case DESC_RATEVHTSS2MCS2:
2899                 ret_rate = MPT_RATE_VHT2SS_MCS2;
2900                 break;
2901         case DESC_RATEVHTSS2MCS3:
2902                 ret_rate = MPT_RATE_VHT2SS_MCS3;
2903                 break;
2904         case DESC_RATEVHTSS2MCS4:
2905                 ret_rate = MPT_RATE_VHT2SS_MCS4;
2906                 break;
2907         case DESC_RATEVHTSS2MCS5:
2908                 ret_rate = MPT_RATE_VHT2SS_MCS5;
2909                 break;
2910         case DESC_RATEVHTSS2MCS6:
2911                 ret_rate = MPT_RATE_VHT2SS_MCS6;
2912                 break;
2913         case DESC_RATEVHTSS2MCS7:
2914                 ret_rate = MPT_RATE_VHT2SS_MCS7;
2915                 break;
2916         case DESC_RATEVHTSS2MCS8:
2917                 ret_rate = MPT_RATE_VHT2SS_MCS8;
2918                 break;
2919         case DESC_RATEVHTSS2MCS9:
2920                 ret_rate = MPT_RATE_VHT2SS_MCS9;
2921                 break;
2922         case DESC_RATEVHTSS3MCS0:
2923                 ret_rate = MPT_RATE_VHT3SS_MCS0;
2924                 break;
2925         case DESC_RATEVHTSS3MCS1:
2926                 ret_rate = MPT_RATE_VHT3SS_MCS1;
2927                 break;
2928         case DESC_RATEVHTSS3MCS2:
2929                 ret_rate = MPT_RATE_VHT3SS_MCS2;
2930                 break;
2931         case DESC_RATEVHTSS3MCS3:
2932                 ret_rate = MPT_RATE_VHT3SS_MCS3;
2933                 break;
2934         case DESC_RATEVHTSS3MCS4:
2935                 ret_rate = MPT_RATE_VHT3SS_MCS4;
2936                 break;
2937         case DESC_RATEVHTSS3MCS5:
2938                 ret_rate = MPT_RATE_VHT3SS_MCS5;
2939                 break;
2940         case DESC_RATEVHTSS3MCS6:
2941                 ret_rate = MPT_RATE_VHT3SS_MCS6;
2942                 break;
2943         case DESC_RATEVHTSS3MCS7:
2944                 ret_rate = MPT_RATE_VHT3SS_MCS7;
2945                 break;
2946         case DESC_RATEVHTSS3MCS8:
2947                 ret_rate = MPT_RATE_VHT3SS_MCS8;
2948                 break;
2949         case DESC_RATEVHTSS3MCS9:
2950                 ret_rate = MPT_RATE_VHT3SS_MCS9;
2951                 break;
2952         case DESC_RATEVHTSS4MCS0:
2953                 ret_rate = MPT_RATE_VHT4SS_MCS0;
2954                 break;
2955         case DESC_RATEVHTSS4MCS1:
2956                 ret_rate = MPT_RATE_VHT4SS_MCS1;
2957                 break;
2958         case DESC_RATEVHTSS4MCS2:
2959                 ret_rate = MPT_RATE_VHT4SS_MCS2;
2960                 break;
2961         case DESC_RATEVHTSS4MCS3:
2962                 ret_rate = MPT_RATE_VHT4SS_MCS3;
2963                 break;
2964         case DESC_RATEVHTSS4MCS4:
2965                 ret_rate = MPT_RATE_VHT4SS_MCS4;
2966                 break;
2967         case DESC_RATEVHTSS4MCS5:
2968                 ret_rate = MPT_RATE_VHT4SS_MCS5;
2969                 break;
2970         case DESC_RATEVHTSS4MCS6:
2971                 ret_rate = MPT_RATE_VHT4SS_MCS6;
2972                 break;
2973         case DESC_RATEVHTSS4MCS7:
2974                 ret_rate = MPT_RATE_VHT4SS_MCS7;
2975                 break;
2976         case DESC_RATEVHTSS4MCS8:
2977                 ret_rate = MPT_RATE_VHT4SS_MCS8;
2978                 break;
2979         case DESC_RATEVHTSS4MCS9:
2980                 ret_rate = MPT_RATE_VHT4SS_MCS9;
2981                 break;
2982
2983         default:
2984                 RTW_INFO("hw_rate_to_m_rate(): Non supported Rate [%x]!!!\n", rate);
2985                 break;
2986         }
2987         return ret_rate;
2988 }
2989
2990 u8 rtw_mpRateParseFunc(PADAPTER pAdapter, u8 *targetStr)
2991 {
2992         u16 i = 0;
2993         u8 *rateindex_Array[] = { "1M", "2M", "5.5M", "11M", "6M", "9M", "12M", "18M", "24M", "36M", "48M", "54M",
2994                 "HTMCS0", "HTMCS1", "HTMCS2", "HTMCS3", "HTMCS4", "HTMCS5", "HTMCS6", "HTMCS7",
2995                 "HTMCS8", "HTMCS9", "HTMCS10", "HTMCS11", "HTMCS12", "HTMCS13", "HTMCS14", "HTMCS15",
2996                 "HTMCS16", "HTMCS17", "HTMCS18", "HTMCS19", "HTMCS20", "HTMCS21", "HTMCS22", "HTMCS23",
2997                 "HTMCS24", "HTMCS25", "HTMCS26", "HTMCS27", "HTMCS28", "HTMCS29", "HTMCS30", "HTMCS31",
2998                 "VHT1MCS0", "VHT1MCS1", "VHT1MCS2", "VHT1MCS3", "VHT1MCS4", "VHT1MCS5", "VHT1MCS6", "VHT1MCS7", "VHT1MCS8", "VHT1MCS9",
2999                 "VHT2MCS0", "VHT2MCS1", "VHT2MCS2", "VHT2MCS3", "VHT2MCS4", "VHT2MCS5", "VHT2MCS6", "VHT2MCS7", "VHT2MCS8", "VHT2MCS9",
3000                 "VHT3MCS0", "VHT3MCS1", "VHT3MCS2", "VHT3MCS3", "VHT3MCS4", "VHT3MCS5", "VHT3MCS6", "VHT3MCS7", "VHT3MCS8", "VHT3MCS9",
3001                 "VHT4MCS0", "VHT4MCS1", "VHT4MCS2", "VHT4MCS3", "VHT4MCS4", "VHT4MCS5", "VHT4MCS6", "VHT4MCS7", "VHT4MCS8", "VHT4MCS9"
3002                                 };
3003
3004         for (i = 0; i <= 83; i++) {
3005                 if (strcmp(targetStr, rateindex_Array[i]) == 0) {
3006                         RTW_INFO("%s , index = %d\n", __func__ , i);
3007                         return i;
3008                 }
3009         }
3010
3011         printk("%s ,please input a Data RATE String as:", __func__);
3012         for (i = 0; i <= 83; i++) {
3013                 printk("%s ", rateindex_Array[i]);
3014                 if (i % 10 == 0)
3015                         printk("\n");
3016         }
3017         return _FAIL;
3018 }
3019
3020 u8 rtw_mp_mode_check(PADAPTER pAdapter)
3021 {
3022         PADAPTER primary_adapter = GET_PRIMARY_ADAPTER(pAdapter);
3023
3024         if (primary_adapter->registrypriv.mp_mode == 1)
3025                 return _TRUE;
3026         else
3027                 return _FALSE;
3028 }
3029
3030
3031 ULONG mpt_ProQueryCalTxPower(
3032         PADAPTER        pAdapter,
3033         u8              RfPath
3034 )
3035 {
3036
3037         HAL_DATA_TYPE   *pHalData       = GET_HAL_DATA(pAdapter);
3038         PMPT_CONTEXT            pMptCtx = &(pAdapter->mppriv.mpt_ctx);
3039
3040         ULONG                   TxPower = 1;
3041         struct txpwr_idx_comp tic;
3042         u8 mgn_rate = mpt_to_mgnt_rate(pMptCtx->mpt_rate_index);
3043
3044         TxPower = rtw_hal_get_tx_power_index(pAdapter, RfPath, mgn_rate, pHalData->current_channel_bw, pHalData->current_channel, &tic);
3045
3046         RTW_INFO("bw=%d, ch=%d, rate=%d, txPower:%u = %u + (%d=%d:%d) + (%d) + (%d)\n",
3047                 pHalData->current_channel_bw, pHalData->current_channel, mgn_rate
3048                 , TxPower, tic.base, (tic.by_rate > tic.limit ? tic.limit : tic.by_rate), tic.by_rate, tic.limit, tic.tpt, tic.ebias);
3049
3050         pAdapter->mppriv.txpoweridx = (u8)TxPower;
3051         if (RfPath == RF_PATH_A)
3052                 pMptCtx->TxPwrLevel[RF_PATH_A] = (u8)TxPower;
3053         else if (RfPath == RF_PATH_B)
3054                 pMptCtx->TxPwrLevel[RF_PATH_B] = (u8)TxPower;
3055         else if (RfPath == RF_PATH_C)
3056                 pMptCtx->TxPwrLevel[RF_PATH_C] = (u8)TxPower;
3057         else if (RfPath == RF_PATH_D)
3058                 pMptCtx->TxPwrLevel[RF_PATH_D]    = (u8)TxPower;
3059         hal_mpt_SetTxPower(pAdapter);
3060
3061         return TxPower;
3062 }
3063
3064 #ifdef CONFIG_MP_VHT_HW_TX_MODE
3065 static inline void dump_buf(u8 *buf, u32 len)
3066 {
3067         u32 i;
3068
3069         RTW_INFO("-----------------Len %d----------------\n", len);
3070         for (i = 0; i < len; i++)
3071                 RTW_INFO("%2.2x-", *(buf + i));
3072         RTW_INFO("\n");
3073 }
3074
3075 void ByteToBit(
3076         UCHAR   *out,
3077         bool    *in,
3078         UCHAR   in_size)
3079 {
3080         UCHAR i = 0, j = 0;
3081
3082         for (i = 0; i < in_size; i++) {
3083                 for (j = 0; j < 8; j++) {
3084                         if (in[8 * i + j])
3085                                 out[i] |= (1 << j);
3086                 }
3087         }
3088 }
3089
3090
3091 void CRC16_generator(
3092         bool *out,
3093         bool *in,
3094         UCHAR in_size
3095 )
3096 {
3097         UCHAR i = 0;
3098         bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1};
3099
3100         for (i = 0; i < in_size; i++) {/* take one's complement and bit reverse*/
3101                 temp = in[i] ^ reg[15];
3102                 reg[15] = reg[14];
3103                 reg[14] = reg[13];
3104                 reg[13] = reg[12];
3105                 reg[12] = reg[11];
3106                 reg[11] = reg[10];
3107                 reg[10] = reg[9];
3108                 reg[9]  = reg[8];
3109                 reg[8]  = reg[7];
3110
3111                 reg[7]  = reg[6];
3112                 reg[6]  = reg[5];
3113                 reg[5]  = reg[4];
3114                 reg[4]  = reg[3];
3115                 reg[3]  = reg[2];
3116                 reg[2]  = reg[1];
3117                 reg[1]  = reg[0];
3118                 reg[12] = reg[12] ^ temp;
3119                 reg[5]  = reg[5] ^ temp;
3120                 reg[0]  = temp;
3121         }
3122         for (i = 0; i < 16; i++)        /* take one's complement and bit reverse*/
3123                 out[i] = 1 - reg[15 - i];
3124 }
3125
3126
3127
3128 /*========================================
3129         SFD             SIGNAL  SERVICE LENGTH  CRC
3130         16 bit  8 bit   8 bit   16 bit  16 bit
3131 ========================================*/
3132 void CCK_generator(
3133         PRT_PMAC_TX_INFO        pPMacTxInfo,
3134         PRT_PMAC_PKT_INFO       pPMacPktInfo
3135 )
3136 {
3137         double  ratio = 0;
3138         bool    crc16_in[32] = {0}, crc16_out[16] = {0};
3139         bool LengthExtBit;
3140         double LengthExact;
3141         double LengthPSDU;
3142         UCHAR i;
3143         UINT PacketLength = pPMacTxInfo->PacketLength;
3144
3145         if (pPMacTxInfo->bSPreamble)
3146                 pPMacTxInfo->SFD = 0x05CF;
3147         else
3148                 pPMacTxInfo->SFD = 0xF3A0;
3149
3150         switch (pPMacPktInfo->MCS) {
3151         case 0:
3152                 pPMacTxInfo->SignalField = 0xA;
3153                 ratio = 8;
3154                 /*CRC16_in(1,0:7)=[0 1 0 1 0 0 0 0]*/
3155                 crc16_in[1] = crc16_in[3] = 1;
3156                 break;
3157         case 1:
3158                 pPMacTxInfo->SignalField = 0x14;
3159                 ratio = 4;
3160                 /*CRC16_in(1,0:7)=[0 0 1 0 1 0 0 0];*/
3161                 crc16_in[2] = crc16_in[4] = 1;
3162                 break;
3163         case 2:
3164                 pPMacTxInfo->SignalField = 0x37;
3165                 ratio = 8.0 / 5.5;
3166                 /*CRC16_in(1,0:7)=[1 1 1 0 1 1 0 0];*/
3167                 crc16_in[0] = crc16_in[1] = crc16_in[2] = crc16_in[4] = crc16_in[5] = 1;
3168                 break;
3169         case 3:
3170                 pPMacTxInfo->SignalField = 0x6E;
3171                 ratio = 8.0 / 11.0;
3172                 /*CRC16_in(1,0:7)=[0 1 1 1 0 1 1 0];*/
3173                 crc16_in[1] = crc16_in[2] = crc16_in[3] = crc16_in[5] = crc16_in[6] = 1;
3174                 break;
3175         }
3176
3177         LengthExact = PacketLength * ratio;
3178         LengthPSDU = ceil(LengthExact);
3179
3180         if ((pPMacPktInfo->MCS == 3) &&
3181             ((LengthPSDU - LengthExact) >= 0.727 || (LengthPSDU - LengthExact) <= -0.727))
3182                 LengthExtBit = 1;
3183         else
3184                 LengthExtBit = 0;
3185
3186
3187         pPMacTxInfo->LENGTH = (UINT)LengthPSDU;
3188         /* CRC16_in(1,16:31) = LengthPSDU[0:15]*/
3189         for (i = 0; i < 16; i++)
3190                 crc16_in[i + 16] = (pPMacTxInfo->LENGTH >> i) & 0x1;
3191
3192         if (LengthExtBit == 0) {
3193                 pPMacTxInfo->ServiceField = 0x0;
3194                 /* CRC16_in(1,8:15) = [0 0 0 0 0 0 0 0];*/
3195         } else {
3196                 pPMacTxInfo->ServiceField = 0x80;
3197                 /*CRC16_in(1,8:15)=[0 0 0 0 0 0 0 1];*/
3198                 crc16_in[15] = 1;
3199         }
3200
3201         CRC16_generator(crc16_out, crc16_in, 32);
3202
3203         _rtw_memset(pPMacTxInfo->CRC16, 0, 2);
3204         ByteToBit(pPMacTxInfo->CRC16, crc16_out, 2);
3205
3206 }
3207
3208
3209 void PMAC_Get_Pkt_Param(
3210         PRT_PMAC_TX_INFO        pPMacTxInfo,
3211         PRT_PMAC_PKT_INFO       pPMacPktInfo)
3212 {
3213
3214         UCHAR           TX_RATE_HEX = 0, MCS = 0;
3215         UCHAR           TX_RATE = pPMacTxInfo->TX_RATE;
3216
3217         /*      TX_RATE & Nss   */
3218         if (MPT_IS_2SS_RATE(TX_RATE))
3219                 pPMacPktInfo->Nss = 2;
3220         else if (MPT_IS_3SS_RATE(TX_RATE))
3221                 pPMacPktInfo->Nss = 3;
3222         else if (MPT_IS_4SS_RATE(TX_RATE))
3223                 pPMacPktInfo->Nss = 4;
3224         else
3225                 pPMacPktInfo->Nss = 1;
3226
3227         RTW_INFO("PMacTxInfo.Nss =%d\n", pPMacPktInfo->Nss);
3228
3229         /*      MCS & TX_RATE_HEX*/
3230         if (MPT_IS_CCK_RATE(TX_RATE)) {
3231                 switch (TX_RATE) {
3232                 case MPT_RATE_1M:
3233                         TX_RATE_HEX = MCS = 0;
3234                         break;
3235                 case MPT_RATE_2M:
3236                         TX_RATE_HEX = MCS = 1;
3237                         break;
3238                 case MPT_RATE_55M:
3239                         TX_RATE_HEX = MCS = 2;
3240                         break;
3241                 case MPT_RATE_11M:
3242                         TX_RATE_HEX = MCS = 3;
3243                         break;
3244                 }
3245         } else if (MPT_IS_OFDM_RATE(TX_RATE)) {
3246                 MCS = TX_RATE - MPT_RATE_6M;
3247                 TX_RATE_HEX = MCS + 4;
3248         } else if (MPT_IS_HT_RATE(TX_RATE)) {
3249                 MCS = TX_RATE - MPT_RATE_MCS0;
3250                 TX_RATE_HEX = MCS + 12;
3251         } else if (MPT_IS_VHT_RATE(TX_RATE)) {
3252                 TX_RATE_HEX = TX_RATE - MPT_RATE_VHT1SS_MCS0 + 44;
3253
3254                 if (MPT_IS_VHT_2S_RATE(TX_RATE))
3255                         MCS = TX_RATE - MPT_RATE_VHT2SS_MCS0;
3256                 else if (MPT_IS_VHT_3S_RATE(TX_RATE))
3257                         MCS = TX_RATE - MPT_RATE_VHT3SS_MCS0;
3258                 else if (MPT_IS_VHT_4S_RATE(TX_RATE))
3259                         MCS = TX_RATE - MPT_RATE_VHT4SS_MCS0;
3260                 else
3261                         MCS = TX_RATE - MPT_RATE_VHT1SS_MCS0;
3262         }
3263
3264         pPMacPktInfo->MCS = MCS;
3265         pPMacTxInfo->TX_RATE_HEX = TX_RATE_HEX;
3266
3267         RTW_INFO(" MCS=%d, TX_RATE_HEX =0x%x\n", MCS, pPMacTxInfo->TX_RATE_HEX);
3268         /*      mSTBC & Nsts*/
3269         pPMacPktInfo->Nsts = pPMacPktInfo->Nss;
3270         if (pPMacTxInfo->bSTBC) {
3271                 if (pPMacPktInfo->Nss == 1) {
3272                         pPMacTxInfo->m_STBC = 2;
3273                         pPMacPktInfo->Nsts = pPMacPktInfo->Nss * 2;
3274                 } else
3275                         pPMacTxInfo->m_STBC = 1;
3276         } else
3277                 pPMacTxInfo->m_STBC = 1;
3278 }
3279
3280
3281 UINT LDPC_parameter_generator(
3282         UINT N_pld_int,
3283         UINT N_CBPSS,
3284         UINT N_SS,
3285         UINT R,
3286         UINT m_STBC,
3287         UINT N_TCB_int
3288 )
3289 {
3290         double  CR = 0.;
3291         double  N_pld = (double)N_pld_int;
3292         double  N_TCB = (double)N_TCB_int;
3293         double  N_CW = 0., N_shrt = 0., N_spcw = 0., N_fshrt = 0.;
3294         double  L_LDPC = 0., K_LDPC = 0., L_LDPC_info = 0.;
3295         double  N_punc = 0., N_ppcw = 0., N_fpunc = 0., N_rep = 0., N_rpcw = 0., N_frep = 0.;
3296         double  R_eff = 0.;
3297         UINT    VHTSIGA2B3  = 0;/* extra symbol from VHT-SIG-A2 Bit 3*/
3298
3299         if (R == 0)
3300                 CR      = 0.5;
3301         else if (R == 1)
3302                 CR = 2. / 3.;
3303         else if (R == 2)
3304                 CR = 3. / 4.;
3305         else if (R == 3)
3306                 CR = 5. / 6.;
3307
3308         if (N_TCB <= 648.) {
3309                 N_CW    = 1.;
3310                 if (N_TCB >= N_pld + 912.*(1. - CR))
3311                         L_LDPC  = 1296.;
3312                 else
3313                         L_LDPC  = 648.;
3314         } else if (N_TCB <= 1296.) {
3315                 N_CW    = 1.;
3316                 if (N_TCB >= (double)N_pld + 1464.*(1. - CR))
3317                         L_LDPC  = 1944.;
3318                 else
3319                         L_LDPC  = 1296.;
3320         } else if       (N_TCB <= 1944.) {
3321                 N_CW    = 1.;
3322                 L_LDPC  = 1944.;
3323         } else if (N_TCB <= 2592.) {
3324                 N_CW    = 2.;
3325                 if (N_TCB >= N_pld + 2916.*(1. - CR))
3326                         L_LDPC  = 1944.;
3327                 else
3328                         L_LDPC  = 1296.;
3329         } else {
3330                 N_CW = ceil(N_pld / 1944. / CR);
3331                 L_LDPC  = 1944.;
3332         }
3333         /*      Number of information bits per CW*/
3334         K_LDPC = L_LDPC * CR;
3335         /*      Number of shortening bits                                       max(0, (N_CW * L_LDPC * R) - N_pld)*/
3336         N_shrt = (N_CW * K_LDPC - N_pld) > 0. ? (N_CW * K_LDPC - N_pld) : 0.;
3337         /*      Number of shortening bits per CW                        N_spcw = rtfloor(N_shrt/N_CW)*/
3338         N_spcw = rtfloor(N_shrt / N_CW);
3339         /*      The first N_fshrt CWs shorten 1 bit more*/
3340         N_fshrt = (double)((int)N_shrt % (int)N_CW);
3341         /*      Number of data bits for the last N_CW-N_fshrt CWs*/
3342         L_LDPC_info = K_LDPC - N_spcw;
3343         /*      Number of puncturing bits*/
3344         N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
3345         if (((N_punc > .1 * N_CW * L_LDPC * (1. - CR)) && (N_shrt < 1.2 * N_punc * CR / (1. - CR))) ||
3346             (N_punc > 0.3 * N_CW * L_LDPC * (1. - CR))) {
3347                 /*cout << "*** N_TCB and N_punc are Recomputed ***" << endl;*/
3348                 VHTSIGA2B3 = 1;
3349                 N_TCB += (double)N_CBPSS * N_SS * m_STBC;
3350                 N_punc = (N_CW * L_LDPC - N_TCB - N_shrt) > 0. ? (N_CW * L_LDPC - N_TCB - N_shrt) : 0.;
3351         } else
3352                 VHTSIGA2B3 = 0;
3353
3354         return VHTSIGA2B3;
3355 }       /* function end of LDPC_parameter_generator */
3356
3357 /*========================================
3358         Data field of PPDU
3359         Get N_sym and SIGA2BB3
3360 ========================================*/
3361 void PMAC_Nsym_generator(
3362         PRT_PMAC_TX_INFO        pPMacTxInfo,
3363         PRT_PMAC_PKT_INFO       pPMacPktInfo)
3364 {
3365         UINT    SIGA2B3 = 0;
3366         UCHAR   TX_RATE = pPMacTxInfo->TX_RATE;
3367
3368         UINT R, R_list[10] = {0, 0, 2, 0, 2, 1, 2, 3, 2, 3};
3369         double CR = 0;
3370         UINT N_SD, N_BPSC_list[10] = {1, 2, 2, 4, 4, 6, 6, 6, 8, 8};
3371         UINT N_BPSC = 0, N_CBPS = 0, N_DBPS = 0, N_ES = 0, N_SYM = 0, N_pld = 0, N_TCB = 0;
3372         int D_R = 0;
3373
3374         RTW_INFO("TX_RATE = %d\n", TX_RATE);
3375         /*      N_SD*/
3376         if (pPMacTxInfo->BandWidth == 0)
3377                 N_SD = 52;
3378         else if (pPMacTxInfo->BandWidth == 1)
3379                 N_SD = 108;
3380         else
3381                 N_SD = 234;
3382
3383         if (MPT_IS_HT_RATE(TX_RATE)) {
3384                 UCHAR MCS_temp;
3385
3386                 if (pPMacPktInfo->MCS > 23)
3387                         MCS_temp = pPMacPktInfo->MCS - 24;
3388                 else if (pPMacPktInfo->MCS > 15)
3389                         MCS_temp = pPMacPktInfo->MCS - 16;
3390                 else if (pPMacPktInfo->MCS > 7)
3391                         MCS_temp = pPMacPktInfo->MCS - 8;
3392                 else
3393                         MCS_temp = pPMacPktInfo->MCS;
3394
3395                 R = R_list[MCS_temp];
3396
3397                 switch (R) {
3398                 case 0:
3399                         CR = .5;
3400                         break;
3401                 case 1:
3402                         CR = 2. / 3.;
3403                         break;
3404                 case 2:
3405                         CR = 3. / 4.;
3406                         break;
3407                 case 3:
3408                         CR = 5. / 6.;
3409                         break;
3410                 }
3411
3412                 N_BPSC = N_BPSC_list[MCS_temp];
3413                 N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
3414                 N_DBPS = (UINT)((double)N_CBPS * CR);
3415
3416                 if (pPMacTxInfo->bLDPC == FALSE) {
3417                         N_ES = (UINT)ceil((double)(N_DBPS * pPMacPktInfo->Nss) / 4. / 300.);
3418                         RTW_INFO("N_ES = %d\n", N_ES);
3419
3420                         /*      N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
3421                         N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) /
3422                                         (double)(N_DBPS * pPMacTxInfo->m_STBC));
3423
3424                 } else {
3425                         N_ES = 1;
3426                         /*      N_pld = length * 8 + 16*/
3427                         N_pld = pPMacTxInfo->PacketLength * 8 + 16;
3428                         RTW_INFO("N_pld = %d\n", N_pld);
3429                         N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(N_pld) /
3430                                         (double)(N_DBPS * pPMacTxInfo->m_STBC));
3431                         RTW_INFO("N_SYM = %d\n", N_SYM);
3432                         /*      N_avbits = N_CBPS *m_STBC *(N_pld/N_CBPS*R*m_STBC)*/
3433                         N_TCB = N_CBPS * N_SYM;
3434                         RTW_INFO("N_TCB = %d\n", N_TCB);
3435                         SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
3436                         RTW_INFO("SIGA2B3 = %d\n", SIGA2B3);
3437                         N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
3438                         RTW_INFO("N_SYM = %d\n", N_SYM);
3439                 }
3440         } else if (MPT_IS_VHT_RATE(TX_RATE)) {
3441                 R = R_list[pPMacPktInfo->MCS];
3442
3443                 switch (R) {
3444                 case 0:
3445                         CR = .5;
3446                         break;
3447                 case 1:
3448                         CR = 2. / 3.;
3449                         break;
3450                 case 2:
3451                         CR = 3. / 4.;
3452                         break;
3453                 case 3:
3454                         CR = 5. / 6.;
3455                         break;
3456                 }
3457                 N_BPSC = N_BPSC_list[pPMacPktInfo->MCS];
3458                 N_CBPS = N_BPSC * N_SD * pPMacPktInfo->Nss;
3459                 N_DBPS = (UINT)((double)N_CBPS * CR);
3460                 if (pPMacTxInfo->bLDPC == FALSE) {
3461                         if (pPMacTxInfo->bSGI)
3462                                 N_ES = (UINT)ceil((double)(N_DBPS) / 3.6 / 600.);
3463                         else
3464                                 N_ES = (UINT)ceil((double)(N_DBPS) / 4. / 600.);
3465                         /*      N_SYM = m_STBC* (8*length+16+6*N_ES) / (m_STBC*N_DBPS)*/
3466                         N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16 + N_ES * 6) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
3467                         SIGA2B3 = 0;
3468                 } else {
3469                         N_ES = 1;
3470                         /*      N_SYM = m_STBC* (8*length+N_service) / (m_STBC*N_DBPS)*/
3471                         N_SYM = pPMacTxInfo->m_STBC * (UINT)ceil((double)(pPMacTxInfo->PacketLength * 8 + 16) / (double)(N_DBPS * pPMacTxInfo->m_STBC));
3472                         /*      N_avbits = N_sys_init * N_CBPS*/
3473                         N_TCB = N_CBPS * N_SYM;
3474                         /*      N_pld = N_sys_init * N_DBPS*/
3475                         N_pld = N_SYM * N_DBPS;
3476                         SIGA2B3 = LDPC_parameter_generator(N_pld, N_CBPS, pPMacPktInfo->Nss, R, pPMacTxInfo->m_STBC, N_TCB);
3477                         N_SYM = N_SYM + SIGA2B3 * pPMacTxInfo->m_STBC;
3478                 }
3479
3480                 switch (R) {
3481                 case 0:
3482                         D_R = 2;
3483                         break;
3484                 case 1:
3485                         D_R = 3;
3486                         break;
3487                 case 2:
3488                         D_R = 4;
3489                         break;
3490                 case 3:
3491                         D_R = 6;
3492                         break;
3493                 }
3494
3495                 if (((N_CBPS / N_ES) % D_R) != 0) {
3496                         RTW_INFO("MCS= %d is not supported when Nss=%d and BW= %d !!\n",  pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
3497                         return;
3498                 }
3499
3500                 RTW_INFO("MCS= %d Nss=%d and BW= %d !!\n",  pPMacPktInfo->MCS, pPMacPktInfo->Nss, pPMacTxInfo->BandWidth);
3501         }
3502
3503         pPMacPktInfo->N_sym = N_SYM;
3504         pPMacPktInfo->SIGA2B3 = SIGA2B3;
3505 }
3506
3507 /*========================================
3508         L-SIG   Rate    R       Length  P       Tail
3509                         4b              1b      12b             1b      6b
3510 ========================================*/
3511
3512 void L_SIG_generator(
3513         UINT    N_SYM,          /* Max: 750*/
3514         PRT_PMAC_TX_INFO        pPMacTxInfo,
3515         PRT_PMAC_PKT_INFO       pPMacPktInfo)
3516 {
3517         u8      sig_bi[24] = {0};       /* 24 BIT*/
3518         UINT    mode, LENGTH;
3519         int i;
3520
3521         if (MPT_IS_OFDM_RATE(pPMacTxInfo->TX_RATE)) {
3522                 mode = pPMacPktInfo->MCS;
3523                 LENGTH = pPMacTxInfo->PacketLength;
3524         } else {
3525                 UCHAR   N_LTF;
3526                 double  T_data;
3527                 UINT    OFDM_symbol;
3528
3529                 mode = 0;
3530
3531                 /*      Table 20-13 Num of HT-DLTFs request*/
3532                 if (pPMacPktInfo->Nsts <= 2)
3533                         N_LTF = pPMacPktInfo->Nsts;
3534                 else
3535                         N_LTF = 4;
3536
3537                 if (pPMacTxInfo->bSGI)
3538                         T_data = 3.6;
3539                 else
3540                         T_data = 4.0;
3541
3542                 /*(L-SIG, HT-SIG, HT-STF, HT-LTF....HT-LTF, Data)*/
3543                 if (MPT_IS_VHT_RATE(pPMacTxInfo->TX_RATE))
3544                         OFDM_symbol = (UINT)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data + 4) / 4.);
3545                 else
3546                         OFDM_symbol = (UINT)ceil((double)(8 + 4 + N_LTF * 4 + N_SYM * T_data) / 4.);
3547
3548                 RTW_INFO("%s , OFDM_symbol =%d\n", __func__, OFDM_symbol);
3549                 LENGTH = OFDM_symbol * 3 - 3;
3550                 RTW_INFO("%s , LENGTH =%d\n", __func__, LENGTH);
3551
3552         }
3553         /*      Rate Field*/
3554         switch (mode) {
3555         case    0:
3556                 sig_bi[0] = 1;
3557                 sig_bi[1] = 1;
3558                 sig_bi[2] = 0;
3559                 sig_bi[3] = 1;
3560                 break;
3561         case    1:
3562                 sig_bi[0] = 1;
3563                 sig_bi[1] = 1;
3564                 sig_bi[2] = 1;
3565                 sig_bi[3] = 1;
3566                 break;
3567         case    2:
3568                 sig_bi[0] = 0;
3569                 sig_bi[1] = 1;
3570                 sig_bi[2] = 0;
3571                 sig_bi[3] = 1;
3572                 break;
3573         case    3:
3574                 sig_bi[0] = 0;
3575                 sig_bi[1] = 1;
3576                 sig_bi[2] = 1;
3577                 sig_bi[3] = 1;
3578                 break;
3579         case    4:
3580                 sig_bi[0] = 1;
3581                 sig_bi[1] = 0;
3582                 sig_bi[2] = 0;
3583                 sig_bi[3] = 1;
3584                 break;
3585         case    5:
3586                 sig_bi[0] = 1;
3587                 sig_bi[1] = 0;
3588                 sig_bi[2] = 1;
3589                 sig_bi[3] = 1;
3590                 break;
3591         case    6:
3592                 sig_bi[0] = 0;
3593                 sig_bi[1] = 0;
3594                 sig_bi[2] = 0;
3595                 sig_bi[3] = 1;
3596                 break;
3597         case    7:
3598                 sig_bi[0] = 0;
3599                 sig_bi[1] = 0;
3600                 sig_bi[2] = 1;
3601                 sig_bi[3] = 1;
3602                 break;
3603         }
3604         /*Reserved bit*/
3605         sig_bi[4] = 0;
3606
3607         /*      Length Field*/
3608         for (i = 0; i < 12; i++)
3609                 sig_bi[i + 5] = (LENGTH >> i) & 1;
3610
3611         /* Parity Bit*/
3612         sig_bi[17] = 0;
3613         for (i = 0; i < 17; i++)
3614                 sig_bi[17] = sig_bi[17] + sig_bi[i];
3615
3616         sig_bi[17] %= 2;
3617
3618         /*      Tail Field*/
3619         for (i = 18; i < 24; i++)
3620                 sig_bi[i] = 0;
3621
3622         /* dump_buf(sig_bi,24);*/
3623         _rtw_memset(pPMacTxInfo->LSIG, 0, 3);
3624         ByteToBit(pPMacTxInfo->LSIG, (bool *)sig_bi, 3);
3625 }
3626
3627
3628 void CRC8_generator(
3629         bool    *out,
3630         bool    *in,
3631         UCHAR   in_size
3632 )
3633 {
3634         UCHAR i = 0;
3635         bool temp = 0, reg[] = {1, 1, 1, 1, 1, 1, 1, 1};
3636
3637         for (i = 0; i < in_size; i++) { /* take one's complement and bit reverse*/
3638                 temp = in[i] ^ reg[7];
3639                 reg[7]  = reg[6];
3640                 reg[6]  = reg[5];
3641                 reg[5]  = reg[4];
3642                 reg[4]  = reg[3];
3643                 reg[3]  = reg[2];
3644                 reg[2]  = reg[1] ^ temp;
3645                 reg[1]  = reg[0] ^ temp;
3646                 reg[0]  = temp;
3647         }
3648         for (i = 0; i < 8; i++)/* take one's complement and bit reverse*/
3649                 out[i] = reg[7 - i] ^ 1;
3650 }
3651
3652 /*/================================================================================
3653         HT-SIG1 MCS     CW      Length          24BIT + 24BIT
3654                         7b      1b      16b
3655         HT-SIG2 Smoothing       Not sounding    Rsvd            AGG     STBC    FEC     SGI     N_ELTF  CRC     Tail
3656                         1b                      1b                      1b              1b      2b              1b      1b      2b              8b      6b
3657 ================================================================================*/
3658 void HT_SIG_generator(
3659         PRT_PMAC_TX_INFO        pPMacTxInfo,
3660         PRT_PMAC_PKT_INFO       pPMacPktInfo
3661 )
3662 {
3663         UINT i;
3664         bool sig_bi[48] = {0}, crc8[8] = {0};
3665         /*      MCS Field*/
3666         for (i = 0; i < 7; i++)
3667                 sig_bi[i] = (pPMacPktInfo->MCS >> i) & 0x1;
3668         /*      Packet BW Setting*/
3669         sig_bi[7] = pPMacTxInfo->BandWidth;
3670         /*      HT-Length Field*/
3671         for (i = 0; i < 16; i++)
3672                 sig_bi[i + 8] = (pPMacTxInfo->PacketLength >> i) & 0x1;
3673         /*      Smoothing;      1->allow smoothing*/
3674         sig_bi[24] = 1;
3675         /*Not Sounding*/
3676         sig_bi[25] = 1 - pPMacTxInfo->NDP_sound;
3677         /*Reserved bit*/
3678         sig_bi[26] = 1;
3679         /*/Aggregate*/
3680         sig_bi[27] = 0;
3681         /*STBC Field*/
3682         if (pPMacTxInfo->bSTBC) {
3683                 sig_bi[28] = 1;
3684                 sig_bi[29] = 0;
3685         } else {
3686                 sig_bi[28] = 0;
3687                 sig_bi[29] = 0;
3688         }
3689         /*Advance Coding,       0: BCC, 1: LDPC*/
3690         sig_bi[30] = pPMacTxInfo->bLDPC;
3691         /* Short GI*/
3692         sig_bi[31] = pPMacTxInfo->bSGI;
3693         /* N_ELTFs*/
3694         if (pPMacTxInfo->NDP_sound == FALSE) {
3695                 sig_bi[32]      = 0;
3696                 sig_bi[33]      = 0;
3697         } else {
3698                 int     N_ELTF = pPMacTxInfo->Ntx - pPMacPktInfo->Nss;
3699
3700                 for (i = 0; i < 2; i++)
3701                         sig_bi[32 + i] = (N_ELTF >> i) % 2;
3702         }
3703         /*      CRC-8*/
3704         CRC8_generator(crc8, sig_bi, 34);
3705
3706         for (i = 0; i < 8; i++)
3707                 sig_bi[34 + i] = crc8[i];
3708
3709         /*Tail*/
3710         for (i = 42; i < 48; i++)
3711                 sig_bi[i] = 0;
3712
3713         _rtw_memset(pPMacTxInfo->HT_SIG, 0, 6);
3714         ByteToBit(pPMacTxInfo->HT_SIG, sig_bi, 6);
3715 }
3716
3717
3718 /*======================================================================================
3719         VHT-SIG-A1
3720         BW      Reserved        STBC    G_ID    SU_Nsts P_AID   TXOP_PS_NOT_ALLOW       Reserved
3721         2b      1b                      1b              6b      3b      9b              1b              2b                                      1b
3722         VHT-SIG-A2
3723         SGI     SGI_Nsym        SU/MU coding    LDPC_Extra      SU_NCS  Beamformed      Reserved        CRC     Tail
3724         1b      1b                      1b                              1b                      4b              1b                      1b                      8b      6b
3725 ======================================================================================*/
3726 void VHT_SIG_A_generator(
3727         PRT_PMAC_TX_INFO        pPMacTxInfo,
3728         PRT_PMAC_PKT_INFO       pPMacPktInfo)
3729 {
3730         UINT i;
3731         bool sig_bi[48], crc8[8];
3732
3733         _rtw_memset(sig_bi, 0, 48);
3734         _rtw_memset(crc8, 0, 8);
3735
3736         /*      BW Setting*/
3737         for (i = 0; i < 2; i++)
3738                 sig_bi[i] = (pPMacTxInfo->BandWidth >> i) & 0x1;
3739         /* Reserved Bit*/
3740         sig_bi[2] = 1;
3741         /*STBC Field*/
3742         sig_bi[3] = pPMacTxInfo->bSTBC;
3743         /*Group ID: Single User->A value of 0 or 63 indicates an SU PPDU. */
3744         for (i = 0; i < 6; i++)
3745                 sig_bi[4 + i] = 0;
3746         /*      N_STS/Partial AID*/
3747         for (i = 0; i < 12; i++) {
3748                 if (i < 3)
3749                         sig_bi[10 + i] = ((pPMacPktInfo->Nsts - 1) >> i) & 0x1;
3750                 else
3751                         sig_bi[10 + i] = 0;
3752         }
3753         /*TXOP_PS_NOT_ALLPWED*/
3754         sig_bi[22]      = 0;
3755         /*Reserved Bits*/
3756         sig_bi[23]      = 1;
3757         /*Short GI*/
3758         sig_bi[24] = pPMacTxInfo->bSGI;
3759         if (pPMacTxInfo->bSGI > 0 && (pPMacPktInfo->N_sym % 10) == 9)
3760                 sig_bi[25] = 1;
3761         else
3762                 sig_bi[25] = 0;
3763         /* SU/MU[0] Coding*/
3764         sig_bi[26] = pPMacTxInfo->bLDPC;        /*      0:BCC, 1:LDPC           */
3765         sig_bi[27] = pPMacPktInfo->SIGA2B3;     /*/     Record Extra OFDM Symols is added or not when LDPC is used*/
3766         /*SU MCS/MU[1-3] Coding*/
3767         for (i = 0; i < 4; i++)
3768                 sig_bi[28 + i] = (pPMacPktInfo->MCS >> i) & 0x1;
3769         /*SU Beamform */
3770         sig_bi[32] = 0; /*packet.TXBF_en;*/
3771         /*Reserved Bit*/
3772         sig_bi[33] = 1;
3773         /*CRC-8*/
3774         CRC8_generator(crc8, sig_bi, 34);
3775         for (i = 0; i < 8; i++)
3776                 sig_bi[34 + i]  = crc8[i];
3777         /*Tail*/
3778         for (i = 42; i < 48; i++)
3779                 sig_bi[i] = 0;
3780
3781         _rtw_memset(pPMacTxInfo->VHT_SIG_A, 0, 6);
3782         ByteToBit(pPMacTxInfo->VHT_SIG_A, sig_bi, 6);
3783 }
3784
3785 /*======================================================================================
3786         VHT-SIG-B
3787         Length                          Resesrved       Trail
3788         17/19/21 BIT            3/2/2 BIT       6b
3789 ======================================================================================*/
3790 void VHT_SIG_B_generator(
3791         PRT_PMAC_TX_INFO        pPMacTxInfo)
3792 {
3793         bool sig_bi[32], crc8_bi[8];
3794         UINT i, len, res, tail = 6, total_len, crc8_in_len;
3795         UINT sigb_len;
3796
3797         _rtw_memset(sig_bi, 0, 32);
3798         _rtw_memset(crc8_bi, 0, 8);
3799
3800         /*Sounding Packet*/
3801         if (pPMacTxInfo->NDP_sound == 1) {
3802                 if (pPMacTxInfo->BandWidth == 0) {
3803                         bool sigb_temp[26] = {0, 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
3804
3805                         _rtw_memcpy(sig_bi, sigb_temp, 26);
3806                 } else if (pPMacTxInfo->BandWidth == 1) {
3807                         bool sigb_temp[27] = {1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0};
3808
3809                         _rtw_memcpy(sig_bi, sigb_temp, 27);
3810                 } else if (pPMacTxInfo->BandWidth == 2) {
3811                         bool sigb_temp[29] = {0, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0};
3812
3813                         _rtw_memcpy(sig_bi, sigb_temp, 29);
3814                 }
3815         } else {        /* Not NDP Sounding*/
3816                 bool *sigb_temp[29] = {0};
3817
3818                 if (pPMacTxInfo->BandWidth == 0) {
3819                         len = 17;
3820                         res = 3;
3821                 } else if (pPMacTxInfo->BandWidth == 1) {
3822                         len = 19;
3823                         res = 2;
3824                 } else if (pPMacTxInfo->BandWidth == 2) {
3825                         len     = 21;
3826                         res     = 2;
3827                 } else {
3828                         len     = 21;
3829                         res     = 2;
3830                 }
3831                 total_len = len + res + tail;
3832                 crc8_in_len = len + res;
3833
3834                 /*Length Field*/
3835                 sigb_len = (pPMacTxInfo->PacketLength + 3) >> 2;
3836
3837                 for (i = 0; i < len; i++)
3838                         sig_bi[i] = (sigb_len >> i) & 0x1;
3839                 /*Reserved Field*/
3840                 for (i = 0; i < res; i++)
3841                         sig_bi[len + i] = 1;
3842                 /* CRC-8*/
3843                 CRC8_generator(crc8_bi, sig_bi, crc8_in_len);
3844
3845                 /* Tail */
3846                 for (i = 0; i < tail; i++)
3847                         sig_bi[len + res + i] = 0;
3848         }
3849
3850         _rtw_memset(pPMacTxInfo->VHT_SIG_B, 0, 4);
3851         ByteToBit(pPMacTxInfo->VHT_SIG_B, sig_bi, 4);
3852
3853         pPMacTxInfo->VHT_SIG_B_CRC = 0;
3854         ByteToBit(&(pPMacTxInfo->VHT_SIG_B_CRC), crc8_bi, 1);
3855 }
3856
3857 /*=======================
3858  VHT Delimiter
3859 =======================*/
3860 void VHT_Delimiter_generator(
3861         PRT_PMAC_TX_INFO        pPMacTxInfo
3862 )
3863 {
3864         bool sig_bi[32] = {0}, crc8[8] = {0};
3865         UINT crc8_in_len = 16;
3866         UINT PacketLength = pPMacTxInfo->PacketLength;
3867         int j;
3868
3869         /* Delimiter[0]: EOF*/
3870         sig_bi[0] = 1;
3871         /* Delimiter[1]: Reserved*/
3872         sig_bi[1] = 0;
3873         /* Delimiter[3:2]: MPDU Length High*/
3874         sig_bi[2] = ((PacketLength - 4) >> 12) % 2;
3875         sig_bi[3] = ((PacketLength - 4) >> 13) % 2;
3876         /* Delimiter[15:4]: MPDU Length Low*/
3877         for (j = 4; j < 16; j++)
3878                 sig_bi[j] = ((PacketLength - 4) >> (j - 4)) % 2;
3879         CRC8_generator(crc8, sig_bi, crc8_in_len);
3880         for (j = 16; j < 24; j++) /* Delimiter[23:16]: CRC 8*/
3881                 sig_bi[j] = crc8[j - 16];
3882         for (j = 24; j < 32; j++) /* Delimiter[31:24]: Signature ('4E' in Hex, 78 in Dec)*/
3883                 sig_bi[j]       = (78 >> (j - 24)) % 2;
3884
3885         _rtw_memset(pPMacTxInfo->VHT_Delimiter, 0, 4);
3886         ByteToBit(pPMacTxInfo->VHT_Delimiter, sig_bi, 4);
3887 }
3888
3889 #endif
3890 #endif