1 /******************************************************************************
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __HALRF_IQK_H__
27 #define __HALRF_IQK_H__
29 /*--------------------------Define Parameters-------------------------------*/
31 #define WBIQK_delay 10
37 #define kcount_limit_80m 2
38 #define kcount_limit_others 4
39 #define rxiqk_gs_limit 10
42 /*-----------------------End Define Parameters-----------------------*/
45 boolean lok_fail[NUM];
46 boolean iqk_fail[2][NUM];
47 u32 iqc_matrix[2][NUM];
56 u8 rfk_ing; /*bit0:IQKing, bit1:LCKing, bit2:DPKing*/
57 boolean rfk_forbidden;
58 #if (RTL8814A_SUPPORT == 1 || RTL8822B_SUPPORT == 1 || RTL8821C_SUPPORT == 1 ||\
59 RTL8195B_SUPPORT == 1 || RTL8198F_SUPPORT == 1)
61 boolean iqk_fail_report[2][4][2]; /*channel/path/TRX(TX:0, RX:1) */
62 /*channel / path / TRX(TX:0, RX:1) / CFIR_real*/
63 /*channel index = 2 is just for debug*/
64 u32 iqk_cfir_real[3][4][2][8];
65 /*channel / path / TRX(TX:0, RX:1) / CFIR_imag*/
66 /*channel index = 2 is just for debug*/
67 u32 iqk_cfir_imag[3][4][2][8];
68 u8 retry_count[2][4][3]; /* channel / path / (TXK:0, RXK1:1, RXK2:2) */
69 u8 gs_retry_count[2][4][2]; /* channel / path / (GSRXK1:0, GSRXK2:1) */
70 /* channel / path 0:SRXK1 fail, 1:RXK1 fail 2:RXK2 fail */
71 u8 rxiqk_fail_code[2][4];
72 u32 lok_idac[2][4]; /*channel / path*/
73 u16 rxiqk_agc[2][4]; /*channel / path*/
74 u32 bypass_iqk[2][4]; /*channel / 0xc94/0xe94*/
75 u32 txgap_result[8]; /*txagpK result */
83 boolean trximr_enable;
92 #endif /*#ifndef __HALRF_IQK_H__*/