rtl8821ce/hal/phydm/halrf/halrf_kfree.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2017  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __HALRF_KFREE_H__
  27 #define __HALRF_KFREE_H__
  28
  29 #define KFREE_VERSION "1.0"
  30
  31 #define KFREE_BAND_NUM 6
  32 #define KFREE_CH_NUM 3
  33
  34 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
  35
  36 #define BB_GAIN_NUM 6
  37
  38 #endif
  39
  40 #define KFREE_FLAG_ON BIT(0)
  41 #define KFREE_FLAG_THERMAL_K_ON BIT(1)
  42
  43 #define KFREE_FLAG_ON_2G BIT(2)
  44 #define KFREE_FLAG_ON_5G BIT(3)
  45
  46 #define PA_BIAS_FLAG_ON BIT(4)
  47
  48 #define PPG_THERMAL_OFFSET_21C 0x1EF
  49 #define PPG_2G_TXAB_21C 0x1EE
  50 #define PPG_5GL1_TXA_21C 0x1EC
  51 #define PPG_5GL2_TXA_21C 0x1E8
  52 #define PPG_5GM1_TXA_21C 0x1E4
  53 #define PPG_5GM2_TXA_21C 0x1E0
  54 #define PPG_5GH1_TXA_21C 0x1DC
  55
  56 #define PPG_THERMAL_OFFSET_22B 0x3EF
  57 #define PPG_2G_TXAB_22B 0x3EE
  58 #define PPG_2G_TXCD_22B 0x3ED
  59 #define PPG_5GL1_TXA_22B 0x3EC
  60 #define PPG_5GL1_TXB_22B 0x3EB
  61 #define PPG_5GL1_TXC_22B 0x3EA
  62 #define PPG_5GL1_TXD_22B 0x3E9
  63 #define PPG_5GL2_TXA_22B 0x3E8
  64 #define PPG_5GL2_TXB_22B 0x3E7
  65 #define PPG_5GL2_TXC_22B 0x3E6
  66 #define PPG_5GL2_TXD_22B 0x3E5
  67 #define PPG_5GM1_TXA_22B 0x3E4
  68 #define PPG_5GM1_TXB_22B 0x3E3
  69 #define PPG_5GM1_TXC_22B 0x3E2
  70 #define PPG_5GM1_TXD_22B 0x3E1
  71 #define PPG_5GM2_TXA_22B 0x3E0
  72 #define PPG_5GM2_TXB_22B 0x3DF
  73 #define PPG_5GM2_TXC_22B 0x3DE
  74 #define PPG_5GM2_TXD_22B 0x3DD
  75 #define PPG_5GH1_TXA_22B 0x3DC
  76 #define PPG_5GH1_TXB_22B 0x3DB
  77 #define PPG_5GH1_TXC_22B 0x3DA
  78 #define PPG_5GH1_TXD_22B 0x3D9
  79
  80 #define PPG_PABIAS_2GA_22B 0x3D5
  81 #define PPG_PABIAS_2GB_22B 0x3D6
  82
  83 struct odm_power_trim_data {
  84         u8 flag;
  85         u8 pa_bias_flag;
  86         s8 bb_gain[KFREE_BAND_NUM][MAX_RF_PATH];
  87         s8 thermal;
  88 };
  89
  90 enum phydm_kfree_channeltosw {
  91         PHYDM_2G = 0,
  92         PHYDM_5GLB1 = 1,
  93         PHYDM_5GLB2 = 2,
  94         PHYDM_5GMB1 = 3,
  95         PHYDM_5GMB2 = 4,
  96         PHYDM_5GHB = 5,
  97 };
  98
  99 void phydm_get_thermal_trim_offset(void *dm_void);
 100
 101 void phydm_get_power_trim_offset(void *dm_void);
 102
 103 void phydm_get_pa_bias_offset(void *dm_void);
 104
 105 s8 phydm_get_thermal_offset(void *dm_void);
 106
 107 void phydm_clear_kfree_to_rf(void *dm_void, u8 e_rf_path, u8 data);
 108
 109 void phydm_config_kfree(void *dm_void, u8 channel_to_sw);
 110
 111 #endif /*#ifndef __HALRF_KFREE_H__*/