rtl8821ce/hal/phydm/halrf/rtl8821c/halrf_iqk_8821c.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2016 - 2017 Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  *****************************************************************************/
  15
  16 #include "mp_precomp.h"
  17 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
  18 #if RT_PLATFORM == PLATFORM_MACOSX
  19 #include "phydm_precomp.h"
  20 #else
  21 #include "../phydm_precomp.h"
  22 #endif
  23 #else
  24 #include "../../phydm_precomp.h"
  25 #endif
  26
  27 #if (RTL8821C_SUPPORT == 1)
  28 /*---------------------------Define Local Constant---------------------------*/
  29
  30 static u32 dpk_result[DPK_BACKUP_REG_NUM_8821C];
  31 static boolean txgap_done[3] = {false, false, false};
  32 static boolean overflowflag;
  33 #define dpk_forcein_sram4 1
  34 #define txgap_ref_index 0x0
  35 #define txgap_k_number 0x7
  36
  37 /*---------------------------Define Local Constant---------------------------*/
  38 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
  39 void do_iqk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
  40                   u8 threshold)
  41 {
  42         struct dm_struct *dm = (struct dm_struct *)dm_void;
  43         struct dm_iqk_info *iqk_info = &dm->IQK_info;
  44
  45         dm->rf_calibrate_info.thermal_value_iqk = thermal_value;
  46         halrf_segment_iqk_trigger(dm, true, iqk_info->segment_iqk);
  47 }
  48 #else
  49 /*Originally config->do_iqk is hooked phy_iq_calibrate_8821c, but do_iqk_8821c and phy_iq_calibrate_8821c have different arguments*/
  50 void do_iqk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
  51                   u8 threshold)
  52 {
  53         struct dm_struct *dm = (struct dm_struct *)dm_void;
  54         struct dm_iqk_info *iqk_info = &dm->IQK_info;
  55         /*boolean               is_recovery = (boolean) delta_thermal_index;*/
  56         halrf_segment_iqk_trigger(dm, true, iqk_info->segment_iqk);
  57 }
  58 #endif
  59 void do_dpk_8821c(void *dm_void, u8 delta_thermal_index, u8 thermal_value,
  60                   u8 threshold)
  61 {
  62         struct dm_struct *dm = (struct dm_struct *)dm_void;
  63         /*boolean               is_recovery = (boolean) delta_thermal_index;*/
  64         phy_dp_calibrate_8821c(dm, true);
  65 }
  66
  67 boolean
  68 _iqk_check_nctl_done_8821c(struct dm_struct *dm, u8 path, u32 IQK_CMD)
  69 {
  70         /*this function is only used after the version of nctl8.0*/
  71         boolean notready = true;
  72         boolean fail = true;
  73         u32 delay_count = 0x0;
  74
  75         while (notready) {
  76                 if ((IQK_CMD & 0x00000f00) >> 8 == 0xc) {
  77                         if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) == 0x1a3b5)
  78                                 notready = false;
  79                         else
  80                                 notready = true;
  81                 } else {
  82                         if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) == 0x12345)
  83                                 notready = false;
  84                         else
  85                                 notready = true;
  86                 }
  87                 if (notready) {
  88                         /*ODM_sleep_ms(1);*/
  89                         ODM_delay_ms(1);
  90                         delay_count++;
  91                 } else {
  92                         fail = (boolean)odm_get_bb_reg(dm, R_0x1b08, BIT(26));
  93                         if (fail) {
  94                                 RF_DBG(dm, DBG_RF_IQK,
  95                                        "[IQK](1)IQK_CMD =0x%x, Fail, 0x1b08=0x%x, RF08=0x%x, 1b00=0x%x,fail=0x%x, notready=0x%x!!!\n",
  96                                        IQK_CMD, odm_read_4byte(dm, 0x1b08),
  97                                        odm_get_rf_reg(dm, path, RF_0x08,
  98                                                       RFREGOFFSETMASK),
  99                                        odm_read_4byte(dm, 0x1b00), fail,
 100                                                       notready);
 101                         }
 102                         break;
 103                 }
 104                 if (delay_count >= 50) {
 105                         RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d IQK timeout!!!\n",
 106                                path);
 107                         break;
 108                 }
 109         }
 110         odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
 111
 112         if (!fail) {
 113                 RF_DBG(dm, DBG_RF_IQK,
 114                        "[IQK]IQK_CMD =0x%x, delay_count =0x%x RF0x08=0x%x, 0x1b08=0x%x,RF0xef=0x%x,RF0xdf=0x%x, !!!\n",
 115                        IQK_CMD, delay_count,
 116                        odm_get_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK),
 117                        odm_read_4byte(dm, 0x1b08),
 118                        odm_get_rf_reg(dm, path, RF_0xef, RFREGOFFSETMASK),
 119                        odm_get_rf_reg(dm, path, RF_0xdf, RFREGOFFSETMASK));
 120         } else {
 121                 RF_DBG(dm, DBG_RF_IQK,
 122                        "[IQK](2)IQK_CMD =0x%x, Fail, 0x1b08=0x%x, RF08=0x%x!!!\n",
 123                        IQK_CMD, odm_read_4byte(dm, 0x1b08),
 124                        odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK));
 125         }
 126         return fail;
 127 }
 128
 129 void phydm_get_read_counter_8821c(struct dm_struct *dm)
 130 {
 131         u32 counter = 0x0;
 132
 133         while (1) {
 134                 if ((odm_get_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK) == 0xabcde) || counter > 300)
 135                         break;
 136                 counter++;
 137                 /*ODM_sleep_ms(1);*/
 138                 ODM_delay_ms(1);
 139         };
 140         odm_set_rf_reg(dm, RF_PATH_A, RF_0x8, RFREGOFFSETMASK, 0x0);
 141         RF_DBG(dm, DBG_RF_IQK, "[IQK]counter = %d\n", counter);
 142 }
 143
 144 void _iqk_check_coex_status(struct dm_struct *dm, boolean beforeK)
 145 {
 146         u8 u1b_tmp;
 147         u16 count = 0;
 148         u8 h2c_parameter;
 149
 150         h2c_parameter = 1;
 151
 152         if (beforeK) {
 153                 u1b_tmp = odm_read_1byte(dm, 0x49c);
 154                 RF_DBG(dm, DBG_RF_IQK,
 155                        "[IQK]check 0x49c[0] = 0x%x before h2c 0x6d\n", u1b_tmp);
 156
 157                 /*check if BT IQK */
 158                 u1b_tmp = odm_read_1byte(dm, 0x49c);
 159                 while ((u1b_tmp & BIT(1)) && (count < 100)) {
 160                         /*ODM_sleep_ms(10);*/
 161                         ODM_delay_ms(10);
 162                         u1b_tmp = odm_read_1byte(dm, 0x49c);
 163                         count++;
 164                         RF_DBG(dm, DBG_RF_IQK,
 165                                "[IQK]check 0x49c[1]=0x%x, count = %d\n",
 166                                u1b_tmp, count);
 167                 }
 168 #if 1
 169                 odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
 170
 171                 u1b_tmp = odm_read_1byte(dm, 0x49c);
 172                 RF_DBG(dm, DBG_RF_IQK,
 173                        "[IQK]check 0x49c[0] = 0x%x after h2c 0x6d\n", u1b_tmp);
 174
 175                 u1b_tmp = odm_read_1byte(dm, 0x49c);
 176                 /*check if WL IQK available form WL FW */
 177                 while ((!(u1b_tmp & BIT(0))) && (count < 100)) {
 178 #if 0
 179                         /*ODM_sleep_ms(10);*/
 180 #endif
 181                         ODM_delay_ms(10);
 182                         u1b_tmp = odm_read_1byte(dm, 0x49c);
 183                         count++;
 184                         RF_DBG(dm, DBG_RF_IQK,
 185                                "[IQK]check 0x49c[1]=0x%x, count = %d\n",
 186                                u1b_tmp, count);
 187                 }
 188
 189                 if (count >= 100)
 190                         RF_DBG(dm, DBG_RF_IQK,
 191                                "[IQK]Polling 0x49c to 1 for WiFi calibration H2C cmd FAIL! count(%d)\n",
 192                                count);
 193 #endif
 194
 195         } else {
 196                 odm_set_bb_reg(dm, R_0x49c, BIT(0), 0x0);
 197         }
 198 }
 199
 200 u32 _iqk_indirect_read_reg(struct dm_struct *dm, u16 reg_addr)
 201 {
 202         u32 j = 0;
 203
 204         /*wait for ready bit before access 0x1700*/
 205         odm_write_4byte(dm, 0x1700, 0x800f0000 | reg_addr);
 206
 207         do {
 208                 j++;
 209         } while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
 210
 211         return odm_read_4byte(dm, 0x1708); /*get read data*/
 212 }
 213
 214 void _iqk_indirect_write_reg(struct dm_struct *dm, u16 reg_addr, u32 bit_mask,
 215                              u32 reg_value)
 216 {
 217         u32 val, i = 0, j = 0, bitpos = 0;
 218
 219         if (bit_mask == 0x0)
 220                 return;
 221         if (bit_mask == 0xffffffff) {
 222                 odm_write_4byte(dm, 0x1704, reg_value); /*put write data*/
 223
 224                 /*wait for ready bit before access 0x1700*/
 225                 do {
 226                         j++;
 227                 } while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
 228
 229                 odm_write_4byte(dm, 0x1700, 0xc00f0000 | reg_addr);
 230         } else {
 231                 for (i = 0; i <= 31; i++) {
 232                         if (((bit_mask >> i) & 0x1) == 0x1) {
 233                                 bitpos = i;
 234                                 break;
 235                         }
 236                 }
 237
 238                 /*read back register value before write*/
 239                 val = _iqk_indirect_read_reg(dm, reg_addr);
 240                 val = (val & (~bit_mask)) | (reg_value << bitpos);
 241
 242                 odm_write_4byte(dm, 0x1704, val); /*put write data*/
 243
 244                 /*wait for ready bit before access 0x1700*/
 245                 do {
 246                         j++;
 247                 } while (((odm_read_1byte(dm, 0x1703) & BIT(5)) == 0) && (j < 30000));
 248
 249                 odm_write_4byte(dm, 0x1700, 0xc00f0000 | reg_addr);
 250         }
 251 }
 252
 253 void _iqk_set_gnt_wl_high(struct dm_struct *dm)
 254 {
 255         u32 val = 0;
 256         u8 state = 0x1, sw_control = 0x1;
 257
 258         /*GNT_WL = 1*/
 259         val = (sw_control) ? ((state << 1) | 0x1) : 0;
 260         _iqk_indirect_write_reg(dm, 0x38, 0x3000, val); /*0x38[13:12]*/
 261         _iqk_indirect_write_reg(dm, 0x38, 0x0300, val); /*0x38[9:8]*/
 262 }
 263
 264 void _iqk_set_gnt_bt_low(struct dm_struct *dm)
 265 {
 266         u32 val = 0;
 267         u8 state = 0x0, sw_control = 0x1;
 268
 269         /*GNT_BT = 0*/
 270         val = (sw_control) ? ((state << 1) | 0x1) : 0;
 271         _iqk_indirect_write_reg(dm, 0x38, 0xc000, val); /*0x38[15:14]*/
 272         _iqk_indirect_write_reg(dm, 0x38, 0x0c00, val); /*0x38[11:10]*/
 273 }
 274
 275 void _iqk_set_gnt_wl_gnt_bt(struct dm_struct *dm, boolean beforeK)
 276 {
 277         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 278
 279         if (beforeK) {
 280                 _iqk_set_gnt_wl_high(dm);
 281                 _iqk_set_gnt_bt_low(dm);
 282         } else {
 283                 _iqk_indirect_write_reg(dm, 0x38, MASKDWORD, iqk_info->tmp_gntwl);
 284         }
 285 }
 286
 287 void _iqk_fail_count_8821c(void *dm_void)
 288 {
 289         struct dm_struct *dm = (struct dm_struct *)dm_void;
 290         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 291         u8 i;
 292
 293         dm->n_iqk_cnt++;
 294         if (odm_get_rf_reg(dm, RF_PATH_A, RF_0x1bf0, BIT(16)) == 1)
 295                 iqk_info->is_reload = true;
 296         else
 297                 iqk_info->is_reload = false;
 298
 299         if (!iqk_info->is_reload) {
 300                 for (i = 0; i < 8; i++) {
 301                         if (odm_get_bb_reg(dm, R_0x1bf0, BIT(i)) == 1)
 302                                 dm->n_iqk_fail_cnt++;
 303                 }
 304         }
 305         RF_DBG(dm, DBG_RF_IQK, "[IQK]All/Fail = %d %d\n", dm->n_iqk_cnt,
 306                dm->n_iqk_fail_cnt);
 307 }
 308
 309 void _iqk_fill_iqk_report_8821c(void *dm_void, u8 channel)
 310 {
 311         struct dm_struct *dm = (struct dm_struct *)dm_void;
 312         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 313         u32 tmp1 = 0x0, tmp2 = 0x0, tmp3 = 0x0;
 314         u8 i;
 315
 316         for (i = 0; i < SS_8821C; i++) {
 317                 tmp1 = tmp1 + ((iqk_info->iqk_fail_report[channel][i][TX_IQK] & 0x1) << i);
 318                 tmp2 = tmp2 + ((iqk_info->iqk_fail_report[channel][i][RX_IQK] & 0x1) << (i + 4));
 319                 tmp3 = tmp3 + ((iqk_info->rxiqk_fail_code[channel][i] & 0x3) << (i * 2 + 8));
 320         }
 321         odm_write_4byte(dm, 0x1b00, 0xf8000008);
 322         odm_set_bb_reg(dm, R_0x1bf0, 0x00ffffff, tmp1 | tmp2 | tmp3);
 323
 324         for (i = 0; i < SS_8821C; i++)
 325                 odm_write_4byte(dm, 0x1be8 + (i * 4), (iqk_info->rxiqk_agc[channel][(i * 2) + 1] << 16) | iqk_info->rxiqk_agc[channel][i * 2]);
 326         RF_DBG(dm, DBG_RF_IQK, "[IQK] 0x1be8 = %x\n",
 327                odm_read_4byte(dm, 0x1be8));
 328 }
 329
 330 void _iqk_iqk_fail_report_8821c(struct dm_struct *dm)
 331 {
 332         u32 tmp1bf0 = 0x0;
 333         u8 i;
 334
 335         tmp1bf0 = odm_read_4byte(dm, 0x1bf0);
 336
 337         for (i = 0; i < 4; i++) {
 338                 if (tmp1bf0 & (0x1 << i))
 339 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
 340                         RF_DBG(dm, DBG_RF_IQK, "[IQK] please check S%d TXIQK\n",
 341                                i);
 342 #else
 343                         panic_printk("[IQK] please check S%d TXIQK\n", i);
 344 #endif
 345                 if (tmp1bf0 & (0x1 << (i + 12)))
 346 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
 347                         RF_DBG(dm, DBG_RF_IQK, "[IQK] please check S%d RXIQK\n",
 348                                i);
 349 #else
 350                         panic_printk("[IQK] please check S%d RXIQK\n", i);
 351 #endif
 352         }
 353 }
 354
 355 void _iqk_backup_mac_bb_8821c(struct dm_struct *dm, u32 *MAC_backup,
 356                               u32 *BB_backup, u32 *backup_mac_reg,
 357                               u32 *backup_bb_reg, u8 num_backup_bb_reg)
 358 {
 359         u32 i;
 360
 361         for (i = 0; i < MAC_REG_NUM_8821C; i++)
 362                 MAC_backup[i] = odm_read_4byte(dm, backup_mac_reg[i]);
 363
 364         for (i = 0; i < num_backup_bb_reg; i++)
 365                 BB_backup[i] = odm_read_4byte(dm, backup_bb_reg[i]);
 366 #if 0
 367         /*      RF_DBG(dm, DBG_RF_IQK, "[IQK]BackupMacBB Success!!!!\n"); */
 368 #endif
 369 }
 370
 371 void _iqk_backup_rf_8821c(struct dm_struct *dm, u32 RF_backup[][SS_8821C],
 372                           u32 *backup_rf_reg)
 373 {
 374         u32 i, j;
 375
 376         for (i = 0; i < RF_REG_NUM_8821C; i++)
 377                 for (j = 0; j < SS_8821C; j++)
 378                         RF_backup[i][j] = odm_get_rf_reg(dm, (u8)j, backup_rf_reg[i], RFREGOFFSETMASK);
 379 #if 0
 380         /*      RF_DBG(dm, DBG_RF_IQK, "[IQK]BackupRF Success!!!!\n"); */
 381 #endif
 382 }
 383
 384 void _iqk_agc_bnd_int_8821c(struct dm_struct *dm)
 385 {
 386         /*initialize RX AGC bnd, it must do after bbreset*/
 387         odm_write_4byte(dm, 0x1b00, 0xf8000008);
 388         odm_write_4byte(dm, 0x1b00, 0xf80a7008);
 389         odm_write_4byte(dm, 0x1b00, 0xf8015008);
 390         odm_write_4byte(dm, 0x1b00, 0xf8000008);
 391 #if 0
 392         /*RF_DBG(dm, DBG_RF_IQK, "[IQK]init. rx agc bnd\n");*/
 393 #endif
 394 }
 395
 396 void _iqk_bb_reset_8821c(struct dm_struct *dm)
 397 {
 398         boolean cca_ing = false;
 399         u32 count = 0;
 400
 401         odm_set_rf_reg(dm, RF_PATH_A, RF_0x0, RFREGOFFSETMASK, 0x10000);
 402         odm_set_bb_reg(dm, R_0x8f8,
 403                        BIT(27) | BIT26 | BIT25 | BIT24 | BIT23 | BIT22 | BIT21 | BIT20, 0x0);
 404
 405         while (1) {
 406                 odm_write_4byte(dm, 0x8fc, 0x0);
 407                 odm_set_bb_reg(dm, R_0x198c, 0x7, 0x7);
 408                 cca_ing = (boolean)odm_get_bb_reg(dm, R_0xfa0, BIT(3));
 409
 410                 if (count > 30)
 411                         cca_ing = false;
 412
 413                 if (cca_ing) {
 414                         ODM_sleep_ms(1);
 415                         count++;
 416                 } else {
 417                         odm_write_1byte(dm, 0x808, 0x0); /*RX ant off*/
 418                         odm_set_bb_reg(dm, R_0xa04, BIT(27) | BIT26 | BIT25 | BIT24, 0x0); /*CCK RX path off*/
 419
 420                         /*BBreset*/
 421                         odm_set_bb_reg(dm, R_0x0, BIT(16), 0x0);
 422                         odm_set_bb_reg(dm, R_0x0, BIT(16), 0x1);
 423
 424                         if (odm_get_bb_reg(dm, R_0x660, BIT(16)))
 425                                 odm_write_4byte(dm, 0x6b4, 0x89000006);
 426                         RF_DBG(dm, DBG_RF_IQK, "[IQK]BBreset!!!!\n");
 427                         break;
 428                 }
 429         }
 430 }
 431
 432 void _iqk_afe_setting_8821c(struct dm_struct *dm, boolean do_iqk)
 433 {
 434         if (do_iqk) {
 435                 /*IQK AFE setting RX_WAIT_CCA mode */
 436                 odm_write_4byte(dm, 0xc60, 0x50000000);
 437                 odm_write_4byte(dm, 0xc60, 0x700F0040);
 438
 439                 /*AFE setting*/
 440                 odm_write_4byte(dm, 0xc58, 0xd8000402);
 441                 odm_write_4byte(dm, 0xc5c, 0xd1000120);
 442                 odm_write_4byte(dm, 0xc6c, 0x00000a15);
 443                 _iqk_bb_reset_8821c(dm);
 444 #if 0
 445                 /*              RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE setting for IQK mode!!!!\n"); */
 446 #endif
 447         } else {
 448                 /*IQK AFE setting RX_WAIT_CCA mode */
 449                 odm_write_4byte(dm, 0xc60, 0x50000000);
 450                 odm_write_4byte(dm, 0xc60, 0x700B8040);
 451
 452                 /*AFE setting*/
 453                 odm_write_4byte(dm, 0xc58, 0xd8020402);
 454                 odm_write_4byte(dm, 0xc5c, 0xde000120);
 455                 odm_write_4byte(dm, 0xc6c, 0x0000122a);
 456 #if 0
 457                 /*              RF_DBG(dm, DBG_RF_IQK, "[IQK]AFE setting for Normal mode!!!!\n"); */
 458 #endif
 459         }
 460         /*0x9a4[31]=0: Select da clock*/
 461         odm_set_bb_reg(dm, R_0x9a4, BIT(31), 0x0);
 462 }
 463
 464 void _iqk_restore_mac_bb_8821c(struct dm_struct *dm, u32 *MAC_backup,
 465                                u32 *BB_backup, u32 *backup_mac_reg,
 466                                u32 *backup_bb_reg, u8 num_backup_bb_reg)
 467 {
 468         u32 i;
 469
 470         for (i = 0; i < MAC_REG_NUM_8821C; i++)
 471                 odm_write_4byte(dm, backup_mac_reg[i], MAC_backup[i]);
 472         for (i = 0; i < num_backup_bb_reg; i++)
 473                 odm_write_4byte(dm, backup_bb_reg[i], BB_backup[i]);
 474 #if 0
 475         /*      RF_DBG(dm, DBG_RF_IQK, "[IQK]RestoreMacBB Success!!!!\n"); */
 476 #endif
 477 }
 478
 479 void _iqk_restore_rf_8821c(struct dm_struct *dm, u32 *backup_rf_reg,
 480                            u32 RF_backup[][SS_8821C])
 481 {
 482         u32 i;
 483
 484         odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x0);
 485         odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, RFREGOFFSETMASK, 0x0);
 486         odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, RF_backup[0][RF_PATH_A] & (~BIT(4)));
 487 #if 0
 488         /*odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK, RF_backup[1][RF_PATH_A]|BIT(4));*/
 489 #endif
 490         odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK, RF_backup[1][RF_PATH_A] & (~BIT(4)));
 491
 492         for (i = 2; i < (RF_REG_NUM_8821C - 1); i++)
 493                 odm_set_rf_reg(dm, RF_PATH_A, backup_rf_reg[i], RFREGOFFSETMASK, RF_backup[i][RF_PATH_A]);
 494
 495         odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, (RF_backup[4][RF_PATH_A] & (~BIT(0))));
 496 #if 0
 497         /*RF_DBG(dm, DBG_RF_IQK, "[IQK]RestoreRF Success!!!!\n"); */
 498 #endif
 499 }
 500
 501 void _iqk_backup_iqk_8821c(struct dm_struct *dm, u8 step, u8 path)
 502 {
 503         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 504         u8 i, j, k;
 505 #if 0
 506         /*u16           iqk_apply[2] = {0xc94, 0xe94};*/
 507 #endif
 508
 509         switch (step) {
 510         case 0:
 511                 iqk_info->iqk_channel[1] = iqk_info->iqk_channel[0];
 512                 for (i = 0; i < SS_8821C; i++) {
 513                         iqk_info->lok_idac[1][i] = iqk_info->lok_idac[0][i];
 514                         iqk_info->rxiqk_agc[1][i] = iqk_info->rxiqk_agc[0][i];
 515                         iqk_info->bypass_iqk[1][i] = iqk_info->bypass_iqk[0][i];
 516                         iqk_info->rxiqk_fail_code[1][i] = iqk_info->rxiqk_fail_code[0][i];
 517                         for (j = 0; j < 2; j++) {
 518                                 iqk_info->iqk_fail_report[1][i][j] = iqk_info->iqk_fail_report[0][i][j];
 519                                 for (k = 0; k < 8; k++) {
 520                                         iqk_info->iqk_cfir_real[1][i][j][k] = iqk_info->iqk_cfir_real[0][i][j][k];
 521                                         iqk_info->iqk_cfir_imag[1][i][j][k] = iqk_info->iqk_cfir_imag[0][i][j][k];
 522                                 }
 523                         }
 524                 }
 525                 for (i = 0; i < 4; i++) {
 526                         iqk_info->rxiqk_fail_code[0][i] = 0x0;
 527                         iqk_info->rxiqk_agc[0][i] = 0x0;
 528                         for (j = 0; j < 2; j++) {
 529                                 iqk_info->iqk_fail_report[0][i][j] = true;
 530                                 iqk_info->gs_retry_count[0][i][j] = 0x0;
 531                         }
 532                         for (j = 0; j < 3; j++)
 533                                 iqk_info->retry_count[0][i][j] = 0x0;
 534                 }
 535                 /*backup channel*/
 536                 iqk_info->iqk_channel[0] = iqk_info->rf_reg18;
 537                 break;
 538         case 1: /*LOK backup*/
 539                 iqk_info->lok_idac[0][path] = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK);
 540                 break;
 541         case 2: /*TXIQK backup*/
 542         case 3: /*RXIQK backup*/
 543                 phydm_get_iqk_cfir(dm, (step - 2), path, false);
 544                 break;
 545         }
 546 }
 547
 548 void _iqk_reload_iqk_setting_8821c(struct dm_struct *dm, u8 channel,
 549                                    u8 reload_idx
 550                                    /*1: reload TX, 2: reload TX, RX*/)
 551 {
 552         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 553         u8 i, path, idx;
 554         u16 iqk_apply[2] = {0xc94, 0xe94};
 555
 556         for (path = 0; path < SS_8821C; path++) {
 557 #if 0
 558                 if (reload_idx == 2) {
 559                         odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, BIT(4), 0x1);
 560                         odm_set_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK, iqk_info->lok_idac[channel][path]);
 561                 }
 562 #endif
 563                 for (idx = 0; idx < reload_idx; idx++) {
 564                         odm_set_bb_reg(dm, R_0x1b00, MASKDWORD, 0xf8000008 | path << 1);
 565                         odm_set_bb_reg(dm, R_0x1b2c, MASKDWORD, 0x7);
 566                         odm_set_bb_reg(dm, R_0x1b38, MASKDWORD, 0x20000000);
 567                         odm_set_bb_reg(dm, R_0x1b3c, MASKDWORD, 0x20000000);
 568                         odm_set_bb_reg(dm, R_0x1bcc, MASKDWORD, 0x00000000);
 569                         if (idx == 0)
 570                                 odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x3);
 571                         else
 572                                 odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x1);
 573                         odm_set_bb_reg(dm, R_0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x10);
 574                         for (i = 0; i < 8; i++) {
 575                                 odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x3) + (i * 4) + (iqk_info->iqk_cfir_real[channel][path][idx][i] << 9));
 576                                 odm_write_4byte(dm, 0x1bd8, ((0xc0000000 >> idx) + 0x1) + (i * 4) + (iqk_info->iqk_cfir_imag[channel][path][idx][i] << 9));
 577                         }
 578                         if (idx == 0)
 579                                 odm_set_bb_reg(dm, iqk_apply[path], BIT(0), ~(u32)(iqk_info->iqk_fail_report[channel][path][idx]));
 580                         else
 581                                 odm_set_bb_reg(dm, iqk_apply[path], BIT(10), ~(u32)(iqk_info->iqk_fail_report[channel][path][idx]));
 582                 }
 583                 odm_set_bb_reg(dm, R_0x1bd8, MASKDWORD, 0x0);
 584                 odm_set_bb_reg(dm, R_0x1b0c, BIT(13) | BIT(12), 0x0);
 585         }
 586 }
 587
 588 boolean
 589 _iqk_reload_iqk_8821c(struct dm_struct *dm, boolean reset)
 590 {
 591         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 592         u8 i;
 593         iqk_info->is_reload = false;
 594         odm_set_bb_reg(dm, R_0x1bf0, BIT(16), 0x0); /*clear the reload flag*/
 595
 596         if (reset) {
 597                 for (i = 0; i < SS_8821C; i++)
 598                         iqk_info->iqk_channel[i] = 0x0;
 599         } else {
 600                 iqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK);
 601
 602                 for (i = 0; i < SS_8821C; i++) {
 603                         if (iqk_info->rf_reg18 == iqk_info->iqk_channel[i]) {
 604                                 _iqk_reload_iqk_setting_8821c(dm, i, 2);
 605                                 _iqk_fill_iqk_report_8821c(dm, i);
 606                                 RF_DBG(dm, DBG_RF_IQK,
 607                                        "[IQK]reload IQK result before!!!!\n");
 608                                 odm_set_bb_reg(dm, R_0x1bf0, BIT(16), 0x1);
 609                                 iqk_info->is_reload = true;
 610                         }
 611                 }
 612         }
 613
 614         return iqk_info->is_reload;
 615 }
 616
 617 void _iqk_rfe_setting_8821c(struct dm_struct *dm, boolean ext_pa_on)
 618 {
 619         if (ext_pa_on) {
 620                 /*RFE setting*/
 621                 odm_write_4byte(dm, 0xcb0, 0x77777777);
 622                 odm_write_4byte(dm, 0xcb4, 0x00007777);
 623                 odm_write_4byte(dm, 0xcbc, 0x0000083B);
 624 #if 0
 625                 /*odm_write_4byte(dm, 0x1990, 0x00000c30);*/
 626 #endif
 627                 RF_DBG(dm, DBG_RF_IQK, "[IQK]external PA on!!!!\n");
 628         } else {
 629                 /*RFE setting*/
 630                 odm_write_4byte(dm, 0xcb0, 0x77171117);
 631                 odm_write_4byte(dm, 0xcb4, 0x00001177);
 632                 odm_write_4byte(dm, 0xcbc, 0x00000404);
 633 #if 0
 634                 /*odm_write_4byte(dm, 0x1990, 0x00000c30);*/
 635 #endif
 636                 RF_DBG(dm, DBG_RF_IQK, "[IQK]external PA off!!!!\n");
 637         }
 638 }
 639
 640 void _iqk_rfsetting_8821c(struct dm_struct *dm)
 641 {
 642         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 643
 644         u8 path;
 645         u32 tmp;
 646
 647         odm_write_4byte(dm, 0x1b00, 0xf8000008);
 648         odm_write_4byte(dm, 0x1bb8, 0x00000000);
 649
 650         for (path = 0; path < SS_8821C; path++) {
 651                 /*0xdf:B11 = 1,B4 = 0, B1 = 1*/
 652                 tmp = odm_get_rf_reg(dm, (enum rf_path)path, RF_0xdf, RFREGOFFSETMASK);
 653                 tmp = (tmp & (~BIT(4))) | BIT(1) | BIT(11);
 654                 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xdf, RFREGOFFSETMASK, tmp);
 655
 656                 if (iqk_info->is_btg) {
 657                         tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK);
 658                         tmp = (tmp & (~BIT(4))) | BIT(15);
 659 #if 0
 660                         /*tmp = tmp|BIT(4)|BIT(15); //manual LOK value  for A-cut*/
 661 #endif
 662                         odm_set_rf_reg(dm, RF_PATH_A, RF_0xde, RFREGOFFSETMASK, tmp);
 663                 }
 664
 665                 if (!iqk_info->is_btg) {
 666                         /*WLAN_AG*/
 667                         /*TX IQK         mode init*/
 668                         odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, RFREGOFFSETMASK, 0x80000);
 669                         odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00024);
 670                         odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x0003f);
 671 #if 0
 672                         /*odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x60fde);*/
 673 #endif
 674                         odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0xe0fde);
 675                         odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, RFREGOFFSETMASK, 0x00000);
 676                         if (*dm->band_type == ODM_BAND_5G) {
 677                                 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1);
 678                                 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00026);
 679                                 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00037);
 680                                 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0xdefce);
 681                                 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0);
 682                         } else {
 683                                 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x1);
 684                                 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00026);
 685                                 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3e, RFREGOFFSETMASK, 0x00037);
 686                                 odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x5efce);
 687                                 odm_set_rf_reg(dm, (enum rf_path)path, RF_0xef, BIT(19), 0x0);
 688                         }
 689                 } else {
 690                         /*WLAN_BTG*/
 691                         /*TX IQK         mode init*/
 692                         odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, RFREGOFFSETMASK, 0x01000);
 693                         odm_set_rf_reg(dm, (enum rf_path)path, RF_0x33, RFREGOFFSETMASK, 0x00004);
 694                         odm_set_rf_reg(dm, (enum rf_path)path, RF_0x3f, RFREGOFFSETMASK, 0x01ec1);
 695                         odm_set_rf_reg(dm, (enum rf_path)path, RF_0xee, RFREGOFFSETMASK, 0x00000);
 696                 }
 697         }
 698 }
 699
 700 void _iqk_configure_macbb_8821c(struct dm_struct *dm)
 701 {
 702         /*MACBB register setting*/
 703         odm_write_1byte(dm, 0x522, 0x7f);
 704         odm_set_bb_reg(dm, R_0x1518, BIT(16), 0x1);
 705         odm_set_bb_reg(dm, R_0x550, BIT(11) | BIT(3), 0x0);
 706         odm_set_bb_reg(dm, R_0x90c, BIT(15), 0x1); /*0x90c[15]=1: dac_buf reset selection*/
 707
 708         /*0xc94[0]=1, 0xe94[0]=1: Let tx from IQK*/
 709         odm_set_bb_reg(dm, R_0xc94, BIT(0), 0x1);
 710         odm_set_bb_reg(dm, R_0xc94, (BIT(11) | BIT(10)), 0x1);
 711         /* 3-wire off*/
 712         odm_write_4byte(dm, 0xc00, 0x00000004);
 713         /*disable PMAC*/
 714         odm_set_bb_reg(dm, R_0xb00, BIT(8), 0x0);
 715 #if 0
 716         /*      RF_DBG(dm, DBG_RF_IQK, "[IQK]Set MACBB setting for IQK!!!!\n");*/
 717 #endif
 718         /*disable CCK block*/
 719         odm_set_bb_reg(dm, R_0x808, BIT(28), 0x0);
 720         /*disable OFDM CCA*/
 721         odm_set_bb_reg(dm, R_0x838, BIT(3) | BIT(2) | BIT(1), 0x7);
 722
 723 }
 724
 725 void _iqk_lok_setting_8821c(struct dm_struct *dm, u8 path, u8 pad_index)
 726 {
 727         u32 LOK0x56_2G = 0x50ef3;
 728         u32 LOK0x56_5G = 0x50ee8;
 729         u32 LOK0x33 = 0;
 730         u32 LOK0x78 = 0xbcbba;
 731         u32 tmp = 0;
 732
 733         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 734
 735         LOK0x33 = pad_index;
 736         /*add delay of MAC send packet*/
 737
 738         if (*dm->mp_mode)
 739                 odm_set_bb_reg(dm, R_0x810, BIT(7) | BIT(6) | BIT(5) | BIT(4), 0x8);
 740
 741         if (iqk_info->is_btg) {
 742                 tmp = (LOK0x78 & 0x1c000) >> 14;
 743                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
 744                 odm_write_4byte(dm, 0x1bcc, 0x1b);
 745                 odm_write_1byte(dm, 0x1b23, 0x00);
 746                 odm_write_1byte(dm, 0x1b2b, 0x80);
 747                 /*0x78[11:0] = IDAC value*/
 748                 LOK0x78 = LOK0x78 & (0xe3fff | ((u32)pad_index << 14));
 749                 odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, LOK0x78);
 750                 odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x05320);
 751                 odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xac018);
 752                 odm_set_rf_reg(dm, RF_PATH_A, RF_0xee, BIT(4), 0x1);
 753                 odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, BIT(3), 0x0);
 754                 RF_DBG(dm, DBG_RF_IQK, "[IQK] In the BTG\n");
 755         } else {
 756                 /*tmp = (LOK0x56 & 0xe0) >> 5;*/
 757                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
 758                 odm_write_4byte(dm, 0x1bcc, 0x9);
 759                 odm_write_1byte(dm, 0x1b23, 0x00);
 760
 761                 switch (*dm->band_type) {
 762                 case ODM_BAND_2_4G:
 763                         odm_write_1byte(dm, 0x1b2b, 0x00);
 764                         LOK0x56_2G = LOK0x56_2G & (0xfff1f | ((u32)pad_index << 5));
 765                         odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, LOK0x56_2G);
 766                         odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xadc18);
 767                         odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(4), 0x1);
 768                         odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, BIT(3), 0x0);
 769                         break;
 770                 case ODM_BAND_5G:
 771                         odm_write_1byte(dm, 0x1b2b, 0x00);
 772                         LOK0x56_5G = LOK0x56_5G & (0xfff1f | ((u32)pad_index << 5));
 773                         odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, LOK0x56_5G);
 774                         odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xadc18);
 775                         odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, BIT(4), 0x1);
 776                         odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, BIT(3), 0x1);
 777                         break;
 778                 }
 779         }
 780         /*for IDAC LUT by PAD idx*/
 781         odm_set_rf_reg(dm, path, RF_0x33, BIT(2) | BIT(1) | BIT(0), LOK0x33);
 782 #if 0
 783         /*      RF_DBG(dm, DBG_RF_IQK, "[IQK]Set LOK setting!!!!\n");*/
 784 #endif
 785 }
 786
 787 void _iqk_txk_setting_8821c(struct dm_struct *dm, u8 path)
 788 {
 789         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 790
 791         if (iqk_info->is_btg) {
 792                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
 793                 odm_write_4byte(dm, 0x1bcc, 0x1b);
 794                 odm_write_4byte(dm, 0x1b20, 0x00840008);
 795
 796                 /*0x78[11:0] = IDAC value*/
 797                 odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0xbcbba);
 798                 odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x04320);
 799                 odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xac018);
 800                 odm_write_1byte(dm, 0x1b2b, 0x80);
 801         } else {
 802                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
 803                 odm_write_4byte(dm, 0x1bcc, 0x9);
 804                 odm_write_4byte(dm, 0x1b20, 0x01440008);
 805
 806                 switch (*dm->band_type) {
 807                 case ODM_BAND_2_4G:
 808                         odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x50EF3);
 809                         odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xadc18);
 810                         odm_write_1byte(dm, 0x1b2b, 0x00);
 811                         break;
 812                 case ODM_BAND_5G:
 813 #if 0
 814                         /*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x50EF0);*/
 815                         /*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x50Ec8);*/
 816 #endif
 817                         odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x5004e);
 818                         odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c18);
 819                         odm_write_1byte(dm, 0x1b2b, 0x00);
 820                         break;
 821                 }
 822         }
 823 #if 0
 824         /*      RF_DBG(dm, DBG_RF_IQK, "[IQK]Set TXK setting!!!!\n");*/
 825 #endif
 826 }
 827
 828 void _iqk_rxk1setting_8821c(struct dm_struct *dm, u8 path)
 829 {
 830         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 831
 832         if (iqk_info->is_btg) {
 833                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
 834                 odm_write_1byte(dm, 0x1b2b, 0x80);
 835                 odm_write_4byte(dm, 0x1bcc, 0x09);
 836                 odm_write_4byte(dm, 0x1b20, 0x01450008);
 837                 odm_write_4byte(dm, 0x1b24, 0x01460c88);
 838
 839                 /*0x78[11:0] = IDAC value*/
 840                 odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0x8cbba);
 841                 odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x00320);
 842                 odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa8018);
 843         } else {
 844                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
 845                 switch (*dm->band_type) {
 846                 case ODM_BAND_2_4G:
 847                         odm_write_1byte(dm, 0x1bcc, 0x12);
 848                         odm_write_1byte(dm, 0x1b2b, 0x00);
 849                         odm_write_4byte(dm, 0x1b20, 0x01450008);
 850                         odm_write_4byte(dm, 0x1b24, 0x01461068);
 851
 852                         odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3);
 853                         odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
 854                         break;
 855                 case ODM_BAND_5G:
 856                         odm_write_1byte(dm, 0x1bcc, 0x9);
 857                         odm_write_1byte(dm, 0x1b2b, 0x00);
 858                         odm_write_4byte(dm, 0x1b20, 0x00450008);
 859                         odm_write_4byte(dm, 0x1b24, 0x00461468);
 860
 861                         odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3);
 862                         odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
 863                         break;
 864                 }
 865         }
 866 #if 0
 867         /*RF_DBG(dm, DBG_RF_IQK, "[IQK]Set RXK setting!!!!\n");*/
 868 #endif
 869 }
 870
 871 static u8 btg_lna[5] = {0x0, 0x4, 0x8, 0xc, 0xf};
 872 static u8 wlg_lna[5] = {0x0, 0x1, 0x2, 0x3, 0x5};
 873 static u8 wla_lna[5] = {0x0, 0x1, 0x3, 0x4, 0x5};
 874
 875 void _iqk_rxk2setting_8821c(struct dm_struct *dm, u8 path, boolean is_gs)
 876 {
 877         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 878
 879         if (iqk_info->is_btg) {
 880                 if (is_gs) {
 881                         iqk_info->tmp1bcc = 0x1b;
 882                         iqk_info->lna_idx = 2;
 883                 }
 884                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
 885                 odm_write_1byte(dm, 0x1b2b, 0x80);
 886                 odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc);
 887                 odm_write_4byte(dm, 0x1b20, 0x01450008);
 888                 odm_write_4byte(dm, 0x1b24, (0x01460048 | (btg_lna[iqk_info->lna_idx] << 10)));
 889                 /*0x78[11:0] = IDAC value*/
 890                 odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0x8cbba);
 891                 odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x00320);
 892                 odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa8018);
 893         } else {
 894                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
 895                 switch (*dm->band_type) {
 896                 case ODM_BAND_2_4G:
 897                         if (is_gs) {
 898                                 iqk_info->tmp1bcc = 0x12;
 899                                 iqk_info->lna_idx = 2;
 900                         }
 901                         odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
 902                         odm_write_1byte(dm, 0x1b2b, 0x00);
 903                         odm_write_4byte(dm, 0x1b20, 0x01450008);
 904                         odm_write_4byte(dm, 0x1b24, (0x01460048 | (wlg_lna[iqk_info->lna_idx] << 10)));
 905                         odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3);
 906                         odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
 907                         break;
 908                 case ODM_BAND_5G:
 909                         if (is_gs) {
 910                                 /*iqk_info->tmp1bcc = 0x12;*/
 911                                 iqk_info->tmp1bcc = 0x09;
 912                                 iqk_info->lna_idx = 2;
 913                         }
 914                         odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
 915                         odm_write_1byte(dm, 0x1b2b, 0x00);
 916                         odm_write_4byte(dm, 0x1b20, 0x00450008);
 917                         odm_write_4byte(dm, 0x1b24, (0x01460048 | (wla_lna[iqk_info->lna_idx] << 10)));
 918 #if 0
 919                         /*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51000);*/
 920 #endif
 921                         odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51060);
 922                         odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
 923                         break;
 924                 }
 925         }
 926 #if 0
 927         /*      RF_DBG(dm, DBG_RF_IQK, "[IQK]Set RXK setting!!!!\n");*/
 928 #endif
 929 }
 930
 931 boolean
 932 _iqk_check_cal_8821c(struct dm_struct *dm, u32 IQK_CMD)
 933 {
 934         boolean notready = true, fail = true;
 935         u32 delay_count = 0x0;
 936
 937         while (notready) {
 938                 if (odm_read_4byte(dm, 0x1b00) == (IQK_CMD & 0xffffff0f)) {
 939                         fail = (boolean)odm_get_bb_reg(dm, R_0x1b08, BIT(26));
 940                         notready = false;
 941                 } else {
 942 #if 0
 943                         /*ODM_sleep_ms(1);*/
 944 #endif
 945                         ODM_delay_ms(1);
 946                         delay_count++;
 947                 }
 948
 949                 if (delay_count >= 50) {
 950                         fail = true;
 951                         RF_DBG(dm, DBG_RF_IQK, "[IQK]IQK timeout!!!\n");
 952                         break;
 953                 }
 954         }
 955 #if 0
 956         /*
 957         RF_DBG(dm, DBG_RF_IQK,
 958                      "[IQK]delay count = 0x%x!!!\n", delay_count);
 959 */
 960 #endif
 961         return fail;
 962 }
 963
 964 boolean
 965 _iqk_rx_iqk_gain_search_fail_8821c(struct dm_struct *dm, u8 path, u8 step)
 966 {
 967         struct dm_iqk_info *iqk_info = &dm->IQK_info;
 968         boolean fail = true;
 969         u32 IQK_CMD = 0x0, rf_reg0, tmp, rxbb;
 970         u8 IQMUX[4] = {0x9, 0x12, 0x1b, 0x24}, *plna;
 971         u8 idx;
 972         /*u8    lna_setting[5];*/
 973
 974         if (iqk_info->is_btg)
 975                 plna = btg_lna;
 976         else if (*dm->band_type == ODM_BAND_2_4G)
 977                 plna = wlg_lna;
 978         else
 979                 plna = wla_lna;
 980
 981         for (idx = 0; idx < 4; idx++)
 982                 if (iqk_info->tmp1bcc == IQMUX[idx])
 983                         break;
 984
 985         odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
 986         odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc);
 987
 988         if (step == RXIQK1)
 989                 RF_DBG(dm, DBG_RF_IQK,
 990                        "[IQK]============ S%d RXIQK GainSearch ============\n",
 991                        iqk_info->is_btg);
 992
 993         if (step == RXIQK1)
 994                 IQK_CMD = 0xf8000208 | (1 << (path + 4));
 995         else
 996                 IQK_CMD = 0xf8000308 | (1 << (path + 4));
 997
 998         RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d GS%d_Trigger = 0x%x\n", path, step,
 999                IQK_CMD);
1000
1001         _iqk_set_gnt_wl_gnt_bt(dm, true);
1002         odm_write_4byte(dm, 0x1b00, IQK_CMD);
1003         odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
1004 #if 0
1005         /*ODM_sleep_ms(GS_delay_8821C);*/
1006 #endif
1007         ODM_delay_ms(GS_delay_8821C);
1008         fail = _iqk_check_cal_8821c(dm, IQK_CMD);
1009         RF_DBG(dm, DBG_RF_IQK, "[IQK]check 0x49c = %x\n",
1010                odm_read_1byte(dm, 0x49c));
1011         _iqk_set_gnt_wl_gnt_bt(dm, false);
1012
1013         if (step == RXIQK2) {
1014                 rf_reg0 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x0, RFREGOFFSETMASK);
1015                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
1016                 RF_DBG(dm, DBG_RF_IQK,
1017                        "[IQK]S%d ==> RF0x0 = 0x%x, tmp1bcc = 0x%x, idx = %d, 0x1b3c = 0x%x\n",
1018                        path, rf_reg0, iqk_info->tmp1bcc, idx,
1019                        odm_read_4byte(dm, 0x1b3c));
1020                 tmp = (rf_reg0 & 0x1fe0) >> 5;
1021                 rxbb = tmp & 0x1f;
1022 #if 1
1023
1024                 if (rxbb == 0x1) {
1025                         if (idx != 3)
1026                                 idx++;
1027                         else if (iqk_info->lna_idx != 0x0)
1028                                 iqk_info->lna_idx--;
1029                         else
1030                                 iqk_info->isbnd = true;
1031                         fail = true;
1032                 } else if (rxbb == 0xa) {
1033                         if (idx != 0)
1034                                 idx--;
1035                         else if (iqk_info->lna_idx != 0x4)
1036                                 iqk_info->lna_idx++;
1037                         else
1038                                 iqk_info->isbnd = true;
1039                         fail = true;
1040                 } else {
1041                         fail = false;
1042                 }
1043
1044                 if (iqk_info->isbnd)
1045                         fail = false;
1046 #endif
1047
1048 #if 0
1049                 if (rxbb == 0x1) {
1050                         if (iqk_info->lna_idx != 0x0)
1051                                 iqk_info->lna_idx--;
1052                         else if (idx != 3)
1053                                 idx++;
1054                         else
1055                                 iqk_info->isbnd = true;
1056                         fail = true;
1057                 } else if (rxbb == 0xa) {
1058                         if (idx != 0)
1059                                 idx--;
1060                         else if (iqk_info->lna_idx != 0x7)
1061                                 iqk_info->lna_idx++;
1062                         else
1063                                 iqk_info->isbnd = true;
1064                         fail = true;
1065                 } else
1066                         fail = false;
1067
1068                 if (iqk_info->isbnd == true)
1069                         fail = false;
1070 #endif
1071                 iqk_info->tmp1bcc = IQMUX[idx];
1072
1073                 if (fail) {
1074                         odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
1075                         odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0xffffc3ff) | (*(plna + iqk_info->lna_idx) << 10));
1076                 }
1077         }
1078         return fail;
1079 }
1080 void _iqk_rxk2setting_by_toneindex_8821c(struct dm_struct *dm, u8 path,
1081                                          boolean is_gs, u8 toneindex)
1082 {
1083         struct dm_iqk_info *iqk_info = &dm->IQK_info;
1084
1085         if (iqk_info->is_btg) {
1086                 iqk_info->tmp1bcc = 0x1b;
1087                 iqk_info->lna_idx = 2;
1088                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
1089                 odm_write_1byte(dm, 0x1b2b, 0x80);
1090                 odm_write_4byte(dm, 0x1bcc, iqk_info->tmp1bcc);
1091                 odm_write_4byte(dm, 0x1b20, 0x01450008);
1092                 odm_write_4byte(dm, 0x1b24, (0x01460048 | (btg_lna[iqk_info->lna_idx] << 10)));
1093                 /*0x78[11:0] = IDAC value*/
1094                 odm_set_rf_reg(dm, path, RF_0x78, RFREGOFFSETMASK, 0x8cbba);
1095                 odm_set_rf_reg(dm, path, RF_0x5c, RFREGOFFSETMASK, 0x00320);
1096                 odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa8018);
1097         } else {
1098                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
1099                 switch (*dm->band_type) {
1100                 case ODM_BAND_2_4G:
1101                         iqk_info->tmp1bcc = 0x12;
1102                         iqk_info->lna_idx = 2;
1103                         odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
1104                         odm_write_1byte(dm, 0x1b2b, 0x00);
1105                         odm_write_4byte(dm, 0x1b20, 0x01450008);
1106                         odm_write_4byte(dm, 0x1b24, (0x01460048 | (wlg_lna[iqk_info->lna_idx] << 10)));
1107                         odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x510f3);
1108                         odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
1109                         break;
1110                 case ODM_BAND_5G:
1111                         iqk_info->tmp1bcc = 0x09;
1112                         iqk_info->lna_idx = 2;
1113                         odm_write_1byte(dm, 0x1bcc, iqk_info->tmp1bcc);
1114                         odm_write_1byte(dm, 0x1b2b, 0x00);
1115                         odm_write_4byte(dm, 0x1b20, 0x00450008);
1116                         odm_write_4byte(dm, 0x1b24, (0x01460048 | (wla_lna[iqk_info->lna_idx] << 10)));
1117 #if 0
1118                         /*odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51000);*/
1119 #endif
1120                         odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, 0x51060);
1121                         odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
1122                         break;
1123                 }
1124         }
1125         odm_write_4byte(dm, 0x1b20, (odm_read_4byte(dm, 0x1b20) & 0x000fffff) | toneindex << 20);
1126         odm_write_4byte(dm, 0x1b24, (odm_read_4byte(dm, 0x1b24) & 0x000fffff) | toneindex << 20);
1127 }
1128
1129 boolean
1130 _iqk_rx_iqk_gain_search_fail_by_toneindex_8821c(struct dm_struct *dm, u8 path,
1131                                                 u8 step, u8 tone_index)
1132 {
1133         boolean fail = true;
1134         u32 IQK_CMD;
1135 #if 0
1136         /*u8    lna_setting[5];*/
1137 #endif
1138
1139         _iqk_rxk2setting_by_toneindex_8821c(dm, path, RXIQK1, tone_index);
1140         odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
1141
1142         IQK_CMD = 0xf8000208 | (1 << (path + 4));
1143
1144         _iqk_set_gnt_wl_gnt_bt(dm, true);
1145         odm_write_4byte(dm, 0x1b00, IQK_CMD);
1146         odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
1147 #if 0
1148         /*ODM_sleep_ms(GS_delay_8821C);*/
1149 #endif
1150         ODM_delay_ms(GS_delay_8821C);
1151         fail = _iqk_check_cal_8821c(dm, IQK_CMD);
1152         _iqk_set_gnt_wl_gnt_bt(dm, false);
1153
1154         return fail;
1155 }
1156
1157 boolean
1158 _lok_one_shot_8821c(void *dm_void, u8 path, u8 pad_index)
1159 {
1160         struct dm_struct *dm = (struct dm_struct *)dm_void;
1161         struct dm_iqk_info *iqk_info = &dm->IQK_info;
1162         u8 delay_count = 0;
1163         boolean LOK_notready = false;
1164         u32 LOK_temp2 = 0, LOK_temp3 = 0;
1165         u32 IQK_CMD = 0x0;
1166 #if 0
1167         /*u8            LOKreg[] = {0x58, 0x78};*/
1168 #endif
1169         RF_DBG(dm, DBG_RF_IQK, "[IQK]==========S%d LOK ==========\n",
1170                iqk_info->is_btg);
1171
1172         IQK_CMD = 0xf8000008 | (1 << (4 + path));
1173
1174         RF_DBG(dm, DBG_RF_IQK, "[IQK]LOK_Trigger = 0x%x\n", IQK_CMD);
1175
1176         _iqk_set_gnt_wl_gnt_bt(dm, true);
1177         odm_write_4byte(dm, 0x1b00, IQK_CMD);
1178         odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
1179         /*LOK: CMD ID = 0       {0xf8000018, 0xf8000028}*/
1180         /*LOK: CMD ID = 0       {0xf8000019, 0xf8000029}*/
1181 #if 0
1182         /*ODM_sleep_ms(LOK_delay_8821C);*/
1183 #endif
1184         ODM_delay_ms(LOK_delay_8821C);
1185
1186         delay_count = 0;
1187         LOK_notready = true;
1188
1189         while (LOK_notready) {
1190                 if (odm_get_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK) == 0x12345)
1191                         LOK_notready = false;
1192                 else
1193                         LOK_notready = true;
1194
1195                 if (LOK_notready) {
1196 #if 0
1197                         /*ODM_sleep_ms(1);*/
1198 #endif
1199                         ODM_delay_ms(1);
1200                         delay_count++;
1201                 }
1202
1203                 if (delay_count >= 50) {
1204                         RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d LOK timeout!!!\n",
1205                                path);
1206                         break;
1207                 }
1208         }
1209         odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
1210
1211         _iqk_set_gnt_wl_gnt_bt(dm, false);
1212         RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d ==> delay_count = 0x%x\n", path,
1213                delay_count);
1214
1215         if (!LOK_notready) {
1216                 LOK_temp2 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x8, RFREGOFFSETMASK);
1217                 LOK_temp3 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x58, RFREGOFFSETMASK);
1218
1219                 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x8 = 0x%x, 0x58 = 0x%x\n",
1220                        LOK_temp2, LOK_temp3);
1221         } else {
1222                 RF_DBG(dm, DBG_RF_IQK, "[IQK]==>S%d LOK Fail!!!\n", path);
1223         }
1224
1225         iqk_info->lok_fail[path] = LOK_notready;
1226
1227         /*fill IDAC LUT table*/
1228 #if 0
1229         /*
1230         for (i = 0; i < 8; i++) {
1231                 odm_set_rf_reg(dm, path, RF_0x33, BIT(2)|BIT(1)|BIT(0), i);
1232                 odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, LOK_temp2);
1233         }
1234         */
1235 #endif
1236         return LOK_notready;
1237 }
1238
1239 boolean
1240 _iqk_one_shot_8821c(void *dm_void, u8 path, u8 idx)
1241 {
1242         struct dm_struct *dm = (struct dm_struct *)dm_void;
1243         struct dm_iqk_info *iqk_info = &dm->IQK_info;
1244         u8 delay_count = 0;
1245         boolean fail = true;
1246         u32 IQK_CMD = 0x0;
1247         u16 iqk_apply[2] = {0xc94, 0xe94};
1248
1249         if (idx == TX_IQK)
1250                 RF_DBG(dm, DBG_RF_IQK,
1251                        "[IQK]============ S%d WBTXIQK ============\n",
1252                        iqk_info->is_btg);
1253         else if (idx == RXIQK1)
1254                 RF_DBG(dm, DBG_RF_IQK,
1255                        "[IQK]============ S%d WBRXIQK STEP1============\n",
1256                        iqk_info->is_btg);
1257         else
1258                 RF_DBG(dm, DBG_RF_IQK,
1259                        "[IQK]============ S%d WBRXIQK STEP2============\n",
1260                        iqk_info->is_btg);
1261
1262         if (idx == TXIQK) {
1263                 IQK_CMD = 0xf8000008 | ((*dm->band_width + 4) << 8) | (1 << (path + 4));
1264                 RF_DBG(dm, DBG_RF_IQK, "[IQK]TXK_Trigger = 0x%x\n", IQK_CMD);
1265 #if 0
1266                 /*{0xf8000418, 0xf800042a} ==> 20 WBTXK (CMD = 4)*/
1267                 /*{0xf8000518, 0xf800052a} ==> 40 WBTXK (CMD = 5)*/
1268                 /*{0xf8000618, 0xf800062a} ==> 80 WBTXK (CMD = 6)*/
1269 #endif
1270         } else if (idx == RXIQK1) {
1271                 if (*dm->band_width == 2)
1272                         IQK_CMD = 0xf8000808 | (1 << (path + 4));
1273                 else
1274                         IQK_CMD = 0xf8000708 | (1 << (path + 4));
1275                 RF_DBG(dm, DBG_RF_IQK, "[IQK]RXK1_Trigger = 0x%x\n", IQK_CMD);
1276 #if 0
1277                 /*{0xf8000718, 0xf800072a} ==> 20 WBTXK (CMD = 7)*/
1278                 /*{0xf8000718, 0xf800072a} ==> 40 WBTXK (CMD = 7)*/
1279                 /*{0xf8000818, 0xf800082a} ==> 80 WBTXK (CMD = 8)*/
1280 #endif
1281         } else if (idx == RXIQK2) {
1282                 IQK_CMD = 0xf8000008 | ((*dm->band_width + 9) << 8) | (1 << (path + 4));
1283                 RF_DBG(dm, DBG_RF_IQK, "[IQK]RXK2_Trigger = 0x%x\n", IQK_CMD);
1284 #if 0
1285                 /*{0xf8000918, 0xf800092a} ==> 20 WBRXK (CMD = 9)*/
1286                 /*{0xf8000a18, 0xf8000a2a} ==> 40 WBRXK (CMD = 10)*/
1287                 /*{0xf8000b18, 0xf8000b2a} ==> 80 WBRXK (CMD = 11)*/
1288 #endif
1289         }
1290
1291         _iqk_set_gnt_wl_gnt_bt(dm, true);
1292
1293         odm_write_4byte(dm, 0x1bc8, 0x80000000);
1294         odm_write_4byte(dm, 0x8f8, 0x41400080);
1295
1296         if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0)
1297                 odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
1298
1299         odm_write_4byte(dm, 0x1b00, IQK_CMD);
1300         odm_write_4byte(dm, 0x1b00, IQK_CMD + 0x1);
1301
1302 #if 0
1303         /*ODM_sleep_ms(WBIQK_delay_8821C);*/
1304 #endif
1305         ODM_delay_ms(WBIQK_delay_8821C);
1306
1307         fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD);
1308
1309         RF_DBG(dm, DBG_RF_IQK, "[IQK]check 0x49c = %x\n",
1310                odm_read_1byte(dm, 0x49c));
1311
1312         _iqk_set_gnt_wl_gnt_bt(dm, false);
1313
1314         if (dm->debug_components & DBG_RF_IQK) {
1315                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
1316                 RF_DBG(dm, DBG_RF_IQK,
1317                        "[IQK]S%d ==> 0x1b00 = 0x%x, 0x1b08 = 0x%x\n", path,
1318                        odm_read_4byte(dm, 0x1b00), odm_read_4byte(dm, 0x1b08));
1319                 RF_DBG(dm, DBG_RF_IQK, "[IQK]S%d ==> delay_count = 0x%x\n",
1320                        path, delay_count);
1321                 if (idx != TXIQK)
1322                         RF_DBG(dm, DBG_RF_IQK,
1323                                "[IQK]S%d ==> RF0x0 = 0x%x, RF0x%x = 0x%x\n",
1324                                path,
1325                                odm_get_rf_reg(dm, path, RF_0x0,
1326                                               RFREGOFFSETMASK),
1327                                (iqk_info->is_btg) ? 0x78 : 0x56,
1328                                (iqk_info->is_btg) ?
1329                                odm_get_rf_reg(dm, path, RF_0x78,
1330                                               RFREGOFFSETMASK) :
1331                                odm_get_rf_reg(dm, path, RF_0x56,
1332                                               RFREGOFFSETMASK));
1333         }
1334
1335         odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
1336         if (idx == TXIQK) {
1337                 if (fail)
1338                         odm_set_bb_reg(dm, iqk_apply[path], BIT(0), 0x0);
1339                 else
1340                         _iqk_backup_iqk_8821c(dm, 0x2, path);
1341         }
1342         if (idx == RXIQK2) {
1343                 iqk_info->rxiqk_agc[0][path] =
1344                         (u16)(((odm_get_rf_reg(dm, (enum rf_path)path, RF_0x0, RFREGOFFSETMASK) >> 5) & 0xff) |
1345                               (iqk_info->tmp1bcc << 8));
1346
1347                 odm_write_4byte(dm, 0x1b38, 0x20000000);
1348
1349                 if (fail)
1350                         odm_set_bb_reg(dm, iqk_apply[path], (BIT(11) | BIT(10)), 0x0);
1351                 else
1352                         _iqk_backup_iqk_8821c(dm, 0x3, path);
1353         }
1354
1355         if (idx == TXIQK)
1356                 iqk_info->iqk_fail_report[0][path][TXIQK] = fail;
1357         else
1358                 iqk_info->iqk_fail_report[0][path][RXIQK] = fail;
1359
1360         return fail;
1361 }
1362
1363 boolean
1364 _iqk_rxiqkbystep_8821c(void *dm_void, u8 path)
1365 {
1366         struct dm_struct *dm = (struct dm_struct *)dm_void;
1367         struct dm_iqk_info *iqk_info = &dm->IQK_info;
1368         boolean KFAIL = true, gonext;
1369
1370 #if 1
1371         switch (iqk_info->rxiqk_step) {
1372         case 1: /*gain search_RXK1*/
1373                 _iqk_rxk1setting_8821c(dm, path);
1374                 gonext = false;
1375                 while (1) {
1376                         KFAIL = _iqk_rx_iqk_gain_search_fail_8821c(dm, path, RXIQK1);
1377                         if (KFAIL && iqk_info->gs_retry_count[0][path][0] < 2) {
1378                                 iqk_info->gs_retry_count[0][path][0]++;
1379                         } else if (KFAIL) {
1380                                 iqk_info->rxiqk_fail_code[0][path] = 0;
1381                                 iqk_info->rxiqk_step = 5;
1382                                 gonext = true;
1383                         } else {
1384                                 iqk_info->rxiqk_step++;
1385                                 gonext = true;
1386                         }
1387                         if (gonext)
1388                                 break;
1389                 }
1390                 halrf_iqk_xym_read(dm, 0x0, 0x2);
1391                 break;
1392         case 2: /*gain search_RXK2*/
1393                 _iqk_rxk2setting_8821c(dm, path, true);
1394                 iqk_info->isbnd = false;
1395                 while (1) {
1396                         KFAIL = _iqk_rx_iqk_gain_search_fail_8821c(dm, path, RXIQK2);
1397                         if (KFAIL && iqk_info->gs_retry_count[0][path][1] < rxiqk_gs_limit) {
1398                                 iqk_info->gs_retry_count[0][path][1]++;
1399                         } else {
1400                                 iqk_info->rxiqk_step++;
1401                                 break;
1402                         }
1403                 }
1404                 halrf_iqk_xym_read(dm, 0x0, 0x3);
1405                 break;
1406         case 3: /*RXK1*/
1407                 _iqk_rxk1setting_8821c(dm, path);
1408                 gonext = false;
1409                 while (1) {
1410                         KFAIL = _iqk_one_shot_8821c(dm, path, RXIQK1);
1411                         if (KFAIL && iqk_info->retry_count[0][path][RXIQK1] < 2) {
1412                                 iqk_info->retry_count[0][path][RXIQK1]++;
1413                         } else if (KFAIL) {
1414                                 iqk_info->rxiqk_fail_code[0][path] = 1;
1415                                 iqk_info->rxiqk_step = 5;
1416                                 gonext = true;
1417                         } else {
1418                                 iqk_info->rxiqk_step++;
1419                                 gonext = true;
1420                         }
1421                         if (gonext)
1422                                 break;
1423                 }
1424                 halrf_iqk_xym_read(dm, 0x0, 0x4);
1425                 break;
1426         case 4: /*RXK2*/
1427                 _iqk_rxk2setting_8821c(dm, path, false);
1428                 gonext = false;
1429                 while (1) {
1430                         KFAIL = _iqk_one_shot_8821c(dm, path, RXIQK2);
1431                         if (KFAIL && iqk_info->retry_count[0][path][RXIQK2] < 2) {
1432                                 iqk_info->retry_count[0][path][RXIQK2]++;
1433                         } else if (KFAIL) {
1434                                 iqk_info->rxiqk_fail_code[0][path] = 2;
1435                                 iqk_info->rxiqk_step = 5;
1436                                 gonext = true;
1437                         } else {
1438                                 iqk_info->rxiqk_step++;
1439                                 gonext = true;
1440                         }
1441                         if (gonext)
1442                                 break;
1443                 }
1444                 halrf_iqk_xym_read(dm, 0x0, 0x0);
1445                 break;
1446         }
1447         return KFAIL;
1448 #endif
1449 }
1450 void _iqk_iqk_by_path_8821c(void *dm_void, boolean segment_iqk)
1451 {
1452         struct dm_struct *dm = (struct dm_struct *)dm_void;
1453         struct dm_iqk_info *iqk_info = &dm->IQK_info;
1454         boolean KFAIL = true;
1455         u8 i, kcount_limit;
1456
1457 #if 0
1458         /*      RF_DBG(dm, DBG_RF_IQK, "[IQK]iqk_step = 0x%x\n", dm->rf_calibrate_info.iqk_step); */
1459 #endif
1460         if (*dm->band_width == 2)
1461                 kcount_limit = kcount_limit_80m;
1462         else
1463                 kcount_limit = kcount_limit_others;
1464
1465         while (1) {
1466                 switch (dm->rf_calibrate_info.iqk_step) {
1467                 case 1: /*S0 LOK*/
1468                         for (i = 0; i < 8; i++) { /* the LOK Cal in the each PAD stage*/
1469                                 _iqk_lok_setting_8821c(dm, RF_PATH_A, i);
1470                                 _lok_one_shot_8821c(dm, RF_PATH_A, i);
1471                         }
1472                         dm->rf_calibrate_info.iqk_step++;
1473                         break;
1474                 case 2: /*S0 TXIQK*/
1475                         _iqk_txk_setting_8821c(dm, RF_PATH_A);
1476                         KFAIL = _iqk_one_shot_8821c(dm, RF_PATH_A, TXIQK);
1477                         iqk_info->kcount++;
1478                         RF_DBG(dm, DBG_RF_IQK, "[IQK]KFail = 0x%x\n", KFAIL);
1479                         if (KFAIL && iqk_info->retry_count[0][RF_PATH_A][TXIQK] < 3)
1480                                 iqk_info->retry_count[0][RF_PATH_A][TXIQK]++;
1481                         else
1482                                 dm->rf_calibrate_info.iqk_step++;
1483                         halrf_iqk_xym_read(dm, 0x0, 0x1);
1484                         break;
1485                 case 3: /*S0 RXIQK*/
1486                         while (1) {
1487                                 KFAIL = _iqk_rxiqkbystep_8821c(dm, RF_PATH_A);
1488                                 RF_DBG(dm, DBG_RF_IQK,
1489                                        "[IQK]S0RXK KFail = 0x%x\n", KFAIL);
1490                                 if (iqk_info->rxiqk_step == 5) {
1491                                         dm->rf_calibrate_info.iqk_step++;
1492                                         iqk_info->rxiqk_step = 1;
1493                                         if (KFAIL)
1494                                                 RF_DBG(dm, DBG_RF_IQK, "[IQK]S0RXK fail code: %d!!!\n", iqk_info->rxiqk_fail_code[0][RF_PATH_A]);
1495                                         break;
1496                                 }
1497                         }
1498                         iqk_info->kcount++;
1499                         break;
1500                 }
1501
1502                 if (dm->rf_calibrate_info.iqk_step == 4) {
1503                         RF_DBG(dm, DBG_RF_IQK,
1504                                "[IQK]==========LOK summary ==========\n");
1505                         RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_LOK_notready = %d\n",
1506                                iqk_info->lok_fail[RF_PATH_A]);
1507                         RF_DBG(dm, DBG_RF_IQK,
1508                                "[IQK]==========IQK summary ==========\n");
1509                         RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_TXIQK_fail = %d\n",
1510                                iqk_info->iqk_fail_report[0][RF_PATH_A][TXIQK]);
1511                         RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_RXIQK_fail = %d\n",
1512                                iqk_info->iqk_fail_report[0][RF_PATH_A][RXIQK]);
1513                         RF_DBG(dm, DBG_RF_IQK, "[IQK]PathA_TXIQK_retry = %d\n",
1514                                iqk_info->retry_count[0][RF_PATH_A][TXIQK]);
1515                         RF_DBG(dm, DBG_RF_IQK,
1516                                "[IQK]PathA_RXK1_retry = %d, PathA_RXK2_retry = %d\n",
1517                                iqk_info->retry_count[0][RF_PATH_A][RXIQK1],
1518                                iqk_info->retry_count[0][RF_PATH_A][RXIQK2]);
1519                         RF_DBG(dm, DBG_RF_IQK,
1520                                "[IQK]PathA_GS1_retry = %d, PathA_GS2_retry = %d\n",
1521                                iqk_info->gs_retry_count[0][RF_PATH_A][0],
1522                                iqk_info->gs_retry_count[0][RF_PATH_A][1]);
1523
1524                         for (i = 0; i < SS_8821C; i++) {
1525                                 odm_write_4byte(dm, 0x1b00, 0xf8000008 | i << 1);
1526                                 odm_write_4byte(dm, 0x1b2c, 0x7);
1527                                 odm_write_4byte(dm, 0x1bcc, 0x0);
1528                                 odm_write_4byte(dm, 0x1b38, 0x20000000);
1529                         }
1530                         break;
1531                 }
1532                 RF_DBG(dm, DBG_RF_IQK, "[IQK]segmentIQK = %d, Kcount = %d\n",
1533                        segment_iqk, iqk_info->kcount);
1534                 if (segment_iqk && iqk_info->kcount == kcount_limit)
1535                         break;
1536         }
1537 }
1538
1539 void _iqk_start_iqk_8821c(struct dm_struct *dm, boolean segment_iqk)
1540 {
1541         struct dm_iqk_info *iqk_info = &dm->IQK_info;
1542         u32 tmp;
1543
1544         odm_write_4byte(dm, 0x1b00, 0xf8000008);
1545         odm_write_4byte(dm, 0x1bb8, 0x00000000);
1546         /*GNT_WL = 1*/
1547         if (iqk_info->is_btg) {
1548                 tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK);
1549                 tmp = (tmp & (~BIT(3))) | BIT(0) | BIT(2) | BIT(5);
1550                 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, tmp);
1551         } else {
1552                 tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK);
1553                 tmp = ((tmp & (~BIT(3))) & (~BIT(5))) | BIT(0) | BIT(2);
1554                 odm_set_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK, tmp);
1555                 RF_DBG(dm, DBG_RF_IQK, "[IQK]==> RF0x1 = 0x%x\n",
1556                        odm_get_rf_reg(dm, RF_PATH_A, RF_0x1, RFREGOFFSETMASK));
1557         }
1558         _iqk_iqk_by_path_8821c(dm, segment_iqk);
1559 }
1560
1561 void _iq_calibrate_8821c_init(struct dm_struct *dm)
1562 {
1563         struct dm_iqk_info *iqk_info = &dm->IQK_info;
1564         u8 i, j, k, m;
1565         static boolean firstrun = true;
1566
1567         if (firstrun) {
1568                 firstrun = false;
1569                 RF_DBG(dm, DBG_RF_IQK,
1570                        "[IQK]=====>PHY_IQCalibrate_8821C_Init\n");
1571
1572                 for (i = 0; i < SS_8821C; i++) {
1573                         for (j = 0; j < 2; j++) {
1574                                 iqk_info->lok_fail[i] = true;
1575                                 iqk_info->iqk_fail[j][i] = true;
1576                                 iqk_info->iqc_matrix[j][i] = 0x20000000;
1577                         }
1578                 }
1579
1580                 for (i = 0; i < 2; i++) {
1581                         iqk_info->iqk_channel[i] = 0x0;
1582
1583                         for (j = 0; j < SS_8821C; j++) {
1584                                 iqk_info->lok_idac[i][j] = 0x0;
1585                                 iqk_info->rxiqk_agc[i][j] = 0x0;
1586                                 iqk_info->bypass_iqk[i][j] = 0x0;
1587
1588                                 for (k = 0; k < 2; k++) {
1589                                         iqk_info->iqk_fail_report[i][j][k] = true;
1590                                         for (m = 0; m < 8; m++) {
1591                                                 iqk_info->iqk_cfir_real[i][j][k][m] = 0x0;
1592                                                 iqk_info->iqk_cfir_imag[i][j][k][m] = 0x0;
1593                                         }
1594                                 }
1595
1596                                 for (k = 0; k < 3; k++)
1597                                         iqk_info->retry_count[i][j][k] = 0x0;
1598                         }
1599                 }
1600         }
1601 }
1602
1603 u8 _txgapk_txpower_compare_8821c(struct dm_struct *dm, u8 path, u32 pw1,
1604                                  u32 pw2, u32 *pwr_table)
1605 {
1606         u8 pwr_delta;
1607         u32 temp = 0x0;
1608         temp = (u32)(pw1 / (pw2 / 1000));
1609
1610         if (temp < pwr_table[0]) /*<-3.5 dB*/
1611                 pwr_delta = 0x0;
1612         else if (temp < pwr_table[1])
1613                 pwr_delta = 0x1;
1614         else if (temp < pwr_table[2])
1615                 pwr_delta = 0x2;
1616         else if (temp < pwr_table[3])
1617                 pwr_delta = 0x3;
1618         else if (temp < pwr_table[4])
1619                 pwr_delta = 0x4;
1620         else if (temp < pwr_table[5])
1621                 pwr_delta = 0x5;
1622         else if (temp < pwr_table[6])
1623                 pwr_delta = 0x6;
1624         else if (temp < pwr_table[7])
1625                 pwr_delta = 0x7;
1626         else if (temp < pwr_table[8])
1627                 pwr_delta = 0x8;
1628         else if (temp < pwr_table[9])
1629                 pwr_delta = 0x9;
1630         else if (temp < pwr_table[0xa])
1631                 pwr_delta = 0xa;
1632         else if (temp < pwr_table[0xb])
1633                 pwr_delta = 0xb;
1634         else if (temp < pwr_table[0xc])
1635                 pwr_delta = 0xc;
1636         else if (temp < pwr_table[0xd])
1637                 pwr_delta = 0xd;
1638         else if (temp < pwr_table[0xe])
1639                 pwr_delta = 0xe;
1640         else if (temp < pwr_table[0xf])
1641                 pwr_delta = 0xf;
1642         else if (temp < pwr_table[0x10])
1643                 pwr_delta = 0x10;
1644         else if (temp < pwr_table[0x11])
1645                 pwr_delta = 0x11;
1646         else if (temp < pwr_table[0x12])
1647                 pwr_delta = 0x12;
1648         else if (temp < pwr_table[0x13])
1649                 pwr_delta = 0x13;
1650         else if (temp < pwr_table[0x14])
1651                 pwr_delta = 0x14;
1652         else if (temp < pwr_table[0x15])
1653                 pwr_delta = 0x15;
1654         else if (temp < pwr_table[0x16])
1655                 pwr_delta = 0x16;
1656         else if (temp < pwr_table[0x17])
1657                 pwr_delta = 0x17;
1658         else if (temp < pwr_table[0x18])
1659                 pwr_delta = 0x18;
1660         else if (temp < pwr_table[0x19])
1661                 pwr_delta = 0x19;
1662         else
1663                 pwr_delta = 0x1a;
1664
1665         RF_DBG(dm, DBG_RF_IQK, "[TXGAPK] temp =%d, pwr_delta =%x\n", temp,
1666                pwr_delta);
1667
1668         return pwr_delta;
1669 }
1670
1671 u32 _txgapk_txgap_compenstion_8821c(struct dm_struct *dm, u8 path,
1672                                     u32 txgain_0x56, u8 pwr_delta)
1673 {
1674         u32 new_txgain_0x56;
1675
1676         /*      0       1       2       3       4       5       6       7       8       9       10      11      12      13      14 */
1677         /*      -3.5    -3 -2.5  -2  -1.5  -1  -0.5    0   0.5    1     1.5   2   2.5     3    3.5 (dB)*/
1678 #if 0
1679         /*      pwr_table[0xf]={89,100,112,125,141,158,177,199,223,251,281,316,354,398,446}*/
1680 #endif
1681
1682         switch (pwr_delta) {
1683         case 0x1a:
1684         case 0x19:
1685         case 0x18:
1686         case 0x17:
1687         case 0x16:
1688         case 0x15:
1689         case 0x14:
1690 #if 0
1691         /*
1692                                                 if ((txgain_0x56 & 0x1f)<=0x1d)
1693                                                         new_txgain_0x56 = txgain_0x56 + 0x2; //< -1.5 ~ -2.5dB
1694                                                 else if ((txgain_0x56 & 0x1f)<=  0x1e)
1695                                                         new_txgain_0x56 = txgain_0x56 + 0x1;
1696                                                 else
1697                                                         new_txgain_0x56 = txgain_0x56;
1698                                                 break;
1699 */
1700 #endif
1701         case 0x13:
1702         case 0x12:
1703                 if ((txgain_0x56 & 0x1f) <= 0x1e)
1704                         new_txgain_0x56 = txgain_0x56 + 0x1;/*< -0.5 ~ -1.5dB*/
1705                 else
1706                         new_txgain_0x56 = txgain_0x56;
1707                 break;
1708         case 0x11:
1709         case 0x10:
1710         case 0xf:
1711         case 0xe:
1712         case 0xd:
1713         case 0xc:
1714                 new_txgain_0x56 = txgain_0x56; /*<  -0.5~0.5dB*/
1715                 break;
1716         case 0xb:
1717         case 0xa:
1718         case 0x9:
1719         case 0x8:
1720         case 0x7:
1721                 if ((txgain_0x56 & 0x1f) >= 0x01)
1722                         new_txgain_0x56 = txgain_0x56 - 0x1; /* >0.5~1.5dB */
1723                 else
1724                         new_txgain_0x56 = txgain_0x56;
1725                 break;
1726         case 0x6:
1727         case 0x5:
1728         case 0x4:
1729         case 0x3:
1730 #if 0
1731         /*
1732                                                 if ((txgain_0x56 & 0x1f)>= 0x02)
1733                                                         new_txgain_0x56 = txgain_0x56 - 0x2; //>1.5~2.5dB
1734                                                 else if ((txgain_0x56 & 0x1f)>= 0x01)
1735                                                         new_txgain_0x56 = txgain_0x56 - 0x1;
1736                                                 else
1737                                                         new_txgain_0x56 = txgain_0x56;
1738                                                 break;
1739 */
1740 #endif
1741         case 0x2:
1742         case 0x1:
1743         case 0x0:
1744 #if 0
1745         /*
1746                                                 if ((txgain_0x56 & 0x1f)>= 0x03)
1747                                                         new_txgain_0x56 = txgain_0x56 - 0x3; //>2.5~3.5dB
1748                                                 else if ((txgain_0x56 & 0x1f)>= 0x02)
1749                                                         new_txgain_0x56 = txgain_0x56 - 0x2;
1750                                                 else if ((txgain_0x56 & 0x1f)>= 0x01)
1751                                                         new_txgain_0x56 = txgain_0x56 - 0x1;
1752                                                 else
1753                                                         new_txgain_0x56 = txgain_0x56;
1754                                                 break;
1755 */
1756 #endif
1757         default:
1758                 new_txgain_0x56 = txgain_0x56;
1759                 break;
1760         }
1761         if ((new_txgain_0x56 & 0x1f) < 0x02)
1762                 new_txgain_0x56 = (new_txgain_0x56 & 0xffffc) + 0x2;
1763         if ((new_txgain_0x56 & 0x1f) > 0x1d)
1764                 new_txgain_0x56 = (new_txgain_0x56 | 0x3) - 0x2;
1765
1766         return new_txgain_0x56;
1767 }
1768
1769 void _txgapk_backup_8821c(struct dm_struct *dm, u32 *backup_txgap,
1770                           u32 *backup_txgap_reg, u8 txgapk_reg_num)
1771 {
1772         u32 i;
1773
1774         for (i = 0; i < txgapk_reg_num; i++)
1775                 backup_txgap[i] = odm_read_4byte(dm, backup_txgap_reg[i]);
1776 }
1777 u32 _txgapk_get_rf_tx_index_8821c(struct dm_struct *dm, u8 path,
1778                                   u32 txgain_index)
1779 {
1780         u32 rf_backup_reg00, rf_backup_regdf, rf_reg56;
1781
1782         rf_backup_reg00 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK);
1783         rf_backup_regdf = odm_get_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK);
1784
1785         odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x08009);
1786         odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, 0x20000 + txgain_index);
1787         /*ODM_sleep_us(10);*/
1788
1789         ODM_delay_us(10);
1790         rf_reg56 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x56, RFREGOFFSETMASK);
1791
1792         RF_DBG(dm, DBG_RF_IQK,
1793                "[TXGAPK](2) txgain_index =0x%x, rf_reg56=0x%x\n", txgain_index,
1794                rf_reg56);
1795         odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_backup_reg00);
1796         odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, rf_backup_regdf);
1797         return rf_reg56;
1798 }
1799
1800 void _txgapk_restore_8821c(struct dm_struct *dm, u32 *backup_txgap,
1801                            u32 *backup_txgap_reg, u8 txgapk_reg_num)
1802 {
1803         u32 i;
1804
1805         for (i = 0; i < txgapk_reg_num; i++)
1806                 odm_write_4byte(dm, backup_txgap_reg[i], backup_txgap[i]);
1807 }
1808
1809 void _txgapk_setting_8821c(struct dm_struct *dm, u8 path)
1810 {
1811         struct dm_iqk_info *iqk_info = &dm->IQK_info;
1812
1813         /*RF*/
1814         odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x80000);
1815         odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00024);
1816         odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0003F);
1817         odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xCBFCE);
1818         odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
1819         if (iqk_info->is_btg) {
1820         } else {
1821                 switch (*dm->band_type) {
1822                 case ODM_BAND_2_4G:
1823                         break;
1824                 case ODM_BAND_5G:
1825                         odm_set_rf_reg(dm, RF_PATH_A, RF_0x8f, RFREGOFFSETMASK, 0xA9C00);
1826                         odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, 0x00809);
1827                         odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, 0x4001c);
1828
1829                         odm_write_4byte(dm, 0x1bcc, 0x00000009); /*try the iqk swing*/
1830                         odm_write_4byte(dm, 0x1b20, 0x01040008);
1831                         odm_write_4byte(dm, 0x1b24, 0x01040848);
1832
1833                         odm_write_4byte(dm, 0x1b14, 0x00001000);
1834                         odm_write_4byte(dm, 0x1b1c, 0x82193d31);
1835
1836                         odm_write_1byte(dm, 0x1b22, 0x04); /*sync with RF0x33[3:0]*/
1837                         odm_write_1byte(dm, 0x1b26, 0x04); /*sync with RF0x33[3:0]*/
1838                         odm_write_1byte(dm, 0x1b2c, 0x03);
1839                         odm_write_4byte(dm, 0x1b38, 0x20000000);
1840                         odm_write_4byte(dm, 0x1b3c, 0x20000000);
1841                         odm_write_4byte(dm, 0xc00, 0x4);
1842
1843                         RF_DBG(dm, DBG_RF_IQK,
1844                                "[IQK](1) txgap calibration setting!!!\n");
1845
1846                         break;
1847                 }
1848         }
1849 }
1850
1851 u32 _txgapk_one_shot_8821c(struct dm_struct *dm_void, u8 path, u32 reg0x56)
1852 {
1853         struct dm_struct *dm = (struct dm_struct *)dm_void;
1854         boolean txgap_k_notready = true;
1855         u8 delay_count = 0x0;
1856         u32 txgap_k_tmp1 = 0x1, txgap_k_tmp2 = 0x2;
1857         u8 offset;
1858         u32 reg_1bb8;
1859         u32 rx_dsp_power;
1860
1861         reg_1bb8 = odm_read_4byte(dm, 0x1bb8);
1862         /*clear the flag*/
1863         odm_write_1byte(dm, 0x1bd6, 0x0b);
1864         odm_set_bb_reg(dm, R_0x1bfc, BIT(1), 0x0);
1865         txgap_k_notready = true;
1866         delay_count = 0x0;
1867         /* get tx gain*/
1868         odm_write_1byte(dm, 0x1b2b, 0x00);
1869         odm_write_1byte(dm, 0x1bb8, 0x00);
1870         odm_set_rf_reg(dm, path, RF_0xdf, RFREGOFFSETMASK, 0x00802);
1871         odm_set_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
1872         odm_set_rf_reg(dm, path, RF_0x56, RFREGOFFSETMASK, reg0x56);
1873         odm_write_4byte(dm, 0x1bb8, 0x00100000);
1874 #if 0
1875         /*ODM_sleep_us(10);*/
1876 #endif
1877
1878         ODM_delay_us(10);
1879         /* one-shot-1*/
1880         odm_write_4byte(dm, 0x1b34, 0x1);
1881         odm_write_4byte(dm, 0x1b34, 0x0);
1882
1883 #if 1
1884         while (txgap_k_notready) {
1885                 odm_write_1byte(dm, 0x1bd6, 0x0b);
1886                 if ((boolean)odm_get_bb_reg(dm, R_0x1bfc, BIT(1)))
1887                         txgap_k_notready = false;
1888                 else
1889                         txgap_k_notready = true;
1890
1891                 if (txgap_k_notready) {
1892 #if 0
1893                         /*ODM_sleep_us(100);*/
1894 #endif
1895                         ODM_delay_us(100);
1896                         delay_count++;
1897                 }
1898
1899                 if (delay_count >= 20) {
1900                         RF_DBG(dm, DBG_RF_IQK,
1901                                "[TXGAPK] (3)txgapktimeout,delay_count=0x%x !!!\n",
1902                                delay_count);
1903                         txgap_k_notready = false;
1904                         break;
1905                 }
1906         }
1907 #else
1908         ODM_sleep_ms(1);
1909         if ((boolean)odm_get_bb_reg(dm, R_0x1bfc, BIT(1)))
1910                 txgap_k_notready = false;
1911         else
1912                 txgap_k_notready = true;
1913
1914 #endif
1915
1916         if (!txgap_k_notready) {
1917                 odm_write_1byte(dm, 0x1bd6, 0x5);
1918                 txgap_k_tmp1 = odm_read_4byte(dm, 0x1bfc) >> 27;
1919                 odm_write_1byte(dm, 0x1bd6, 0xe);
1920                 txgap_k_tmp2 = odm_read_4byte(dm, 0x1bfc);
1921
1922                 RF_DBG(dm, DBG_RF_IQK,
1923                        "[TXGAPK] reg0x56 =0x%x, txgapK_tmp1 =0x%x, txgapK_tmp2 =0x%x!!!\n",
1924                        reg0x56, txgap_k_tmp1, txgap_k_tmp2);
1925
1926                 if (txgap_k_tmp1 == 0)
1927                         offset = 0x0;
1928                 else if (txgap_k_tmp1 < 2)
1929                         offset = 0x1;
1930                 else if (txgap_k_tmp1 < 4)
1931                         offset = 0x2;
1932                 else
1933                         offset = 0x3;
1934
1935                 if (txgap_k_tmp1 == 0x0) {
1936                         rx_dsp_power = txgap_k_tmp2;
1937                 } else {
1938                         txgap_k_tmp1 = txgap_k_tmp1 << (32 - offset);
1939                         txgap_k_tmp2 = txgap_k_tmp2 >> offset;
1940                         rx_dsp_power = txgap_k_tmp1 + txgap_k_tmp2;
1941                         overflowflag = true;
1942                         RF_DBG(dm, DBG_RF_IQK,
1943                                "[TXGAPK](3) (1)overflowflag = true, txgapK_tmp1 =0x%x, txgapK_tmp2 =0x%x!!!\n",
1944                                txgap_k_tmp1, txgap_k_tmp2);
1945                 }
1946         } else {
1947                 RF_DBG(dm, DBG_RF_IQK, "[TXGAPK](3) txgapK Fail!!!\n");
1948         }
1949
1950         odm_write_4byte(dm, 0x1bb8, reg_1bb8);
1951
1952         return rx_dsp_power;
1953 }
1954
1955 void _phy_txgapk_calibrate_8821c(void *dm_void, u8 path)
1956 {
1957         struct dm_struct *dm = (struct dm_struct *)dm_void;
1958         u32 txgain[txgap_k_number] = {0, 0, 0, 0, 0, 0, 0};
1959         u32 txgain_rf56[txgap_k_number] = {0, 0, 0, 0, 0, 0, 0};
1960         u8 add_base, txgapk_num = 0x0, psd_delta = 0x0;
1961         u8 i, bandselect = 0x0;
1962         u32 backup_txgap_reg[11] = {0x1b14, 0x1b1c, 0x1b20, 0x1b24, 0x1b28, 0x1b2c, 0x1b38, 0x1b3c, 0x1bd6, 0x1bb8, 0x1bcc};
1963         u32 backup_txgap[11];
1964         u8 gain_gap_index[txgap_k_number] = {0x13, 0x10, 0xd, 0xa, 0x7, 0x4, 0x1};
1965         u32 txgainindex[txgap_k_number] = {0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x20};
1966         u32 tmp1, tmp2, tmp3, tmp4, tmp5;
1967         u8 skip_low_power_index = 0x3;
1968
1969         s8 psd_single_tone_offset_1db[3][3] = {{-1, 0, 0}, {-2, -1, -1}, {-1, -1, -1} }; /*5G, L,M,H, index 32,26,20*/
1970         static u32 pwr_table_1db[27] = {590, 630, 668, 707, 749, 794, 841, 891, 944, 1000, 1040, 1096, 1148, 1202, 1258, 1318,
1971                                         1380, 1412, 1513, 1584, 1678, 1778, 1888, 1995, 2113, 2387, 2391};
1972         static u32 pwr_table_3db[27] = {944, 1000, 1059, 1122, 1185, 1258, 1333, 1412, 1496, 1584, 1659, 1737, 1819, 1905, 1995, 2089,
1973                                         2187, 2290, 2398, 2511, 2660, 2818, 2985, 3162, 3349, 3548, 3758};
1974         boolean txgapkdone = false;
1975         u8 txgap_changed = 0x0;
1976         u8 ref_val = 0x0;
1977
1978         overflowflag = 0;
1979         RF_DBG(dm, DBG_RF_IQK,
1980                "[TXGAPK] (1) *dm->band_width = %x, *dm->channel =%d, *dm->band_type=%x\n",
1981                *dm->band_width, *dm->channel, *dm->band_type);
1982
1983         if (!(*dm->mp_mode))
1984                 return;
1985
1986         if (!(*dm->band_type == ODM_BAND_5G))
1987                 return;
1988
1989         if (*dm->band_width == 0) {
1990 #if 0
1991                 /*              return;*/
1992 #endif
1993                 if (*dm->channel < 64) {
1994                         bandselect = 0x0;
1995                         add_base = 0x0;
1996                 } else if (*dm->channel < 153) {
1997                         bandselect = 0x1;
1998                         add_base = 0x40;
1999 #if 0
2000                 /*else if (*dm->channel ==153){*/
2001 #endif
2002                 } else {
2003                         bandselect = 0x2;
2004                         add_base = 0x80;
2005                 }
2006         } else if (*dm->band_width == 1) {
2007                 if (*dm->channel < 102) {
2008                         bandselect = 0x0;
2009                         add_base = 0x0;
2010                 } else if (*dm->channel < 151) {
2011                         bandselect = 0x1;
2012                         add_base = 0x40;
2013 #if 0
2014                 /*else if (*dm->channel ==151){*/
2015 #endif
2016                 } else {
2017                         bandselect = 0x2;
2018                         add_base = 0x80;
2019                 }
2020         } else if (*dm->band_width == 2) {
2021                 /*              return;*/
2022                 if (*dm->channel < 106) {
2023                         bandselect = 0x0;
2024                         add_base = 0x0;
2025                 } else if (*dm->channel < 155) {
2026                         bandselect = 0x1;
2027                         add_base = 0x40;
2028 #if 0
2029                 /*else if (*dm->channel ==155){*/
2030 #endif
2031                 } else {
2032                         bandselect = 0x2;
2033                         add_base = 0x80;
2034                 }
2035         } else {
2036                 return;
2037         }
2038
2039         if (txgap_done[bandselect])
2040                 return;
2041
2042         /*Step 1*/
2043         _txgapk_backup_8821c(dm, backup_txgap, backup_txgap_reg, 0xb);
2044         /*step 2*/
2045         phydm_clear_kfree_to_rf(dm, RF_PATH_A, 1);
2046
2047         for (i = 0; i < txgap_k_number; i++) {
2048                 txgain_rf56[i] = _txgapk_get_rf_tx_index_8821c(dm, RF_PATH_A, gain_gap_index[i]);
2049                 txgain[i] = txgain_rf56[i];
2050         }
2051
2052         for (i = 0; i < txgap_k_number; i++) {
2053                 RF_DBG(dm, DBG_RF_IQK, "[TXGAPK] start txgain1[%x]=0x%x\n", i,
2054                        txgain_rf56[i]);
2055         }
2056
2057         _txgapk_setting_8821c(dm, RF_PATH_A);
2058
2059         /*step 3*/
2060
2061         /*1st*/
2062         while (!txgapkdone) {
2063                 txgapk_num++;
2064                 if (txgapk_num > 2)
2065                         break;
2066
2067                 for (i = 0; i < txgap_k_number - 1 - skip_low_power_index; i++) {
2068                         tmp1 = (txgain[i] & 0x000000e0) >> 5;
2069                         tmp2 = (txgain[i + 1] & 0x000000e0) >> 5;
2070                         tmp5 = txgain[i + 1];
2071 #if 0
2072                         //if (tmp1 != tmp2){
2073 #endif
2074                         if (true) {
2075                                 tmp3 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i] - 2);
2076                                 tmp4 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i + 1]);
2077                                 if (overflowflag)
2078                                         overflowflag = false;
2079 #if 0
2080                                         //tmp4 = tmp4>>1;
2081 #endif
2082
2083                                 psd_delta =
2084                                         _txgapk_txpower_compare_8821c(dm, RF_PATH_A, tmp3, tmp4, pwr_table_1db);
2085
2086                                 psd_delta = psd_delta + psd_single_tone_offset_1db[bandselect][i];
2087                                 RF_DBG(dm, DBG_RF_IQK,
2088                                        "[TXGAPK] new psd_detla = %x\n",
2089                                        psd_delta);
2090
2091                                 if (psd_delta <= 0xb)
2092                                         txgap_changed++;
2093                                 else if (psd_delta <= 0x11)
2094                                         ;
2095                                 else
2096                                         txgap_changed++;
2097
2098                                 txgain[i + 1] =
2099                                         _txgapk_txgap_compenstion_8821c(dm, RF_PATH_A, txgain[i + 1], psd_delta);
2100                         } else {
2101                                 RF_DBG(dm, DBG_RF_IQK,
2102                                        "[TXGAPK]skip i=%d, txgain[%x]=0x%x\n",
2103                                        i, i + 1, txgain[i + 1]);
2104                         }
2105                 }
2106
2107                 /*2nd*/
2108
2109                 if (txgap_changed > 0x0) {
2110                         RF_DBG(dm, DBG_RF_IQK, "[TXGAPK] do 3dB check\n");
2111
2112                         for (i = 0; i < txgap_k_number - 1 - skip_low_power_index; i++) {
2113                                 tmp1 = (txgain[i] & 0x000000e0) >> 5;
2114                                 tmp2 = (txgain[i + 1] & 0x000000e0) >> 5;
2115
2116                                 if (tmp1 != tmp2) {
2117                                         if (i == 0)
2118                                                 tmp3 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i] - 2);
2119                                         else
2120                                                 tmp3 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i]);
2121
2122                                         tmp4 = _txgapk_one_shot_8821c(dm, RF_PATH_A, txgain[i + 1]);
2123
2124                                         if (overflowflag) {
2125                                                 overflowflag = false;
2126                                                 RF_DBG(dm, DBG_RF_IQK, "[IQK] tmp3= %x, tmp4= %x\n", tmp3, tmp4);
2127                                         }
2128                                         if (i == 0)
2129                                                 psd_delta =
2130                                                         _txgapk_txpower_compare_8821c(dm, RF_PATH_A, tmp3, tmp4, pwr_table_1db);
2131
2132                                         else
2133                                                 psd_delta =
2134                                                         _txgapk_txpower_compare_8821c(dm, RF_PATH_A, tmp3, tmp4, pwr_table_3db);
2135
2136                                         if (psd_delta <= 0xa)
2137                                                 ref_val++;
2138                                         else if (psd_delta <= 0x12)
2139                                                 ;
2140                                         else
2141                                                 ref_val++;
2142                                 } else {
2143                                         RF_DBG(dm, DBG_RF_IQK, "[TXGAPK]skip i=%d, txgain[%x]=0x%x\n", i, i + 1, txgain[i + 1]);
2144                                 }
2145                         }
2146
2147                         if (ref_val == 0x0) {
2148                                 txgapkdone = true;
2149                                 txgap_changed = 0x0;
2150                         } else {
2151                                 /* restore default rf 0x56 */
2152                                 for (i = 0; i < txgap_k_number; i++)
2153                                         txgain[i] = txgain_rf56[i];
2154                         }
2155
2156                 } else {
2157                         txgapkdone = true;
2158                 }
2159         }
2160
2161         /*step 7*/
2162         _txgapk_restore_8821c(dm, backup_txgap, backup_txgap_reg, 0xb);
2163
2164         /*step 8*/
2165         RF_DBG(dm, DBG_RF_IQK,
2166                "[TXGAPK]txgapkdone =%x, txgap_changed=0x%x, ref_val =0x%x\n",
2167                txgapkdone, txgap_changed, ref_val);
2168
2169         if (txgapkdone) {
2170                 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00800);
2171
2172                 for (i = 0; i < txgap_k_number; i++) {
2173                         odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, txgainindex[i] + add_base);
2174                         odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, txgain[i]);
2175                 }
2176                 odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
2177                 txgap_done[bandselect] = true;
2178                 txgapkdone = false;
2179         }
2180 }
2181
2182 #if 0
2183 /*
2184 void
2185 _DPK_BackupReg_8821C(
2186         struct dm_struct*       dm,
2187         static u32*     DPK_backup,
2188         u32*            backup_dpk_reg
2189         )
2190 {
2191
2192         u32 i;
2193
2194         for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++)
2195                 DPK_backup[i] = odm_read_4byte(dm, backup_dpk_reg[i]);
2196
2197 }
2198 void
2199 _DPK_Restore_8821C(
2200         struct dm_struct*               dm,
2201         static  u32*            DPK_backup,
2202         u32*            backup_dpk_reg
2203         )
2204 {
2205         u32 i;
2206         for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++)
2207                 odm_write_4byte(dm, backup_dpk_reg[i], DPK_backup[i]);
2208 }
2209
2210 */
2211 #endif
2212 void _dpk_toggle_rxagc(struct dm_struct *dm, boolean reset)
2213 {
2214         /*toggle RXAGC  workaround method*/
2215         u32 tmp1;
2216         tmp1 = odm_read_4byte(dm, 0xc50);
2217         odm_set_bb_reg(dm, R_0xc50, BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x0);
2218 #if 0
2219         /*       ODM_sleep_ms(2);*/
2220 #endif
2221         ODM_delay_ms(2);
2222         odm_set_bb_reg(dm, R_0xc50, BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x2);
2223 #if 0
2224         /*       ODM_sleep_ms(2);*/
2225 #endif
2226         ODM_delay_ms(2);
2227         odm_set_bb_reg(dm, R_0xc50, BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x0);
2228         odm_write_4byte(dm, 0xc50, tmp1);
2229 }
2230
2231 void _dpk_set_gain_scaling(struct dm_struct *dm, u8 path)
2232 {
2233         u32 tmp1, tmp2, tmp3, tmp4, reg_1bfc;
2234         u32 lut_i = 0x0, lut_q = 0x0, lut_pw = 0x0, lut_pw_avg = 0x0;
2235         u16 gain_scaling = 0x0;
2236
2237         tmp1 = odm_read_4byte(dm, 0x1b00);
2238         tmp2 = odm_read_4byte(dm, 0x1b08);
2239         tmp3 = odm_read_4byte(dm, 0x1bd4);
2240         tmp4 = odm_read_4byte(dm, 0x1bdc);
2241
2242         odm_write_4byte(dm, 0x1b00, 0xf8000008);
2243         odm_write_4byte(dm, 0x1b08, 0x00000080);
2244         odm_write_4byte(dm, 0x1bd4, 0x00040001);
2245         odm_write_4byte(dm, 0x1bdc, 0xc0000081);
2246
2247         reg_1bfc = odm_read_4byte(dm, 0x1bfc);
2248         lut_i = (reg_1bfc & 0x003ff800) >> 11;
2249         lut_q = (reg_1bfc & 0x00007ff);
2250
2251         if ((lut_i & 0x400) == 0x400)
2252                 lut_i = 0x800 - lut_i;
2253         if ((lut_q & 0x400) == 0x400)
2254                 lut_q = 0x800 - lut_q;
2255
2256         lut_pw = lut_i * lut_i + lut_q * lut_q;
2257         lut_pw_avg = (u32)(lut_i + lut_q) >> 1;
2258         gain_scaling = (u16)(0x800000 / lut_pw_avg);
2259
2260         odm_set_bb_reg(dm, R_0x1b98, 0x0000ffff, gain_scaling);
2261         odm_set_bb_reg(dm, R_0x1b98, 0xffff0000, gain_scaling);
2262
2263         odm_write_4byte(dm, 0x1b00, tmp1);
2264         odm_write_4byte(dm, 0x1b08, tmp2);
2265         odm_write_4byte(dm, 0x1bd4, tmp3);
2266         odm_write_4byte(dm, 0x1bdc, tmp4);
2267
2268         RF_DBG(dm, DBG_RF_IQK,
2269                "[IQK] reg_1bfc =0x%x, lut_pw =0x%x, lut_i = 0x%x, lut_q = 0x%x, lut_pw_avg = 0x%x, gain_scaling = 0x%x, 0x1b98 =0x%x!!!\n",
2270                reg_1bfc, lut_pw, lut_i, lut_q, lut_pw_avg, gain_scaling,
2271                odm_read_4byte(dm, 0x1b98));
2272 }
2273
2274 void _dpk_set_dpk_pa_scan(struct dm_struct *dm, u8 path)
2275 {
2276         u32 tmp1, tmp2, reg_1bfc;
2277         u32 pa_scan_i = 0x0, pa_scan_q = 0x0, pa_scan_pw = 0x0;
2278         u32 gainloss_back = 0x0;
2279 #if 0
2280         /*      boolean pa_scan_search_fail = false;*/
2281 #endif
2282         tmp1 = odm_read_4byte(dm, 0x1bcf);
2283         tmp2 = odm_read_4byte(dm, 0x1bd4);
2284
2285         odm_write_4byte(dm, 0x1bcf, 0x11);
2286         odm_write_4byte(dm, 0x1bd4, 0x00060000);
2287
2288         reg_1bfc = odm_read_4byte(dm, 0x1bfc);
2289         odm_write_4byte(dm, 0x1bcf, 0x15);
2290         pa_scan_i = (reg_1bfc & 0xffff0000) >> 16;
2291         pa_scan_q = (reg_1bfc & 0x0000ffff);
2292
2293         if ((pa_scan_i & 0x8000) == 0x8000)
2294                 pa_scan_i = 0x10000 - pa_scan_i;
2295         if ((pa_scan_q & 0x8000) == 0x8000)
2296                 pa_scan_q = 0x10000 - pa_scan_q;
2297
2298         pa_scan_pw = pa_scan_i * pa_scan_i + pa_scan_q * pa_scan_q;
2299
2300         /*estimated pa_scan_pw*/
2301 #if 0
2302         /*0dB => (512^2) * 10^(0/10) = 262144*/
2303         /*1dB => (512^2) * 10^(1/10) = 330019*/
2304         /*2dB => (512^2) * 10^(2/10) = 415470*/
2305         /*3dB => (512^2) * 10^(3/10) = 523046*/
2306         /*4dB => (512^2) * 10^(4/10) = 658475*/
2307         /*5dB => (512^2) * 10^(5/10) = 828972*/
2308         /*6dB => (512^2) * 10^(6/10) = 1043614*/
2309         /*7dB => (512^2) * 10^(7/10) = 1313832*/
2310         /*8dB => (512^2) * 10^(0/10) = 1654016*/
2311         /*9dB => (512^2) * 10^(1/10) = 2082283*/
2312         /*10dB => (512^2) * 10^(2/10) = 2621440*/
2313         /*11dB => (512^2) * 10^(3/10) = 3300197*/
2314         /*12dB => (512^2) * 10^(4/10) = 4154702*/
2315         /*13dB => (512^2) * 10^(5/10) = 5230460*/
2316         /*14dB => (512^2) * 10^(6/10) = 6584759*/
2317         /*15dB => (512^2) * 10^(7/10) = 8289721*/
2318 #endif
2319         if (pa_scan_pw >= 0x7e7db9)
2320                 pa_scan_pw = 0x0f;
2321         else if (pa_scan_pw >= 0x6479b7)
2322                 pa_scan_pw = 0x0e;
2323         else if (pa_scan_pw >= 0x4fcf7c)
2324                 pa_scan_pw = 0x0d;
2325         else if (pa_scan_pw >= 0x3f654e)
2326                 pa_scan_pw = 0x0c;
2327         else if (pa_scan_pw >= 0x325b65)
2328                 pa_scan_pw = 0x0b;
2329         else if (pa_scan_pw >= 0x280000)
2330                 pa_scan_pw = 0x0a;
2331         else if (pa_scan_pw >= 0x1fc5eb)
2332                 pa_scan_pw = 0x09;
2333         else if (pa_scan_pw >= 0x193d00)
2334                 pa_scan_pw = 0x8;
2335         else if (pa_scan_pw >= 0x140c28)
2336                 pa_scan_pw = 0x7;
2337         else if (pa_scan_pw >= 0xefc9e)
2338                 pa_scan_pw = 0x6;
2339         else if (pa_scan_pw >= 0xca62c)
2340                 pa_scan_pw = 0x5;
2341         else if (pa_scan_pw > 0xa0c2b)
2342                 pa_scan_pw = 0x4;
2343         else if (pa_scan_pw > 0x7fb26)
2344                 pa_scan_pw = 0x3;
2345         else if (pa_scan_pw > 0x656ee)
2346                 pa_scan_pw = 0x2;
2347         else if (pa_scan_pw > 0x50923)
2348                 pa_scan_pw = 0x1;
2349         else /*262144 >= pa_scan_pw*/
2350                 pa_scan_pw = 0x0;
2351
2352         odm_write_4byte(dm, 0x1bd4, 0x00060001);
2353         gainloss_back = (odm_read_4byte(dm, 0x1bfc) & 0x0000000f);
2354
2355         if (gainloss_back <= 0xa)
2356                 gainloss_back = 0xa - gainloss_back;
2357
2358         if (gainloss_back > pa_scan_pw + 0x8)
2359                 odm_set_rf_reg(dm, path, RF_0x8f, BIT(14) | BIT(13), 0x11);
2360         else if ((pa_scan_pw + 0x8 - gainloss_back) >= 0x6)
2361                 odm_set_rf_reg(dm, path, RF_0x8f, BIT(14) | BIT(13), 0x00);
2362         else
2363 #if 0
2364                 /*if (0x6 >= (pa_scan_pw + 0x8 - gainloss_back)> 0x0 )*/
2365 #endif
2366                 odm_set_rf_reg(dm, path, RF_0x8f, BIT(14) | BIT(13), 0x01);
2367
2368         RF_DBG(dm, DBG_RF_IQK,
2369                "[IQK] reg_1bfc =0x%x, pa_scan_pw =0x%x, gainloss_back = 0x%x, pa_scan_i = 0x%x, pa_scan_q = 0x%x, RF0x8f = 0x%x, !!!\n",
2370                reg_1bfc, pa_scan_pw, gainloss_back, pa_scan_i, pa_scan_q,
2371                odm_get_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK));
2372
2373         odm_write_4byte(dm, 0x1bcf, tmp1);
2374         odm_write_4byte(dm, 0x1bd4, tmp2);
2375 }
2376
2377 void _dpk_disable_bb_dynamic_pwr_threshold(struct dm_struct *dm, boolean flag)
2378 {
2379         if (flag) /*disable BB dynamic pwr threshold hold*/
2380                 odm_set_bb_reg(dm, R_0x1c74, BIT(31) | BIT(30) | BIT(29) | BIT(28), 0x0);
2381         else
2382                 odm_set_bb_reg(dm, R_0x1c74, BIT(31) | BIT(30) | BIT(29) | BIT(28), 0x2);
2383         RF_DBG(dm, DBG_RF_IQK, "[DPK]\nset 0x1c74 = 0x%x\n",
2384                odm_read_4byte(dm, 0x1c74));
2385 }
2386
2387 void _dpk_set_dpk_sram_to_10_8821c(struct dm_struct *dm, u8 path)
2388 {
2389         u32 tmp1, tmp2;
2390         u8 i;
2391         tmp1 = odm_read_4byte(dm, 0x1b00);
2392         tmp2 = odm_read_4byte(dm, 0x1b08);
2393
2394         for (i = 0; i < 64; i++)
2395                 odm_write_4byte(dm, 0x1bdc, 0xd0000001 + (i * 2) + 1);
2396
2397         for (i = 0; i < 64; i++)
2398                 odm_write_4byte(dm, 0x1bdc, 0x90000080 + (i * 2) + 1);
2399
2400 #if 0
2401         /*
2402         RF_DBG(dm, DBG_RF_IQK,
2403                 "[DPK]return  txagc = 0x%x , 1bfc = 0x%x,rf00=0x%x\n",
2404                 tmp4, odm_read_4byte(dm, 0x1bfc),
2405                 odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK));
2406 */
2407 #endif
2408         odm_write_4byte(dm, 0x1bdc, 0x0);
2409         odm_write_4byte(dm, 0x1b00, tmp1);
2410         odm_write_4byte(dm, 0x1b08, tmp2);
2411 }
2412
2413 void _dpk_set_bbtxagc_8821c(struct dm_struct *dm, u8 path)
2414 {
2415         u8 hw_rate, tmp;
2416
2417         for (hw_rate = 0; hw_rate < 0x53; hw_rate++) {
2418                 phydm_write_txagc_1byte_8821c(dm, 0x30, (enum rf_path)0x0, hw_rate);
2419
2420                 tmp = config_phydm_read_txagc_8821c(dm, (enum rf_path)0x0, hw_rate);
2421 #if 0
2422                 /*
2423           RF_DBG(dm, DBG_RF_IQK,
2424                   "hw_rate =0x%x, tmp =0x%x \n", hw_rate, tmp);
2425 */
2426 #endif
2427         }
2428 }
2429
2430 u8 _dpk_get_txagcindpk_8821c(struct dm_struct *dm, u8 path)
2431 {
2432         u32 tmp1, tmp2, tmp3;
2433         u8 tmp4;
2434         tmp1 = odm_read_4byte(dm, 0x1bcc);
2435         odm_set_bb_reg(dm, R_0x1bcc, BIT(26), 0x01);
2436         tmp2 = odm_read_4byte(dm, 0x1bd4);
2437         odm_set_bb_reg(dm, R_0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x0a);
2438         tmp3 = odm_read_4byte(dm, 0x1bfc);
2439         tmp4 = ((u8)odm_get_bb_reg(dm, R_0x1bfc, MASKDWORD)) >> 2;
2440 #if 0
2441         /*
2442         RF_DBG(dm, DBG_RF_IQK,
2443                 "[DPK]return  txagc = 0x%x , 1bfc = 0x%x,rf00=0x%x\n",
2444                 tmp4, odm_read_4byte(dm, 0x1bfc),
2445                 odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK));
2446 */
2447 #endif
2448         odm_write_4byte(dm, 0x1bcc, tmp1);
2449         odm_write_4byte(dm, 0x1bd4, tmp2);
2450
2451         return tmp4;
2452 }
2453
2454 void _dpk_ampmcurce_8821c(struct dm_struct *dm, u8 path)
2455 {
2456         u8 i;
2457         RF_DBG(dm, DBG_RF_IQK, "[DPK] 0x1bcc = 0x%x, 0x1bb8 =0x%x\n",
2458                odm_read_4byte(dm, 0x1bcc), odm_read_4byte(dm, 0x1bb8));
2459
2460         odm_write_4byte(dm, 0x1bcc, 0x118f8800);
2461         for (i = 0; i < 8; i++) {
2462                 odm_write_4byte(dm, 0x1b90, 0x0101e018 + i);
2463                 odm_write_4byte(dm, 0x1bd4, 0x00060000);
2464                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2465                 odm_write_4byte(dm, 0x1bd4, 0x00070000);
2466                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2467                 odm_write_4byte(dm, 0x1bd4, 0x00080000);
2468                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2469                 odm_write_4byte(dm, 0x1bd4, 0x00090000);
2470                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2471         }
2472
2473         odm_write_4byte(dm, 0x1b90, 0x0001e018);
2474 }
2475 void _dpk_readsram_8821c(struct dm_struct *dm, u8 path)
2476 {
2477         /* dbg message*/
2478         u8 i;
2479         odm_write_4byte(dm, 0x1b00, 0xf8000008);
2480         odm_write_4byte(dm, 0x1b08, 0x00000080);
2481         odm_write_4byte(dm, 0x1bd4, 0x00040001);
2482
2483         RF_DBG(dm, DBG_RF_IQK, "[DPK] SRAM value!!!\n");
2484
2485         for (i = 0; i < 64; i++) {
2486 #if 0
2487                 /*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/
2488 #endif
2489                 odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2);
2490
2491                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2492         }
2493         odm_write_4byte(dm, 0x1bd4, 0x00050001);
2494         for (i = 0; i < 64; i++) {
2495 #if 0
2496                 /*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/
2497 #endif
2498                 odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2);
2499
2500                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2501         }
2502 #if 0
2503         /*ODM_sleep_ms(200);*/
2504 #endif
2505         ODM_delay_ms(200);
2506 #if 0
2507         /*odm_write_4byte(dm, 0x1b08, 0x00000080);*/
2508 #endif
2509         odm_write_4byte(dm, 0x1bd4, 0xA0001);
2510         odm_write_4byte(dm, 0x1bdc, 0x00000000);
2511 }
2512
2513 void _dpk_restore_8821c(struct dm_struct *dm, u8 path)
2514 {
2515         odm_write_4byte(dm, 0xc60, 0x700B8040);
2516         odm_write_4byte(dm, 0xc60, 0x700B8040);
2517         odm_write_4byte(dm, 0xc60, 0x70146040);
2518         odm_write_4byte(dm, 0xc60, 0x70246040);
2519         odm_write_4byte(dm, 0xc60, 0x70346040);
2520         odm_write_4byte(dm, 0xc60, 0x70446040);
2521         odm_write_4byte(dm, 0xc60, 0x705B2040);
2522         odm_write_4byte(dm, 0xc60, 0x70646040);
2523         odm_write_4byte(dm, 0xc60, 0x707B8040);
2524         odm_write_4byte(dm, 0xc60, 0x708B8040);
2525         odm_write_4byte(dm, 0xc60, 0x709B8040);
2526         odm_write_4byte(dm, 0xc60, 0x70aB8040);
2527         odm_write_4byte(dm, 0xc60, 0x70bB6040);
2528         odm_write_4byte(dm, 0xc60, 0x70c06040);
2529         odm_write_4byte(dm, 0xc60, 0x70d06040);
2530         odm_write_4byte(dm, 0xc60, 0x70eF6040);
2531         odm_write_4byte(dm, 0xc60, 0x70f06040);
2532
2533         odm_write_4byte(dm, 0xc58, 0xd8020402);
2534         odm_write_4byte(dm, 0xc5c, 0xde000120);
2535         odm_write_4byte(dm, 0xc6c, 0x0000122a);
2536
2537         odm_write_4byte(dm, 0x808, 0x24028211);
2538 #if 0
2539         /*odm_write_4byte(dm, 0x810, 0x211042A5);*/
2540 #endif
2541         odm_write_4byte(dm, 0x90c, 0x13000000);
2542         odm_write_4byte(dm, 0x9a4, 0x80000088);
2543         odm_write_4byte(dm, 0xc94, 0x01000101);
2544         odm_write_4byte(dm, 0x1904, 0x00238000);
2545         odm_write_4byte(dm, 0x1904, 0x00228000);
2546         odm_write_4byte(dm, 0xC00, 0x00000007);
2547 }
2548
2549 void _dpk_clear_sram_8821c(struct dm_struct *dm, u8 path)
2550 {
2551         u8 i;
2552
2553         /* write pwsf*/
2554         /*S3*/
2555         odm_write_4byte(dm, 0x1bdc, 0x40caffe1);
2556         odm_write_4byte(dm, 0x1bdc, 0x4080a1e3);
2557         odm_write_4byte(dm, 0x1bdc, 0x405165e5);
2558         odm_write_4byte(dm, 0x1bdc, 0x403340e7);
2559         odm_write_4byte(dm, 0x1bdc, 0x402028e9);
2560         odm_write_4byte(dm, 0x1bdc, 0x401419eb);
2561         odm_write_4byte(dm, 0x1bdc, 0x400d10ed);
2562         odm_write_4byte(dm, 0x1bdc, 0x40080aef);
2563
2564         odm_write_4byte(dm, 0x1bdc, 0x400506f1);
2565         odm_write_4byte(dm, 0x1bdc, 0x400304f3);
2566         odm_write_4byte(dm, 0x1bdc, 0x400203f5);
2567         odm_write_4byte(dm, 0x1bdc, 0x400102f7);
2568         odm_write_4byte(dm, 0x1bdc, 0x400101f9);
2569         odm_write_4byte(dm, 0x1bdc, 0x400101fb);
2570         odm_write_4byte(dm, 0x1bdc, 0x400101fd);
2571         odm_write_4byte(dm, 0x1bdc, 0x400101ff);
2572         /*S0*/
2573         odm_write_4byte(dm, 0x1bdc, 0x40caff81);
2574         odm_write_4byte(dm, 0x1bdc, 0x4080a183);
2575         odm_write_4byte(dm, 0x1bdc, 0x40516585);
2576         odm_write_4byte(dm, 0x1bdc, 0x40334087);
2577         odm_write_4byte(dm, 0x1bdc, 0x40202889);
2578         odm_write_4byte(dm, 0x1bdc, 0x4014198b);
2579         odm_write_4byte(dm, 0x1bdc, 0x400d108d);
2580         odm_write_4byte(dm, 0x1bdc, 0x40080a8f);
2581         odm_write_4byte(dm, 0x1bdc, 0x40050691);
2582         odm_write_4byte(dm, 0x1bdc, 0x40030493);
2583         odm_write_4byte(dm, 0x1bdc, 0x40020395);
2584         odm_write_4byte(dm, 0x1bdc, 0x40010297);
2585         odm_write_4byte(dm, 0x1bdc, 0x40010199);
2586         odm_write_4byte(dm, 0x1bdc, 0x4001019b);
2587         odm_write_4byte(dm, 0x1bdc, 0x4001019d);
2588         odm_write_4byte(dm, 0x1bdc, 0x4001019f);
2589
2590         odm_write_4byte(dm, 0x1bdc, 0x00000000);
2591
2592         /*clear sram even*/
2593         for (i = 0; i < 0x40; i++)
2594                 odm_write_4byte(dm, 0x1bdc, 0xd0000000 + ((i * 2) + 1));
2595         /*clear sram odd*/
2596         for (i = 0; i < 0x40; i++)
2597                 odm_write_4byte(dm, 0x1bdc, 0x90000080 + ((i * 2) + 1));
2598
2599         odm_write_4byte(dm, 0x1bdc, 0x0);
2600         RF_DBG(dm, DBG_RF_IQK, "[DPK]==========write pwsf and clear sram/n");
2601 }
2602
2603 void _dpk_setting_8821c(struct dm_struct *dm, u8 path)
2604 {
2605         RF_DBG(dm, DBG_RF_IQK,
2606                "[DPK]==========Start the DPD setting Initilaize/n");
2607         /*AFE setting*/
2608         odm_write_4byte(dm, 0xc60, 0x50000000);
2609         odm_write_4byte(dm, 0xc60, 0x700F0040);
2610         odm_write_4byte(dm, 0xc5c, 0xd1000120);
2611         odm_write_4byte(dm, 0xc58, 0xd8000402);
2612         odm_write_4byte(dm, 0xc6c, 0x00000a15);
2613         odm_write_4byte(dm, 0xc00, 0x00000004);
2614 #if 0
2615         /*_iqk_bb_reset_8821c(dm);*/
2616 #endif
2617         odm_write_4byte(dm, 0xe5c, 0xD1000120);
2618         odm_write_4byte(dm, 0xc6c, 0x00000A15);
2619         odm_write_4byte(dm, 0xe6c, 0x00000A15);
2620         odm_write_4byte(dm, 0x808, 0x2D028200);
2621 #if 0
2622         /*odm_write_4byte(dm, 0x810, 0x211042A5);*/
2623 #endif
2624         odm_write_4byte(dm, 0x8f4, 0x00d80fb1);
2625         odm_write_4byte(dm, 0x90c, 0x0B00C000);
2626         odm_write_4byte(dm, 0x9a4, 0x00000080);
2627         odm_write_4byte(dm, 0xc94, 0x01000101);
2628         odm_write_4byte(dm, 0xe94, 0x01000101);
2629         odm_write_4byte(dm, 0xe5c, 0xD1000120);
2630         odm_write_4byte(dm, 0xc6c, 0x00000A15);
2631         odm_write_4byte(dm, 0xe6c, 0x00000A15);
2632         odm_write_4byte(dm, 0x1904, 0x00020000);
2633         /*path A*/
2634         /*RF*/
2635         odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x80000);
2636         odm_set_rf_reg(dm, RF_PATH_A, RF_0x33, RFREGOFFSETMASK, 0x00024);
2637         odm_set_rf_reg(dm, RF_PATH_A, RF_0x3e, RFREGOFFSETMASK, 0x0003F);
2638         odm_set_rf_reg(dm, RF_PATH_A, RF_0x3f, RFREGOFFSETMASK, 0xCBFCE);
2639         odm_set_rf_reg(dm, RF_PATH_A, RF_0xef, RFREGOFFSETMASK, 0x00000);
2640         /*AGC boundary selection*/
2641         odm_write_4byte(dm, 0x1bbc, 0x0001abf6);
2642         odm_write_4byte(dm, 0x1b90, 0x0001e018);
2643         odm_write_4byte(dm, 0x1bb8, 0x000fffff);
2644         odm_write_4byte(dm, 0x1bc8, 0x000c55aa);
2645 #if 0
2646         /*odm_write_4byte(dm, 0x1bcc, 0x11978200);*/
2647 #endif
2648         odm_write_4byte(dm, 0x1bcc, 0x11978800);
2649 #if 0
2650         /*odm_write_4byte(dm, 0xcb0, 0x77775747);*/
2651         /*odm_write_4byte(dm, 0xcb4, 0x100000f7);*/
2652         /*odm_write_4byte(dm, 0xcb4, 0x10000007);*/
2653         /*odm_write_4byte(dm, 0xcbc, 0x0);*/
2654 #endif
2655 }
2656
2657 void _dpk_dynamic_bias_8821c(struct dm_struct *dm, u8 path, u8 dynamicbias)
2658 {
2659         u32 tmp;
2660         tmp = odm_get_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK);
2661         tmp = tmp | BIT(8);
2662         odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, tmp);
2663         if ((*dm->band_type == ODM_BAND_5G) && (*dm->band_width == 1))
2664                 odm_set_rf_reg(dm, path, RF_0x61, BIT(7) | BIT(6) | BIT(5) | BIT(4), dynamicbias);
2665         if ((*dm->band_type == ODM_BAND_5G) && (*dm->band_width == 2))
2666                 odm_set_rf_reg(dm, path, RF_0x61, BIT(7) | BIT(6) | BIT(5) | BIT(4), dynamicbias);
2667         tmp = tmp & (~BIT(8));
2668         odm_set_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK, tmp);
2669         RF_DBG(dm, DBG_RF_IQK, "[DPK]Set DynamicBias 0xdf=0x%x, 0x61=0x%x\n",
2670                odm_get_rf_reg(dm, RF_PATH_A, RF_0xdf, RFREGOFFSETMASK),
2671                odm_get_rf_reg(dm, RF_PATH_A, RF_0x61, RFREGOFFSETMASK));
2672 }
2673
2674 void _dpk_boundary_selection_8821c(struct dm_struct *dm, u8 path)
2675 {
2676         u8 tmp_pad, compared_pad, compared_txbb;
2677         u32 rf_backup_reg00;
2678         u8 i = 0;
2679         u8 j = 1;
2680         u32 boundaryselect = 0;
2681         struct dm_iqk_info *iqk_info = &dm->IQK_info;
2682
2683         RF_DBG(dm, DBG_RF_IQK, "[DPK]Start the DPD boundary selection\n");
2684         rf_backup_reg00 = odm_get_rf_reg(dm, (enum rf_path)path, RF_0x00, RFREGOFFSETMASK);
2685         tmp_pad = 0;
2686         compared_pad = 0;
2687         boundaryselect = 0;
2688 #if dpk_forcein_sram4
2689         for (i = 0x1f; i > 0x0; i--) { /*i=tx index*/
2690                 odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, 0x20000 + i);
2691
2692                 if (iqk_info->is_btg) {
2693                         compared_pad = (u8)((0x1c000 & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x78, RFREGOFFSETMASK)) >> 14);
2694                         compared_txbb = (u8)((0x07C00 & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x5c, RFREGOFFSETMASK)) >> 10);
2695                 } else {
2696                         compared_pad = (u8)((0xe0 & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x56, RFREGOFFSETMASK)) >> 5);
2697                         compared_txbb = (u8)((0x1f & odm_get_rf_reg(dm, (enum rf_path)path, RF_0x56, RFREGOFFSETMASK)));
2698                 }
2699                 if (i == 0x1f) {
2700                         /*boundaryselect = compared_txbb;*/
2701                         boundaryselect = 0x1f;
2702                         tmp_pad = compared_pad;
2703                 }
2704                 if (compared_pad < tmp_pad) {
2705                         boundaryselect = boundaryselect + (i << (j * 5));
2706                         tmp_pad = compared_pad;
2707                         j++;
2708                 }
2709
2710                 if (j >= 4)
2711                         break;
2712         }
2713
2714 #else
2715         boundaryselect = 0x0;
2716 #endif
2717         odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_backup_reg00);
2718         odm_write_4byte(dm, 0x1bbc, boundaryselect);
2719 }
2720
2721 u8 _dpk_get_dpk_tx_agc_8821c(struct dm_struct *dm, u8 path)
2722 {
2723         u8 tx_agc_init_value = 0x1f; /* DPK TXAGC value*/
2724         u32 rf_reg00 = 0x0;
2725         u8 gainloss = 0x1;
2726         u8 best_tx_agc, txagcindpk = 0x0;
2727         u8 tmp;
2728         boolean fail = true;
2729         u32 IQK_CMD = 0xf8000d18;
2730
2731         /* rf_reg00 = 0x40000 + tx_agc_init_value;  set TXAGC value */
2732         if (*dm->band_type == ODM_BAND_5G) {
2733                 tx_agc_init_value = 0x1c;
2734                 rf_reg00 = 0x40000 + tx_agc_init_value; /* set TXAGC value*/
2735 #if 0
2736                 /*rf_reg00 = 0x54000 + tx_agc_init_value;*/ /* set TXAGC value*/
2737 #endif
2738                 odm_write_4byte(dm, 0x1bc8, 0x000c55aa);
2739                 odm_set_rf_reg(dm, RF_PATH_A, RF_0x8f, RFREGOFFSETMASK, 0xa9c00);
2740         } else {
2741                 tx_agc_init_value = 0x17;
2742                 rf_reg00 = 0x44000 + tx_agc_init_value; /* set TXAGC value*/
2743 #if 0
2744                 /*rf_reg00 = 0x54000 + tx_agc_init_value; */ /* set TXAGC value*/
2745 #endif
2746                 odm_write_4byte(dm, 0x1bc8, 0x000c44aa);
2747                 odm_set_rf_reg(dm, RF_PATH_A, RF_0x8f, RFREGOFFSETMASK, 0xaec00);
2748         }
2749         odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_reg00);
2750         odm_set_bb_reg(dm, R_0x1b8c, BIT(15) | BIT(14) | BIT(13), gainloss);
2751         odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1);
2752         odm_set_bb_reg(dm, R_0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5);
2753
2754         _dpk_set_bbtxagc_8821c(dm, RF_PATH_A);
2755         txagcindpk = _dpk_get_txagcindpk_8821c(dm, RF_PATH_A);
2756
2757         if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0)
2758                 odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
2759         ;
2760 #if 0
2761         /*ODM_sleep_ms(1);*/
2762 #endif
2763         ODM_delay_ms(1);
2764         odm_write_4byte(dm, 0x1b00, IQK_CMD);
2765         odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
2766
2767         fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD);
2768
2769         odm_write_4byte(dm, 0x1b90, 0x0001e018);
2770 #if 0
2771         /*
2772         RF_DBG(dm, DBG_RF_IQK,
2773                 "[DPK]rf_reg00 =0x%x, 0x8F =0x%x, txagcindpk =0x%x\n",
2774                 odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK),
2775                 odm_get_rf_reg(dm, path, RF_0x8f, RFREGOFFSETMASK),txagcindpk);
2776 */
2777 #endif
2778
2779         odm_write_4byte(dm, 0x1bd4, 0x60001);
2780         tmp = (u8)odm_read_4byte(dm, 0x1bfc);
2781         best_tx_agc = tx_agc_init_value - (0xa - tmp);
2782 #if 0
2783 /*
2784         RF_DBG(dm, DBG_RF_IQK,
2785                 "[DPK](2), 0x1b8c =0x%x, rf_reg00 = 0x%x, 0x1b00 = 0x%x, 0x1bfc = 0x%x, 0x1bd4 = 0x%x,best_tx_agc =0x%x, 0x1bfc[7:0] =0x%x\n",
2786                 odm_read_4byte(dm, 0x1b8c),
2787                 odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK),
2788                 odm_read_4byte(dm, 0x1b00),
2789                 odm_read_4byte(dm, 0x1bfc), odm_read_4byte(dm, 0x1bd4),
2790                 best_tx_agc, tmp);
2791 */
2792 #endif
2793 /* dbg message*/
2794 #if 0
2795
2796         RF_DBG(dm, DBG_RF_IQK, "[DPK] 0x1bcc = 0x%x, 0x1bb8 =0x%x\n",
2797                odm_read_4byte(dm, 0x1bcc), odm_read_4byte(dm, 0x1bb8));
2798
2799         odm_write_4byte(dm, 0x1bcc, 0x118f8800);
2800         for (i = 0 ; i < 8; i++) {
2801                 odm_write_4byte(dm, 0x1b90, 0x0101e018 + i);
2802                 odm_write_4byte(dm, 0x1bd4, 0x00060000);
2803                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2804                 odm_write_4byte(dm, 0x1bd4, 0x00070000);
2805                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2806                 odm_write_4byte(dm, 0x1bd4, 0x00080000);
2807                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2808                 odm_write_4byte(dm, 0x1bd4, 0x00090000);
2809                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2810         }
2811
2812         odm_write_4byte(dm, 0x1b90, 0x0001e018);
2813
2814 #endif
2815         return best_tx_agc;
2816 }
2817
2818 boolean
2819 _dpk_enable_dpk_8821c(struct dm_struct *dm, u8 path, u8 best_tx_agc)
2820 {
2821         u32 rf_reg00 = 0x0;
2822         boolean fail = true;
2823         u32 IQK_CMD = 0xf8000e18;
2824
2825         if (*dm->band_type == ODM_BAND_5G)
2826                 rf_reg00 = 0x40000 + best_tx_agc; /* set TXAGC value*/
2827         else
2828                 rf_reg00 = 0x44000 + best_tx_agc; /* set TXAGC value*/
2829         odm_set_rf_reg(dm, RF_PATH_A, RF_0x00, RFREGOFFSETMASK, rf_reg00);
2830         _dpk_set_dpk_pa_scan(dm, RF_PATH_A);
2831
2832         /*ODM_sleep_ms(1);*/
2833         ODM_delay_ms(1);
2834         odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1);
2835         odm_write_4byte(dm, 0x8f8, 0x41400080);
2836
2837         if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0)
2838                 odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
2839
2840         /*ODM_sleep_ms(1);*/
2841         ODM_delay_ms(1);
2842         odm_write_4byte(dm, 0x1b00, IQK_CMD);
2843         odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
2844
2845         odm_write_4byte(dm, 0x1b90, 0x0001e018);
2846         odm_write_4byte(dm, 0x1bd4, 0xA0001);
2847         fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD);
2848 #if 0
2849 /*
2850         RF_DBG(dm, DBG_RF_IQK,
2851                 "[DPK] (3) 0x1b0b = 0x%x, 0x1bc8 = 0x%x, rf_reg00 = 0x%x, ,0x1bfc = 0x%x, 0x1b90=0x%x, 0x1b94=0x%x\n",
2852                 odm_read_1byte(dm, 0x1b0b), odm_read_4byte(dm, 0x1bc8), odm_get_rf_reg(dm, path, RF_0x00, RFREGOFFSETMASK),
2853                 odm_read_4byte(dm, 0x1bfc), odm_read_4byte(dm, 0x1b90), odm_read_4byte(dm, 0x1b94));
2854 */
2855 #endif
2856 #if 0 /* dbg message*/
2857         u8 delay_count = 0x0;
2858     u8 i;
2859         u32 tmp;
2860         odm_write_4byte(dm, 0x1b00, 0xf8000008);
2861         odm_write_4byte(dm, 0x1b08, 0x00000080);
2862         odm_write_4byte(dm, 0x1bd4, 0x00040001);
2863
2864         RF_DBG(dm, DBG_RF_IQK, "[DPK] SRAM value!!!\n");
2865
2866         for (i = 0 ; i < 64; i++) {
2867                 /*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/
2868                 odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2);
2869
2870                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2871         }
2872         odm_write_4byte(dm, 0x1bd4, 0x00050001);
2873         for (i = 0 ; i < 64; i++) {
2874                 /*odm_write_4byte(dm, 0x1b90, 0x0101e018+i);*/
2875                 odm_write_4byte(dm, 0x1bdc, 0xc0000081 + i * 2);
2876
2877                 RF_DBG(dm, DBG_RF_IQK, "0x%x\n", odm_read_4byte(dm, 0x1bfc));
2878         }
2879
2880         /*odm_write_4byte(dm, 0x1b08, 0x00000080);*/
2881         odm_write_4byte(dm, 0x1bd4, 0xA0001);
2882         odm_write_4byte(dm, 0x1bdc, 0x00000000);
2883 #endif
2884         return fail;
2885 }
2886
2887 boolean
2888 _dpk_enable_dpd_8821c(struct dm_struct *dm, u8 path, u8 best_tx_agc)
2889 {
2890         boolean fail = true;
2891         u8 offset = 0x0;
2892         u32 IQK_CMD = 0xf8000f18;
2893         u8 external_pswf_gain;
2894         boolean gain_scaling_enable = false;
2895
2896         odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1);
2897         odm_write_4byte(dm, 0x8f8, 0x41400080);
2898         if (odm_get_rf_reg(dm, path, RF_0x08, RFREGOFFSETMASK) != 0x0)
2899                 odm_set_rf_reg(dm, path, RF_0x8, RFREGOFFSETMASK, 0x0);
2900         /*ODM_sleep_ms(1);*/
2901         ODM_delay_ms(1);
2902         odm_write_4byte(dm, 0x1b00, IQK_CMD);
2903         odm_write_4byte(dm, 0x1b00, IQK_CMD + 1);
2904         fail = _iqk_check_nctl_done_8821c(dm, path, IQK_CMD);
2905
2906         odm_write_4byte(dm, 0x1b90, 0x0001e018);
2907         odm_write_4byte(dm, 0x1bd4, 0xA0001);
2908
2909         if (!fail) {
2910                 odm_write_4byte(dm, 0x1bcf, 0x19);
2911                 odm_write_4byte(dm, 0x1bdc, 0x0);
2912                 /*add 2db extrnal for compensate performnace, the reason is unknown*/
2913                 external_pswf_gain = 0x2;
2914                 best_tx_agc = best_tx_agc + external_pswf_gain;
2915
2916                 if (best_tx_agc >= 0x19)
2917                         offset = best_tx_agc - 0x19;
2918                 else
2919                         offset = 0x20 - (0x19 - best_tx_agc);
2920                 odm_set_bb_reg(dm, R_0x1bd0, BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), offset);
2921                 if (gain_scaling_enable)
2922                         _dpk_set_gain_scaling(dm, RF_PATH_A);
2923                 else
2924                         odm_write_4byte(dm, 0x1b98, 0x4c004c00);
2925
2926         } else {
2927                 RF_DBG(dm, DBG_RF_IQK,
2928                        "[DPK](4)0x1b08 =%x, 0x1bc8 = 0x%x,0x1bfc = 0x%x, ,0x1bd0 = 0x%x, offset =%x, 1bcc =%x\n",
2929                        odm_read_4byte(dm, 0x1b08), odm_read_4byte(dm, 0x1bc8),
2930                        odm_read_1byte(dm, 0x1bfc), odm_read_4byte(dm, 0x1bd0),
2931                        offset, odm_read_4byte(dm, 0x1bcc));
2932         }
2933
2934         return fail;
2935 }
2936
2937 void _phy_dpd_calibrate_8821c(struct dm_struct *dm, boolean reset)
2938 {
2939         u32 backup_dpdbb[3];
2940         u8 best_tx_agc = 0x1c;
2941         u32 MAC_backup[MAC_REG_NUM_8821C], RF_backup[RF_REG_NUM_8821C][1];
2942         u32 backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518};
2943         u32 BB_backup[DPK_BB_REG_NUM_8821C];
2944         u32 backup_bb_reg[DPK_BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0x1990, 0x9a4, 0xa04, 0xc58, 0xc5c, 0xe58, 0xe5c, 0xc6c, 0xe6c, 0x90c, 0xc94, 0xe94, 0x1904, 0xcb0, 0xcb4, 0xcbc, 0xc00};
2945         u32 backup_rf_reg[RF_REG_NUM_8821C] = {0xdf, 0xde, 0x8f, 0x0, 0x1};
2946         u8 i;
2947         u32 backup_dpk_reg[3] = {0x1bd0, 0x1b98, 0x1bbc};
2948
2949         struct dm_iqk_info *iqk_info = &dm->IQK_info;
2950         iqk_info->is_btg = (boolean)odm_get_bb_reg(dm, R_0xcb8, BIT(16));
2951         if (!(*dm->mp_mode))
2952                 if (_iqk_reload_iqk_8821c(dm, reset))
2953                         return;
2954         if (!(*dm->band_type == ODM_BAND_5G))
2955                 return;
2956
2957         RF_DBG(dm, DBG_RF_IQK, "[DPK]==========DPK strat!!!!!==========\n");
2958         RF_DBG(dm, DBG_RF_IQK,
2959                "[DPK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n",
2960                (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width,
2961                dm->ext_pa, dm->ext_pa_5g);
2962         _iqk_backup_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, DPK_BB_REG_NUM_8821C);
2963         _iqk_afe_setting_8821c(dm, true);
2964         _iqk_backup_rf_8821c(dm, RF_backup, backup_rf_reg);
2965
2966         if (iqk_info->is_btg) {
2967         } else {
2968                 if (*dm->band_type == ODM_BAND_2_4G)
2969                         odm_set_bb_reg(dm, R_0xcb8, BIT(8), 0x1);
2970                 else
2971                         odm_set_bb_reg(dm, R_0xcb8, BIT(8), 0x0);
2972         }
2973
2974         /*backup 0x1b2c, 1b38,0x1b3c*/
2975         backup_dpdbb[0] = odm_read_4byte(dm, 0x1b2c);
2976         backup_dpdbb[1] = odm_read_4byte(dm, 0x1b38);
2977         backup_dpdbb[2] = odm_read_4byte(dm, 0x1b3c);
2978         RF_DBG(dm, DBG_RF_IQK, "[DPK]In DPD Process(1), Backup\n");
2979
2980         /*PDK Init Register setting*/
2981         _dpk_clear_sram_8821c(dm, RF_PATH_A);
2982         _dpk_setting_8821c(dm, RF_PATH_A);
2983         _dpk_boundary_selection_8821c(dm, RF_PATH_A);
2984         odm_set_bb_reg(dm, R_0x1bc8, BIT(31), 0x1);
2985         odm_set_bb_reg(dm, R_0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5);
2986         /* Get the best TXAGC*/
2987
2988         best_tx_agc = _dpk_get_dpk_tx_agc_8821c(dm, RF_PATH_A);
2989 #if 0
2990         /*ODM_sleep_ms(2);*/
2991 #endif
2992
2993         ODM_delay_ms(2);
2994         RF_DBG(dm, DBG_RF_IQK, "[DPK]In DPD Process(2), Best TXAGC = 0x%x\n",
2995                best_tx_agc);
2996
2997         if (_dpk_enable_dpk_8821c(dm, RF_PATH_A, best_tx_agc)) {
2998                 RF_DBG(dm, DBG_RF_IQK,
2999                        "[DPK]In DPD Process(3), DPK process is Fail\n");
3000         }
3001 #if 0
3002         /*ODM_sleep_ms(2);*/
3003 #endif
3004         ODM_delay_ms(2);
3005         if (_dpk_enable_dpd_8821c(dm, RF_PATH_A, best_tx_agc)) {
3006                 RF_DBG(dm, DBG_RF_IQK,
3007                        "[DPK]In DPD Process(4), DPD process is Fail\n");
3008         }
3009         /* restore IQK */
3010         iqk_info->rf_reg18 = odm_get_rf_reg(dm, RF_PATH_A, RF_0x18, RFREGOFFSETMASK);
3011         _iqk_reload_iqk_setting_8821c(dm, 0, 2);
3012         _iqk_fill_iqk_report_8821c(dm, 0);
3013 #if 0
3014         /*
3015         RF_DBG(dm, DBG_RF_IQK,
3016                 "[DPK]reload IQK result before, iqk_info->rf_reg18=0x%x, iqk_info->iqk_channel[0]=0x%x, iqk_info->iqk_channel[1]=0x%x!!!!\n",
3017                 iqk_info->rf_reg18, iqk_info->iqk_channel[0], iqk_info->iqk_channel[1]);
3018       */
3019 #endif
3020
3021         /* Restore setup */
3022 #if 0
3023         /*_dpk_readsram_8821c(dm, RF_PATH_A);*/
3024 #endif
3025         _dpk_restore_8821c(dm, RF_PATH_A);
3026         odm_set_bb_reg(dm, R_0x8f8, BIT(25) | BIT(24) | BIT(23) | BIT(22), 0x5);
3027         odm_set_bb_reg(dm, R_0x1bd4, BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16), 0x0);
3028         odm_set_bb_reg(dm, R_0x1b00, BIT(2) | BIT(1), 0x0);
3029         odm_set_bb_reg(dm, R_0x1b08, BIT(6) | BIT(5), 0x2);
3030
3031         odm_write_4byte(dm, 0x1b2c, backup_dpdbb[0]);
3032         odm_write_4byte(dm, 0x1b38, backup_dpdbb[1]);
3033         odm_write_4byte(dm, 0x1b3c, backup_dpdbb[2]);
3034         /*enable DPK*/
3035         odm_set_bb_reg(dm, R_0x1b2c, BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2) | BIT(1) | BIT(0), 0x5);
3036 /*enable boundary condition*/
3037 #if dpk_forcein_sram4 /* disable : froce in sram4*/
3038         odm_set_bb_reg(dm, R_0x1bcc, BIT(27), 0x1);
3039 #endif
3040         odm_write_4byte(dm, 0x1bcc, 0x11868800);
3041         RF_DBG(dm, DBG_RF_IQK, "[DPK]In DPD Process(5), Restore\n");
3042         _iqk_restore_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, DPK_BB_REG_NUM_8821C);
3043         _iqk_afe_setting_8821c(dm, false);
3044         _iqk_restore_rf_8821c(dm, backup_rf_reg, RF_backup);
3045         /*toggle dynamic_pwr_threshold*/
3046
3047         /* backup the DPK current result*/
3048         for (i = 0; i < DPK_BACKUP_REG_NUM_8821C; i++)
3049                 dpk_result[i] = odm_read_4byte(dm, backup_dpk_reg[i]);
3050
3051         RF_DBG(dm, DBG_RF_IQK,
3052                "[DPK]the DPD calibration Process Finish (6), 0x1bd0 = 0x%x, 0x1b98 = 0x%x, 0x1bbc0= 0x%x\n",
3053                dpk_result[0], dpk_result[1], dpk_result[2]);
3054 }
3055
3056 u32 _iqk_tximr_selfcheck_8821c(void *dm_void, u8 tone_index, u8 path)
3057 {
3058         u32 tx_ini_power_H[2], tx_ini_power_L[2];
3059         u32 tmp1, tmp2, tmp3, tmp4, tmp5;
3060         u32 IQK_CMD;
3061         u32 tximr = 0x0;
3062         u8 i;
3063
3064         struct dm_struct *dm = (struct dm_struct *)dm_void;
3065         /*backup*/
3066         odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
3067         odm_write_4byte(dm, 0x1bc8, 0x80000000);
3068         odm_write_4byte(dm, 0x8f8, 0x41400080);
3069         tmp1 = odm_read_4byte(dm, 0x1b0c);
3070         tmp2 = odm_read_4byte(dm, 0x1b14);
3071         tmp3 = odm_read_4byte(dm, 0x1b1c);
3072         tmp4 = odm_read_4byte(dm, 0x1b20);
3073         tmp5 = odm_read_4byte(dm, 0x1b24);
3074         /*setup*/
3075         odm_write_4byte(dm, 0x1b0c, 0x00003000);
3076         odm_write_4byte(dm, 0x1b1c, 0xA2193C32);
3077         odm_write_1byte(dm, 0x1b15, 0x00);
3078         odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008));
3079         odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060008));
3080         odm_write_4byte(dm, 0x1b2c, 0x07);
3081         odm_write_4byte(dm, 0x1b38, 0x20000000);
3082         odm_write_4byte(dm, 0x1b3c, 0x20000000);
3083         /* ======derive pwr1========*/
3084         for (i = 0; i < 2; i++) {
3085                 if (i == 0)
3086                         odm_write_4byte(dm, 0x1bcc, 0x0f);
3087                 else
3088                         odm_write_4byte(dm, 0x1bcc, 0x09);
3089                 /* One Shot*/
3090                 IQK_CMD = 0x00000800;
3091                 odm_write_4byte(dm, 0x1b34, IQK_CMD + 1);
3092                 odm_write_4byte(dm, 0x1b34, IQK_CMD);
3093                 ODM_delay_ms(1);
3094                 odm_write_4byte(dm, 0x1bd4, 0x00040001);
3095                 tx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc);
3096                 odm_write_4byte(dm, 0x1bd4, 0x000C0001);
3097                 tx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc);
3098         }
3099         /*restore*/
3100         odm_write_4byte(dm, 0x1b0c, tmp1);
3101         odm_write_4byte(dm, 0x1b14, tmp2);
3102         odm_write_4byte(dm, 0x1b1c, tmp3);
3103         odm_write_4byte(dm, 0x1b20, tmp4);
3104         odm_write_4byte(dm, 0x1b24, tmp5);
3105
3106         if (tx_ini_power_H[1] == tx_ini_power_H[0])
3107                 tximr = (3 * (halrf_psd_log2base(tx_ini_power_L[0] << 2) - halrf_psd_log2base(tx_ini_power_L[1]))) / 100;
3108         else
3109                 tximr = 0;
3110         return tximr;
3111 }
3112
3113 u32 _iqk_rximr_selfcheck_8821c(void *dm_void, u8 tone_index, u8 path,
3114                                u32 tmp1b38)
3115 {
3116         u32 rx_ini_power_H[2], rx_ini_power_L[2]; /*[0]: psd tone; [1]: image tone*/
3117         u32 tmp1, tmp2, tmp3, tmp4, tmp5;
3118         u32 IQK_CMD, tmp1bcc;
3119         u8 i;
3120         u32 rximr = 0x0;
3121
3122         struct dm_struct *dm = (struct dm_struct *)dm_void;
3123
3124         /*backup*/
3125         odm_write_4byte(dm, 0x1b00, 0xf8000008 | path << 1);
3126         tmp1 = odm_read_4byte(dm, 0x1b0c);
3127         tmp2 = odm_read_4byte(dm, 0x1b14);
3128         tmp3 = odm_read_4byte(dm, 0x1b1c);
3129         tmp4 = odm_read_4byte(dm, 0x1b20);
3130         tmp5 = odm_read_4byte(dm, 0x1b24);
3131
3132         tmp1bcc = (odm_read_4byte(dm, 0x1be8) & 0x0000ff00) >> 8;
3133         odm_write_4byte(dm, 0x1b0c, 0x00001000);
3134         odm_write_1byte(dm, 0x1b15, 0x00);
3135         odm_write_4byte(dm, 0x1b1c, 0x82193d31);
3136         odm_write_4byte(dm, 0x1b20, (u32)(tone_index << 20 | 0x00040008));
3137         odm_write_4byte(dm, 0x1b24, (u32)(tone_index << 20 | 0x00060048));
3138         odm_write_4byte(dm, 0x1b2c, 0x07);
3139 #if 0
3140         //odm_write_4byte(dm, 0x1b38, iqk_info->rxk1_tmp1b38[path][(tone_index&0xff0)>>4]);
3141 #endif
3142         odm_write_4byte(dm, 0x1b38, tmp1b38);
3143
3144         odm_write_4byte(dm, 0x1b3c, 0x20000000);
3145         odm_write_4byte(dm, 0x1bcc, tmp1bcc);
3146         for (i = 0; i < 2; i++) {
3147                 if (i == 0)
3148                         odm_write_4byte(dm, 0x1b1c, 0x82193d31);
3149                 else
3150                         odm_write_4byte(dm, 0x1b1c, 0xA2193d31);
3151                 IQK_CMD = 0x00000800;
3152                 odm_write_4byte(dm, 0x1b34, IQK_CMD + 1);
3153                 odm_write_4byte(dm, 0x1b34, IQK_CMD);
3154                 ODM_delay_us(2000);
3155                 odm_write_1byte(dm, 0x1bd6, 0xb);
3156 #if 0
3157                 /*if ((boolean)odm_get_bb_reg(dm, R_0x1bfc, BIT(1))){*/
3158 #endif
3159                 if (1) {
3160                         odm_write_1byte(dm, 0x1bd6, 0x5);
3161                         rx_ini_power_H[i] = odm_read_4byte(dm, 0x1bfc);
3162                         odm_write_1byte(dm, 0x1bd6, 0xe);
3163                         rx_ini_power_L[i] = odm_read_4byte(dm, 0x1bfc);
3164                 } else {
3165                         rx_ini_power_H[i] = 0x0;
3166                         rx_ini_power_L[i] = 0x0;
3167                 }
3168         }
3169         /*restore*/
3170         odm_write_4byte(dm, 0x1b0c, tmp1);
3171         odm_write_4byte(dm, 0x1b14, tmp2);
3172         odm_write_4byte(dm, 0x1b1c, tmp3);
3173         odm_write_4byte(dm, 0x1b20, tmp4);
3174         odm_write_4byte(dm, 0x1b24, tmp5);
3175
3176         for (i = 0; i < 2; i++)
3177                 rx_ini_power_H[i] = (rx_ini_power_H[i] & 0xf8000000) >> 27;
3178
3179         if (rx_ini_power_H[0] != rx_ini_power_H[1])
3180                 switch (rx_ini_power_H[0]) {
3181                 case 1:
3182                         rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 1) | 0x80000000);
3183                         rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 1;
3184                         break;
3185                 case 2:
3186                         rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 2) | 0x80000000);
3187                         rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 2;
3188                         break;
3189                 case 3:
3190                         rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 2) | 0xc0000000);
3191                         rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 2;
3192                         break;
3193                 case 4:
3194                         rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0x80000000);
3195                         rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
3196                         break;
3197                 case 5:
3198                         rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xa0000000);
3199                         rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
3200                         break;
3201                 case 6:
3202                         rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xc0000000);
3203                         rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
3204                         break;
3205                 case 7:
3206                         rx_ini_power_L[0] = (u32)((rx_ini_power_L[0] >> 3) | 0xe0000000);
3207                         rx_ini_power_L[1] = (u32)rx_ini_power_L[1] >> 3;
3208                         break;
3209                 default:
3210                         break;
3211                 }
3212         rximr = (u32)(3 * ((halrf_psd_log2base(rx_ini_power_L[0] / 100) - halrf_psd_log2base(rx_ini_power_L[1] / 100))) / 100);
3213 #if 0
3214         /*
3215                 RF_DBG(dm, DBG_RF_IQK, "%-20s: 0x%x, 0x%x, 0x%x, 0x%x,0x%x, tone_index=%x, rximr= %d\n",
3216                 (path == 0) ? "PATH A RXIMR ": "PATH B RXIMR",
3217                 rx_ini_power_H[0], rx_ini_power_L[0], rx_ini_power_H[1], rx_ini_power_L[1], tmp1bcc, tone_index, rximr);
3218 */
3219 #endif
3220         return rximr;
3221 }
3222
3223 void _iqk_start_imr_test_8821c(void *dm_void, u8 path)
3224 {
3225         u8 imr_limit, i, tone_index;
3226         u32 tmp;
3227         boolean KFAIL;
3228         u32 rxk1_tmp1b38[2][15];
3229         u32 imr_result[2];
3230
3231         struct dm_struct *dm = (struct dm_struct *)dm_void;
3232
3233         /*TX IMR*/
3234         if (*dm->band_width == 2)
3235                 imr_limit = 0xe;
3236         else if (*dm->band_width == 1)
3237                 imr_limit = 0x7;
3238         else
3239                 imr_limit = 0x3;
3240
3241         _iqk_txk_setting_8821c(dm, RF_PATH_A);
3242         KFAIL = _iqk_one_shot_8821c(dm, RF_PATH_A, TXIQK);
3243         for (i = 0x0; i <= imr_limit; i++) {
3244                 tone_index = (u8)(0x08 | i << 4);
3245                 imr_result[RF_PATH_A] = _iqk_tximr_selfcheck_8821c(dm, tone_index, RF_PATH_A);
3246                 RF_DBG(dm, DBG_RF_IQK, "[IQK]toneindex = %x, TXIMR = %d\n",
3247                        tone_index, imr_result[RF_PATH_A]);
3248         }
3249         RF_DBG(dm, DBG_RF_IQK, "\n");
3250         /*RX IMR*/
3251         /*get the rxk1 tone index 0x1b38 setting*/
3252         _iqk_rxk1setting_8821c(dm, path);
3253         tmp = odm_read_4byte(dm, 0x1b1c);
3254         for (path = 0; path < SS_8821C; path++) {
3255                 for (i = 0; i <= imr_limit; i++) {
3256                         tone_index = (u8)(0x08 | i << 4);
3257                         KFAIL = _iqk_rx_iqk_gain_search_fail_by_toneindex_8821c(dm, path, RXIQK1, tone_index);
3258                         if (!KFAIL) {
3259                                 odm_write_4byte(dm, 0x1b1c, 0xa2193c32);
3260                                 odm_write_4byte(dm, 0x1b14, 0xe5);
3261                                 odm_write_4byte(dm, 0x1b14, 0x0);
3262                                 rxk1_tmp1b38[path][i] = odm_read_4byte(dm, 0x1b38);
3263                         } else {
3264                                 rxk1_tmp1b38[path][i] = 0x0;
3265                         }
3266                 }
3267         }
3268         _iqk_rxk2setting_8821c(dm, path, true);
3269         for (path = 0; path < SS_8821C; path++) {
3270                 for (i = 0x0; i <= imr_limit; i++) {
3271                         tone_index = (u8)(0x08 | i << 4);
3272                         imr_result[RF_PATH_A] = _iqk_rximr_selfcheck_8821c(dm, tone_index, RF_PATH_A, rxk1_tmp1b38[path][i]);
3273                         RF_DBG(dm, DBG_RF_IQK,
3274                                "[IQK]toneindex = %x, RXIMR = %d\n", tone_index,
3275                                imr_result[RF_PATH_A]);
3276                 }
3277         }
3278         odm_write_4byte(dm, 0x1b1c, tmp);
3279         odm_write_4byte(dm, 0x1b38, 0x20000000);
3280 }
3281
3282 void _phy_iq_calibrate_8821c(struct dm_struct *dm, boolean reset,
3283                              boolean segment_iqk, boolean do_imr_test)
3284 {
3285         u32 MAC_backup[MAC_REG_NUM_8821C], BB_backup[BB_REG_NUM_8821C];
3286         u32 RF_backup[RF_REG_NUM_8821C][1];
3287         u32 backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518};
3288         u32 backup_bb_reg[BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0,
3289                                                 0xcb4, 0xcbc, 0x1990,
3290                                                 0x9a4, 0xa04, 0x838};
3291         u32 backup_rf_reg[RF_REG_NUM_8821C] = {0xdf, 0xde, 0x8f, 0x0, 0x1};
3292         boolean is_mp = false;
3293
3294         struct dm_iqk_info *iqk_info = &dm->IQK_info;
3295
3296         if (*dm->mp_mode)
3297                 is_mp = true;
3298         else if (dm->is_linked)
3299                 segment_iqk = false;
3300         iqk_info->is_btg = (boolean)odm_get_bb_reg(dm, R_0xcb8, BIT(16));
3301
3302         if (!is_mp)
3303                 if (_iqk_reload_iqk_8821c(dm, reset))
3304                         return;
3305         if (!do_imr_test)
3306                 RF_DBG(dm, DBG_RF_IQK,
3307                        "[IQK]==========IQK strat!!!!!==========\n");
3308         RF_DBG(dm, DBG_RF_IQK,
3309                "[IQK]band_type = %s, band_width = %d, ExtPA2G = %d, ext_pa_5g = %d\n",
3310                (*dm->band_type == ODM_BAND_5G) ? "5G" : "2G", *dm->band_width,
3311                dm->ext_pa, dm->ext_pa_5g);
3312         RF_DBG(dm, DBG_RF_IQK, "[IQK]Interface = %d, cut_version = %x\n",
3313                dm->support_interface, dm->cut_version);
3314
3315         iqk_info->tmp_gntwl = _iqk_indirect_read_reg(dm, 0x38);
3316         iqk_info->iqk_times++;
3317         iqk_info->kcount = 0;
3318         dm->rf_calibrate_info.iqk_total_progressing_time = 0;
3319         dm->rf_calibrate_info.iqk_step = 1;
3320         iqk_info->rxiqk_step = 1;
3321         iqk_info->is_reload = false;
3322
3323         _iqk_backup_iqk_8821c(dm, 0x0, 0x0);
3324         _iqk_backup_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C);
3325         _iqk_backup_rf_8821c(dm, RF_backup, backup_rf_reg);
3326
3327         while (1) {
3328                 if (!is_mp)
3329                         dm->rf_calibrate_info.iqk_start_time = odm_get_current_time(dm);
3330
3331                 _iqk_configure_macbb_8821c(dm);
3332                 _iqk_afe_setting_8821c(dm, true);
3333                 _iqk_rfe_setting_8821c(dm, false);
3334                 _iqk_agc_bnd_int_8821c(dm);
3335                 _iqk_rfsetting_8821c(dm);
3336                 if (do_imr_test) {
3337                         _iqk_start_imr_test_8821c(dm, 0x0);
3338                         dm->rf_calibrate_info.iqk_step = 4;
3339                 } else {
3340                         _iqk_start_iqk_8821c(dm, segment_iqk);
3341                 }
3342                 _iqk_afe_setting_8821c(dm, false);
3343                 _iqk_restore_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C);
3344                 _iqk_restore_rf_8821c(dm, backup_rf_reg, RF_backup);
3345
3346                 if (!is_mp) {
3347                         dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);
3348                         dm->rf_calibrate_info.iqk_total_progressing_time += odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);
3349                         RF_DBG(dm, DBG_RF_IQK,
3350                                "[IQK]IQK progressing_time = %lld ms\n",
3351                                dm->rf_calibrate_info.iqk_progressing_time);
3352                 }
3353
3354                 if (dm->rf_calibrate_info.iqk_step == 4)
3355                         break;
3356
3357                 iqk_info->kcount = 0;
3358                 RF_DBG(dm, DBG_RF_IQK, "[IQK]delay 50ms!!!\n");
3359 #if 0
3360                 /*ODM_sleep_ms(50);*/
3361 #endif
3362                 ODM_delay_ms(50);
3363         }
3364
3365         if (!do_imr_test) {
3366                 if (segment_iqk)
3367                         _iqk_reload_iqk_setting_8821c(dm, 0x0, 0x1);
3368                 _iqk_fill_iqk_report_8821c(dm, 0);
3369                 if (!is_mp)
3370                         RF_DBG(dm, DBG_RF_IQK,
3371                                "[IQK]Total IQK progressing_time = %lld ms\n",
3372                                dm->rf_calibrate_info.iqk_total_progressing_time)
3373                                ;
3374                 RF_DBG(dm, DBG_RF_IQK,
3375                        "[IQK]==========IQK end!!!!!==========\n");
3376                 RF_DBG(dm, DBG_RF_IQK, "[IQK]check 0x49c = %x\n",
3377                        odm_read_1byte(dm, 0x49c));
3378         }
3379 }
3380
3381 void _phy_iq_calibrate_by_fw_8821c(void *dm_void, u8 clear, u8 segment_iqk)
3382 {
3383         struct dm_struct *dm = (struct dm_struct *)dm_void;
3384         enum hal_status status = HAL_STATUS_FAILURE;
3385
3386         if (*dm->mp_mode)
3387                 clear = 0x1;
3388         else if (dm->is_linked)
3389                 segment_iqk = 0x1;
3390
3391         status = odm_iq_calibrate_by_fw(dm, clear, segment_iqk);
3392
3393         if (status == HAL_STATUS_SUCCESS)
3394                 RF_DBG(dm, DBG_RF_IQK, "[IQK]FWIQK  OK!!!\n");
3395         else
3396                 RF_DBG(dm, DBG_RF_IQK, "[IQK]FWIQK fail!!!\n");
3397 }
3398
3399 /*********debug message start**************/
3400
3401 void _phy_iqk_XYM_Read_Using_0x1b38_8821c(struct dm_struct *dm, u8 path)
3402 {
3403         u32 tmp = 0x0;
3404         u32 tmp2;
3405         u8 i;
3406
3407         tmp = odm_read_4byte(dm, 0x1b1c);
3408         odm_write_4byte(dm, 0x1b1c, 0xA2193C32);
3409         RF_DBG(dm, DBG_RF_IQK, "\n");
3410         for (i = 0; i < 0xa; i++) {
3411                 odm_write_4byte(dm, 0x1b14, 0xe6 + i);
3412                 odm_write_4byte(dm, 0x1b14, 0x0);
3413                 tmp2 = odm_read_4byte(dm, 0x1b38);
3414                 RF_DBG(dm, DBG_RF_IQK, "%x\n", tmp2);
3415         }
3416         odm_write_4byte(dm, 0x1b1c, tmp);
3417         RF_DBG(dm, DBG_RF_IQK, "\n");
3418         odm_write_4byte(dm, 0x1b38, 0x20000000);
3419 }
3420
3421 void _phy_iqk_debug_inner_lpbk_psd_8821c(struct dm_struct *dm, u8 path)
3422 {
3423         s16 tx_x;
3424         s16 tx_y;
3425         u32 temp = 0x0;
3426         u32 psd_pwr = 0x0;
3427         u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9, tmp10;
3428
3429         tmp1 = odm_read_4byte(dm, 0x1b20);
3430         tmp2 = odm_read_4byte(dm, 0x1b24);
3431         tmp3 = odm_read_4byte(dm, 0x1b15);
3432         tmp4 = odm_read_4byte(dm, 0x1b18);
3433         tmp5 = odm_read_4byte(dm, 0x1b1c);
3434         tmp6 = odm_read_4byte(dm, 0x1b28);
3435         tmp7 = odm_read_4byte(dm, 0x1b90);
3436         tmp8 = odm_read_4byte(dm, 0x1bcc);
3437         tmp9 = odm_read_4byte(dm, 0x1b2c);
3438         tmp10 = odm_read_4byte(dm, 0x1b30);
3439         odm_write_4byte(dm, 0x1b20, 0x03840008);
3440         odm_write_4byte(dm, 0x1b24, 0x03860008);
3441         odm_write_1byte(dm, 0x1b15, 0x00);
3442         odm_write_4byte(dm, 0x1b18, 0x00010101);
3443         odm_write_4byte(dm, 0x1b1c, 0x02effcb2);
3444         odm_write_4byte(dm, 0x1b28, 0x00060c00);
3445         odm_write_4byte(dm, 0x1b90, 0x00080003);
3446         odm_write_4byte(dm, 0x1bcc, 0x00000009);
3447         odm_write_4byte(dm, 0x1b2c, 0x20000003);
3448         odm_write_4byte(dm, 0x1b30, 0x20000000);
3449         RF_DBG(dm, DBG_RF_IQK, "\n");
3450         for (tx_x = 507; tx_x <= 532; tx_x++) {
3451                 for (tx_y = 0; tx_y <= 10 + 20; tx_y++) {
3452                         if (tx_y < 0)
3453                                 temp = (tx_x << 20) | (tx_y + 2048) << 8;
3454                         else
3455                                 temp = (tx_x << 20) | (tx_y << 8);
3456                         odm_write_4byte(dm, 0x1b38, temp);
3457                         odm_write_4byte(dm, 0x1b3c, 0x20000000);
3458                         odm_write_4byte(dm, 0x1b34, 0x00000801);
3459                         odm_write_4byte(dm, 0x1b34, 0x00000800);
3460                         ODM_delay_ms(2);
3461                         /*PSD_bef_K*/
3462                         odm_write_4byte(dm, 0x1bd4, 0x000c0001);
3463                         psd_pwr = odm_read_4byte(dm, 0x1bfc);
3464                         RF_DBG(dm, DBG_RF_IQK, "%d ", psd_pwr);
3465                 }
3466         }
3467         RF_DBG(dm, DBG_RF_IQK, "\n");
3468         odm_write_4byte(dm, 0x1b20, tmp1);
3469         odm_write_4byte(dm, 0x1b24, tmp2);
3470         odm_write_4byte(dm, 0x1b15, tmp3);
3471         odm_write_4byte(dm, 0x1b18, tmp4);
3472         odm_write_4byte(dm, 0x1b1c, tmp5);
3473         odm_write_4byte(dm, 0x1b28, tmp6);
3474         odm_write_4byte(dm, 0x1b90, tmp7);
3475         odm_write_4byte(dm, 0x1bcc, tmp8);
3476         odm_write_4byte(dm, 0x1b2c, tmp9);
3477         odm_write_4byte(dm, 0x1b30, tmp10);
3478         odm_write_4byte(dm, 0x1b38, 0x20000000);
3479 }
3480
3481 void _iqk_readsram_8821c(struct dm_struct *dm, u8 path)
3482 {
3483         u32 tmp1bd4, tmp1bd8, tmp;
3484         u8 i;
3485
3486         tmp1bd4 = odm_read_4byte(dm, 0x1bd4);
3487         tmp1bd8 = odm_read_4byte(dm, 0x1bd8);
3488         odm_write_4byte(dm, 0x1bd4, 0x00010001);
3489         for (i = 0; i < 0x80; i++) {
3490                 odm_write_4byte(dm, 0x1bd8, 0xa0000101 + (u32)(i << 1));
3491                 tmp = (u32)odm_read_4byte(dm, 0x1bfc) & 0x3ff;
3492                 if (i < 0x40)
3493                         RF_DBG(dm, DBG_RF_IQK, "adc_i[%d] = %x\n", i, tmp);
3494                 else
3495                         RF_DBG(dm, DBG_RF_IQK, "adc_q[%d] = %x\n", i, tmp);
3496         }
3497 }
3498
3499 void do_imr_test_8821c(void *dm_void)
3500 {
3501         struct dm_struct *dm = (struct dm_struct *)dm_void;
3502
3503         RF_DBG(dm, DBG_RF_IQK,
3504                "[IQK]  ************IMR Test *****************\n");
3505         _phy_iq_calibrate_8821c(dm, false, false, true);
3506         RF_DBG(dm, DBG_RF_IQK,
3507                "[IQK]  **********End IMR Test *******************\n");
3508 }
3509
3510 /*********debug message end***************/
3511
3512 /*IQK version:0x23, NCTL:0x8*/
3513 /*1. modify the iqk counters for coex.*/
3514
3515 void phy_iq_calibrate_8821c(void *dm_void, boolean clear, boolean segment_iqk)
3516 {
3517         struct dm_struct *dm = (struct dm_struct *)dm_void;
3518         struct _hal_rf_ *rf = &dm->rf_table;
3519
3520         if (!(*dm->mp_mode))
3521                 _iqk_check_coex_status(dm, true);
3522
3523         RF_DBG(dm, DBG_RF_IQK, "[IQK]fw_ver= 0x%x\n", rf->fw_ver);
3524         if (*dm->mp_mode)
3525                 halrf_iqk_hwtx_check(dm, true);
3526         /*FW IQK*/
3527         if (dm->fw_offload_ability & PHYDM_RF_IQK_OFFLOAD) {
3528                 _phy_iq_calibrate_by_fw_8821c(dm, clear, segment_iqk);
3529                 phydm_get_read_counter_8821c(dm);
3530                 RF_DBG(dm, DBG_RF_IQK, "[IQK]0x38= 0x%x\n",
3531                        _iqk_indirect_read_reg(dm, 0x38));
3532         } else {
3533                 _iq_calibrate_8821c_init(dm);
3534                 _phy_iq_calibrate_8821c(dm, clear, segment_iqk, false);
3535         }
3536         _iqk_fail_count_8821c(dm);
3537
3538         if (*dm->mp_mode)
3539                 halrf_iqk_hwtx_check(dm, false);
3540 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
3541         _iqk_iqk_fail_report_8821c(dm);
3542 #endif
3543         halrf_iqk_dbg(dm);
3544
3545         if (!(*dm->mp_mode))
3546                 _iqk_check_coex_status(dm, false);
3547         RF_DBG(dm, DBG_RF_IQK, "[IQK]final 0x49c = %x\n",
3548                odm_read_1byte(dm, 0x49c));
3549 }
3550
3551 void phy_dp_calibrate_8821c(void *dm_void, boolean clear)
3552 {
3553         struct dm_struct *dm = (struct dm_struct *)dm_void;
3554         struct _hal_rf_ *rf = &dm->rf_table;
3555
3556 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
3557         if (odm_check_power_status(dm) == false)
3558                 return;
3559 #endif
3560
3561 #if (MP_DRIVER)
3562         if ((dm->mp_mode != NULL) && (rf->is_con_tx != NULL) && (rf->is_single_tone != NULL) && (rf->is_carrier_suppresion != NULL))
3563                 if (*(dm->mp_mode) && ((*(rf->is_con_tx) || *(rf->is_single_tone) || *(rf->is_carrier_suppresion))))
3564                         return;
3565 #endif
3566
3567 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3568         if (!(rf->rf_supportability & HAL_RF_DPK))
3569                 return;
3570 #endif
3571
3572 #if DISABLE_BB_RF
3573         return;
3574 #endif
3575
3576         RF_DBG(dm, DBG_RF_IQK, "[DPK] In PHY, dm->dpk_en == %x\n", rf->dpk_en);
3577
3578         /*if dpk is not enable*/
3579         if (rf->dpk_en == 0x0)
3580                 return;
3581
3582         /*start*/
3583         if (!dm->rf_calibrate_info.is_iqk_in_progress) {
3584                 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
3585                 dm->rf_calibrate_info.is_iqk_in_progress = true;
3586                 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
3587                 if (*dm->mp_mode)
3588                         dm->rf_calibrate_info.iqk_start_time = odm_get_current_time(dm);
3589
3590                 if (*dm->mp_mode) {
3591                         /*do DPK*/
3592                         _phy_dpd_calibrate_8821c(dm, clear);
3593                         _dpk_toggle_rxagc(dm, clear);
3594                 }
3595
3596                 if (*dm->mp_mode) {
3597                         dm->rf_calibrate_info.iqk_progressing_time = odm_get_progressing_time(dm, dm->rf_calibrate_info.iqk_start_time);
3598                         RF_DBG(dm, DBG_RF_IQK,
3599                                "[DPK]DPK progressing_time = %lld ms\n",
3600                                dm->rf_calibrate_info.iqk_progressing_time);
3601                 }
3602                 odm_acquire_spin_lock(dm, RT_IQK_SPINLOCK);
3603                 dm->rf_calibrate_info.is_iqk_in_progress = false;
3604                 odm_release_spin_lock(dm, RT_IQK_SPINLOCK);
3605         } else {
3606                 RF_DBG(dm, DBG_RF_IQK,
3607                        "[DPK]== Return the DPK CMD, because the DPK in Progress ==\n");
3608         }
3609 }
3610 void phy_txtap_calibrate_8821c(void *dm_void, boolean clear)
3611 {
3612         u32 MAC_backup[MAC_REG_NUM_8821C], BB_backup[BB_REG_NUM_8821C], RF_backup[RF_REG_NUM_8821C][1];
3613         u32 backup_mac_reg[MAC_REG_NUM_8821C] = {0x520, 0x550, 0x1518};
3614         u32 backup_bb_reg[BB_REG_NUM_8821C] = {0x808, 0x90c, 0xc00, 0xcb0, 0xcb4, 0xcbc, 0x1990, 0x9a4, 0xa04};
3615         u32 backup_rf_reg[RF_REG_NUM_8821C] = {0xdf, 0xde, 0x8f, 0x0, 0x1};
3616
3617         struct dm_struct *dm = (struct dm_struct *)dm_void;
3618         struct dm_iqk_info *iqk_info = &dm->IQK_info;
3619
3620 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3621         struct _ADAPTER *adapter = dm->adapter;
3622
3623 #if (MP_DRIVER == 1)
3624 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3625         PMPT_CONTEXT p_mpt_ctx = &(adapter->MptCtx);
3626 #else
3627 #ifdef CONFIG_MP_INCLUDED
3628         PMPT_CONTEXT p_mpt_ctx = &(adapter->mppriv.mpt_ctx);
3629 #endif
3630 #endif
3631 #endif
3632
3633         struct _hal_rf_ *rf = &dm->rf_table;
3634
3635 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3636         if (!(rf->rf_supportability & HAL_RF_IQK))
3637                 return;
3638 #endif
3639
3640 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
3641         if (odm_check_power_status(adapter) == false)
3642                 return;
3643 #endif
3644
3645 #if MP_DRIVER == 1
3646 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3647         if (p_mpt_ctx->bSingleTone || p_mpt_ctx->bCarrierSuppression)
3648                 return;
3649 #else
3650 #ifdef CONFIG_MP_INCLUDED
3651         if (p_mpt_ctx->is_single_tone || p_mpt_ctx->is_carrier_suppression)
3652                 return;
3653 #endif
3654 #endif
3655 #endif
3656 #endif
3657
3658         if (!(*dm->mp_mode))
3659                 _iqk_check_coex_status(dm, true);
3660
3661         if ((dm->rf_table.rf_supportability & HAL_RF_TXGAPK))
3662                 if (iqk_info->lok_fail[RF_PATH_A] == 0 &&
3663                     iqk_info->iqk_fail_report[0][RF_PATH_A][TXIQK] == 0 &&
3664                     iqk_info->iqk_fail_report[0][RF_PATH_A][RXIQK] == 0) {
3665                         _iqk_backup_iqk_8821c(dm, 0x0, 0x0);
3666                         _iqk_backup_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C);
3667                         _iqk_backup_rf_8821c(dm, RF_backup, backup_rf_reg);
3668
3669                         _iqk_configure_macbb_8821c(dm);
3670                         _iqk_afe_setting_8821c(dm, true);
3671                         _iqk_rfe_setting_8821c(dm, false);
3672                         _iqk_agc_bnd_int_8821c(dm);
3673                         _iqk_rfsetting_8821c(dm);
3674
3675                         _phy_txgapk_calibrate_8821c(dm, RF_PATH_A);
3676
3677                         _iqk_afe_setting_8821c(dm, false);
3678                         _iqk_restore_mac_bb_8821c(dm, MAC_backup, BB_backup, backup_mac_reg, backup_bb_reg, BB_REG_NUM_8821C);
3679                         _iqk_restore_rf_8821c(dm, backup_rf_reg, RF_backup);
3680                 }
3681 }
3682 void dpk_temperature_compensate_8821c(void *dm_void)
3683 {
3684         struct dm_struct *dm = (struct dm_struct *)dm_void;
3685         struct _hal_rf_ *rf = &dm->rf_table;
3686 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)
3687         void *adapter = dm->adapter;
3688         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3689         u8 pgthermal = hal_data->eeprom_thermal_meter;
3690 #else
3691         struct rtl8192cd_priv *priv = dm->priv;
3692         u8 pgthermal = (u8)priv->pmib->dot11RFEntry.ther;
3693
3694 #endif
3695         static u8 dpk_tm_trigger;
3696         u8 thermal_value = 0, delta_dpk, i = 0;
3697         u8 thermal_value_avg_count = 0;
3698         u8 thermal_value_avg_times = 2;
3699         u32 thermal_value_avg = 0;
3700         u8 tmp, abs_temperature;
3701
3702         /*if dpk is not enable*/
3703         if (rf->dpk_en == 0x0)
3704                 return;
3705         /*if ap mode, disable dpk*/
3706         if (DM_ODM_SUPPORT_TYPE & ODM_AP)
3707                 return;
3708         if (!dpk_tm_trigger) {
3709                 odm_set_rf_reg(dm, RF_PATH_A, RF_0x42, BIT(17) | BIT(16), 0x03);
3710 #if 0
3711                 /*RF_DBG(dm, DBG_RF_IQK, "[DPK] (1) Trigger Thermal Meter!!\n");*/
3712 #endif
3713                 dpk_tm_trigger = 1;
3714                 return;
3715         }
3716
3717         /* Initialize */
3718         dpk_tm_trigger = 0;
3719 #if 0
3720         /*RF_DBG(dm, DBG_RF_IQK, "[DPK] (2) calculate the thermal !!\n");
3721         */
3722 #endif
3723
3724         /* calculate average thermal meter */
3725         thermal_value = (u8)odm_get_rf_reg(dm, RF_PATH_A, RF_0x42, 0xfc00); /*0x42: RF Reg[15:10] 88E*/
3726         RF_DBG(dm, DBG_RF_IQK, "[DPK] (3) current Thermal Meter = %d\n",
3727                thermal_value);
3728
3729         dm->rf_calibrate_info.thermal_value_dpk = thermal_value;
3730         dm->rf_calibrate_info.thermal_value_avg[dm->rf_calibrate_info.thermal_value_avg_index] = thermal_value;
3731         dm->rf_calibrate_info.thermal_value_avg_index++;
3732         if (dm->rf_calibrate_info.thermal_value_avg_index == thermal_value_avg_times)
3733                 dm->rf_calibrate_info.thermal_value_avg_index = 0;
3734         for (i = 0; i < thermal_value_avg_times; i++) {
3735                 if (dm->rf_calibrate_info.thermal_value_avg[i]) {
3736                         thermal_value_avg += dm->rf_calibrate_info.thermal_value_avg[i];
3737                         thermal_value_avg_count++;
3738                 }
3739         }
3740         if (thermal_value_avg_count) /*Calculate Average thermal_value after average enough times*/
3741                 thermal_value = (u8)(thermal_value_avg / thermal_value_avg_count);
3742         /* compensate the DPK */
3743         delta_dpk = (thermal_value > pgthermal) ? (thermal_value - pgthermal) : (pgthermal - thermal_value);
3744         tmp = (u8)((dpk_result[0] & 0x00001f00) >> 8);
3745         RF_DBG(dm, DBG_RF_IQK,
3746                "[DPK] (5)delta_dpk = %d, eeprom_thermal_meter = %d, tmp=%d\n",
3747                delta_dpk, pgthermal, tmp);
3748
3749         if (thermal_value > pgthermal) {
3750                 abs_temperature = thermal_value - pgthermal;
3751                 if (abs_temperature >= 20)
3752                         tmp = tmp + 4;
3753                 else if (abs_temperature >= 15)
3754                         tmp = tmp + 3;
3755                 else if (abs_temperature >= 10)
3756                         tmp = tmp + 2;
3757                 else if (abs_temperature >= 5)
3758                         tmp = tmp + 1;
3759         } else { /*low temperature*/
3760                 abs_temperature = pgthermal - thermal_value;
3761                 if (abs_temperature >= 20)
3762                         tmp = tmp - 4;
3763                 else if (abs_temperature >= 15)
3764                         tmp = tmp - 3;
3765                 else if (abs_temperature >= 10)
3766                         tmp = tmp - 2;
3767                 else if (abs_temperature >= 5)
3768                         tmp = tmp - 1;
3769         }
3770
3771         odm_set_bb_reg(dm, R_0x1bd0, BIT(12) | BIT(11) | BIT(10) | BIT(9) | BIT(8), tmp);
3772         RF_DBG(dm, DBG_RF_IQK,
3773                "[DPK] (6)delta_dpk = %d, eeprom_thermal_meter = %d, new tmp=%d, 0x1bd0=0x%x\n",
3774                delta_dpk, pgthermal, tmp, odm_read_4byte(dm, 0x1bd0));
3775 }
3776
3777 #endif