rtl8821ce/hal/phydm/phydm_adc_sampling.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2017  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "mp_precomp.h"
  27 #include "phydm_precomp.h"
  28
  29 #if (PHYDM_LA_MODE_SUPPORT)
  30
  31 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
  32 #if (RTL8197F_SUPPORT || RTL8822B_SUPPORT || RTL8192F_SUPPORT)
  33 #include "rtl8197f/Hal8197FPhyReg.h"
  34 #include "WlanHAL/HalMac88XX/halmac_reg2.h"
  35 #else
  36 #include "WlanHAL/HalHeader/HalComReg.h"
  37 #endif
  38 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
  39 #if WPP_SOFTWARE_TRACE
  40 #include "phydm_adc_sampling.tmh"
  41 #endif
  42 #endif
  43
  44 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
  45 boolean
  46 phydm_la_buffer_allocate(void *dm_void)
  47 {
  48         struct dm_struct *dm = (struct dm_struct *)dm_void;
  49         struct rt_adcsmp *smp = &dm->adcsmp;
  50         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
  51         void *adapter = dm->adapter;
  52         #endif
  53         struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
  54         boolean ret = true;
  55
  56         pr_debug("[LA mode BufferAllocate]\n");
  57
  58         if (buf->length == 0) {
  59         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
  60                 if (PlatformAllocateMemoryWithZero(adapter, (void **)&
  61                                                    buf->octet,
  62                                                    buf->buffer_size) !=
  63                                                    RT_STATUS_SUCCESS)
  64                         ret = false;
  65         #else
  66                 odm_allocate_memory(dm, (void **)&buf->octet, buf->buffer_size);
  67
  68                 if (!buf->octet)
  69                         ret = false;
  70         #endif
  71
  72                 if (ret)
  73                         buf->length = buf->buffer_size;
  74         }
  75
  76         return ret;
  77 }
  78 #endif
  79
  80 void phydm_la_get_tx_pkt_buf(void *dm_void)
  81 {
  82         struct dm_struct *dm = (struct dm_struct *)dm_void;
  83         struct rt_adcsmp *smp = &dm->adcsmp;
  84         struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
  85         u32 i = 0, value32 = 0, data_l = 0, data_h = 0;
  86         u32 addr = 0, finish_addr = 0;
  87         boolean is_round_up = false;
  88         static u32 page = 0xFF;
  89         u32 smp_cnt = 0, smp_number = 10, addr_8byte = 0;
  90         #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
  91         #if (RTL8197F_SUPPORT || RTL8198F_SUPPORT)
  92         u8 backup_dma = 0;
  93         #endif
  94         #endif
  95
  96         odm_memory_set(dm, buf->octet, 0, buf->length);
  97         pr_debug("GetTxPktBuf\n");
  98
  99         if (dm->support_ic_type & ODM_RTL8192F) {
 100                 value32 = odm_read_4byte(dm, 0x7F0);
 101                 is_round_up = (boolean)((value32 & BIT(31)) >> 31);
 102                 /*Reg7F0[30:15]: finish addr (unit: 8byte)*/
 103                 finish_addr = (value32 & 0x7FFF8000) >> 15;
 104         } else {
 105                 odm_write_1byte(dm, 0x0106, 0x69);
 106                 value32 = odm_read_4byte(dm, 0x7C0);
 107                 is_round_up = (boolean)((value32 & BIT(31)) >> 31);
 108                 /*Reg7C0[30:16]: finish addr (unit: 8byte)*/
 109                 if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C |
 110                     ODM_RTL8821C | ODM_RTL8814A | ODM_RTL8814B))
 111                         finish_addr = (value32 & 0x7FFF0000) >> 16;
 112                 /*Reg7C0[30:15]: finish addr (unit: 8byte)*/
 113                 else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8197F))
 114                         finish_addr = (value32 & 0x7FFF8000) >> 15;
 115         }
 116
 117         #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 118         #if (RTL8197F_SUPPORT || RTL8198F_SUPPORT)
 119         if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8198F)) {
 120                 pr_debug("98F GetTxPktBuf from iMEM\n");
 121                 odm_set_bb_reg(dm, R_0x7c0, BIT(0), 0x0);
 122
 123                 /*Stop DMA*/
 124                 backup_dma = odm_get_mac_reg(dm, R_0x300, MASKLWORD);
 125                 odm_set_mac_reg(dm, R_0x300, 0x7fff, 0x7fff);
 126
 127                 /*@move LA mode content from IMEM to TxPktBuffer
 128                         Source : OCPBASE_IMEM 0x00000000
 129                         Destination : OCPBASE_TXBUF 0x18780000
 130                         Length : 64K*/
 131                 GET_HAL_INTERFACE(dm->priv)->init_ddma_handler(dm->priv,
 132                                                                OCPBASE_IMEM,
 133                                                                OCPBASE_TXBUF,
 134                                                                0x10000);
 135         }
 136         #endif
 137         #endif
 138
 139         pr_debug("start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((%d))\n",
 140                  buf->start_pos, buf->end_pos, buf->buffer_size);
 141         if (is_round_up) {
 142                 pr_debug("buf_start(%d)|----2---->|finish_addr(%d)|----1---->|buf_end(%d)\n",
 143                          buf->start_pos, finish_addr << 3, buf->end_pos);
 144                 addr = (finish_addr + 1) << 3;
 145                 pr_debug("is_round_up = ((%d)), finish_addr=((0x%x)), 0x7c0/0x7F0=((0x%x))\n",
 146                          is_round_up, finish_addr, value32);
 147                 /*@Byte to 8Byte (64bit)*/
 148                 smp_number = (buf->buffer_size) >> 3;
 149         } else {
 150                 pr_debug("buf_start(%d)|------->|finish_addr(%d)             |buf_end(%d)\n",
 151                          buf->start_pos, finish_addr << 3, buf->end_pos);
 152                 addr = buf->start_pos;
 153                 addr_8byte = addr >> 3;
 154
 155                 if (addr_8byte > finish_addr)
 156                         smp_number = addr_8byte - finish_addr;
 157                 else
 158                         smp_number = finish_addr - addr_8byte;
 159
 160                 pr_debug("is_round_up = ((%d)), finish_addr=((0x%x * 8Byte)), Start_Addr = ((0x%x * 8Byte)), smp_number = ((%d))\n",
 161                          is_round_up, finish_addr, addr_8byte, smp_number);
 162         }
 163         #if 0
 164         dbg_print("is_round_up = %d, finish_addr=0x%x, value32=0x%x\n",
 165                   is_round_up, finish_addr, value32);
 166         dbg_print(
 167                   "end_addr = %x, buf->start_pos = 0x%x, buf->buffer_size = 0x%x\n",
 168                   end_addr, buf->start_pos, buf->buffer_size);
 169         #endif
 170
 171         #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 172         #if (RTL8197F_SUPPORT || RTL8198F_SUPPORT)
 173         if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8198F)) {
 174                 for (addr = 0x0; addr < buf->end_pos; addr += 8) {/*@64K byte*/
 175                         if ((addr & 0xfff) == 0)
 176                                 odm_set_bb_reg(dm, R_0x0140, MASKLWORD, 0x780 +
 177                                                (addr >> 12));
 178                         data_l = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff),
 179                                                 MASKDWORD);
 180                         data_h = odm_get_bb_reg(dm, 0x8000 + (addr & 0xfff) +
 181                                                 4, MASKDWORD);
 182
 183                         pr_debug("%08x%08x\n", data_h, data_l);
 184                 }
 185         } else
 186         #endif
 187         #endif
 188         {
 189                 for (i = 0; smp_cnt < smp_number; smp_cnt++, i += 2) {
 190                         if (dm->support_ic_type & ODM_RTL8192F) {
 191                         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 192                                 indirect_access_sdram_8192f(dm->adapter,
 193                                                             TX_PACKET_BUFFER,
 194                                                             TRUE,
 195                                                             (u16)addr >> 3, 0,
 196                                                             &data_h, &data_l);
 197                         #else
 198                         odm_write_1byte(dm, R_0x0106, 0x69);
 199                         odm_set_bb_reg(dm, R_0x0140, MASKDWORD, addr >> 3);
 200                         data_l = odm_get_bb_reg(dm, R_0x0144, MASKDWORD);
 201                         data_h = odm_get_bb_reg(dm, R_0x0148, MASKDWORD);
 202                         odm_write_1byte(dm, R_0x0106, 0x0);
 203                         #endif
 204
 205                         } else {
 206                                 if (page != (addr >> 12)) {
 207                                         /* Reg140=0x780+(addr>>12),
 208                                          * addr=0x30~0x3F, total 16 pages
 209                                          */
 210                                         page = addr >> 12;
 211                                 }
 212                                 odm_set_bb_reg(dm, R_0x0140, MASKLWORD, 0x780 +
 213                                                page);
 214
 215                                 /*pDataL = 0x8000+(addr&0xfff);*/
 216                                 data_l = odm_get_bb_reg(dm, 0x8000 + (addr &
 217                                                         0xfff), MASKDWORD);
 218                                 data_h = odm_get_bb_reg(dm, 0x8000 + (addr &
 219                                                         0xfff) + 4, MASKDWORD);
 220                         }
 221                         #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 222                         buf->octet[i] = data_h;
 223                         buf->octet[i + 1] = data_l;
 224                         #endif
 225                         #if DBG /*WIN driver check build*/
 226                         pr_debug("%08x%08x\n", data_h, data_l);
 227                         #else   /*WIN driver free build*/
 228                         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 229                         RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
 230                                     ("%08x%08x\n", buf->octet[i],
 231                                     buf->octet[i + 1]));
 232                         #endif
 233                         #endif
 234                         if ((addr + 8) > buf->end_pos)
 235                                 addr = buf->start_pos;
 236                         else
 237                                 addr = addr + 8;
 238                 }
 239                 pr_debug("smp_cnt = ((%d))\n", smp_cnt);
 240
 241                 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 242                 RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
 243                             ("smp_cnt = ((%d))\n", smp_cnt));
 244                 #endif
 245         }
 246         #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 247         #if (RTL8197F_SUPPORT)
 248         if (dm->support_ic_type & ODM_RTL8197F)
 249                 odm_set_mac_reg(dm, R_0x300, 0x7fff, backup_dma);/*Resume DMA*/
 250         #endif
 251         #endif
 252 }
 253
 254 void phydm_la_mode_set_mac_iq_dump(void *dm_void, boolean en_fake_trig)
 255 {
 256         struct dm_struct *dm = (struct dm_struct *)dm_void;
 257         struct rt_adcsmp *smp = &dm->adcsmp;
 258         u32 reg_value = 0;
 259         u32 reg1 = 0, reg2 = 0, reg3 = 0;
 260
 261         if (dm->support_ic_type & ODM_RTL8192F) {
 262                 reg1 = 0x7f0;
 263                 reg2 = 0x7f4;
 264                 reg3 = 0x7f8;
 265         } else {
 266                 reg1 = 0x7c0;
 267                 reg2 = 0x7c4;
 268                 reg3 = 0x7c8;
 269         }
 270
 271         odm_write_1byte(dm, reg1, 0); /*@clear all reg1*/
 272         /*@Enable LA mode HW block*/
 273         odm_set_mac_reg(dm, reg1, BIT(0), 1);
 274
 275         if (smp->la_trig_mode == PHYDM_MAC_TRIG) {
 276                 smp->is_bb_trigger = 0;
 277                 /*polling bit for MAC mode*/
 278                 odm_set_mac_reg(dm, reg1, BIT(2), 1);
 279                 /*trigger mode for MAC*/
 280                 odm_set_mac_reg(dm, reg1, BIT(4) | BIT(3),
 281                                 smp->la_trigger_edge);
 282                 pr_debug("[MAC_trig] ref_mask = ((0x%x)), ref_value = ((0x%x)), dbg_port = ((0x%x))\n",
 283                          smp->la_mac_mask_or_hdr_sel, smp->la_trig_sig_sel,
 284                          smp->la_dbg_port);
 285                 /*@[Set MAC Debug Port]*/
 286                 odm_set_mac_reg(dm, R_0xf4, BIT(16), 1);
 287                 odm_set_mac_reg(dm, R_0x38, 0xff0000, smp->la_dbg_port);
 288                 odm_set_mac_reg(dm, reg2, MASKDWORD,
 289                                 smp->la_mac_mask_or_hdr_sel);
 290                 odm_set_mac_reg(dm, reg3, MASKDWORD, smp->la_trig_sig_sel);
 291
 292         } else {
 293                 smp->is_bb_trigger = 1;
 294                 /*polling bit for BB ADC mode*/
 295                 odm_set_mac_reg(dm, reg1, BIT(1), 1);
 296
 297                 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
 298                         /*polling bit for MAC trigger event*/
 299                         if (!en_fake_trig)
 300                                 odm_set_mac_reg(dm, R_0x7c0, BIT(3), 1);
 301
 302                         odm_set_mac_reg(dm, reg1, BIT(7) | BIT(6),
 303                                         smp->la_trig_sig_sel);
 304                         if (smp->la_trig_sig_sel == ADCSMP_TRIG_REG)
 305                                 /* @manual trigger reg1[5] = 0->1*/
 306                                 odm_set_mac_reg(dm, reg1, BIT(5), 1);
 307                 }
 308         }
 309
 310         reg_value = odm_get_bb_reg(dm, reg1, 0xff);
 311         pr_debug("4. [Set MAC IQ dump] 0x%x[7:0] = ((0x%x))\n", reg1,
 312                  reg_value);
 313
 314         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 315         RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
 316                     ("4. [Set MAC IQ dump] 0x%x[7:0] = ((0x%x))\n", reg1,
 317                     reg_value));
 318         #endif
 319 }
 320
 321 void phydm_adc_smp_start(void *dm_void)
 322 {
 323         struct dm_struct *dm = (struct dm_struct *)dm_void;
 324         struct rt_adcsmp *smp = &dm->adcsmp;
 325         u8 tmp_u1b = 0;
 326         u8 while_cnt = 0;
 327         u8 target_polling_bit = 0;
 328         boolean polling_ok = false;
 329         boolean en_fake_trig = false;
 330
 331         if (smp->la_dma_type >= 0 && smp->la_dma_type <= 5)
 332                 en_fake_trig = true;
 333
 334         if (en_fake_trig) {
 335                 smp->is_fake_trig = true;
 336                 phydm_la_mode_bb_setting(dm, en_fake_trig);
 337         } else {
 338                 smp->is_fake_trig = false;
 339                 phydm_la_mode_bb_setting(dm, en_fake_trig);
 340         }
 341
 342         phydm_la_mode_set_trigger_time(dm, smp->la_trigger_time);
 343
 344         if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
 345                 odm_set_bb_reg(dm, R_0xd00, BIT(26), 0x1);
 346         else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C))
 347                 odm_set_bb_reg(dm, R_0x1eb4, BIT(23), 0x1);
 348         else    /*@for 8814A and 8822B?*/
 349                 odm_write_1byte(dm, 0x8b4, 0x80);
 350 #if 0
 351                 /* odm_set_bb_reg(dm, R_0x8b4, BIT(7), 1); */
 352 #endif
 353
 354         phydm_la_mode_set_mac_iq_dump(dm, en_fake_trig);
 355
 356         #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 357         watchdog_stop(dm->priv);
 358         #endif
 359
 360         if (en_fake_trig) {
 361                 ODM_delay_ms(100);
 362                 if (smp->la_trig_mode == PHYDM_ADC_BB_TRIG) {
 363                         smp->is_fake_trig = false;
 364                         phydm_la_mode_bb_setting(dm, en_fake_trig);
 365                 }
 366                 if (smp->la_trig_mode == PHYDM_ADC_MAC_TRIG) {
 367                         if (dm->support_ic_type & ODM_RTL8192F)
 368                                 odm_set_mac_reg(dm, 0x7f0, BIT(3), 1);
 369                         else
 370                                 odm_set_mac_reg(dm, 0x7c0, BIT(3), 1);
 371                 }
 372         }
 373
 374         target_polling_bit = (smp->is_bb_trigger) ? BIT(1) : BIT(2);
 375         do { /*Polling time always use 100ms, when it exceed 2s, break loop*/
 376                 if (dm->support_ic_type & ODM_RTL8192F) {
 377                         tmp_u1b = odm_read_1byte(dm, 0x7F0);
 378                         pr_debug("[%d], 0x7F0[7:0] = ((0x%x))\n", while_cnt,
 379                                  tmp_u1b);
 380                 } else {
 381                         tmp_u1b = odm_read_1byte(dm, 0x7C0);
 382                         pr_debug("[%d], 0x7C0[7:0] = ((0x%x))\n", while_cnt,
 383                                  tmp_u1b);
 384                 }
 385
 386                 if (smp->adc_smp_state != ADCSMP_STATE_SET) {
 387                         pr_debug("[state Error] adc_smp_state != ADCSMP_STATE_SET\n");
 388                         break;
 389
 390                 } else if (tmp_u1b & target_polling_bit) {
 391                         ODM_delay_ms(100);
 392                         while_cnt = while_cnt + 1;
 393                         continue;
 394                 } else {
 395                         pr_debug("[LA Query OK] polling_bit=((0x%x))\n",
 396                                  target_polling_bit);
 397                         polling_ok = true;
 398                         break;
 399                 }
 400         } while (while_cnt < 20);
 401
 402         if (smp->adc_smp_state == ADCSMP_STATE_SET) {
 403                 if (polling_ok)
 404                         phydm_la_get_tx_pkt_buf(dm);
 405                 else
 406                         pr_debug("[Polling timeout]\n");
 407         }
 408
 409         #if (DM_ODM_SUPPORT_TYPE & ODM_AP)
 410         watchdog_resume(dm->priv);
 411         #endif
 412
 413         #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 414         if (smp->adc_smp_state == ADCSMP_STATE_SET)
 415                 smp->adc_smp_state = ADCSMP_STATE_QUERY;
 416         #endif
 417
 418         pr_debug("[LA mode] LA_pattern_count = ((%d))\n", smp->la_count);
 419         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 420         RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
 421                     ("[LA mode] la_count = ((%d))\n", smp->la_count));
 422         #endif
 423
 424         adc_smp_stop(dm);
 425
 426         if (smp->la_count == 0) {
 427                 pr_debug("LA Dump finished ---------->\n\n\n");
 428                 phydm_release_bb_dbg_port(dm);
 429
 430                 if ((dm->support_ic_type & ODM_RTL8821C) &&
 431                     dm->cut_version >= ODM_CUT_B)
 432                         odm_set_bb_reg(dm, R_0x95c, BIT(23), 0);
 433
 434         } else {
 435                 smp->la_count--;
 436                 pr_debug("LA Dump more ---------->\n\n\n");
 437                 adc_smp_set(dm, smp->la_trig_mode, smp->la_trig_sig_sel,
 438                             smp->la_dma_type, smp->la_trigger_time, 0);
 439         }
 440 }
 441
 442 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 443 void adc_smp_work_item_callback(void *context)
 444 {
 445         void *adapter = (void *)context;
 446         PHAL_DATA_TYPE hal_data = GET_HAL_DATA(((PADAPTER)adapter));
 447         struct dm_struct *dm = &hal_data->DM_OutSrc;
 448         struct rt_adcsmp *smp = &dm->adcsmp;
 449
 450         pr_debug("[WorkItem Call back] LA_State=((%d))\n", smp->adc_smp_state);
 451         phydm_adc_smp_start(dm);
 452 }
 453 #endif
 454
 455 void adc_smp_set(void *dm_void, u8 trig_mode, u32 trig_sig_sel,
 456                  u8 dma_data_sig_sel, u32 trig_time, u16 polling_time)
 457 {
 458         struct dm_struct *dm = (struct dm_struct *)dm_void;
 459         boolean is_set_success = true;
 460         struct rt_adcsmp *smp = &dm->adcsmp;
 461
 462         smp->la_trig_mode = trig_mode;
 463         smp->la_trig_sig_sel = trig_sig_sel;
 464         smp->la_dma_type = dma_data_sig_sel;
 465         smp->la_trigger_time = trig_time;
 466
 467         #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 468         if (smp->adc_smp_state != ADCSMP_STATE_IDLE)
 469                 is_set_success = false;
 470         else if (smp->adc_smp_buf.length == 0)
 471                 is_set_success = phydm_la_buffer_allocate(dm);
 472         #endif
 473
 474         if (is_set_success) {
 475                 smp->adc_smp_state = ADCSMP_STATE_SET;
 476
 477                 pr_debug("[LA Set Success] LA_State=((%d))\n",
 478                          smp->adc_smp_state);
 479
 480                 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 481
 482                 pr_debug("ADCSmp_work_item_index = ((%d))\n",
 483                          smp->la_work_item_index);
 484                 if (smp->la_work_item_index != 0) {
 485                         odm_schedule_work_item(&smp->adc_smp_work_item_1);
 486                         smp->la_work_item_index = 0;
 487                 } else {
 488                         odm_schedule_work_item(&smp->adc_smp_work_item);
 489                         smp->la_work_item_index = 1;
 490                 }
 491                 #else
 492                 phydm_adc_smp_start(dm);
 493                 #endif
 494         } else {
 495                 pr_debug("[LA Set Fail] LA_State=((%d))\n", smp->adc_smp_state);
 496         }
 497 }
 498
 499 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 500 enum rt_status
 501 adc_smp_query(void *dm_void, ULONG info_buf_length, void *info_buf,
 502               PULONG bytes_written)
 503 {
 504         struct dm_struct *dm = (struct dm_struct *)dm_void;
 505         struct rt_adcsmp *smp = &dm->adcsmp;
 506         enum rt_status ret_status = RT_STATUS_SUCCESS;
 507         struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
 508
 509         pr_debug("[%s] LA_State=((%d))", __func__, smp->adc_smp_state);
 510
 511         if (info_buf_length != buf->buffer_size) {
 512                 *bytes_written = 0;
 513                 ret_status = RT_STATUS_RESOURCE;
 514         } else if (buf->length != buf->buffer_size) {
 515                 *bytes_written = 0;
 516                 ret_status = RT_STATUS_RESOURCE;
 517         } else if (smp->adc_smp_state != ADCSMP_STATE_QUERY) {
 518                 *bytes_written = 0;
 519                 ret_status = RT_STATUS_PENDING;
 520         } else {
 521                 odm_move_memory(dm, info_buf, buf->octet, buf->buffer_size);
 522                 *bytes_written = buf->buffer_size;
 523
 524                 smp->adc_smp_state = ADCSMP_STATE_IDLE;
 525         }
 526
 527         pr_debug("Return status %d\n", ret_status);
 528
 529         return ret_status;
 530 }
 531 #elif (DM_ODM_SUPPORT_TYPE & ODM_CE)
 532
 533 void adc_smp_query(void *dm_void, void *output, u32 out_len, u32 *pused)
 534 {
 535         struct dm_struct *dm = (struct dm_struct *)dm_void;
 536         struct rt_adcsmp *smp = &dm->adcsmp;
 537         struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
 538         u32 used = *pused;
 539         u32 i = 0;
 540 #if 0
 541         /* struct timespec t; */
 542         /* rtw_get_current_timespec(&t); */
 543 #endif
 544
 545         pr_debug("%s adc_smp_state %d", __func__, smp->adc_smp_state);
 546
 547         for (i = 0; i < (buf->length >> 2) - 2; i += 2) {
 548                 PDM_SNPF(out_len, used, output + used, out_len - used,
 549                          "%08x%08x\n", buf->octet[i], buf->octet[i + 1]);
 550         }
 551
 552         PDM_SNPF(out_len, used, output + used, out_len - used, "\n");
 553         /* PDM_SNPF(output + used, out_len - used, "\n[%lu.%06lu]\n", */
 554         /*          t.tv_sec, t.tv_nsec); */
 555         *pused = used;
 556 }
 557
 558 s32 adc_smp_get_sample_counts(void *dm_void)
 559 {
 560         struct dm_struct *dm = (struct dm_struct *)dm_void;
 561         struct rt_adcsmp *smp = &dm->adcsmp;
 562         struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
 563
 564         return (buf->length >> 2) - 2;
 565 }
 566
 567 s32 adc_smp_query_single_data(void *dm_void, void *output, u32 out_len, u32 idx)
 568 {
 569         struct dm_struct *dm = (struct dm_struct *)dm_void;
 570         struct rt_adcsmp *smp = &dm->adcsmp;
 571         struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
 572         u32 used = 0;
 573
 574         /* @dbg_print("%s adc_smp_state %d\n", __func__,*/
 575         /*            smp->adc_smp_state);*/
 576         if (smp->adc_smp_state != ADCSMP_STATE_QUERY) {
 577                 PDM_SNPF(out_len, used, output + used, out_len - used,
 578                          "Error: la data is not ready yet ...\n");
 579                 return -1;
 580         }
 581
 582         if (idx < ((buf->length >> 2) - 2)) {
 583                 PDM_SNPF(out_len, used, output + used, out_len - used,
 584                          "%08x%08x\n", buf->octet[idx], buf->octet[idx + 1]);
 585         }
 586         return 0;
 587 }
 588
 589 #endif
 590
 591 void adc_smp_stop(void *dm_void)
 592 {
 593         struct dm_struct *dm = (struct dm_struct *)dm_void;
 594         struct rt_adcsmp *smp = &dm->adcsmp;
 595
 596         smp->adc_smp_state = ADCSMP_STATE_IDLE;
 597
 598         PHYDM_DBG(dm, DBG_TMP, "[LA_Stop] LA_state = %d\n", smp->adc_smp_state);
 599 }
 600
 601 void adc_smp_init(void *dm_void)
 602 {
 603         struct dm_struct *dm = (struct dm_struct *)dm_void;
 604         struct rt_adcsmp *smp = &dm->adcsmp;
 605         struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
 606
 607         smp->adc_smp_state = ADCSMP_STATE_IDLE;
 608
 609         if (dm->support_ic_type & ODM_RTL8814A) {
 610                 buf->start_pos = 0x30000;
 611                 buf->buffer_size = 0x10000;
 612         } else if (dm->support_ic_type & (ODM_RTL8822B | ODM_RTL8822C)) {
 613                 buf->start_pos = 0x20000;
 614                 buf->buffer_size = 0x20000;
 615         } else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8198F)) {
 616                 buf->start_pos = 0x00000;
 617                 buf->buffer_size = 0x10000;
 618         } else if (dm->support_ic_type & ODM_RTL8192F) {
 619                 buf->start_pos = 0x2000;
 620                 buf->buffer_size = 0xE000;
 621         } else if (dm->support_ic_type & ODM_RTL8821C) {
 622                 buf->start_pos = 0x8000;
 623                 buf->buffer_size = 0x8000;
 624         }
 625
 626         buf->end_pos = buf->start_pos + buf->buffer_size;
 627
 628         PHYDM_DBG(dm, DBG_TMP,
 629                   "start_addr = ((0x%x)), end_addr = ((0x%x)), buffer_size = ((%d))\n",
 630                   buf->start_pos, buf->end_pos, buf->buffer_size);
 631 }
 632
 633 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 634 void adc_smp_de_init(void *dm_void)
 635 {
 636         struct dm_struct *dm = (struct dm_struct *)dm_void;
 637         struct rt_adcsmp *smp = &dm->adcsmp;
 638         struct rt_adcsmp_string *buf = &smp->adc_smp_buf;
 639
 640         adc_smp_stop(dm);
 641
 642         if (buf->length != 0x0) {
 643                 odm_free_memory(dm, buf->octet, buf->length);
 644                 buf->length = 0x0;
 645         }
 646 }
 647
 648 #endif
 649
 650 void phydm_la_mode_bb_setting(void *dm_void, boolean en_fake_trig)
 651 {
 652         struct dm_struct *dm = (struct dm_struct *)dm_void;
 653         struct rt_adcsmp *smp = &dm->adcsmp;
 654
 655         u8      trig_mode = smp->la_trig_mode;
 656         u32     trig_sel = smp->la_trig_sig_sel;
 657         u32     dbg_port = smp->la_dbg_port;
 658         u8      edge = smp->la_trigger_edge;
 659         u8      smp_rate = smp->la_smp_rate;
 660         u8      dma_type = smp->la_dma_type;
 661         u8      is_fake_trig = smp->is_fake_trig;
 662         u32     dbg_port_hdr_sel = 0;
 663         #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
 664         boolean en_new_bbtrigger = smp->la_en_new_bbtrigger;
 665         boolean ori_bb_dis = smp->la_ori_bb_dis;
 666         u8      and1_sel = smp->la_and1_sel;
 667         u8      and1_val = smp->la_and1_val;
 668         u8      and2_sel = smp->la_and2_sel;
 669         u8      and2_val = smp->la_and2_val;
 670         u8      and3_sel = smp->la_and3_sel;
 671         u8      and3_val = smp->la_and3_val;
 672         u32     and4_en = smp->la_and4_en;
 673         u32     and4_val = smp->la_and4_val;
 674         #endif
 675
 676         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 677         RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD,
 678                     ("1. [LA mode bb_setting]trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
 679                     trig_mode, dbg_port, edge, smp_rate, trig_sel, dma_type));
 680         #endif
 681
 682         if (trig_mode == PHYDM_MAC_TRIG)
 683                 trig_sel = 0; /*@ignore this setting*/
 684
 685         /*set BB debug port*/
 686         if (is_fake_trig) {
 687                 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, 0xf))
 688                         pr_debug("Set fake dbg_port success\n");
 689                 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 690                         /*@0x95C[4:0], BB debug port bit*/
 691                         odm_set_bb_reg(dm, R_0x95c, 0x1f, 0x0);
 692                 #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
 693                 } else if (dm->support_ic_type &
 694                            (ODM_RTL8198F | ODM_RTL8822C)) {
 695                         if (!(en_new_bbtrigger))
 696                                 odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, 0x0);
 697                         else if (!(ori_bb_dis))
 698                                 odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, 0x0);
 699                 #endif
 700                 } else {
 701                         /*@0x9A0[4:0], BB debug port bit*/
 702                         odm_set_bb_reg(dm, R_0x9a0, 0x1f, 0x0);
 703                 }
 704
 705                 pr_debug("1. [BB Setting] is_fake\n");
 706         } else {
 707                 if (en_fake_trig)
 708                         phydm_release_bb_dbg_port(dm);
 709                 if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_3, dbg_port))
 710                         pr_debug("Set dbg_port((0x%x)) success\n", dbg_port);
 711                 else
 712                         pr_debug("Set dbg_port fail!\n");
 713                 if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 714                         /*@0x95C[4:0], BB debug port bit*/
 715                         odm_set_bb_reg(dm, R_0x95c, 0x1f, trig_sel);
 716                 #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
 717                 } else if (dm->support_ic_type &
 718                            (ODM_RTL8198F | ODM_RTL8822C)) {
 719                         if (!(en_new_bbtrigger))
 720                                 odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel);
 721                         else if (!(ori_bb_dis))
 722                                 odm_set_bb_reg(dm, R_0x1ce4, 0x3e000, trig_sel);
 723                 #endif
 724                 } else {
 725                         /*@0x9A0[4:0], BB debug port bit*/
 726                         odm_set_bb_reg(dm, R_0x9a0, 0x1f, trig_sel);
 727                 }
 728                 pr_debug("1. [BB Setting] is_fake = ((%d)),  trig_mode = ((%d)), dbg_port = ((0x%x)), Trig_Edge = ((%d)), smp_rate = ((%d)), Trig_Sel = ((0x%x)), Dma_type = ((%d))\n",
 729                          is_fake_trig, trig_mode, dbg_port, edge, smp_rate,
 730                          trig_sel, dma_type);
 731                 if (en_fake_trig)
 732                         return;
 733         }
 734
 735         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 736                 if (trig_mode == PHYDM_ADC_RF0_TRIG)
 737                         dbg_port_hdr_sel = 9; /*@DBGOUT_RFC_a[31:0]*/
 738                 else if (trig_mode == PHYDM_ADC_RF1_TRIG)
 739                         dbg_port_hdr_sel = 8; /*@DBGOUT_RFC_b[31:0]*/
 740                 else if ((trig_mode == PHYDM_ADC_BB_TRIG) ||
 741                          (trig_mode == PHYDM_ADC_MAC_TRIG)) {
 742                         if (smp->la_mac_mask_or_hdr_sel <= 0xf)
 743                                 dbg_port_hdr_sel = smp->la_mac_mask_or_hdr_sel;
 744                         else
 745                                 dbg_port_hdr_sel = 0;
 746                 }
 747
 748                 phydm_bb_dbg_port_header_sel(dm, dbg_port_hdr_sel);
 749
 750                 /*@0x95C[11:8]*/
 751                 odm_set_bb_reg(dm, R_0x95c, 0xf00, dma_type);
 752                 /*@0: posedge, 1: negedge*/
 753                 odm_set_bb_reg(dm, R_0x95c, BIT(31), edge);
 754                 odm_set_bb_reg(dm, R_0x95c, 0xe0, smp_rate);
 755                 /*      @(0:) '80MHz'
 756                  *      (1:) '40MHz'
 757                  *      (2:) '20MHz'
 758                  *      (3:) '10MHz'
 759                  *      (4:) '5MHz'
 760                  *      (5:) '2.5MHz'
 761                  *      (6:) '1.25MHz'
 762                  *      (7:) '160MHz (for BW160 ic)'
 763                  */
 764                 if ((dm->support_ic_type & ODM_RTL8821C) &&
 765                     (dm->cut_version >= ODM_CUT_B))
 766                         odm_set_bb_reg(dm, R_0x95c, BIT(23), 1);
 767         #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
 768         } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) {
 769                 /*@MAC-PHY timing*/
 770                 odm_set_bb_reg(dm, R_0x1ce4, BIT(7) | BIT(6), 0);
 771                 odm_set_bb_reg(dm, R_0x1cf4, BIT(23), 1); /*@LA mode on*/
 772                 odm_set_bb_reg(dm, R_0x1ce4, 0x3f, dma_type);
 773                 /*@0: posedge, 1: negedge ??*/
 774                 odm_set_bb_reg(dm, R_0x1ce4, BIT(26), edge);
 775                 odm_set_bb_reg(dm, R_0x1ce4, 0x700, smp_rate);
 776
 777                 if (!en_new_bbtrigger) { /*normal LA mode & back to default*/
 778
 779                         pr_debug("Set bb default setting\n");
 780
 781                         /*path 1 default: enable ori. BB trigger*/
 782                         odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0);
 783
 784                         /*@AND1~AND4 default: off*/
 785                         odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS, 0); /*@AND 1*/
 786                         odm_set_bb_reg(dm, R_0x1ce8, 0x1f, 0); /*@AND 1 val*/
 787                         odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@AND 1 inv*/
 788
 789                         odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, 0); /*@AND 2*/
 790                         odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, 0); /*@AND 2 val*/
 791                         /*@AND 2 inv*/
 792                         odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0);
 793
 794                         odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, 0); /*@AND 3*/
 795                         /*@AND 3 val*/
 796                         odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000, 0);
 797                         /*@AND 3 inv*/
 798                         odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0);
 799
 800                         /*@AND 4 en*/
 801                         odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, 0);
 802                         /*@AND 4 val*/
 803                         odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, 0);
 804                         /*@AND 4 inv*/
 805                         odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0);
 806
 807                         pr_debug("Set bb default setting finished\n");
 808
 809                 } else if (en_new_bbtrigger) {
 810                         /*path 1 default: enable ori. BB trigger*/
 811                         if (ori_bb_dis)
 812                                 odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 1);
 813                         else
 814                                 odm_set_bb_reg(dm, R_0x1ce4, BIT(27), 0);
 815
 816                         /* @AND1 */
 817                         odm_set_bb_reg(dm, R_0x1ce8, BIT(5), 0); /*@invert*/
 818
 819                         if (and1_sel == 0x4 || and1_sel == 0x5 ||
 820                             and1_sel == 0x6) {
 821                                 /* rx_state, rx_state_freq, field */
 822                                 odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS,
 823                                                and1_sel);
 824                                 odm_set_bb_reg(dm, R_0x1ce8, 0x1f, and1_val);
 825
 826                         } else if (and1_sel == 0x7) {
 827                                 /* @mux state */
 828                                 odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS,
 829                                                and1_sel);
 830                                 odm_set_bb_reg(dm, R_0x1ce8, 0xf, and1_val);
 831
 832                         } else {
 833                                 odm_set_bb_reg(dm, R_0x1ce4, MASKH4BITS,
 834                                                and1_sel);
 835                         }
 836
 837                         /* @AND2 */
 838                         odm_set_bb_reg(dm, R_0x1ce8, BIT(15), 0); /*@invert*/
 839
 840                         if (and2_sel == 0x4 || and2_sel == 0x5 ||
 841                             and2_sel == 0x6) {
 842                                 /* rx_state, rx_state_freq, field */
 843                                 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, and2_sel);
 844                                 odm_set_bb_reg(dm, R_0x1ce8, 0x7c00, and2_val);
 845
 846                         } else if (and2_sel == 0x7) {
 847                                 /* @mux state */
 848                                 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, and2_sel);
 849                                 odm_set_bb_reg(dm, R_0x1ce8, 0x3c00, and2_val);
 850
 851                         } else {
 852                                 odm_set_bb_reg(dm, R_0x1ce8, 0x3c0, and2_sel);
 853                         }
 854
 855                         /* @AND3 */
 856                         odm_set_bb_reg(dm, R_0x1ce8, BIT(25), 0); /*@invert*/
 857
 858                         if (and3_sel == 0x4 || and3_sel == 0x5 ||
 859                             and3_sel == 0x6) {
 860                                 /* rx_state, rx_state_freq, field */
 861                                 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, and3_sel);
 862                                 odm_set_bb_reg(dm, R_0x1ce8, 0x1f00000,
 863                                                and3_val);
 864
 865                         } else if (and3_sel == 0x7) {
 866                                 /* @mux state */
 867                                 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, and3_sel);
 868                                 odm_set_bb_reg(dm, R_0x1ce8, 0xf00000,
 869                                                and3_val);
 870                         } else {
 871                                 odm_set_bb_reg(dm, R_0x1ce8, 0xf0000, and3_sel);
 872                         }
 873
 874                         /* @AND4 */
 875                         odm_set_bb_reg(dm, R_0x1ce8, BIT(26), 0); /*@invert*/
 876                         odm_set_bb_reg(dm, R_0x1cf0, MASKDWORD, and4_en);
 877                         odm_set_bb_reg(dm, R_0x1cec, MASKDWORD, and4_val);
 878                         }
 879         #endif
 880         } else {
 881                 #if (RTL8192F_SUPPORT)
 882                 if ((dm->support_ic_type & ODM_RTL8192F))
 883                         /*@LA reset HW block enable for true-mac asic*/
 884                         odm_set_bb_reg(dm, R_0x9a0, BIT(15), 1);
 885                 #endif
 886                 /*@0x9A0[11:8]*/
 887                 odm_set_bb_reg(dm, R_0x9a0, 0xf00, dma_type);
 888                 /*@0: posedge, 1: negedge*/
 889                 odm_set_bb_reg(dm, R_0x9a0, BIT(31), edge);
 890                 odm_set_bb_reg(dm, R_0x9a0, 0xe0, smp_rate);
 891                 /*      @(0:) '80MHz'
 892                  *      (1:) '40MHz'
 893                  *      (2:) '20MHz'
 894                  *      (3:) '10MHz'
 895                  *      (4:) '5MHz'
 896                  *      (5:) '2.5MHz'
 897                  *      (6:) '1.25MHz'
 898                  *      (7:) '160MHz (for BW160 ic)'
 899                  */
 900         }
 901 }
 902
 903 void phydm_la_mode_set_trigger_time(void *dm_void, u32 trigger_time_mu_sec)
 904 {
 905         struct dm_struct *dm = (struct dm_struct *)dm_void;
 906         u8 time_unit_num = 0;
 907         u32 unit = 0;
 908
 909         if (trigger_time_mu_sec < 128)
 910                 unit = 0; /*unit: 1mu sec*/
 911         else if (trigger_time_mu_sec < 256)
 912                 unit = 1; /*unit: 2mu sec*/
 913         else if (trigger_time_mu_sec < 512)
 914                 unit = 2; /*unit: 4mu sec*/
 915         else if (trigger_time_mu_sec < 1024)
 916                 unit = 3; /*unit: 8mu sec*/
 917         else if (trigger_time_mu_sec < 2048)
 918                 unit = 4; /*unit: 16mu sec*/
 919         else if (trigger_time_mu_sec < 4096)
 920                 unit = 5; /*unit: 32mu sec*/
 921         else if (trigger_time_mu_sec < 8192)
 922                 unit = 6; /*unit: 64mu sec*/
 923
 924         time_unit_num = (u8)(trigger_time_mu_sec >> unit);
 925
 926         pr_debug("2. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
 927                  time_unit_num, unit);
 928         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 929         RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, (
 930                     "3. [Set Trigger Time] Trig_Time = ((%d)) * unit = ((2^%d us))\n",
 931                     time_unit_num, unit));
 932         #endif
 933
 934         if (dm->support_ic_type & ODM_RTL8192F) {
 935                 odm_set_mac_reg(dm, R_0x7fc, BIT(2) | BIT(1) | BIT(0), unit);
 936                 odm_set_mac_reg(dm, R_0x7f0, 0x7f00, (time_unit_num & 0x7f));
 937         #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
 938         } else if (dm->support_ic_type & (ODM_RTL8198F | ODM_RTL8822C)) {
 939                 odm_set_mac_reg(dm, R_0x7cc, BIT(18) | BIT(17) | BIT(16), unit);
 940                 odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
 941         #endif
 942         } else {
 943                 odm_set_mac_reg(dm, R_0x7cc, BIT(20) | BIT(19) | BIT(18), unit);
 944                 odm_set_mac_reg(dm, R_0x7c0, 0x7f00, (time_unit_num & 0x7f));
 945         }
 946 }
 947
 948 void phydm_lamode_trigger_cmd(void *dm_void, char input[][16], u32 *_used,
 949                               char *output, u32 *_out_len)
 950 {
 951         struct dm_struct *dm = (struct dm_struct *)dm_void;
 952         struct rt_adcsmp *smp = &dm->adcsmp;
 953         u8 trig_mode = 0, dma_data_sig_sel = 0;
 954         u32 trig_sig_sel = 0;
 955         u8 enable_la_mode = 0;
 956         u32 trigger_time_mu_sec = 0;
 957         char help[] = "-h";
 958         u32 var1[10] = {0};
 959         u32 used = *_used;
 960         u32 out_len = *_out_len;
 961
 962         if (dm->support_ic_type & PHYDM_IC_SUPPORT_LA_MODE) {
 963                 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
 964                 enable_la_mode = (u8)var1[0];
 965 #if 0
 966                 /*@dbg_print("echo cmd input_num = %d\n", input_num);*/
 967 #endif
 968
 969                 if ((strcmp(input[1], help) == 0)) {
 970                         PDM_SNPF(out_len, used, output + used, out_len - used,
 971                                  "{En} {0:BB,1:BB_MAC,2:RF0,3:RF1,4:MAC} \n {BB:dbg_port[bit],BB_MAC:0-ok/1-fail/2-cca,MAC:ref} {DMA type} {TrigTime} \n {DbgPort_head/ref_mask} {dbg_port} {0:P_Edge, 1:N_Edge} {SpRate:0-80M,1-40M,2-20M} {Capture num}\n");
 972                 } else if (enable_la_mode == 1) {
 973                         PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
 974
 975                         trig_mode = (u8)var1[1];
 976
 977                         if (trig_mode == PHYDM_MAC_TRIG)
 978                                 PHYDM_SSCANF(input[3], DCMD_HEX, &var1[2]);
 979                         else
 980                                 PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
 981                         trig_sig_sel = var1[2];
 982
 983                         PHYDM_SSCANF(input[4], DCMD_DECIMAL, &var1[3]);
 984                         PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
 985                         PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
 986                         PHYDM_SSCANF(input[7], DCMD_HEX, &var1[6]);
 987                         PHYDM_SSCANF(input[8], DCMD_DECIMAL, &var1[7]);
 988                         PHYDM_SSCANF(input[9], DCMD_DECIMAL, &var1[8]);
 989                         PHYDM_SSCANF(input[10], DCMD_DECIMAL, &var1[9]);
 990
 991                         dma_data_sig_sel = (u8)var1[3];
 992                         trigger_time_mu_sec = var1[4]; /*unit: us*/
 993
 994                         smp->la_mac_mask_or_hdr_sel = var1[5];
 995                         smp->la_dbg_port = var1[6];
 996                         smp->la_trigger_edge = (u8)var1[7];
 997                         smp->la_smp_rate = (u8)(var1[8] & 0x7);
 998                         smp->la_count = var1[9];
 999
1000                         #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
1001                         smp->la_en_new_bbtrigger = false;
1002                         #endif
1003
1004                         pr_debug("echo lamode %d %d %d %d %d %d %x %d %d %d\n",
1005                                  var1[0], var1[1], var1[2], var1[3], var1[4],
1006                                  var1[5], var1[6], var1[7], var1[8], var1[9]);
1007                         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
1008                         RT_TRACE_EX(COMP_LA_MODE, DBG_LOUD, (
1009                                     "echo lamode %d %d %d %d %d %d %x %d %d %d\n",
1010                                     var1[0], var1[1], var1[2], var1[3],
1011                                     var1[4], var1[5], var1[6], var1[7],
1012                                     var1[8], var1[9]));
1013                         #endif
1014
1015                         PDM_SNPF(out_len, used, output + used, out_len - used,
1016                                  "a.En= ((1)),  b.mode = ((%d)), c.Trig_Sel = ((0x%x)), d.Dma_type = ((%d))\n",
1017                                  trig_mode, trig_sig_sel, dma_data_sig_sel);
1018                         PDM_SNPF(out_len, used, output + used, out_len - used,
1019                                  "e.Trig_Time = ((%dus)), f.Dbg_head/mac_ref_mask = ((0x%x)), g.dbg_port = ((0x%x))\n",
1020                                  trigger_time_mu_sec,
1021                                  smp->la_mac_mask_or_hdr_sel, smp->la_dbg_port);
1022                         PDM_SNPF(out_len, used, output + used, out_len - used,
1023                                  "h.Trig_edge = ((%d)), i.smp rate = ((%d MHz)), j.Cap_num = ((%d))\n",
1024                                  smp->la_trigger_edge, (80 >> smp->la_smp_rate),
1025                                  smp->la_count);
1026
1027                         #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
1028                         PDM_SNPF(out_len, used, output + used, out_len - used,
1029                                  "k.en_new_bbtrigger = ((%d))\n",
1030                                  smp->la_en_new_bbtrigger);
1031                         #endif
1032
1033                         adc_smp_set(dm, trig_mode, trig_sig_sel,
1034                                     dma_data_sig_sel, trigger_time_mu_sec, 0);
1035
1036                 #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT)
1037                 } else if (enable_la_mode == 100) {
1038                         smp->la_en_new_bbtrigger = true;
1039
1040                         PHYDM_SSCANF(input[2], DCMD_DECIMAL, &var1[1]);
1041                         PHYDM_SSCANF(input[3], DCMD_DECIMAL, &var1[2]);
1042                         PHYDM_SSCANF(input[4], DCMD_HEX, &var1[3]);
1043                         PHYDM_SSCANF(input[5], DCMD_DECIMAL, &var1[4]);
1044                         PHYDM_SSCANF(input[6], DCMD_HEX, &var1[5]);
1045                         PHYDM_SSCANF(input[7], DCMD_DECIMAL, &var1[6]);
1046                         PHYDM_SSCANF(input[8], DCMD_HEX, &var1[7]);
1047                         PHYDM_SSCANF(input[9], DCMD_HEX, &var1[8]);
1048                         PHYDM_SSCANF(input[10], DCMD_HEX, &var1[9]);
1049
1050                         smp->la_ori_bb_dis = (boolean)var1[1];
1051                         smp->la_and1_sel = (u8)var1[2];
1052                         smp->la_and1_val = (u8)var1[3];
1053                         smp->la_and2_sel = (u8)var1[4];
1054                         smp->la_and2_val = (u8)var1[5];
1055                         smp->la_and3_sel = (u8)var1[6];
1056                         smp->la_and3_val = (u8)var1[7];
1057                         smp->la_and4_en = (u32)var1[8];
1058                         smp->la_and4_val = (u32)var1[9];
1059
1060                         phydm_adc_smp_start(dm);
1061
1062                 } else if (enable_la_mode == 101) {
1063                         smp->la_en_new_bbtrigger = false;
1064                         phydm_adc_smp_start(dm);
1065                 #endif
1066                 } else {
1067                         adc_smp_stop(dm);
1068                         PDM_SNPF(out_len, used, output + used, out_len - used,
1069                                  "Disable LA mode\n");
1070                 }
1071         }
1072         *_used = used;
1073         *_out_len = out_len;
1074 }
1075
1076 #endif /*@endif PHYDM_LA_MODE_SUPPORT*/