rtl8821ce/hal/phydm/phydm_antdiv.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2017  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 /*************************************************************
  27  * include files
  28  ************************************************************/
  29
  30 #include "mp_precomp.h"
  31 #include "phydm_precomp.h"
  32
  33 /*******************************************************
  34  * when antenna test utility is on or some testing need to disable antenna diversity
  35  * call this function to disable all ODM related mechanisms which will switch antenna.
  36  *****************************************************
  37  */
  38 #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
  39 void odm_stop_antenna_switch_dm(void *dm_void)
  40 {
  41         struct dm_struct *dm = (struct dm_struct *)dm_void;
  42         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
  43         /* @disable ODM antenna diversity */
  44         dm->support_ability &= ~ODM_BB_ANT_DIV;
  45         if (fat_tab->div_path_type == ANT_PATH_A)
  46                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
  47         else if (fat_tab->div_path_type == ANT_PATH_B)
  48                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
  49         else if (fat_tab->div_path_type == ANT_PATH_AB)
  50                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
  51         odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
  52         PHYDM_DBG(dm, DBG_ANT_DIV, "STOP Antenna Diversity\n");
  53 }
  54
  55 void phydm_enable_antenna_diversity(void *dm_void)
  56 {
  57         struct dm_struct *dm = (struct dm_struct *)dm_void;
  58
  59         dm->support_ability |= ODM_BB_ANT_DIV;
  60         dm->antdiv_select = 0;
  61         PHYDM_DBG(dm, DBG_ANT_DIV, "AntDiv is enabled & Re-Init AntDiv\n");
  62         odm_antenna_diversity_init(dm);
  63 }
  64
  65 void odm_set_ant_config(void *dm_void, u8 ant_setting /* @0=A, 1=B, 2=C, .... */)
  66 {
  67         struct dm_struct *dm = (struct dm_struct *)dm_void;
  68
  69         if (dm->support_ic_type == ODM_RTL8723B) {
  70                 if (ant_setting == 0) /* @ant A*/
  71                         odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000000);
  72                 else if (ant_setting == 1)
  73                         odm_set_bb_reg(dm, R_0x948, MASKDWORD, 0x00000280);
  74         } else if (dm->support_ic_type == ODM_RTL8723D) {
  75                 if (ant_setting == 0) /* @ant A*/
  76                         odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0000);
  77                 else if (ant_setting == 1)
  78                         odm_set_bb_reg(dm, R_0x948, MASKLWORD, 0x0280);
  79         }
  80 }
  81
  82 /* ****************************************************** */
  83
  84 void odm_sw_ant_div_rest_after_link(void *dm_void)
  85 {
  86 #if (defined(CONFIG_PHYDM_ANTENNA_DIVERSITY))
  87         struct dm_struct *dm = (struct dm_struct *)dm_void;
  88         struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
  89         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
  90         u32 i;
  91
  92         if (dm->ant_div_type == S0S1_SW_ANTDIV) {
  93                 dm_swat_table->try_flag = SWAW_STEP_INIT;
  94                 dm_swat_table->rssi_trying = 0;
  95                 dm_swat_table->double_chk_flag = 0;
  96                 fat_tab->rx_idle_ant = MAIN_ANT;
  97
  98                 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
  99                         phydm_antdiv_reset_statistic(dm, i);
 100         }
 101
 102 #endif
 103 }
 104
 105 void phydm_n_on_off(void *dm_void, u8 swch, u8 path)
 106 {
 107         struct dm_struct *dm = (struct dm_struct *)dm_void;
 108         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
 109
 110         if (path == ANT_PATH_A) {
 111                 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
 112         } else if (path == ANT_PATH_B) {
 113                 odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
 114         } else if (path == ANT_PATH_AB) {
 115                 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
 116                 odm_set_bb_reg(dm, R_0xc58, BIT(7), swch);
 117         }
 118         odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
 119 #if (RTL8723D_SUPPORT == 1)
 120         /*@Mingzhi 2017-05-08*/
 121         if (dm->support_ic_type == ODM_RTL8723D) {
 122                 if (swch == ANTDIV_ON) {
 123                         odm_set_bb_reg(dm, R_0xce0, BIT(1), 1);
 124                         odm_set_bb_reg(dm, R_0x948, BIT(6), 1);
 125                         /*@1:HW ctrl  0:SW ctrl*/
 126                 } else {
 127                         odm_set_bb_reg(dm, R_0xce0, BIT(1), 0);
 128                         odm_set_bb_reg(dm, R_0x948, BIT(6), 0);
 129                         /*@1:HW ctrl  0:SW ctrl*/
 130                 }
 131         }
 132 #endif
 133 }
 134
 135 void phydm_ac_on_off(void *dm_void, u8 swch, u8 path)
 136 {
 137         struct dm_struct *dm = (struct dm_struct *)dm_void;
 138         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
 139
 140         if (dm->support_ic_type & ODM_RTL8812) {
 141                 odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
 142                 /* OFDM AntDiv function block enable */
 143                 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
 144                 /* @CCK AntDiv function block enable */
 145         } else if (dm->support_ic_type & ODM_RTL8822B) {
 146                 odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
 147                 odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
 148                 if (path == ANT_PATH_A) {
 149                         odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
 150                 } else if (path == ANT_PATH_B) {
 151                         odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
 152                 } else if (path == ANT_PATH_AB) {
 153                         odm_set_bb_reg(dm, R_0xc50, BIT(7), swch);
 154                         odm_set_bb_reg(dm, R_0xe50, BIT(7), swch);
 155                 }
 156         } else {
 157                 odm_set_bb_reg(dm, R_0x8d4, BIT(24), swch);
 158                 /* OFDM AntDiv function block enable */
 159
 160                 if (dm->cut_version >= ODM_CUT_C &&
 161                     dm->support_ic_type == ODM_RTL8821 &&
 162                     dm->ant_div_type != S0S1_SW_ANTDIV) {
 163                         PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
 164                                   (swch == ANTDIV_ON) ? "ON" : "OFF");
 165                         odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
 166                         odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
 167                         /* @CCK AntDiv function block enable */
 168                 } else if (dm->support_ic_type == ODM_RTL8821C) {
 169                         PHYDM_DBG(dm, DBG_ANT_DIV, "(Turn %s) CCK HW-AntDiv\n",
 170                                   (swch == ANTDIV_ON) ? "ON" : "OFF");
 171                         odm_set_bb_reg(dm, R_0x800, BIT(25), swch);
 172                         odm_set_bb_reg(dm, R_0xa00, BIT(15), swch);
 173                         /* @CCK AntDiv function block enable */
 174                 }
 175         }
 176 }
 177
 178 void odm_ant_div_on_off(void *dm_void, u8 swch, u8 path)
 179 {
 180         struct dm_struct *dm = (struct dm_struct *)dm_void;
 181         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
 182
 183         if (fat_tab->ant_div_on_off != swch) {
 184                 if (dm->ant_div_type == S0S1_SW_ANTDIV)
 185                         return;
 186
 187                 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
 188                         PHYDM_DBG(dm, DBG_ANT_DIV,
 189                                   "(( Turn %s )) N-Series HW-AntDiv block\n",
 190                                   (swch == ANTDIV_ON) ? "ON" : "OFF");
 191                         phydm_n_on_off(dm, swch, path);
 192
 193                 } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
 194                         PHYDM_DBG(dm, DBG_ANT_DIV,
 195                                   "(( Turn %s )) AC-Series HW-AntDiv block\n",
 196                                   (swch == ANTDIV_ON) ? "ON" : "OFF");
 197                         phydm_ac_on_off(dm, swch, path);
 198                 }
 199         }
 200         fat_tab->ant_div_on_off = swch;
 201 }
 202
 203 void odm_tx_by_tx_desc_or_reg(void *dm_void, u8 swch)
 204 {
 205         struct dm_struct *dm = (struct dm_struct *)dm_void;
 206         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
 207         u8 enable;
 208
 209         if (fat_tab->b_fix_tx_ant == NO_FIX_TX_ANT)
 210                 enable = (swch == TX_BY_DESC) ? 1 : 0;
 211         else
 212                 enable = 0; /*@Force TX by Reg*/
 213
 214         if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
 215                 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
 216                         odm_set_bb_reg(dm, R_0x80c, BIT(21), enable);
 217                 else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
 218                         odm_set_bb_reg(dm, R_0x900, BIT(18), enable);
 219
 220                 PHYDM_DBG(dm, DBG_ANT_DIV, "[AntDiv] TX_Ant_BY (( %s ))\n",
 221                           (enable == TX_BY_DESC) ? "DESC" : "REG");
 222         }
 223 }
 224
 225 void phydm_antdiv_reset_statistic(
 226         void *dm_void,
 227         u32 macid)
 228 {
 229         struct dm_struct *dm = (struct dm_struct *)dm_void;
 230         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
 231
 232         fat_tab->main_ant_sum[macid] = 0;
 233         fat_tab->aux_ant_sum[macid] = 0;
 234         fat_tab->main_ant_cnt[macid] = 0;
 235         fat_tab->aux_ant_cnt[macid] = 0;
 236         fat_tab->main_ant_sum_cck[macid] = 0;
 237         fat_tab->aux_ant_sum_cck[macid] = 0;
 238         fat_tab->main_ant_cnt_cck[macid] = 0;
 239         fat_tab->aux_ant_cnt_cck[macid] = 0;
 240 }
 241
 242 void phydm_fast_training_enable(
 243         void *dm_void,
 244         u8 swch)
 245 {
 246         struct dm_struct *dm = (struct dm_struct *)dm_void;
 247         u8 enable;
 248
 249         if (swch == FAT_ON)
 250                 enable = 1;
 251         else
 252                 enable = 0;
 253
 254         PHYDM_DBG(dm, DBG_ANT_DIV, "Fast ant Training_en = ((%d))\n", enable);
 255
 256         if (dm->support_ic_type == ODM_RTL8188E) {
 257                 odm_set_bb_reg(dm, R_0xe08, BIT(16), enable); /*@enable fast training*/
 258         } else if (dm->support_ic_type == ODM_RTL8192E) {
 259                 odm_set_bb_reg(dm, R_0xb34, BIT(28), enable); /*@enable fast training (path-A)*/
 260 #if 0
 261                 /*odm_set_bb_reg(dm, R_0xb34, BIT(29), enable);*/ /*enable fast training (path-B)*/
 262 #endif
 263         } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8822B)) {
 264                 odm_set_bb_reg(dm, R_0x900, BIT(19), enable); /*@enable fast training */
 265         }
 266 }
 267
 268 void phydm_keep_rx_ack_ant_by_tx_ant_time(
 269         void *dm_void,
 270         u32 time)
 271 {
 272         struct dm_struct *dm = (struct dm_struct *)dm_void;
 273
 274         /* Timming issue: keep Rx ant after tx for ACK ( time x 3.2 mu sec)*/
 275         if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT)
 276                 odm_set_bb_reg(dm, R_0xe20, BIT(23) | BIT(22) | BIT(21) | BIT(20), time);
 277         else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT)
 278                 odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), time);
 279 }
 280
 281 void odm_update_rx_idle_ant(
 282         void *dm_void,
 283         u8 ant)
 284 {
 285         struct dm_struct *dm = (struct dm_struct *)dm_void;
 286         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
 287         u32 default_ant, optional_ant, value32, default_tx_ant;
 288
 289         if (fat_tab->rx_idle_ant != ant) {
 290                 PHYDM_DBG(dm, DBG_ANT_DIV,
 291                           "[ Update Rx-Idle-ant ] rx_idle_ant =%s\n",
 292                           (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
 293
 294                 if (!(dm->support_ic_type & ODM_RTL8723B))
 295                         fat_tab->rx_idle_ant = ant;
 296
 297                 if (ant == MAIN_ANT) {
 298                         default_ant = ANT1_2G;
 299                         optional_ant = ANT2_2G;
 300                 } else {
 301                         default_ant = ANT2_2G;
 302                         optional_ant = ANT1_2G;
 303                 }
 304
 305                 if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
 306                         default_tx_ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? 0 : 1;
 307                 else
 308                         default_tx_ant = default_ant;
 309
 310                 if (dm->support_ic_type & ODM_N_ANTDIV_SUPPORT) {
 311                         if (dm->support_ic_type & (ODM_RTL8192E | ODM_RTL8197F)) {
 312                                 odm_set_bb_reg(dm, R_0xb38, BIT(5) | BIT(4) | BIT(3), default_ant); /* @Default RX */
 313                                 odm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), optional_ant); /* Optional RX */
 314                                 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /* @Default TX */
 315                         }
 316 #if (RTL8723B_SUPPORT == 1)
 317                         else if (dm->support_ic_type == ODM_RTL8723B) {
 318                                 value32 = odm_get_bb_reg(dm, R_0x948, 0xFFF);
 319
 320                                 if (value32 != 0x280)
 321                                         odm_update_rx_idle_ant_8723b(dm, ant, default_ant, optional_ant);
 322                                 else
 323                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n");
 324                         }
 325 #endif
 326
 327 #if (RTL8723D_SUPPORT == 1) /*@Mingzhi 2017-05-08*/
 328                         else if (dm->support_ic_type == ODM_RTL8723D) {
 329                                 phydm_set_tx_ant_pwr_8723d(dm, ant);
 330                                 odm_update_rx_idle_ant_8723d(dm, ant, default_ant, optional_ant);
 331                         }
 332 #endif
 333
 334                         else { /*@8188E & 8188F*/
 335 /*@
 336                                 if (dm->support_ic_type == ODM_RTL8723D) {
 337 #if (RTL8723D_SUPPORT == 1)
 338                                         phydm_set_tx_ant_pwr_8723d(dm, ant);
 339 #endif
 340                                 }
 341 */
 342 #if (RTL8188F_SUPPORT == 1)
 343                                 if (dm->support_ic_type == ODM_RTL8188F)
 344                                         phydm_update_rx_idle_antenna_8188F(dm, default_ant);
 345 #endif
 346
 347                                 odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*@Default RX*/
 348                                 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
 349                                 odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_tx_ant); /*@Default TX*/
 350                         }
 351                 } else if (dm->support_ic_type & ODM_AC_ANTDIV_SUPPORT) {
 352                         u16 value16 = odm_read_2byte(dm, ODM_REG_TRMUX_11AC + 2);
 353                         /* @2014/01/14 MH/Luke.Lee Add direct write for register 0xc0a to prevnt */
 354                         /* @incorrect 0xc08 bit0-15 .We still not know why it is changed. */
 355                         value16 &= ~(BIT(11) | BIT(10) | BIT(9) | BIT(8) | BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3));
 356                         value16 |= ((u16)default_ant << 3);
 357                         value16 |= ((u16)optional_ant << 6);
 358                         value16 |= ((u16)default_tx_ant << 9);
 359                         odm_write_2byte(dm, ODM_REG_TRMUX_11AC + 2, value16);
 360 #if 0
 361                         odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(21) | BIT20 | BIT19, default_ant);    /* @Default RX */
 362                         odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(24) | BIT23 | BIT22, optional_ant); /* Optional RX */
 363                         odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC, BIT(27) | BIT26 | BIT25, default_ant);    /* @Default TX */
 364 #endif
 365                 }
 366
 367                 if (dm->support_ic_type & (ODM_RTL8821C | ODM_RTL8822B | ODM_RTL8814A))
 368                         odm_set_mac_reg(dm, R_0x6d8, 0x7, default_tx_ant); /*PathA Resp Tx*/
 369                 else if (dm->support_ic_type == ODM_RTL8188E)
 370                         odm_set_mac_reg(dm, R_0x6d8, BIT(7) | BIT(6), default_tx_ant); /*PathA Resp Tx*/
 371                 else
 372                         odm_set_mac_reg(dm, R_0x6d8, BIT(10) | BIT(9) | BIT(8), default_tx_ant); /*PathA Resp Tx*/
 373
 374         } else { /* @fat_tab->rx_idle_ant == ant */
 375                 PHYDM_DBG(dm, DBG_ANT_DIV,
 376                           "[ Stay in Ori-ant ]  rx_idle_ant =%s\n",
 377                           (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
 378                 fat_tab->rx_idle_ant = ant;
 379         }
 380 }
 381
 382 void phydm_update_rx_idle_ant_pathb(void *dm_void, u8 ant)
 383 {
 384         struct dm_struct *dm = (struct dm_struct *)dm_void;
 385         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
 386         u32 default_ant, optional_ant, value32, default_tx_ant;
 387
 388         if (fat_tab->rx_idle_ant2 != ant) {
 389                 PHYDM_DBG(dm, DBG_ANT_DIV,
 390                           "[ Update Rx-Idle-ant2 ] rx_idle_ant2 =%s\n",
 391                           (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
 392                 if (ant == MAIN_ANT) {
 393                         default_ant = ANT1_2G;
 394                         optional_ant = ANT2_2G;
 395                 } else {
 396                         default_ant = ANT2_2G;
 397                         optional_ant = ANT1_2G;
 398                 }
 399
 400                 if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
 401                         default_tx_ant = (fat_tab->b_fix_tx_ant ==
 402                                           FIX_TX_AT_MAIN) ? 0 : 1;
 403                 else
 404                         default_tx_ant = default_ant;
 405                 if (dm->support_ic_type & ODM_RTL8822B) {
 406                         u16 v16 = odm_read_2byte(dm, ODM_REG_ANT_11AC_B + 2);
 407
 408                         v16 &= ~(0xff8);/*0xE08[11:3]*/
 409                         v16 |= ((u16)default_ant << 3);
 410                         v16 |= ((u16)optional_ant << 6);
 411                         v16 |= ((u16)default_tx_ant << 9);
 412                         odm_write_2byte(dm, ODM_REG_ANT_11AC_B + 2, v16);
 413                         odm_set_mac_reg(dm, R_0x6d8, 0x38, default_tx_ant);
 414                         /*PathB Resp Tx*/
 415                 }
 416         } else {
 417                 /* fat_tab->rx_idle_ant2 == ant */
 418                 PHYDM_DBG(dm, DBG_ANT_DIV, "[Stay Ori Ant] rx_idle_ant2 = %s\n",
 419                           (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
 420                 fat_tab->rx_idle_ant2 = ant;
 421         }
 422 }
 423
 424 void phydm_set_antdiv_val(
 425         void *dm_void,
 426         u32 *val_buf,
 427         u8 val_len)
 428 {
 429         struct dm_struct *dm = (struct dm_struct *)dm_void;
 430
 431         if (val_len != 1) {
 432                 PHYDM_DBG(dm, ODM_COMP_API, "[Error][antdiv]Need val_len=1\n");
 433                 return;
 434         }
 435
 436         odm_update_rx_idle_ant(dm, (u8)(*val_buf));
 437 }
 438
 439 void odm_update_tx_ant(
 440         void *dm_void,
 441         u8 ant,
 442         u32 mac_id)
 443 {
 444         struct dm_struct *dm = (struct dm_struct *)dm_void;
 445         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
 446         u8 tx_ant;
 447
 448         if (fat_tab->b_fix_tx_ant != NO_FIX_TX_ANT)
 449                 ant = (fat_tab->b_fix_tx_ant == FIX_TX_AT_MAIN) ? MAIN_ANT : AUX_ANT;
 450
 451         if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
 452                 tx_ant = ant;
 453         else {
 454                 if (ant == MAIN_ANT)
 455                         tx_ant = ANT1_2G;
 456                 else
 457                         tx_ant = ANT2_2G;
 458         }
 459
 460         fat_tab->antsel_a[mac_id] = tx_ant & BIT(0);
 461         fat_tab->antsel_b[mac_id] = (tx_ant & BIT(1)) >> 1;
 462         fat_tab->antsel_c[mac_id] = (tx_ant & BIT(2)) >> 2;
 463
 464         PHYDM_DBG(dm, DBG_ANT_DIV,
 465                   "[Set TX-DESC value]: mac_id:(( %d )),  tx_ant = (( %s ))\n",
 466                   mac_id, (ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
 467 #if 0
 468         /* PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=(( 3'b%d%d%d ))\n",fat_tab->antsel_c[mac_id] , fat_tab->antsel_b[mac_id] , fat_tab->antsel_a[mac_id] ); */
 469 #endif
 470 }
 471
 472 #ifdef BEAMFORMING_SUPPORT
 473 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
 474
 475 void odm_bdc_init(
 476         void *dm_void)
 477 {
 478         struct dm_struct *dm = (struct dm_struct *)dm_void;
 479         struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
 480
 481         PHYDM_DBG(dm, DBG_ANT_DIV, "\n[ BDC Initialization......]\n");
 482         dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
 483         dm_bdc_table->bdc_mode = BDC_MODE_NULL;
 484         dm_bdc_table->bdc_try_flag = 0;
 485         dm_bdc_table->bd_ccoex_type_wbfer = 0;
 486         dm->bdc_holdstate = 0xff;
 487
 488         if (dm->support_ic_type == ODM_RTL8192E) {
 489                 odm_set_bb_reg(dm, R_0xd7c, 0x0FFFFFFF, 0x1081008);
 490                 odm_set_bb_reg(dm, R_0xd80, 0x0FFFFFFF, 0);
 491         } else if (dm->support_ic_type == ODM_RTL8812) {
 492                 odm_set_bb_reg(dm, R_0x9b0, 0x0FFFFFFF, 0x1081008); /* @0x9b0[30:0] = 01081008 */
 493                 odm_set_bb_reg(dm, R_0x9b4, 0x0FFFFFFF, 0); /* @0x9b4[31:0] = 00000000 */
 494         }
 495 }
 496
 497 void odm_CSI_on_off(
 498         void *dm_void,
 499         u8 CSI_en)
 500 {
 501         struct dm_struct *dm = (struct dm_struct *)dm_void;
 502         if (CSI_en == CSI_ON) {
 503                 if (dm->support_ic_type == ODM_RTL8192E)
 504                         odm_set_mac_reg(dm, R_0xd84, BIT(11), 1); /* @0xd84[11]=1 */
 505                 else if (dm->support_ic_type == ODM_RTL8812)
 506                         odm_set_mac_reg(dm, R_0x9b0, BIT(31), 1); /* @0x9b0[31]=1 */
 507
 508         } else if (CSI_en == CSI_OFF) {
 509                 if (dm->support_ic_type == ODM_RTL8192E)
 510                         odm_set_mac_reg(dm, R_0xd84, BIT(11), 0); /* @0xd84[11]=0 */
 511                 else if (dm->support_ic_type == ODM_RTL8812)
 512                         odm_set_mac_reg(dm, R_0x9b0, BIT(31), 0); /* @0x9b0[31]=0 */
 513         }
 514 }
 515
 516 void odm_bd_ccoex_type_with_bfer_client(
 517         void *dm_void,
 518         u8 swch)
 519 {
 520         struct dm_struct *dm = (struct dm_struct *)dm_void;
 521         struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
 522         u8 bd_ccoex_type_wbfer;
 523
 524         if (swch == DIVON_CSIOFF) {
 525                 PHYDM_DBG(dm, DBG_ANT_DIV,
 526                           "[BDCcoexType: 1] {DIV,CSI} ={1,0}\n");
 527                 bd_ccoex_type_wbfer = 1;
 528
 529                 if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
 530                         odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
 531                         odm_CSI_on_off(dm, CSI_OFF);
 532                         dm_bdc_table->bd_ccoex_type_wbfer = 1;
 533                 }
 534         } else if (swch == DIVOFF_CSION) {
 535                 PHYDM_DBG(dm, DBG_ANT_DIV,
 536                           "[BDCcoexType: 2] {DIV,CSI} ={0,1}\n");
 537                 bd_ccoex_type_wbfer = 2;
 538
 539                 if (bd_ccoex_type_wbfer != dm_bdc_table->bd_ccoex_type_wbfer) {
 540                         odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
 541                         odm_CSI_on_off(dm, CSI_ON);
 542                         dm_bdc_table->bd_ccoex_type_wbfer = 2;
 543                 }
 544         }
 545 }
 546
 547 void odm_bf_ant_div_mode_arbitration(
 548         void *dm_void)
 549 {
 550         struct dm_struct *dm = (struct dm_struct *)dm_void;
 551         struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
 552         u8 current_bdc_mode;
 553
 554 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
 555         PHYDM_DBG(dm, DBG_ANT_DIV, "\n");
 556
 557         /* @2 mode 1 */
 558         if (dm_bdc_table->num_txbfee_client != 0 && dm_bdc_table->num_txbfer_client == 0) {
 559                 current_bdc_mode = BDC_MODE_1;
 560
 561                 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
 562                         dm_bdc_table->bdc_mode = BDC_MODE_1;
 563                         odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
 564                         dm_bdc_table->bdc_rx_idle_update_counter = 1;
 565                         PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode1 ))\n");
 566                 }
 567
 568                 PHYDM_DBG(dm, DBG_ANT_DIV,
 569                           "[Antdiv + BF coextance mode] : (( Mode1 ))\n");
 570         }
 571         /* @2 mode 2 */
 572         else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client != 0)) {
 573                 current_bdc_mode = BDC_MODE_2;
 574
 575                 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
 576                         dm_bdc_table->bdc_mode = BDC_MODE_2;
 577                         dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
 578                         dm_bdc_table->bdc_try_flag = 0;
 579                         PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode2 ))\n");
 580                 }
 581                 PHYDM_DBG(dm, DBG_ANT_DIV,
 582                           "[Antdiv + BF coextance mode] : (( Mode2 ))\n");
 583         }
 584         /* @2 mode 3 */
 585         else if ((dm_bdc_table->num_txbfee_client != 0) && (dm_bdc_table->num_txbfer_client != 0)) {
 586                 current_bdc_mode = BDC_MODE_3;
 587
 588                 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
 589                         dm_bdc_table->bdc_mode = BDC_MODE_3;
 590                         dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
 591                         dm_bdc_table->bdc_try_flag = 0;
 592                         dm_bdc_table->bdc_rx_idle_update_counter = 1;
 593                         PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode3 ))\n");
 594                 }
 595
 596                 PHYDM_DBG(dm, DBG_ANT_DIV,
 597                           "[Antdiv + BF coextance mode] : (( Mode3 ))\n");
 598         }
 599         /* @2 mode 4 */
 600         else if ((dm_bdc_table->num_txbfee_client == 0) && (dm_bdc_table->num_txbfer_client == 0)) {
 601                 current_bdc_mode = BDC_MODE_4;
 602
 603                 if (current_bdc_mode != dm_bdc_table->bdc_mode) {
 604                         dm_bdc_table->bdc_mode = BDC_MODE_4;
 605                         odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
 606                         PHYDM_DBG(dm, DBG_ANT_DIV, "Change to (( Mode4 ))\n");
 607                 }
 608
 609                 PHYDM_DBG(dm, DBG_ANT_DIV,
 610                           "[Antdiv + BF coextance mode] : (( Mode4 ))\n");
 611         }
 612 #endif
 613 }
 614
 615 void odm_div_train_state_setting(
 616         void *dm_void)
 617 {
 618         struct dm_struct *dm = (struct dm_struct *)dm_void;
 619         struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
 620
 621         PHYDM_DBG(dm, DBG_ANT_DIV,
 622                   "\n*****[S T A R T ]*****  [2-0. DIV_TRAIN_STATE]\n");
 623         dm_bdc_table->bdc_try_counter = 2;
 624         dm_bdc_table->bdc_try_flag = 1;
 625         dm_bdc_table->BDC_state = bdc_bfer_train_state;
 626         odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
 627 }
 628
 629 void odm_bd_ccoex_bfee_rx_div_arbitration(
 630         void *dm_void)
 631 {
 632         struct dm_struct *dm = (struct dm_struct *)dm_void;
 633         struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
 634         boolean stop_bf_flag;
 635         u8 bdc_active_mode;
 636
 637 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
 638
 639         PHYDM_DBG(dm, DBG_ANT_DIV,
 640                   "***{ num_BFee,  num_BFer, num_client}  = (( %d  ,  %d  ,  %d))\n",
 641                   dm_bdc_table->num_txbfee_client,
 642                   dm_bdc_table->num_txbfer_client, dm_bdc_table->num_client);
 643         PHYDM_DBG(dm, DBG_ANT_DIV,
 644                   "***{ num_BF_tars,  num_DIV_tars }  = ((  %d  ,  %d ))\n",
 645                   dm_bdc_table->num_bf_tar, dm_bdc_table->num_div_tar);
 646
 647         /* @2 [ MIB control ] */
 648         if (dm->bdc_holdstate == 2) {
 649                 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
 650                 dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
 651                 PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ BF STATE]\n");
 652                 return;
 653         } else if (dm->bdc_holdstate == 1) {
 654                 dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
 655                 odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
 656                 PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
 657                 return;
 658         }
 659
 660         /* @------------------------------------------------------------ */
 661
 662         /* @2 mode 2 & 3 */
 663         if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
 664                 PHYDM_DBG(dm, DBG_ANT_DIV,
 665                           "\n{ Try_flag,  Try_counter } = {  %d , %d  }\n",
 666                           dm_bdc_table->bdc_try_flag,
 667                           dm_bdc_table->bdc_try_counter);
 668                 PHYDM_DBG(dm, DBG_ANT_DIV, "BDCcoexType = (( %d ))\n\n",
 669                           dm_bdc_table->bd_ccoex_type_wbfer);
 670
 671                 /* @All Client have Bfer-Cap------------------------------- */
 672                 if (dm_bdc_table->num_txbfer_client == dm_bdc_table->num_client) { /* @BFer STA Only?: yes */
 673                         PHYDM_DBG(dm, DBG_ANT_DIV,
 674                                   "BFer STA only?  (( Yes ))\n");
 675                         dm_bdc_table->bdc_try_flag = 0;
 676                         dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
 677                         odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
 678                         return;
 679                 } else
 680                         PHYDM_DBG(dm, DBG_ANT_DIV,
 681                                   "BFer STA only?  (( No ))\n");
 682                 if (dm_bdc_table->is_all_bf_sta_idle == false && dm_bdc_table->is_all_div_sta_idle == true) {
 683                         PHYDM_DBG(dm, DBG_ANT_DIV,
 684                                   "All DIV-STA are idle, but BF-STA not\n");
 685                         dm_bdc_table->bdc_try_flag = 0;
 686                         dm_bdc_table->BDC_state = bdc_bfer_train_state;
 687                         odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
 688                         return;
 689                 } else if (dm_bdc_table->is_all_bf_sta_idle == true && dm_bdc_table->is_all_div_sta_idle == false) {
 690                         PHYDM_DBG(dm, DBG_ANT_DIV,
 691                                   "All BF-STA are idle, but DIV-STA not\n");
 692                         dm_bdc_table->bdc_try_flag = 0;
 693                         dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
 694                         odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
 695                         return;
 696                 }
 697
 698                 /* Select active mode-------------------------------------- */
 699                 if (dm_bdc_table->num_bf_tar == 0) { /* Selsect_1,  Selsect_2 */
 700                         if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
 701                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 702                                           "Select active mode (( 1 ))\n");
 703                                 dm_bdc_table->bdc_active_mode = 1;
 704                         } else {
 705                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 706                                           "Select active mode  (( 2 ))\n");
 707                                 dm_bdc_table->bdc_active_mode = 2;
 708                         }
 709                         dm_bdc_table->bdc_try_flag = 0;
 710                         dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
 711                         odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
 712                         return;
 713                 } else { /* num_bf_tar > 0 */
 714                         if (dm_bdc_table->num_div_tar == 0) { /* Selsect_3 */
 715                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 716                                           "Select active mode (( 3 ))\n");
 717                                 dm_bdc_table->bdc_active_mode = 3;
 718                                 dm_bdc_table->bdc_try_flag = 0;
 719                                 dm_bdc_table->BDC_state = bdc_bfer_train_state;
 720                                 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
 721                                 return;
 722                         } else { /* Selsect_4 */
 723                                 bdc_active_mode = 4;
 724                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 725                                           "Select active mode (( 4 ))\n");
 726
 727                                 if (bdc_active_mode != dm_bdc_table->bdc_active_mode) {
 728                                         dm_bdc_table->bdc_active_mode = 4;
 729                                         PHYDM_DBG(dm, DBG_ANT_DIV, "Change to active mode (( 4 ))  &  return!!!\n");
 730                                         return;
 731                                 }
 732                         }
 733                 }
 734
 735 #if 1
 736                 if (dm->bdc_holdstate == 0xff) {
 737                         dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
 738                         odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
 739                         PHYDM_DBG(dm, DBG_ANT_DIV, "Force in [ DIV STATE]\n");
 740                         return;
 741                 }
 742 #endif
 743
 744                 /* @Does Client number changed ? ------------------------------- */
 745                 if (dm_bdc_table->num_client != dm_bdc_table->pre_num_client) {
 746                         dm_bdc_table->bdc_try_flag = 0;
 747                         dm_bdc_table->BDC_state = BDC_DIV_TRAIN_STATE;
 748                         PHYDM_DBG(dm, DBG_ANT_DIV,
 749                                   "[  The number of client has been changed !!!]   return to (( BDC_DIV_TRAIN_STATE ))\n");
 750                 }
 751                 dm_bdc_table->pre_num_client = dm_bdc_table->num_client;
 752
 753                 if (dm_bdc_table->bdc_try_flag == 0) {
 754                         /* @2 DIV_TRAIN_STATE (mode 2-0) */
 755                         if (dm_bdc_table->BDC_state == BDC_DIV_TRAIN_STATE)
 756                                 odm_div_train_state_setting(dm);
 757                         /* @2 BFer_TRAIN_STATE (mode 2-1) */
 758                         else if (dm_bdc_table->BDC_state == bdc_bfer_train_state) {
 759                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 760                                           "*****[2-1. BFer_TRAIN_STATE ]*****\n");
 761
 762 #if 0
 763                                 /* @if(dm_bdc_table->num_bf_tar==0) */
 764                                 /* @{ */
 765                                 /*      PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( No )),   [ bdc_bfer_train_state ] >> [BDC_DIV_TRAIN_STATE]\n"); */
 766                                 /*      odm_div_train_state_setting( dm); */
 767                                 /* @} */
 768                                 /* else */ /* num_bf_tar != 0 */
 769                                 /* @{ */
 770 #endif
 771                                 dm_bdc_table->bdc_try_counter = 2;
 772                                 dm_bdc_table->bdc_try_flag = 1;
 773                                 dm_bdc_table->BDC_state = BDC_DECISION_STATE;
 774                                 odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
 775                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 776                                           "BF_tars exist?  : (( Yes )),   [ bdc_bfer_train_state ] >> [BDC_DECISION_STATE]\n");
 777                                 /* @} */
 778                         }
 779                         /* @2 DECISION_STATE (mode 2-2) */
 780                         else if (dm_bdc_table->BDC_state == BDC_DECISION_STATE) {
 781                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 782                                           "*****[2-2. DECISION_STATE]*****\n");
 783 #if 0
 784                                 /* @if(dm_bdc_table->num_bf_tar==0) */
 785                                 /* @{ */
 786                                 /*      ODM_AntDiv_Printk(("BF_tars exist?  : (( No )),   [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE]\n")); */
 787                                 /*      odm_div_train_state_setting( dm); */
 788                                 /* @} */
 789                                 /* else */ /* num_bf_tar != 0 */
 790                                 /* @{ */
 791 #endif
 792                                 if (dm_bdc_table->BF_pass == false || dm_bdc_table->DIV_pass == false)
 793                                         stop_bf_flag = true;
 794                                 else
 795                                         stop_bf_flag = false;
 796
 797                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 798                                           "BF_tars exist?  : (( Yes )),  {BF_pass, DIV_pass, stop_bf_flag }  = { %d, %d, %d }\n",
 799                                           dm_bdc_table->BF_pass,
 800                                           dm_bdc_table->DIV_pass, stop_bf_flag);
 801
 802                                 if (stop_bf_flag == true) { /* @DIV_en */
 803                                         dm_bdc_table->bdc_hold_counter = 10; /* @20 */
 804                                         odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
 805                                         dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
 806                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[ stop_bf_flag= ((true)),   BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
 807                                 } else { /* @BF_en */
 808                                         dm_bdc_table->bdc_hold_counter = 10; /* @20 */
 809                                         odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
 810                                         dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
 811                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[stop_bf_flag= ((false)),   BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE]\n");
 812                                 }
 813                                 /* @} */
 814                         }
 815                         /* @2 BF-HOLD_STATE (mode 2-3) */
 816                         else if (dm_bdc_table->BDC_state == BDC_BF_HOLD_STATE) {
 817                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 818                                           "*****[2-3. BF_HOLD_STATE ]*****\n");
 819
 820                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 821                                           "bdc_hold_counter = (( %d ))\n",
 822                                           dm_bdc_table->bdc_hold_counter);
 823
 824                                 if (dm_bdc_table->bdc_hold_counter == 1) {
 825                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
 826                                         odm_div_train_state_setting(dm);
 827                                 } else {
 828                                         dm_bdc_table->bdc_hold_counter--;
 829
 830 #if 0
 831                                         /* @if(dm_bdc_table->num_bf_tar==0) */
 832                                         /* @{ */
 833                                         /*      PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( No )),   [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n"); */
 834                                         /*      odm_div_train_state_setting( dm); */
 835                                         /* @} */
 836                                         /* else */ /* num_bf_tar != 0 */
 837                                         /* @{ */
 838                                         /* PHYDM_DBG(dm,DBG_ANT_DIV, "BF_tars exist?  : (( Yes ))\n"); */
 839 #endif
 840                                         dm_bdc_table->BDC_state = BDC_BF_HOLD_STATE;
 841                                         odm_bd_ccoex_type_with_bfer_client(dm, DIVOFF_CSION);
 842                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE]\n");
 843                                         /* @} */
 844                                 }
 845                         }
 846                         /* @2 DIV-HOLD_STATE (mode 2-4) */
 847                         else if (dm_bdc_table->BDC_state == BDC_DIV_HOLD_STATE) {
 848                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 849                                           "*****[2-4. DIV_HOLD_STATE ]*****\n");
 850
 851                                 PHYDM_DBG(dm, DBG_ANT_DIV,
 852                                           "bdc_hold_counter = (( %d ))\n",
 853                                           dm_bdc_table->bdc_hold_counter);
 854
 855                                 if (dm_bdc_table->bdc_hold_counter == 1) {
 856                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE]\n");
 857                                         odm_div_train_state_setting(dm);
 858                                 } else {
 859                                         dm_bdc_table->bdc_hold_counter--;
 860                                         dm_bdc_table->BDC_state = BDC_DIV_HOLD_STATE;
 861                                         odm_bd_ccoex_type_with_bfer_client(dm, DIVON_CSIOFF);
 862                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE]\n");
 863                                 }
 864                         }
 865
 866                 } else if (dm_bdc_table->bdc_try_flag == 1) {
 867                         /* @2 Set Training counter */
 868                         if (dm_bdc_table->bdc_try_counter > 1) {
 869                                 dm_bdc_table->bdc_try_counter--;
 870                                 if (dm_bdc_table->bdc_try_counter == 1)
 871                                         dm_bdc_table->bdc_try_flag = 0;
 872
 873                                 PHYDM_DBG(dm, DBG_ANT_DIV, "Training !!\n");
 874                                 /* return ; */
 875                         }
 876                 }
 877         }
 878
 879         PHYDM_DBG(dm, DBG_ANT_DIV, "\n[end]\n");
 880
 881 #endif /* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
 882 }
 883
 884 #endif
 885 #endif /* @#ifdef BEAMFORMING_SUPPORT */
 886
 887 #if (RTL8188E_SUPPORT == 1)
 888
 889 void odm_rx_hw_ant_div_init_88e(
 890         void *dm_void)
 891 {
 892         struct dm_struct *dm = (struct dm_struct *)dm_void;
 893         u32 value32;
 894         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
 895
 896 #if 0
 897         if (*dm->mp_mode == true) {
 898                 odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* @disable HW AntDiv */
 899                 odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);  /* @1:CG, 0:CS */
 900                 return;
 901         }
 902 #endif
 903
 904         PHYDM_DBG(dm, DBG_ANT_DIV,
 905                   "***8188E AntDiv_Init =>  ant_div_type=[CGCS_RX_HW_ANTDIV]\n");
 906
 907         /* @MAC setting */
 908         value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
 909         odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
 910         /* Pin Settings */
 911         odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0          */ /* antsel antselb by HW */
 912         odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0      */ /* antsel2 by HW */
 913         odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 1); /* regb2c[22]=1'b0       */ /* disable CS/CG switch */
 914         odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1       */ /* output at CG only */
 915         /* OFDM Settings */
 916         odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
 917         /* @CCK Settings */
 918         odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* @Fix CCK PHY status report issue */
 919         odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
 920
 921         odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0001); /* @antenna mapping table */
 922
 923         fat_tab->enable_ctrl_frame_antdiv = 1;
 924 }
 925
 926 void odm_trx_hw_ant_div_init_88e(
 927         void *dm_void)
 928 {
 929         struct dm_struct *dm = (struct dm_struct *)dm_void;
 930         u32 value32;
 931         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
 932
 933 #if 0
 934         if (*dm->mp_mode == true) {
 935                 odm_set_bb_reg(dm, ODM_REG_IGI_A_11N, BIT(7), 0); /* @disable HW AntDiv */
 936                 odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(5) | BIT4 | BIT3, 0); /* @Default RX   (0/1) */
 937                 return;
 938         }
 939 #endif
 940
 941         PHYDM_DBG(dm, DBG_ANT_DIV,
 942                   "***8188E AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV (SPDT)]\n");
 943
 944         /* @MAC setting */
 945         value32 = odm_get_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD);
 946         odm_set_mac_reg(dm, ODM_REG_ANTSEL_PIN_11N, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
 947         /* Pin Settings */
 948         odm_set_bb_reg(dm, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0          */ /* antsel antselb by HW */
 949         odm_set_bb_reg(dm, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0); /* reg864[10]=1'b0      */ /* antsel2 by HW */
 950         odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(22), 0); /* regb2c[22]=1'b0       */ /* disable CS/CG switch */
 951         odm_set_bb_reg(dm, ODM_REG_LNA_SWITCH_11N, BIT(31), 1); /* regb2c[31]=1'b1       */ /* output at CG only */
 952         /* OFDM Settings */
 953         odm_set_bb_reg(dm, ODM_REG_ANTDIV_PARA1_11N, MASKDWORD, 0x000000a0);
 954         /* @CCK Settings */
 955         odm_set_bb_reg(dm, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1); /* @Fix CCK PHY status report issue */
 956         odm_set_bb_reg(dm, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
 957
 958         /* @antenna mapping table */
 959         if (!dm->is_mp_chip) { /* testchip */
 960                 odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
 961                 odm_set_bb_reg(dm, ODM_REG_RX_DEFAULT_A_11N, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
 962         } else /* @MPchip */
 963                 odm_set_bb_reg(dm, ODM_REG_ANT_MAPPING1_11N, MASKDWORD, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/
 964
 965         fat_tab->enable_ctrl_frame_antdiv = 1;
 966 }
 967
 968 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
 969 void odm_smart_hw_ant_div_init_88e(
 970         void *dm_void)
 971 {
 972         struct dm_struct *dm = (struct dm_struct *)dm_void;
 973         u32 value32, i;
 974         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
 975
 976         PHYDM_DBG(dm, DBG_ANT_DIV,
 977                   "***8188E AntDiv_Init =>  ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
 978
 979 #if 0
 980         if (*dm->mp_mode == true) {
 981                 PHYDM_DBG(dm, ODM_COMP_INIT, "dm->ant_div_type: %d\n",
 982                           dm->ant_div_type);
 983                 return;
 984         }
 985 #endif
 986
 987         fat_tab->train_idx = 0;
 988         fat_tab->fat_state = FAT_PREPARE_STATE;
 989
 990         dm->fat_comb_a = 5;
 991         dm->antdiv_intvl = 0x64; /* @100ms */
 992
 993         for (i = 0; i < 6; i++)
 994                 fat_tab->bssid[i] = 0;
 995         for (i = 0; i < (dm->fat_comb_a); i++) {
 996                 fat_tab->ant_sum_rssi[i] = 0;
 997                 fat_tab->ant_rssi_cnt[i] = 0;
 998                 fat_tab->ant_ave_rssi[i] = 0;
 999         }
1000
1001         /* @MAC setting */
1002         value32 = odm_get_mac_reg(dm, R_0x4c, MASKDWORD);
1003         odm_set_mac_reg(dm, R_0x4c, MASKDWORD, value32 | (BIT(23) | BIT(25))); /* Reg4C[25]=1, Reg4C[23]=1 for pin output */
1004         value32 = odm_get_mac_reg(dm, R_0x7b4, MASKDWORD);
1005         odm_set_mac_reg(dm, R_0x7b4, MASKDWORD, value32 | (BIT(16) | BIT(17))); /* Reg7B4[16]=1 enable antenna training, Reg7B4[17]=1 enable A2 match */
1006         /* value32 = platform_efio_read_4byte(adapter, 0x7B4); */
1007         /* platform_efio_write_4byte(adapter, 0x7b4, value32|BIT(18));   */ /* append MACID in reponse packet */
1008
1009         /* @Match MAC ADDR */
1010         odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, 0);
1011         odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, 0);
1012
1013         odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* reg870[8]=1'b0, reg870[9]=1'b0               */ /* antsel antselb by HW */
1014         odm_set_bb_reg(dm, R_0x864, BIT(10), 0); /* reg864[10]=1'b0      */ /* antsel2 by HW */
1015         odm_set_bb_reg(dm, R_0xb2c, BIT(22), 0); /* regb2c[22]=1'b0      */ /* disable CS/CG switch */
1016         odm_set_bb_reg(dm, R_0xb2c, BIT(31), 0); /* regb2c[31]=1'b1      */ /* output at CS only */
1017         odm_set_bb_reg(dm, R_0xca4, MASKDWORD, 0x000000a0);
1018
1019         /* @antenna mapping table */
1020         if (dm->fat_comb_a == 2) {
1021                 if (!dm->is_mp_chip) { /* testchip */
1022                         odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 1); /* Reg858[10:8]=3'b001 */
1023                         odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 2); /* Reg858[13:11]=3'b010 */
1024                 } else { /* @MPchip */
1025                         odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 1);
1026                         odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2);
1027                 }
1028         } else {
1029                 if (!dm->is_mp_chip) { /* testchip */
1030                         odm_set_bb_reg(dm, R_0x858, BIT(10) | BIT(9) | BIT(8), 0); /* Reg858[10:8]=3'b000 */
1031                         odm_set_bb_reg(dm, R_0x858, BIT(13) | BIT(12) | BIT(11), 1); /* Reg858[13:11]=3'b001 */
1032                         odm_set_bb_reg(dm, R_0x878, BIT(16), 0);
1033                         odm_set_bb_reg(dm, R_0x858, BIT(15) | BIT(14), 2); /* @(Reg878[0],Reg858[14:15])=3'b010 */
1034                         odm_set_bb_reg(dm, R_0x878, BIT(19) | BIT(18) | BIT(17), 3); /* Reg878[3:1]=3b'011 */
1035                         odm_set_bb_reg(dm, R_0x878, BIT(22) | BIT(21) | BIT(20), 4); /* Reg878[6:4]=3b'100 */
1036                         odm_set_bb_reg(dm, R_0x878, BIT(25) | BIT(24) | BIT(23), 5); /* Reg878[9:7]=3b'101 */
1037                         odm_set_bb_reg(dm, R_0x878, BIT(28) | BIT(27) | BIT(26), 6); /* Reg878[12:10]=3b'110 */
1038                         odm_set_bb_reg(dm, R_0x878, BIT(31) | BIT(30) | BIT(29), 7); /* Reg878[15:13]=3b'111 */
1039                 } else { /* @MPchip */
1040                         odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 4); /* @0: 3b'000 */
1041                         odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 2); /* @1: 3b'001 */
1042                         odm_set_bb_reg(dm, R_0x914, MASKBYTE2, 0); /* @2: 3b'010 */
1043                         odm_set_bb_reg(dm, R_0x914, MASKBYTE3, 1); /* @3: 3b'011 */
1044                         odm_set_bb_reg(dm, R_0x918, MASKBYTE0, 3); /* @4: 3b'100 */
1045                         odm_set_bb_reg(dm, R_0x918, MASKBYTE1, 5); /* @5: 3b'101 */
1046                         odm_set_bb_reg(dm, R_0x918, MASKBYTE2, 6); /* @6: 3b'110 */
1047                         odm_set_bb_reg(dm, R_0x918, MASKBYTE3, 255); /* @7: 3b'111 */
1048                 }
1049         }
1050
1051         /* @Default ant setting when no fast training */
1052         odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), 0); /* @Default RX */
1053         odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), 1); /* Optional RX */
1054         odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), 0); /* @Default TX */
1055
1056         /* @Enter Traing state */
1057         odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), (dm->fat_comb_a - 1)); /* reg864[2:0]=3'd6         */ /* ant combination=reg864[2:0]+1 */
1058
1059 #if 0
1060         /* SW Control */
1061         /* phy_set_bb_reg(adapter, 0x864, BIT10, 1); */
1062         /* phy_set_bb_reg(adapter, 0x870, BIT9, 1); */
1063         /* phy_set_bb_reg(adapter, 0x870, BIT8, 1); */
1064         /* phy_set_bb_reg(adapter, 0x864, BIT11, 1); */
1065         /* phy_set_bb_reg(adapter, 0x860, BIT9, 0); */
1066         /* phy_set_bb_reg(adapter, 0x860, BIT8, 0); */
1067 #endif
1068 }
1069 #endif
1070
1071 #endif /* @#if (RTL8188E_SUPPORT == 1) */
1072
1073 #if (RTL8192E_SUPPORT == 1)
1074 void odm_rx_hw_ant_div_init_92e(
1075         void *dm_void)
1076 {
1077         struct dm_struct *dm = (struct dm_struct *)dm_void;
1078         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1079
1080 #if 0
1081         if (*dm->mp_mode == true) {
1082                 odm_ant_div_on_off(dm, ANTDIV_OFF);
1083                 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
1084                 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */
1085                 return;
1086         }
1087 #endif
1088
1089         PHYDM_DBG(dm, DBG_ANT_DIV,
1090                   "***8192E AntDiv_Init =>  ant_div_type=[CGCS_RX_HW_ANTDIV]\n");
1091
1092         /* Pin Settings */
1093         odm_set_bb_reg(dm, R_0x870, BIT(8), 0); /* reg870[8]=1'b0,     */ /* "antsel" is controled by HWs */
1094         odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); /* regc50[8]=1'b1   */ /* " CS/CG switching" is controled by HWs */
1095
1096         /* @Mapping table */
1097         odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */
1098
1099         /* OFDM Settings */
1100         odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1101         odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1102
1103         /* @CCK Settings */
1104         odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
1105         odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1106         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */
1107         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
1108
1109 #ifdef ODM_EVM_ENHANCE_ANTDIV
1110         phydm_evm_sw_antdiv_init(dm);
1111 #endif
1112 }
1113
1114 void odm_trx_hw_ant_div_init_92e(
1115         void *dm_void)
1116 {
1117         struct dm_struct *dm = (struct dm_struct *)dm_void;
1118
1119 #if 0
1120         if (*dm->mp_mode == true) {
1121                 odm_ant_div_on_off(dm, ANTDIV_OFF);
1122                 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
1123                 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */
1124                 return;
1125         }
1126 #endif
1127
1128         PHYDM_DBG(dm, DBG_ANT_DIV,
1129                   "***8192E AntDiv_Init =>  ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n");
1130
1131         /* @3 --RFE pin setting--------- */
1132         /* @[MAC] */
1133         odm_set_mac_reg(dm, R_0x38, BIT(11), 1); /* @DBG PAD Driving control (GPIO 8) */
1134         odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* path-A, RFE_CTRL_3 */
1135         odm_set_mac_reg(dm, R_0x4c, BIT(29), 1); /* path-A, RFE_CTRL_8 */
1136         /* @[BB] */
1137         odm_set_bb_reg(dm, R_0x944, BIT(3), 1); /* RFE_buffer */
1138         odm_set_bb_reg(dm, R_0x944, BIT(8), 1);
1139         odm_set_bb_reg(dm, R_0x940, BIT(7) | BIT(6), 0x0); /* r_rfe_path_sel_   (RFE_CTRL_3) */
1140         odm_set_bb_reg(dm, R_0x940, BIT(17) | BIT(16), 0x0); /* r_rfe_path_sel_   (RFE_CTRL_8) */
1141         odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer */
1142         odm_set_bb_reg(dm, R_0x92c, BIT(3), 0); /* rfe_inv  (RFE_CTRL_3) */
1143         odm_set_bb_reg(dm, R_0x92c, BIT(8), 1); /* rfe_inv  (RFE_CTRL_8) */
1144         odm_set_bb_reg(dm, R_0x930, 0xF000, 0x8); /* path-A, RFE_CTRL_3 */
1145         odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
1146         /* @3 ------------------------- */
1147
1148         /* Pin Settings */
1149         odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* path-A        */ /* disable CS/CG switch */
1150
1151 #if 0
1152         /* @Let it follows PHY_REG for bit9 setting */
1153         if (dm->priv->pshare->rf_ft_var.use_ext_pa || dm->priv->pshare->rf_ft_var.use_ext_lna)
1154                 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1); /* path-A       output at CS */
1155         else
1156                 odm_set_bb_reg(dm, R_0xc50, BIT(9), 0); /* path-A       output at CG ->normal power */
1157 #endif
1158
1159         odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* path-A*/ /* antsel antselb by HW */
1160         odm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A      */ /* antsel2 by HW */
1161
1162         /* @Mapping table */
1163         odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */
1164
1165         /* OFDM Settings */
1166         odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1167         odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1168
1169         /* @CCK Settings */
1170         odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
1171         odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1172         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */
1173         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
1174
1175 #ifdef ODM_EVM_ENHANCE_ANTDIV
1176         phydm_evm_sw_antdiv_init(dm);
1177 #endif
1178 }
1179
1180 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
1181 void odm_smart_hw_ant_div_init_92e(
1182         void *dm_void)
1183 {
1184         struct dm_struct *dm = (struct dm_struct *)dm_void;
1185
1186         PHYDM_DBG(dm, DBG_ANT_DIV,
1187                   "***8192E AntDiv_Init =>  ant_div_type=[CG_TRX_SMART_ANTDIV]\n");
1188 }
1189 #endif
1190
1191 #endif /* @#if (RTL8192E_SUPPORT == 1) */
1192
1193 #if (RTL8192F_SUPPORT == 1)
1194 void odm_rx_hw_ant_div_init_92f(
1195         void *dm_void)
1196 {
1197         struct dm_struct *dm = (struct dm_struct *)dm_void;
1198         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1199
1200         PHYDM_DBG(dm, DBG_ANT_DIV,
1201                   "***8192F AntDiv_Init =>  ant_div_type=[CGCS_RX_HW_ANTDIV]\n");
1202
1203         /* Pin Settings */
1204         odm_set_bb_reg(dm, R_0x870, BIT(8), 0); /* reg870[8]=1'b0, "antsel" is controlled by HWs */
1205         odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); /* regc50[8]=1'b1, " CS/CG switching" is controlled by HWs */
1206
1207         /* @Mapping table */
1208         odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */
1209
1210         /* OFDM Settings */
1211         odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1212         odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1213
1214         /* @CCK Settings */
1215         odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
1216         odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1217         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */
1218         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
1219
1220 #ifdef ODM_EVM_ENHANCE_ANTDIV
1221         phydm_evm_sw_antdiv_init(dm);
1222 #endif
1223 }
1224
1225 void odm_trx_hw_ant_div_init_92f(
1226         void *dm_void)
1227
1228 {
1229         struct dm_struct *dm = (struct dm_struct *)dm_void;
1230
1231         PHYDM_DBG(dm, DBG_ANT_DIV,
1232                   "***8192F AntDiv_Init =>  ant_div_type=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n");
1233         /* @3 --RFE pin setting--------- */
1234         /* @[MAC] */
1235         odm_set_mac_reg(dm, R_0x1048, BIT(0), 1); /* @DBG PAD Driving control (gpioA_0) */
1236         odm_set_mac_reg(dm, R_0x1048, BIT(1), 1); /* @DBG PAD Driving control (gpioA_1) */
1237         odm_set_mac_reg(dm, R_0x4c, BIT(24), 1);
1238         odm_set_mac_reg(dm, R_0x1038, BIT(25) | BIT(24) | BIT(23), 0); /* @gpioA_0,gpioA_1*/
1239         odm_set_mac_reg(dm, R_0x4c, BIT(23), 0);
1240         /* @[BB] */
1241         odm_set_bb_reg(dm, R_0x944, BIT(8), 1); /* output enable */
1242         odm_set_bb_reg(dm, R_0x944, BIT(9), 1);
1243         odm_set_bb_reg(dm, R_0x940, BIT(16) | BIT(17), 0x0); /* r_rfe_path_sel_   (RFE_CTRL_8) */
1244         odm_set_bb_reg(dm, R_0x940, BIT(18) | BIT(19), 0x0); /* r_rfe_path_sel_   (RFE_CTRL_9) */
1245         odm_set_bb_reg(dm, R_0x944, BIT(31), 0); /* RFE_buffer_en */
1246         odm_set_bb_reg(dm, R_0x92c, BIT(8), 0); /* rfe_inv  (RFE_CTRL_8) */
1247         odm_set_bb_reg(dm, R_0x92c, BIT(9), 1); /* rfe_inv  (RFE_CTRL_9) */
1248         odm_set_bb_reg(dm, R_0x934, 0xF, 0x8); /* path-A, RFE_CTRL_8 */
1249         odm_set_bb_reg(dm, R_0x934, 0xF0, 0x8); /* path-A, RFE_CTRL_9 */
1250         /* @3 ------------------------- */
1251
1252         /* Pin Settings */
1253         odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);/* path-A,disable CS/CG switch */
1254         odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0); /* path-A*, antsel antselb by HW */
1255         odm_set_bb_reg(dm, R_0xb38, BIT(10), 0); /* path-A ,antsel2 by HW */
1256
1257         /* @Mapping table */
1258         odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */
1259
1260         /* OFDM Settings */
1261         odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1262         odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1263
1264         /* @CCK Settings */
1265         odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
1266         odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1267         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */
1268         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
1269
1270 #ifdef ODM_EVM_ENHANCE_ANTDIV
1271         phydm_evm_sw_antdiv_init(dm);
1272 #endif
1273 }
1274
1275 #endif /* @#if (RTL8192F_SUPPORT == 1) */
1276
1277 #if (RTL8822B_SUPPORT == 1)
1278 void phydm_trx_hw_ant_div_init_22b(
1279         void *dm_void)
1280 {
1281         struct dm_struct *dm = (struct dm_struct *)dm_void;
1282
1283         PHYDM_DBG(dm, DBG_ANT_DIV,
1284                   "***8822B AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV]\n");
1285
1286         /* Pin Settings */
1287         odm_set_bb_reg(dm, R_0xcb8, BIT(21) | BIT(20), 0x1);
1288         odm_set_bb_reg(dm, R_0xcb8, BIT(23) | BIT(22), 0x1);
1289         odm_set_bb_reg(dm, R_0xc1c, BIT(7) | BIT(6), 0x0);
1290         /* @------------------------- */
1291
1292         /* @Mapping table */
1293         /* @antenna mapping table */
1294         odm_set_bb_reg(dm, R_0xca4, 0xFFFF, 0x0100);
1295
1296         /* OFDM Settings */
1297         /* thershold */
1298         odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0);
1299         /* @bias */
1300         odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0);
1301         odm_set_bb_reg(dm, R_0x668, BIT(3), 0x1);
1302
1303         /* @CCK Settings */
1304         /* Select which path to receive for CCK_1 & CCK_2 */
1305         odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0);
1306         /* @Fix CCK PHY status report issue */
1307         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1308         /* @CCK complete HW AntDiv within 64 samples */
1309         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1310         /* @BT Coexistence */
1311         /* @keep antsel_map when GNT_BT = 1 */
1312         odm_set_bb_reg(dm, R_0xcac, BIT(9), 1);
1313         /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1314         odm_set_bb_reg(dm, R_0x804, BIT(4), 1);
1315         /* response TX ant by RX ant */
1316         odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
1317 #if (defined(CONFIG_2T4R_ANTENNA))
1318         PHYDM_DBG(dm, DBG_ANT_DIV,
1319                   "***8822B AntDiv_Init =>  2T4R case\n");
1320         /* Pin Settings */
1321         odm_set_bb_reg(dm, R_0xeb8, BIT(21) | BIT(20), 0x1);
1322         odm_set_bb_reg(dm, R_0xeb8, BIT(23) | BIT(22), 0x1);
1323         odm_set_bb_reg(dm, R_0xe1c, BIT(7) | BIT(6), 0x0);
1324         /* @BT Coexistence */
1325         odm_set_bb_reg(dm, R_0xeac, BIT(9), 1);
1326         /* @keep antsel_map when GNT_BT = 1 */
1327         /* Mapping table */
1328         /* antenna mapping table */
1329         odm_set_bb_reg(dm, R_0xea4, 0xFFFF, 0x0100);
1330         /*odm_set_bb_reg(dm, R_0x900, 0x30000, 0x3);*/
1331 #endif
1332
1333 #ifdef ODM_EVM_ENHANCE_ANTDIV
1334         phydm_evm_sw_antdiv_init(dm);
1335 #endif
1336 }
1337 #endif /* @#if (RTL8822B_SUPPORT == 1) */
1338
1339 #if (RTL8197F_SUPPORT == 1)
1340 void phydm_rx_hw_ant_div_init_97f(
1341         void *dm_void)
1342 {
1343         struct dm_struct *dm = (struct dm_struct *)dm_void;
1344         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1345
1346 #if 0
1347         if (*dm->mp_mode == true) {
1348                 odm_ant_div_on_off(dm, ANTDIV_OFF);
1349                 odm_set_bb_reg(dm, R_0xc50, BIT(8), 0); /* r_rxdiv_enable_anta  regc50[8]=1'b0  0: control by c50[9] */
1350                 odm_set_bb_reg(dm, R_0xc50, BIT(9), 1);  /* @1:CG, 0:CS */
1351                 return;
1352         }
1353 #endif
1354         PHYDM_DBG(dm, DBG_ANT_DIV,
1355                   "***8197F AntDiv_Init =>  ant_div_type=[CGCS_RX_HW_ANTDIV]\n");
1356
1357         /* Pin Settings */
1358         odm_set_bb_reg(dm, R_0x870, BIT(8), 0); /* reg870[8]=1'b0,     */ /* "antsel" is controlled by HWs */
1359         odm_set_bb_reg(dm, R_0xc50, BIT(8), 1); /* regc50[8]=1'b1   */ /* " CS/CG switching" is controlled by HWs */
1360
1361         /* @Mapping table */
1362         odm_set_bb_reg(dm, R_0x914, 0xFFFF, 0x0100); /* @antenna mapping table */
1363
1364         /* OFDM Settings */
1365         odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xA0); /* thershold */
1366         odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x0); /* @bias */
1367
1368         /* @CCK Settings */
1369         odm_set_bb_reg(dm, R_0xa04, 0xF000000, 0); /* Select which path to receive for CCK_1 & CCK_2 */
1370         odm_set_bb_reg(dm, R_0xb34, BIT(30), 0); /* @(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0 */
1371         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* @Fix CCK PHY status report issue */
1372         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @CCK complete HW AntDiv within 64 samples */
1373
1374 #ifdef ODM_EVM_ENHANCE_ANTDIV
1375         phydm_evm_sw_antdiv_init(dm);
1376 #endif
1377 }
1378
1379 #endif //#if (RTL8197F_SUPPORT == 1)
1380 #if (RTL8723D_SUPPORT == 1)
1381 void odm_trx_hw_ant_div_init_8723d(
1382         void *dm_void)
1383 {
1384         struct dm_struct *dm = (struct dm_struct *)dm_void;
1385
1386         PHYDM_DBG(dm, DBG_ANT_DIV,
1387                   "[8723D] AntDiv_Init =>  ant_div_type=[S0S1_HW_TRX_AntDiv]\n");
1388
1389         /*@BT Coexistence*/
1390         /*@keep antsel_map when GNT_BT = 1*/
1391         odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
1392         /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1393         odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
1394         /* @Disable hw antsw & fast_train.antsw when BT TX/RX */
1395         odm_set_bb_reg(dm, R_0xe64, 0xFFFF0000, 0x000c);
1396
1397         odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
1398 #if 0
1399         /*PTA setting: WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL)*/
1400         /*odm_set_bb_reg(dm, R_0x948, BIT6, 0);*/
1401         /*odm_set_bb_reg(dm, R_0x948, BIT8, 0);*/
1402 #endif
1403         /*@GNT_WL tx*/
1404         odm_set_bb_reg(dm, R_0x950, BIT(29), 0);
1405
1406         /*@Mapping Table*/
1407         odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
1408         odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 3);
1409 #if 0
1410         /* odm_set_bb_reg(dm, R_0x864, BIT5|BIT4|BIT3, 0); */
1411         /* odm_set_bb_reg(dm, R_0x864, BIT8|BIT7|BIT6, 1); */
1412 #endif
1413
1414         /* Set WLBB_SEL_RF_ON 1 if RXFIR_PWDB > 0xCcc[3:0] */
1415         odm_set_bb_reg(dm, R_0xccc, BIT(12), 0);
1416         /* @Low-to-High threshold for WLBB_SEL_RF_ON when OFDM enable */
1417         odm_set_bb_reg(dm, R_0xccc, 0x0F, 0x01);
1418         /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM enable */
1419         odm_set_bb_reg(dm, R_0xccc, 0xF0, 0x0);
1420         /* @b Low-to-High threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */
1421         odm_set_bb_reg(dm, R_0xabc, 0xFF, 0x06);
1422         /* @High-to-Low threshold for WLBB_SEL_RF_ON when OFDM disable ( only CCK ) */
1423         odm_set_bb_reg(dm, R_0xabc, 0xFF00, 0x00);
1424
1425         /*OFDM HW AntDiv Parameters*/
1426         odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0);
1427         odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00);
1428         odm_set_bb_reg(dm, R_0xc5c, BIT(20) | BIT(19) | BIT(18), 0x04);
1429
1430         /*@CCK HW AntDiv Parameters*/
1431         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1);
1432         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1);
1433         odm_set_bb_reg(dm, R_0xaa8, BIT(8), 0);
1434
1435         odm_set_bb_reg(dm, R_0xa0c, 0x0F, 0xf);
1436         odm_set_bb_reg(dm, R_0xa14, 0x1F, 0x8);
1437         odm_set_bb_reg(dm, R_0xa10, BIT(13), 0x1);
1438         odm_set_bb_reg(dm, R_0xa74, BIT(8), 0x0);
1439         odm_set_bb_reg(dm, R_0xb34, BIT(30), 0x1);
1440
1441         /*@disable antenna training     */
1442         odm_set_bb_reg(dm, R_0xe08, BIT(16), 0);
1443         odm_set_bb_reg(dm, R_0xc50, BIT(8), 0);
1444 }
1445 /*@Mingzhi 2017-05-08*/
1446
1447 void odm_s0s1_sw_ant_div_init_8723d(
1448         void            *dm_void
1449 )
1450 {
1451         struct dm_struct                *dm = (struct dm_struct *)dm_void;
1452         struct sw_antenna_switch        *dm_swat_table = &dm->dm_swat_table;
1453         struct phydm_fat_struct         *fat_tab = &dm->dm_fat_table;
1454
1455         PHYDM_DBG(dm, DBG_ANT_DIV,
1456                   "***8723D AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
1457
1458         /*@keep antsel_map when GNT_BT = 1*/
1459         odm_set_bb_reg(dm, R_0x864, BIT(12), 1);
1460
1461         /* @Disable antsw when GNT_BT=1 */
1462         odm_set_bb_reg(dm, R_0x874, BIT(23), 0);
1463
1464         /* @Mapping Table */
1465         odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
1466         odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
1467
1468         /* Output Pin Settings */
1469 #if 0
1470         /* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
1471 #endif
1472         odm_set_bb_reg(dm, R_0x870, BIT(8), 1);
1473         odm_set_bb_reg(dm, R_0x870, BIT(9), 1);
1474
1475         /* Status init */
1476         fat_tab->is_become_linked  = false;
1477         dm_swat_table->try_flag = SWAW_STEP_INIT;
1478         dm_swat_table->double_chk_flag = 0;
1479         dm_swat_table->cur_antenna = MAIN_ANT;
1480         dm_swat_table->pre_antenna = MAIN_ANT;
1481         dm->antdiv_counter = CONFIG_ANTENNA_DIVERSITY_PERIOD;
1482
1483         /* @2 [--For HW Bug setting] */
1484         odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant  by Reg */
1485 }
1486
1487 void odm_update_rx_idle_ant_8723d(
1488         void *dm_void,
1489         u8 ant,
1490         u32 default_ant,
1491         u32 optional_ant)
1492 {
1493         struct dm_struct *dm = (struct dm_struct *)dm_void;
1494         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1495         void *adapter = dm->adapter;
1496         u8 count = 0;
1497
1498 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1499         /*score board to BT ,a002:WL to do ant-div*/
1500         odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa002);
1501         ODM_delay_us(50);
1502 #endif
1503 #if 0
1504         /*      odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);       */
1505 #endif
1506         if (dm->ant_div_type == S0S1_SW_ANTDIV) {
1507         odm_set_bb_reg(dm, R_0x860, BIT(8), default_ant);
1508         odm_set_bb_reg(dm, R_0x860, BIT(9), default_ant);
1509         }
1510         odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*@Default RX*/
1511         odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
1512         odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*@Default TX*/
1513         fat_tab->rx_idle_ant = ant;
1514 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
1515         /*score board to BT ,a000:WL@S1 a001:WL@S0*/
1516         if (default_ant == ANT1_2G)
1517                 odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa000);
1518         else
1519                 odm_set_mac_reg(dm, R_0xa8, MASKHWORD, 0xa001);
1520 #endif
1521 }
1522
1523 void phydm_set_tx_ant_pwr_8723d(
1524         void *dm_void,
1525         u8 ant)
1526 {
1527         struct dm_struct *dm = (struct dm_struct *)dm_void;
1528         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1529         void *adapter = dm->adapter;
1530
1531         fat_tab->rx_idle_ant = ant;
1532
1533 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1534         ((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
1535 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1536         rtw_hal_set_tx_power_level(adapter, *dm->channel);
1537 #endif
1538 }
1539 #endif
1540
1541 #if (RTL8723B_SUPPORT == 1)
1542 void odm_trx_hw_ant_div_init_8723b(
1543         void *dm_void)
1544 {
1545         struct dm_struct *dm = (struct dm_struct *)dm_void;
1546
1547         PHYDM_DBG(dm, DBG_ANT_DIV,
1548                   "***8723B AntDiv_Init =>  ant_div_type=[CG_TRX_HW_ANTDIV(DPDT)]\n");
1549
1550         /* @Mapping Table */
1551         odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
1552         odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
1553
1554         /* OFDM HW AntDiv Parameters */
1555         odm_set_bb_reg(dm, R_0xca4, 0x7FF, 0xa0); /* thershold */
1556         odm_set_bb_reg(dm, R_0xca4, 0x7FF000, 0x00); /* @bias */
1557
1558         /* @CCK HW AntDiv Parameters */
1559         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
1560         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
1561
1562         /* @BT Coexistence */
1563         odm_set_bb_reg(dm, R_0x864, BIT(12), 0); /* @keep antsel_map when GNT_BT = 1 */
1564         odm_set_bb_reg(dm, R_0x874, BIT(23), 0); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1565
1566         /* Output Pin Settings */
1567         odm_set_bb_reg(dm, R_0x870, BIT(8), 0);
1568
1569         odm_set_bb_reg(dm, R_0x948, BIT(6), 0); /* WL_BB_SEL_BTG_TRXG_anta,  (1: HW CTRL  0: SW CTRL) */
1570         odm_set_bb_reg(dm, R_0x948, BIT(7), 0);
1571
1572         odm_set_mac_reg(dm, R_0x40, BIT(3), 1);
1573         odm_set_mac_reg(dm, R_0x38, BIT(11), 1);
1574         odm_set_mac_reg(dm, R_0x4c, BIT(24) | BIT(23), 2); /* select DPDT_P and DPDT_N as output pin */
1575
1576         odm_set_bb_reg(dm, R_0x944, BIT(0) | BIT(1), 3); /* @in/out */
1577         odm_set_bb_reg(dm, R_0x944, BIT(31), 0);
1578
1579         odm_set_bb_reg(dm, R_0x92c, BIT(1), 0); /* @DPDT_P non-inverse */
1580         odm_set_bb_reg(dm, R_0x92c, BIT(0), 1); /* @DPDT_N inverse */
1581
1582         odm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0] */
1583         odm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */
1584
1585         /* @2 [--For HW Bug setting] */
1586         if (dm->ant_type == ODM_AUTO_ANT)
1587                 odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */
1588 }
1589
1590 void odm_s0s1_sw_ant_div_init_8723b(
1591         void *dm_void)
1592 {
1593         struct dm_struct *dm = (struct dm_struct *)dm_void;
1594         struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
1595         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1596
1597         PHYDM_DBG(dm, DBG_ANT_DIV,
1598                   "***8723B AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
1599
1600         /* @Mapping Table */
1601         odm_set_bb_reg(dm, R_0x914, MASKBYTE0, 0);
1602         odm_set_bb_reg(dm, R_0x914, MASKBYTE1, 1);
1603
1604 #if 0
1605         /* Output Pin Settings */
1606         /* odm_set_bb_reg(dm, R_0x948, BIT6, 0x1); */
1607 #endif
1608         odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0);
1609
1610         fat_tab->is_become_linked = false;
1611         dm_swat_table->try_flag = SWAW_STEP_INIT;
1612         dm_swat_table->double_chk_flag = 0;
1613
1614         /* @2 [--For HW Bug setting] */
1615         odm_set_bb_reg(dm, R_0x80c, BIT(21), 0); /* TX ant  by Reg */
1616 }
1617
1618 void odm_update_rx_idle_ant_8723b(
1619         void *dm_void,
1620         u8 ant,
1621         u32 default_ant,
1622         u32 optional_ant)
1623 {
1624         struct dm_struct *dm = (struct dm_struct *)dm_void;
1625         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
1626         void *adapter = dm->adapter;
1627         u8 count = 0;
1628         /*u8                    u1_temp;*/
1629         /*u8                    h2c_parameter;*/
1630
1631         if (!dm->is_linked && dm->ant_type == ODM_AUTO_ANT) {
1632                 PHYDM_DBG(dm, DBG_ANT_DIV,
1633                           "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to no link\n");
1634                 return;
1635         }
1636
1637 #if 0
1638         /* Send H2C command to FW */
1639         /* @Enable wifi calibration */
1640         h2c_parameter = true;
1641         odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
1642
1643         /* @Check if H2C command sucess or not (0x1e6) */
1644         u1_temp = odm_read_1byte(dm, 0x1e6);
1645         while ((u1_temp != 0x1) && (count < 100)) {
1646                 ODM_delay_us(10);
1647                 u1_temp = odm_read_1byte(dm, 0x1e6);
1648                 count++;
1649         }
1650         PHYDM_DBG(dm, DBG_ANT_DIV,
1651                   "[ Update Rx-Idle-ant ] 8723B: H2C command status = %d, count = %d\n",
1652                   u1_temp, count);
1653
1654         if (u1_temp == 0x1) {
1655                 /* @Check if BT is doing IQK (0x1e7) */
1656                 count = 0;
1657                 u1_temp = odm_read_1byte(dm, 0x1e7);
1658                 while ((!(u1_temp & BIT(0)))  && (count < 100)) {
1659                         ODM_delay_us(50);
1660                         u1_temp = odm_read_1byte(dm, 0x1e7);
1661                         count++;
1662                 }
1663                 PHYDM_DBG(dm, DBG_ANT_DIV,
1664                           "[ Update Rx-Idle-ant ] 8723B: BT IQK status = %d, count = %d\n",
1665                           u1_temp, count);
1666
1667                 if (u1_temp & BIT(0)) {
1668                         odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
1669                         odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
1670                         odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT4 | BIT3, default_ant); /* @Default RX */
1671                         odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT7 | BIT6, optional_ant);        /* Optional RX */
1672                         odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT13 | BIT12, default_ant); /* @Default TX */
1673                         fat_tab->rx_idle_ant = ant;
1674
1675                         /* Set TX AGC by S0/S1 */
1676                         /* Need to consider Linux driver */
1677 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1678                         adapter->hal_func.set_tx_power_level_handler(adapter, *dm->channel);
1679 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1680                         rtw_hal_set_tx_power_level(adapter, *dm->channel);
1681 #endif
1682
1683                         /* Set IQC by S0/S1 */
1684                         odm_set_iqc_by_rfpath(dm, default_ant);
1685                         PHYDM_DBG(dm, DBG_ANT_DIV,
1686                                   "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
1687                 } else
1688                         PHYDM_DBG(dm, DBG_ANT_DIV,
1689                                   "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to BT IQK\n");
1690         } else
1691                 PHYDM_DBG(dm, DBG_ANT_DIV,
1692                           "[ Update Rx-Idle-ant ] 8723B: Fail to set RX antenna due to H2C command fail\n");
1693
1694         /* Send H2C command to FW */
1695         /* @Disable wifi calibration */
1696         h2c_parameter = false;
1697         odm_fill_h2c_cmd(dm, ODM_H2C_WIFI_CALIBRATION, 1, &h2c_parameter);
1698 #else
1699
1700         odm_set_bb_reg(dm, R_0x948, BIT(6), 0x1);
1701         odm_set_bb_reg(dm, R_0x948, BIT(9), default_ant);
1702         odm_set_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3), default_ant); /*@Default RX*/
1703         odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), optional_ant); /*Optional RX*/
1704         odm_set_bb_reg(dm, R_0x860, BIT(14) | BIT(13) | BIT(12), default_ant); /*@Default TX*/
1705         fat_tab->rx_idle_ant = ant;
1706
1707 /* Set TX AGC by S0/S1 */
1708 /* Need to consider Linux driver */
1709 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1710         ((PADAPTER)adapter)->HalFunc.SetTxPowerLevelHandler(adapter, *dm->channel);
1711 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
1712         rtw_hal_set_tx_power_level(adapter, *dm->channel);
1713 #endif
1714
1715         /* Set IQC by S0/S1 */
1716         odm_set_iqc_by_rfpath(dm, default_ant);
1717         PHYDM_DBG(dm, DBG_ANT_DIV,
1718                   "[ Update Rx-Idle-ant ] 8723B: Success to set RX antenna\n");
1719
1720 #endif
1721 }
1722
1723 boolean
1724 phydm_is_bt_enable_8723b(
1725         void *dm_void)
1726 {
1727         struct dm_struct *dm = (struct dm_struct *)dm_void;
1728         u32 bt_state;
1729 #if 0
1730         /*u32                   reg75;*/
1731
1732         /*reg75 = odm_get_bb_reg(dm, R_0x74, BIT8);*/
1733         /*odm_set_bb_reg(dm, R_0x74, BIT8, 0x0);*/
1734 #endif
1735         odm_set_bb_reg(dm, R_0xa0, BIT(24) | BIT(25) | BIT(26), 0x5);
1736         bt_state = odm_get_bb_reg(dm, R_0xa0, (BIT(3) | BIT(2) | BIT(1) | BIT(0)));
1737 #if 0
1738         /*odm_set_bb_reg(dm, R_0x74, BIT8, reg75);*/
1739 #endif
1740
1741         if (bt_state == 4 || bt_state == 7 || bt_state == 9 || bt_state == 13)
1742                 return true;
1743         else
1744                 return false;
1745 }
1746 #endif /* @#if (RTL8723B_SUPPORT == 1) */
1747
1748 #if (RTL8821A_SUPPORT == 1)
1749
1750 void odm_trx_hw_ant_div_init_8821a(
1751         void *dm_void)
1752 {
1753         struct dm_struct *dm = (struct dm_struct *)dm_void;
1754
1755         PHYDM_DBG(dm, DBG_ANT_DIV,
1756                   "***8821A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n");
1757
1758         /* Output Pin Settings */
1759         odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
1760
1761         odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
1762         odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
1763
1764         odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
1765
1766         odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
1767         odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
1768         odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
1769         odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
1770         odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
1771         odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
1772
1773         /* @Mapping Table */
1774         odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
1775         odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
1776
1777         /* OFDM HW AntDiv Parameters */
1778         odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
1779         odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
1780
1781         /* @CCK HW AntDiv Parameters */
1782         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
1783         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
1784
1785         odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */
1786         odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */
1787
1788         /* @BT Coexistence */
1789         odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */
1790         odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1791
1792         odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
1793
1794         /* response TX ant by RX ant */
1795         odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
1796 }
1797
1798 void odm_s0s1_sw_ant_div_init_8821a(
1799         void *dm_void)
1800 {
1801         struct dm_struct *dm = (struct dm_struct *)dm_void;
1802         struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
1803
1804         PHYDM_DBG(dm, DBG_ANT_DIV,
1805                   "***8821A AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
1806
1807         /* Output Pin Settings */
1808         odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
1809
1810         odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
1811         odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
1812
1813         odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
1814
1815         odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
1816         odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
1817         odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
1818         odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
1819         odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
1820         odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
1821
1822         /* @Mapping Table */
1823         odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
1824         odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
1825
1826         /* OFDM HW AntDiv Parameters */
1827         odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
1828         odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
1829
1830         /* @CCK HW AntDiv Parameters */
1831         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
1832         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
1833
1834         odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */
1835         odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */
1836
1837         /* @BT Coexistence */
1838         odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */
1839         odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1840
1841         odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
1842
1843         /* response TX ant by RX ant */
1844         odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
1845
1846         odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
1847
1848         dm_swat_table->try_flag = SWAW_STEP_INIT;
1849         dm_swat_table->double_chk_flag = 0;
1850         dm_swat_table->cur_antenna = MAIN_ANT;
1851         dm_swat_table->pre_antenna = MAIN_ANT;
1852         dm_swat_table->swas_no_link_state = 0;
1853 }
1854 #endif /* @#if (RTL8821A_SUPPORT == 1) */
1855
1856 #if (RTL8821C_SUPPORT == 1)
1857 void odm_trx_hw_ant_div_init_8821c(
1858         void *dm_void)
1859 {
1860         struct dm_struct *dm = (struct dm_struct *)dm_void;
1861
1862         PHYDM_DBG(dm, DBG_ANT_DIV,
1863                   "***8821C AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (DPDT)]\n");
1864         /* Output Pin Settings */
1865         odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
1866
1867         odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
1868         odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
1869
1870         odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
1871
1872         odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
1873         odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
1874         odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
1875         odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
1876         odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
1877         odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
1878
1879         /* @Mapping Table */
1880         odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
1881         odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
1882
1883         /* OFDM HW AntDiv Parameters */
1884         odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
1885         odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x10); /* @bias */
1886
1887         /* @CCK HW AntDiv Parameters */
1888         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
1889         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
1890
1891         odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */
1892         odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */
1893
1894         /* @BT Coexistence */
1895         odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */
1896         odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1897
1898         /* Timming issue */
1899         odm_set_bb_reg(dm, R_0x818, BIT(23) | BIT(22) | BIT(21) | BIT(20), 0); /*@keep antidx after tx for ACK ( unit x 3.2 mu sec)*/
1900         odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
1901
1902         /* response TX ant by RX ant */
1903         odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
1904 }
1905
1906 void phydm_s0s1_sw_ant_div_init_8821c(
1907         void *dm_void)
1908 {
1909         struct dm_struct *dm = (struct dm_struct *)dm_void;
1910         struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
1911
1912         PHYDM_DBG(dm, DBG_ANT_DIV,
1913                   "***8821C AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
1914
1915         /* Output Pin Settings */
1916         odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
1917
1918         odm_set_mac_reg(dm, R_0x64, BIT(29), 1); /* PAPE by WLAN control */
1919         odm_set_mac_reg(dm, R_0x64, BIT(28), 1); /* @LNAON by WLAN control */
1920
1921         odm_set_bb_reg(dm, R_0xcb8, BIT(16), 0);
1922
1923         odm_set_mac_reg(dm, R_0x4c, BIT(23), 0); /* select DPDT_P and DPDT_N as output pin */
1924         odm_set_mac_reg(dm, R_0x4c, BIT(24), 1); /* @by WLAN control */
1925         odm_set_bb_reg(dm, R_0xcb4, 0xF, 8); /* @DPDT_P = ANTSEL[0] */
1926         odm_set_bb_reg(dm, R_0xcb4, 0xF0, 8); /* @DPDT_N = ANTSEL[0] */
1927         odm_set_bb_reg(dm, R_0xcb4, BIT(29), 0); /* @DPDT_P non-inverse */
1928         odm_set_bb_reg(dm, R_0xcb4, BIT(28), 1); /* @DPDT_N inverse */
1929
1930         /* @Mapping Table */
1931         odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
1932         odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
1933
1934         /* OFDM HW AntDiv Parameters */
1935         odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
1936         odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x00); /* @bias */
1937
1938         /* @CCK HW AntDiv Parameters */
1939         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
1940         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
1941
1942         odm_set_bb_reg(dm, R_0x800, BIT(25), 0); /* @ANTSEL_CCK sent to the smart_antenna circuit */
1943         odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); /* @CCK AntDiv function block enable */
1944
1945         /* @BT Coexistence */
1946         odm_set_bb_reg(dm, R_0xcac, BIT(9), 1); /* @keep antsel_map when GNT_BT = 1 */
1947         odm_set_bb_reg(dm, R_0x804, BIT(4), 1); /* @Disable hw antsw & fast_train.antsw when GNT_BT=1 */
1948
1949         odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
1950
1951         /* response TX ant by RX ant */
1952         odm_set_mac_reg(dm, R_0x668, BIT(3), 1);
1953
1954         odm_set_bb_reg(dm, R_0x900, BIT(18), 0);
1955
1956         dm_swat_table->try_flag = SWAW_STEP_INIT;
1957         dm_swat_table->double_chk_flag = 0;
1958         dm_swat_table->cur_antenna = MAIN_ANT;
1959         dm_swat_table->pre_antenna = MAIN_ANT;
1960         dm_swat_table->swas_no_link_state = 0;
1961 }
1962 #endif /* @#if (RTL8821C_SUPPORT == 1) */
1963
1964 #if (RTL8881A_SUPPORT == 1)
1965 void odm_trx_hw_ant_div_init_8881a(
1966         void *dm_void)
1967 {
1968         struct dm_struct *dm = (struct dm_struct *)dm_void;
1969
1970         PHYDM_DBG(dm, DBG_ANT_DIV,
1971                   "***8881A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n");
1972
1973         /* Output Pin Settings */
1974         /* @[SPDT related] */
1975         odm_set_mac_reg(dm, R_0x4c, BIT(25), 0);
1976         odm_set_mac_reg(dm, R_0x4c, BIT(26), 0);
1977         odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
1978         odm_set_bb_reg(dm, R_0xcb4, BIT(22), 0);
1979         odm_set_bb_reg(dm, R_0xcb4, BIT(24), 1);
1980         odm_set_bb_reg(dm, R_0xcb0, 0xF00, 8); /* @DPDT_P = ANTSEL[0] */
1981         odm_set_bb_reg(dm, R_0xcb0, 0xF0000, 8); /* @DPDT_N = ANTSEL[0] */
1982
1983         /* @Mapping Table */
1984         odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
1985         odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
1986
1987         /* OFDM HW AntDiv Parameters */
1988         odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
1989         odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
1990         odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
1991
1992         /* @CCK HW AntDiv Parameters */
1993         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
1994         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
1995
1996         /* @2 [--For HW Bug setting] */
1997
1998         odm_set_bb_reg(dm, R_0x900, BIT(18), 0); /* TX ant  by Reg */ /* A-cut bug */
1999 }
2000
2001 #endif /* @#if (RTL8881A_SUPPORT == 1) */
2002
2003 #if (RTL8812A_SUPPORT == 1)
2004 void odm_trx_hw_ant_div_init_8812a(
2005         void *dm_void)
2006 {
2007         struct dm_struct *dm = (struct dm_struct *)dm_void;
2008
2009         PHYDM_DBG(dm, DBG_ANT_DIV,
2010                   "***8812A AntDiv_Init => ant_div_type=[ CG_TRX_HW_ANTDIV (SPDT)]\n");
2011
2012         /* @3 */ /* @3 --RFE pin setting--------- */
2013         /* @[BB] */
2014         odm_set_bb_reg(dm, R_0x900, BIT(10) | BIT(9) | BIT(8), 0x0); /* @disable SW switch */
2015         odm_set_bb_reg(dm, R_0x900, BIT(17) | BIT(16), 0x0);
2016         odm_set_bb_reg(dm, R_0x974, BIT(7) | BIT(6), 0x3); /* @in/out */
2017         odm_set_bb_reg(dm, R_0xcb4, BIT(31), 0); /* @delay buffer */
2018         odm_set_bb_reg(dm, R_0xcb4, BIT(26), 0);
2019         odm_set_bb_reg(dm, R_0xcb4, BIT(27), 1);
2020         odm_set_bb_reg(dm, R_0xcb0, 0xF000000, 8); /* @DPDT_P = ANTSEL[0] */
2021         odm_set_bb_reg(dm, R_0xcb0, 0xF0000000, 8); /* @DPDT_N = ANTSEL[0] */
2022         /* @3 ------------------------- */
2023
2024         /* @Mapping Table */
2025         odm_set_bb_reg(dm, R_0xca4, MASKBYTE0, 0);
2026         odm_set_bb_reg(dm, R_0xca4, MASKBYTE1, 1);
2027
2028         /* OFDM HW AntDiv Parameters */
2029         odm_set_bb_reg(dm, R_0x8d4, 0x7FF, 0xA0); /* thershold */
2030         odm_set_bb_reg(dm, R_0x8d4, 0x7FF000, 0x0); /* @bias */
2031         odm_set_bb_reg(dm, R_0x8cc, BIT(20) | BIT(19) | BIT(18), 3); /* settling time of antdiv by RF LNA = 100ns */
2032
2033         /* @CCK HW AntDiv Parameters */
2034         odm_set_bb_reg(dm, R_0xa74, BIT(7), 1); /* patch for clk from 88M to 80M */
2035         odm_set_bb_reg(dm, R_0xa0c, BIT(4), 1); /* @do 64 samples */
2036
2037         /* @2 [--For HW Bug setting] */
2038
2039         odm_set_bb_reg(dm, R_0x900, BIT(18), 0); /* TX ant  by Reg */ /* A-cut bug */
2040 }
2041
2042 #endif /* @#if (RTL8812A_SUPPORT == 1) */
2043
2044 #if (RTL8188F_SUPPORT == 1)
2045 void odm_s0s1_sw_ant_div_init_8188f(
2046         void *dm_void)
2047 {
2048         struct dm_struct *dm = (struct dm_struct *)dm_void;
2049         struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
2050         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2051
2052         PHYDM_DBG(dm, DBG_ANT_DIV,
2053                   "***8188F AntDiv_Init => ant_div_type=[ S0S1_SW_AntDiv]\n");
2054
2055 #if 0
2056         /*@GPIO setting*/
2057         /*odm_set_mac_reg(dm, R_0x64, BIT(18), 0); */
2058         /*odm_set_mac_reg(dm, R_0x44, BIT(28)|BIT(27), 0);*/
2059         /*odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3);*/ /*enable_output for P_GPIO[4:3]*/
2060         /*odm_set_mac_reg(dm, R_0x44, BIT(12)|BIT(11), 0);*/ /*output value*/
2061         /*odm_set_mac_reg(dm, R_0x40, BIT(1)|BIT(0), 0);*/ /*GPIO function*/
2062 #endif
2063
2064         if (dm->support_ic_type == ODM_RTL8188F) {
2065                 if (dm->support_interface == ODM_ITRF_USB)
2066                         odm_set_mac_reg(dm, R_0x44, BIT(20) | BIT(19), 0x3); /*@enable_output for P_GPIO[4:3]*/
2067                 else if (dm->support_interface == ODM_ITRF_SDIO)
2068                         odm_set_mac_reg(dm, R_0x44, BIT(18), 0x1); /*@enable_output for P_GPIO[2]*/
2069         }
2070
2071         fat_tab->is_become_linked = false;
2072         dm_swat_table->try_flag = SWAW_STEP_INIT;
2073         dm_swat_table->double_chk_flag = 0;
2074 }
2075
2076 void phydm_update_rx_idle_antenna_8188F(
2077         void *dm_void,
2078         u32 default_ant)
2079 {
2080         struct dm_struct *dm = (struct dm_struct *)dm_void;
2081         u8 codeword;
2082
2083         if (dm->support_ic_type == ODM_RTL8188F) {
2084                 if (dm->support_interface == ODM_ITRF_USB) {
2085                         if (default_ant == ANT1_2G)
2086                                 codeword = 1; /*@2'b01*/
2087                         else
2088                                 codeword = 2; /*@2'b10*/
2089                         odm_set_mac_reg(dm, R_0x44, (BIT(12) | BIT(11)), codeword); /*@GPIO[4:3] output value*/
2090                 } else if (dm->support_interface == ODM_ITRF_SDIO) {
2091                         if (default_ant == ANT1_2G) {
2092                                 codeword = 0; /*@1'b0*/
2093                                 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0x3);
2094                                 odm_set_bb_reg(dm, R_0x860, BIT(9) | BIT(8), 0x1);
2095                         } else {
2096                                 codeword = 1; /*@1'b1*/
2097                                 odm_set_bb_reg(dm, R_0x870, BIT(9) | BIT(8), 0x3);
2098                                 odm_set_bb_reg(dm, R_0x860, BIT(9) | BIT(8), 0x2);
2099                         }
2100                         odm_set_mac_reg(dm, R_0x44, BIT(10), codeword); /*@GPIO[2] output value*/
2101                 }
2102         }
2103 }
2104 #endif
2105
2106 #ifdef ODM_EVM_ENHANCE_ANTDIV
2107 void phydm_evm_sw_antdiv_init(
2108         void *dm_void)
2109 {
2110         struct dm_struct *dm = (struct dm_struct *)dm_void;
2111         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2112
2113         /*@EVM enhance AntDiv method init----------------------------------------------------------------------*/
2114         fat_tab->evm_method_enable = 0;
2115         fat_tab->fat_state = NORMAL_STATE_MIAN;
2116         fat_tab->fat_state_cnt = 0;
2117         fat_tab->pre_antdiv_rssi = 0;
2118
2119         dm->antdiv_intvl = 30;
2120         dm->antdiv_train_num = 2;
2121         odm_set_bb_reg(dm, R_0x910, 0x3f, 0xf);
2122         dm->antdiv_evm_en = 1;
2123         /*@dm->antdiv_period=1;*/
2124 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
2125         dm->evm_antdiv_period = 1;
2126 #else
2127         dm->evm_antdiv_period = 3;
2128 #endif
2129         dm->stop_antdiv_rssi_th = 3;
2130         dm->stop_antdiv_tp_th = 80;
2131         dm->antdiv_tp_period = 3;
2132         dm->stop_antdiv_tp_diff_th = 5;
2133 }
2134
2135 void odm_evm_fast_ant_reset(
2136         void *dm_void)
2137 {
2138         struct dm_struct *dm = (struct dm_struct *)dm_void;
2139         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2140
2141         fat_tab->evm_method_enable = 0;
2142         if (fat_tab->div_path_type == ANT_PATH_A)
2143                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
2144         else if (fat_tab->div_path_type == ANT_PATH_B)
2145                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
2146         else if (fat_tab->div_path_type == ANT_PATH_AB)
2147                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
2148         fat_tab->fat_state = NORMAL_STATE_MIAN;
2149         fat_tab->fat_state_cnt = 0;
2150         dm->antdiv_period = 0;
2151         odm_set_mac_reg(dm, R_0x608, BIT(8), 0);
2152 }
2153
2154 void odm_evm_enhance_ant_div(
2155         void *dm_void)
2156 {
2157         struct dm_struct *dm = (struct dm_struct *)dm_void;
2158         u32 main_rssi, aux_rssi;
2159         u32 main_crc_utility = 0, aux_crc_utility = 0, utility_ratio = 1;
2160         u32 main_evm, aux_evm, diff_rssi = 0, diff_EVM = 0;
2161         u32 main_2ss_evm[2], aux_2ss_evm[2];
2162         u32 main_1ss_evm, aux_1ss_evm;
2163         u32 main_2ss_evm_sum, aux_2ss_evm_sum;
2164         u8 score_EVM = 0, score_CRC = 0;
2165         u8 rssi_larger_ant = 0;
2166         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2167         u32 value32, i;
2168         boolean main_above1 = false, aux_above1 = false;
2169         boolean force_antenna = false;
2170         struct cmn_sta_info *sta;
2171         u32 antdiv_tp_main_avg, antdiv_tp_aux_avg;
2172         u8 curr_rssi, rssi_diff;
2173         u32 tp_diff;
2174         u8 tp_diff_return = 0, tp_return = 0, rssi_return = 0;
2175         u8 target_ant_evm_1ss, target_ant_evm_2ss;
2176         u8 decision_evm_ss;
2177         u8 next_ant;
2178
2179         fat_tab->target_ant_enhance = 0xFF;
2180
2181         if ((dm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC)) {
2182                 if (dm->is_one_entry_only) {
2183 #if 0
2184                         /* PHYDM_DBG(dm,DBG_ANT_DIV, "[One Client only]\n"); */
2185 #endif
2186                         i = dm->one_entry_macid;
2187                         sta = dm->phydm_sta_info[i];
2188
2189                         main_rssi = (fat_tab->main_ant_cnt[i] != 0) ? (fat_tab->main_ant_sum[i] / fat_tab->main_ant_cnt[i]) : 0;
2190                         aux_rssi = (fat_tab->aux_ant_cnt[i] != 0) ? (fat_tab->aux_ant_sum[i] / fat_tab->aux_ant_cnt[i]) : 0;
2191
2192                         if ((main_rssi == 0 && aux_rssi != 0 && aux_rssi >= FORCE_RSSI_DIFF) || (main_rssi != 0 && aux_rssi == 0 && main_rssi >= FORCE_RSSI_DIFF))
2193                                 diff_rssi = FORCE_RSSI_DIFF;
2194                         else if (main_rssi != 0 && aux_rssi != 0)
2195                                 diff_rssi = (main_rssi >= aux_rssi) ? (main_rssi - aux_rssi) : (aux_rssi - main_rssi);
2196
2197                         if (main_rssi >= aux_rssi)
2198                                 rssi_larger_ant = MAIN_ANT;
2199                         else
2200                                 rssi_larger_ant = AUX_ANT;
2201
2202                         PHYDM_DBG(dm, DBG_ANT_DIV,
2203                                   "Main_Cnt=(( %d )), main_rssi=(( %d ))\n",
2204                                   fat_tab->main_ant_cnt[i], main_rssi);
2205                         PHYDM_DBG(dm, DBG_ANT_DIV,
2206                                   "Aux_Cnt=(( %d )), aux_rssi=(( %d ))\n",
2207                                   fat_tab->aux_ant_cnt[i], aux_rssi);
2208
2209                         if (((main_rssi >= evm_rssi_th_high || aux_rssi >= evm_rssi_th_high) || fat_tab->evm_method_enable == 1)
2210                             /* @&& (diff_rssi <= FORCE_RSSI_DIFF + 1) */
2211                             ) {
2212                                 PHYDM_DBG(dm, DBG_ANT_DIV,
2213                                           "> TH_H || evm_method_enable==1\n");
2214
2215                                 if ((main_rssi >= evm_rssi_th_low || aux_rssi >= evm_rssi_th_low)) {
2216                                         PHYDM_DBG(dm, DBG_ANT_DIV, "> TH_L, fat_state_cnt =((%d))\n", fat_tab->fat_state_cnt);
2217
2218                                         /*Traning state: 0(alt) 1(ori) 2(alt) 3(ori)============================================================*/
2219                                         if (fat_tab->fat_state_cnt < (dm->antdiv_train_num << 1)) {
2220                                                 if (fat_tab->fat_state_cnt == 0) {
2221                                                         /*Reset EVM 1SS Method */
2222                                                         fat_tab->main_ant_evm_sum[i] = 0;
2223                                                         fat_tab->aux_ant_evm_sum[i] = 0;
2224                                                         fat_tab->main_ant_evm_cnt[i] = 0;
2225                                                         fat_tab->aux_ant_evm_cnt[i] = 0;
2226                                                         /*Reset EVM 2SS Method */
2227                                                         fat_tab->main_ant_evm_2ss_sum[i][0] = 0;
2228                                                         fat_tab->main_ant_evm_2ss_sum[i][1] = 0;
2229                                                         fat_tab->aux_ant_evm_2ss_sum[i][0] = 0;
2230                                                         fat_tab->aux_ant_evm_2ss_sum[i][1] = 0;
2231                                                         fat_tab->main_ant_evm_2ss_cnt[i] = 0;
2232                                                         fat_tab->aux_ant_evm_2ss_cnt[i] = 0;
2233 #if 0
2234                                                         /*Reset TP Method */
2235                                                         fat_tab->antdiv_tp_main = 0;
2236                                                         fat_tab->antdiv_tp_aux = 0;
2237                                                         fat_tab->antdiv_tp_main_cnt = 0;
2238                                                         fat_tab->antdiv_tp_aux_cnt = 0;
2239 #endif
2240                                                         /*Reset CRC Method */
2241                                                         fat_tab->main_crc32_ok_cnt = 0;
2242                                                         fat_tab->main_crc32_fail_cnt = 0;
2243                                                         fat_tab->aux_crc32_ok_cnt = 0;
2244                                                         fat_tab->aux_crc32_fail_cnt = 0;
2245
2246 #ifdef SKIP_EVM_ANTDIV_TRAINING_PATCH
2247                                                         if ((*dm->band_width == CHANNEL_WIDTH_20) && sta->mimo_type == RF_2T2R) {
2248                                                                 /*@1. Skip training: RSSI*/
2249 #if 0
2250                                                                 /*PHYDM_DBG(pDM_Odm,DBG_ANT_DIV, "TargetAnt_enhance=((%d)), RxIdleAnt=((%d))\n", pDM_FatTable->TargetAnt_enhance, pDM_FatTable->RxIdleAnt);*/
2251 #endif
2252                                                                 curr_rssi = (u8)((fat_tab->rx_idle_ant == MAIN_ANT) ? main_rssi : aux_rssi);
2253                                                                 rssi_diff = (curr_rssi > fat_tab->pre_antdiv_rssi) ? (curr_rssi - fat_tab->pre_antdiv_rssi) : (fat_tab->pre_antdiv_rssi - curr_rssi);
2254
2255                                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "[1] rssi_return, curr_rssi=((%d)), pre_rssi=((%d))\n", curr_rssi, fat_tab->pre_antdiv_rssi);
2256
2257                                                                 fat_tab->pre_antdiv_rssi = curr_rssi;
2258                                                                 if (rssi_diff < dm->stop_antdiv_rssi_th && curr_rssi != 0)
2259                                                                         rssi_return = 1;
2260
2261                                                                 /*@2. Skip training: TP Diff*/
2262                                                                 tp_diff = (dm->rx_tp > fat_tab->pre_antdiv_tp) ? (dm->rx_tp - fat_tab->pre_antdiv_tp) : (fat_tab->pre_antdiv_tp - dm->rx_tp);
2263
2264                                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "[2] tp_diff_return, curr_tp=((%d)), pre_tp=((%d))\n", dm->rx_tp, fat_tab->pre_antdiv_tp);
2265                                                                 fat_tab->pre_antdiv_tp = dm->rx_tp;
2266                                                                 if ((tp_diff < (u32)(dm->stop_antdiv_tp_diff_th) && dm->rx_tp != 0))
2267                                                                         tp_diff_return = 1;
2268
2269                                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "[3] tp_return, curr_rx_tp=((%d))\n", dm->rx_tp);
2270                                                                 /*@3. Skip training: TP*/
2271                                                                 if (dm->rx_tp >= (u32)(dm->stop_antdiv_tp_th))
2272                                                                         tp_return = 1;
2273
2274                                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "[4] Return {rssi, tp_diff, tp} = {%d, %d, %d}\n", rssi_return, tp_diff_return, tp_return);
2275                                                                 /*@4. Joint Return Decision*/
2276                                                                 if (tp_return) {
2277                                                                         if (tp_diff_return || rssi_diff) {
2278                                                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "***Return EVM SW AntDiv\n");
2279                                                                                 return;
2280                                                                         }
2281                                                                 }
2282                                                         }
2283 #endif
2284
2285                                                         fat_tab->evm_method_enable = 1;
2286                                                         if (fat_tab->div_path_type == ANT_PATH_A)
2287                                                                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
2288                                                         else if (fat_tab->div_path_type == ANT_PATH_B)
2289                                                                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
2290                                                         else if (fat_tab->div_path_type == ANT_PATH_AB)
2291                                                                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
2292                                                         dm->antdiv_period = dm->evm_antdiv_period;
2293                                                         odm_set_mac_reg(dm, R_0x608, BIT(8), 1); /*RCR accepts CRC32-Error packets*/
2294                                                 }
2295
2296                                                 fat_tab->fat_state_cnt++;
2297                                                 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
2298                                                 odm_update_rx_idle_ant(dm, next_ant);
2299                                                 odm_set_timer(dm, &dm->evm_fast_ant_training_timer, dm->antdiv_intvl); //ms
2300                                         }
2301                                         /*@Decision state: 4==============================================================*/
2302                                         else {
2303                                                 fat_tab->fat_state_cnt = 0;
2304                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "[Decisoin state ]\n");
2305
2306 /* @3 [CRC32 statistic] */
2307 #if 0
2308                                                 if ((fat_tab->main_crc32_ok_cnt > (fat_tab->aux_crc32_ok_cnt << 1)) || (diff_rssi >= 40 && rssi_larger_ant == MAIN_ANT)) {
2309                                                         fat_tab->target_ant_crc32 = MAIN_ANT;
2310                                                         force_antenna = true;
2311                                                         PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Main\n");
2312                                                 } else if ((fat_tab->aux_crc32_ok_cnt > ((fat_tab->main_crc32_ok_cnt) << 1)) || ((diff_rssi >= 40) && (rssi_larger_ant == AUX_ANT))) {
2313                                                         fat_tab->target_ant_crc32 = AUX_ANT;
2314                                                         force_antenna = true;
2315                                                         PHYDM_DBG(dm, DBG_ANT_DIV, "CRC32 Force Aux\n");
2316                                                 } else
2317 #endif
2318                                                 {
2319                                                         if (fat_tab->main_crc32_fail_cnt <= 5)
2320                                                                 fat_tab->main_crc32_fail_cnt = 5;
2321
2322                                                         if (fat_tab->aux_crc32_fail_cnt <= 5)
2323                                                                 fat_tab->aux_crc32_fail_cnt = 5;
2324
2325                                                         if (fat_tab->main_crc32_ok_cnt > fat_tab->main_crc32_fail_cnt)
2326                                                                 main_above1 = true;
2327
2328                                                         if (fat_tab->aux_crc32_ok_cnt > fat_tab->aux_crc32_fail_cnt)
2329                                                                 aux_above1 = true;
2330
2331                                                         if (main_above1 == true && aux_above1 == false) {
2332                                                                 force_antenna = true;
2333                                                                 fat_tab->target_ant_crc32 = MAIN_ANT;
2334                                                         } else if (main_above1 == false && aux_above1 == true) {
2335                                                                 force_antenna = true;
2336                                                                 fat_tab->target_ant_crc32 = AUX_ANT;
2337                                                         } else if (main_above1 == true && aux_above1 == true) {
2338                                                                 main_crc_utility = ((fat_tab->main_crc32_ok_cnt) << 7) / fat_tab->main_crc32_fail_cnt;
2339                                                                 aux_crc_utility = ((fat_tab->aux_crc32_ok_cnt) << 7) / fat_tab->aux_crc32_fail_cnt;
2340                                                                 fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility >= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
2341
2342                                                                 if (main_crc_utility != 0 && aux_crc_utility != 0) {
2343                                                                         if (main_crc_utility >= aux_crc_utility)
2344                                                                                 utility_ratio = (main_crc_utility << 1) / aux_crc_utility;
2345                                                                         else
2346                                                                                 utility_ratio = (aux_crc_utility << 1) / main_crc_utility;
2347                                                                 }
2348                                                         } else if (main_above1 == false && aux_above1 == false) {
2349                                                                 if (fat_tab->main_crc32_ok_cnt == 0)
2350                                                                         fat_tab->main_crc32_ok_cnt = 1;
2351                                                                 if (fat_tab->aux_crc32_ok_cnt == 0)
2352                                                                         fat_tab->aux_crc32_ok_cnt = 1;
2353
2354                                                                 main_crc_utility = ((fat_tab->main_crc32_fail_cnt) << 7) / fat_tab->main_crc32_ok_cnt;
2355                                                                 aux_crc_utility = ((fat_tab->aux_crc32_fail_cnt) << 7) / fat_tab->aux_crc32_ok_cnt;
2356                                                                 fat_tab->target_ant_crc32 = (main_crc_utility == aux_crc_utility) ? (fat_tab->pre_target_ant_enhance) : ((main_crc_utility <= aux_crc_utility) ? MAIN_ANT : AUX_ANT);
2357
2358                                                                 if (main_crc_utility != 0 && aux_crc_utility != 0) {
2359                                                                         if (main_crc_utility >= aux_crc_utility)
2360                                                                                 utility_ratio = (main_crc_utility << 1) / (aux_crc_utility);
2361                                                                         else
2362                                                                                 utility_ratio = (aux_crc_utility << 1) / (main_crc_utility);
2363                                                                 }
2364                                                         }
2365                                                 }
2366                                                 odm_set_mac_reg(dm, R_0x608, BIT(8), 0); /* NOT Accept CRC32 Error packets. */
2367                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "MAIN_CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->main_crc32_ok_cnt, fat_tab->main_crc32_fail_cnt, main_crc_utility);
2368                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "AUX__CRC: Ok=((%d)), Fail = ((%d)), Utility = ((%d))\n", fat_tab->aux_crc32_ok_cnt, fat_tab->aux_crc32_fail_cnt, aux_crc_utility);
2369                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "***1.TargetAnt_CRC32 = ((%s))\n", (fat_tab->target_ant_crc32 == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
2370
2371                                                 /* @3 [EVM statistic] */
2372                                                 /*@1SS EVM*/
2373                                                 main_1ss_evm = (fat_tab->main_ant_evm_cnt[i] != 0) ? (fat_tab->main_ant_evm_sum[i] / fat_tab->main_ant_evm_cnt[i]) : 0;
2374                                                 aux_1ss_evm = (fat_tab->aux_ant_evm_cnt[i] != 0) ? (fat_tab->aux_ant_evm_sum[i] / fat_tab->aux_ant_evm_cnt[i]) : 0;
2375                                                 target_ant_evm_1ss = (main_1ss_evm == aux_1ss_evm) ? (fat_tab->pre_target_ant_enhance) : ((main_1ss_evm >= aux_1ss_evm) ? MAIN_ANT : AUX_ANT);
2376
2377                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main1ss_EVM= ((  %d ))\n", fat_tab->main_ant_evm_cnt[i], main_1ss_evm);
2378                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_1ss_EVM = ((  %d ))\n", fat_tab->main_ant_evm_cnt[i], aux_1ss_evm);
2379
2380                                                 /*@2SS EVM*/
2381                                                 main_2ss_evm[0] = (fat_tab->main_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->main_ant_evm_2ss_sum[i][0] / fat_tab->main_ant_evm_2ss_cnt[i]) : 0;
2382                                                 main_2ss_evm[1] = (fat_tab->main_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->main_ant_evm_2ss_sum[i][1] / fat_tab->main_ant_evm_2ss_cnt[i]) : 0;
2383                                                 main_2ss_evm_sum = main_2ss_evm[0] + main_2ss_evm[1];
2384
2385                                                 aux_2ss_evm[0] = (fat_tab->aux_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->aux_ant_evm_2ss_sum[i][0] / fat_tab->aux_ant_evm_2ss_cnt[i]) : 0;
2386                                                 aux_2ss_evm[1] = (fat_tab->aux_ant_evm_2ss_cnt[i] != 0) ? (fat_tab->aux_ant_evm_2ss_sum[i][1] / fat_tab->aux_ant_evm_2ss_cnt[i]) : 0;
2387                                                 aux_2ss_evm_sum = aux_2ss_evm[0] + aux_2ss_evm[1];
2388
2389                                                 target_ant_evm_2ss = (main_2ss_evm_sum == aux_2ss_evm_sum) ? (fat_tab->pre_target_ant_enhance) : ((main_2ss_evm_sum >= aux_2ss_evm_sum) ? MAIN_ANT : AUX_ANT);
2390
2391                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
2392                                                           fat_tab->main_ant_evm_2ss_cnt[i], main_2ss_evm[0], main_2ss_evm[1], main_2ss_evm_sum);
2393                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_2ss_EVM{A,B,Sum} = {%d, %d, %d}\n",
2394                                                           fat_tab->aux_ant_evm_2ss_cnt[i], aux_2ss_evm[0], aux_2ss_evm[1], aux_2ss_evm_sum);
2395
2396                                                 if ((main_2ss_evm_sum + aux_2ss_evm_sum) != 0) {
2397                                                         decision_evm_ss = 2;
2398                                                         main_evm = main_2ss_evm_sum;
2399                                                         aux_evm = aux_2ss_evm_sum;
2400                                                         fat_tab->target_ant_evm = target_ant_evm_2ss;
2401                                                 } else {
2402                                                         decision_evm_ss = 1;
2403                                                         main_evm = main_1ss_evm;
2404                                                         aux_evm = aux_1ss_evm;
2405                                                         fat_tab->target_ant_evm = target_ant_evm_1ss;
2406                                                 }
2407
2408                                                 if ((main_evm == 0 || aux_evm == 0))
2409                                                         diff_EVM = 100;
2410                                                 else if (main_evm >= aux_evm)
2411                                                         diff_EVM = main_evm - aux_evm;
2412                                                 else
2413                                                         diff_EVM = aux_evm - main_evm;
2414
2415                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "***2.TargetAnt_EVM((%d-ss)) = ((%s))\n", decision_evm_ss, (fat_tab->target_ant_evm == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
2416
2417                                                 //3 [TP statistic]
2418                                                 antdiv_tp_main_avg = (fat_tab->antdiv_tp_main_cnt != 0) ? (fat_tab->antdiv_tp_main / fat_tab->antdiv_tp_main_cnt) : 0;
2419                                                 antdiv_tp_aux_avg = (fat_tab->antdiv_tp_aux_cnt != 0) ? (fat_tab->antdiv_tp_aux / fat_tab->antdiv_tp_aux_cnt) : 0;
2420                                                 fat_tab->target_ant_tp = (antdiv_tp_main_avg == antdiv_tp_aux_avg) ? (fat_tab->pre_target_ant_enhance) : ((antdiv_tp_main_avg >= antdiv_tp_aux_avg) ? MAIN_ANT : AUX_ANT);
2421
2422                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Main_TP = ((%d))\n", fat_tab->antdiv_tp_main_cnt, antdiv_tp_main_avg);
2423                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "Cnt = ((%d)), Aux_TP = ((%d))\n", fat_tab->antdiv_tp_aux_cnt, antdiv_tp_aux_avg);
2424                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "***3.TargetAnt_TP = ((%s))\n", (fat_tab->target_ant_tp == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
2425
2426                                                 /*Reset TP Method */
2427                                                 fat_tab->antdiv_tp_main = 0;
2428                                                 fat_tab->antdiv_tp_aux = 0;
2429                                                 fat_tab->antdiv_tp_main_cnt = 0;
2430                                                 fat_tab->antdiv_tp_aux_cnt = 0;
2431
2432                                                 /* @2 [ Decision state ] */
2433                                                 if (fat_tab->target_ant_evm == fat_tab->target_ant_crc32) {
2434                                                         PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 1, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
2435
2436                                                         if ((utility_ratio < 2 && force_antenna == false) && diff_EVM <= 30)
2437                                                                 fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
2438                                                         else
2439                                                                 fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
2440                                                 }
2441                                                 #if 0
2442                                                 else if ((diff_EVM <= 50 && (utility_ratio > 4 && force_antenna == false)) || (force_antenna == true)) {
2443                                                         PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 2, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
2444                                                         fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
2445                                                 }
2446                                                 #endif
2447                                                 else if (diff_EVM >= 20) {
2448                                                         PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 3, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
2449                                                         fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
2450                                                 } else if (utility_ratio >= 6 && force_antenna == false) {
2451                                                         PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 4, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
2452                                                         fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
2453                                                 } else {
2454                                                         PHYDM_DBG(dm, DBG_ANT_DIV, "Decision type 5, CRC_utility = ((%d)), EVM_diff = ((%d))\n", utility_ratio, diff_EVM);
2455
2456                                                         if (force_antenna == true)
2457                                                                 score_CRC = 2;
2458                                                         else if (utility_ratio >= 5) /*@>2.5*/
2459                                                                 score_CRC = 2;
2460                                                         else if (utility_ratio >= 4) /*@>2*/
2461                                                                 score_CRC = 1;
2462                                                         else
2463                                                                 score_CRC = 0;
2464
2465                                                         if (diff_EVM >= 15)
2466                                                                 score_EVM = 3;
2467                                                         else if (diff_EVM >= 10)
2468                                                                 score_EVM = 2;
2469                                                         else if (diff_EVM >= 5)
2470                                                                 score_EVM = 1;
2471                                                         else
2472                                                                 score_EVM = 0;
2473
2474                                                         if (score_CRC > score_EVM)
2475                                                                 fat_tab->target_ant_enhance = fat_tab->target_ant_crc32;
2476                                                         else if (score_CRC < score_EVM)
2477                                                                 fat_tab->target_ant_enhance = fat_tab->target_ant_evm;
2478                                                         else
2479                                                                 fat_tab->target_ant_enhance = fat_tab->pre_target_ant_enhance;
2480                                                 }
2481                                                 fat_tab->pre_target_ant_enhance = fat_tab->target_ant_enhance;
2482
2483                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "*** 4.TargetAnt_enhance = (( %s ))******\n", (fat_tab->target_ant_enhance == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
2484                                         }
2485                                 } else { /* RSSI< = evm_rssi_th_low */
2486                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[ <TH_L: escape from > TH_L ]\n");
2487                                         odm_evm_fast_ant_reset(dm);
2488                                 }
2489                         } else {
2490                                 PHYDM_DBG(dm, DBG_ANT_DIV,
2491                                           "[escape from> TH_H || evm_method_enable==1]\n");
2492                                 odm_evm_fast_ant_reset(dm);
2493                         }
2494                 } else {
2495                         PHYDM_DBG(dm, DBG_ANT_DIV, "[multi-Client]\n");
2496                         odm_evm_fast_ant_reset(dm);
2497                 }
2498         }
2499 }
2500
2501 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2502 void phydm_evm_antdiv_callback(
2503         struct phydm_timer_list *timer)
2504 {
2505         void *adapter = (void *)timer->Adapter;
2506         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2507         struct dm_struct *dm = &hal_data->DM_OutSrc;
2508
2509         #if DEV_BUS_TYPE == RT_PCI_INTERFACE
2510         #if USE_WORKITEM
2511         odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
2512         #else
2513         {
2514                 odm_hw_ant_div(dm);
2515         }
2516         #endif
2517         #else
2518         odm_schedule_work_item(&dm->phydm_evm_antdiv_workitem);
2519         #endif
2520 }
2521
2522 void phydm_evm_antdiv_workitem_callback(
2523         void *context)
2524 {
2525         void *adapter = (void *)context;
2526         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2527         struct dm_struct *dm = &hal_data->DM_OutSrc;
2528
2529         odm_hw_ant_div(dm);
2530 }
2531
2532 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
2533 void phydm_evm_antdiv_callback(
2534         void *dm_void)
2535 {
2536         struct dm_struct *dm = (struct dm_struct *)dm_void;
2537         void *padapter = dm->adapter;
2538
2539         if (*dm->is_net_closed)
2540                 return;
2541         if (dm->support_interface == ODM_ITRF_PCIE) {
2542                 odm_hw_ant_div(dm);
2543         } else {
2544                 /* @Can't do I/O in timer callback*/
2545                 phydm_run_in_thread_cmd(dm,
2546                                         phydm_evm_antdiv_workitem_callback,
2547                                         padapter);
2548         }
2549 }
2550
2551 void phydm_evm_antdiv_workitem_callback(
2552         void *context)
2553 {
2554         void *adapter = (void *)context;
2555         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
2556         struct dm_struct *dm = &hal_data->odmpriv;
2557
2558         odm_hw_ant_div(dm);
2559 }
2560
2561 #else
2562 void phydm_evm_antdiv_callback(
2563         void *dm_void)
2564 {
2565         struct dm_struct *dm = (struct dm_struct *)dm_void;
2566
2567         PHYDM_DBG(dm, DBG_ANT_DIV, "******AntDiv_Callback******\n");
2568         odm_hw_ant_div(dm);
2569 }
2570 #endif
2571
2572 #endif
2573
2574 void odm_hw_ant_div(
2575         void *dm_void)
2576 {
2577         struct dm_struct *dm = (struct dm_struct *)dm_void;
2578         u32 i, min_max_rssi = 0xFF, ant_div_max_rssi = 0, max_rssi = 0, local_max_rssi;
2579         u32 main_rssi, aux_rssi, mian_cnt, aux_cnt;
2580         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2581         u8 rx_idle_ant = fat_tab->rx_idle_ant, target_ant = 7;
2582         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2583         struct cmn_sta_info *sta;
2584
2585 #if (BEAMFORMING_SUPPORT == 1)
2586 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2587         struct _BF_DIV_COEX_ *dm_bdc_table = &dm->dm_bdc_table;
2588         u32 TH1 = 500000;
2589         u32 TH2 = 10000000;
2590         u32 ma_rx_temp, degrade_TP_temp, improve_TP_temp;
2591         u8 monitor_rssi_threshold = 30;
2592
2593         dm_bdc_table->BF_pass = true;
2594         dm_bdc_table->DIV_pass = true;
2595         dm_bdc_table->is_all_div_sta_idle = true;
2596         dm_bdc_table->is_all_bf_sta_idle = true;
2597         dm_bdc_table->num_bf_tar = 0;
2598         dm_bdc_table->num_div_tar = 0;
2599         dm_bdc_table->num_client = 0;
2600 #endif
2601 #endif
2602
2603         if (!dm->is_linked) { /* @is_linked==False */
2604                 PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
2605
2606                 if (fat_tab->is_become_linked == true) {
2607                         if (fat_tab->div_path_type == ANT_PATH_A)
2608                                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
2609                         else if (fat_tab->div_path_type == ANT_PATH_B)
2610                                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
2611                         else if (fat_tab->div_path_type == ANT_PATH_AB)
2612                                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
2613                         odm_update_rx_idle_ant(dm, MAIN_ANT);
2614                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
2615                         dm->antdiv_period = 0;
2616
2617                         fat_tab->is_become_linked = dm->is_linked;
2618                 }
2619                 return;
2620         } else {
2621                 if (fat_tab->is_become_linked == false) {
2622                         PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
2623                         if (fat_tab->div_path_type == ANT_PATH_A)
2624                                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
2625                         else if (fat_tab->div_path_type == ANT_PATH_B)
2626                                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
2627                         else if (fat_tab->div_path_type == ANT_PATH_AB)
2628                                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
2629 #if 0
2630                         /*odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);*/
2631 #endif
2632
2633 #if 0
2634                         /* @if(dm->support_ic_type == ODM_RTL8821 ) */
2635                         /* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */ /* CCK AntDiv function disable */
2636 #endif
2637
2638 #if 0
2639                         /* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
2640                         /* @else if(dm->support_ic_type == ODM_RTL8881A) */
2641                         /* odm_set_bb_reg(dm, R_0x800, BIT(25), 0); */ /* CCK AntDiv function disable */
2642                         /* @#endif */
2643 #endif
2644
2645 #if 0
2646                         /* @else if(dm->support_ic_type == ODM_RTL8723B ||dm->support_ic_type == ODM_RTL8812) */
2647                         /* odm_set_bb_reg(dm, R_0xa00, BIT(15), 0); */ /* CCK AntDiv function disable */
2648 #endif
2649
2650                         fat_tab->is_become_linked = dm->is_linked;
2651
2652                         if (dm->support_ic_type == ODM_RTL8723B && dm->ant_div_type == CG_TRX_HW_ANTDIV) {
2653                                 odm_set_bb_reg(dm, R_0x930, 0xF0, 8); /* @DPDT_P = ANTSEL[0]   */ /* @for 8723B AntDiv function patch.  BB  Dino  130412 */
2654                                 odm_set_bb_reg(dm, R_0x930, 0xF, 8); /* @DPDT_N = ANTSEL[0] */
2655                         }
2656
2657 /* @2 BDC Init */
2658 #if (BEAMFORMING_SUPPORT == 1)
2659 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2660                         odm_bdc_init(dm);
2661 #endif
2662 #endif
2663
2664 #ifdef ODM_EVM_ENHANCE_ANTDIV
2665                         odm_evm_fast_ant_reset(dm);
2666 #endif
2667                 }
2668         }
2669
2670         if (*fat_tab->p_force_tx_ant_by_desc == false) {
2671                 if (dm->is_one_entry_only == true)
2672                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
2673                 else
2674                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
2675         }
2676
2677 #ifdef ODM_EVM_ENHANCE_ANTDIV
2678         if (dm->antdiv_evm_en == 1) {
2679                 odm_evm_enhance_ant_div(dm);
2680                 if (fat_tab->fat_state_cnt != 0)
2681                         return;
2682         } else
2683                 odm_evm_fast_ant_reset(dm);
2684 #endif
2685
2686 /* @2 BDC mode Arbitration */
2687 #if (BEAMFORMING_SUPPORT == 1)
2688 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2689         if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
2690                 odm_bf_ant_div_mode_arbitration(dm);
2691 #endif
2692 #endif
2693
2694         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
2695                 sta = dm->phydm_sta_info[i];
2696                 if (is_sta_active(sta)) {
2697                         /* @2 Caculate RSSI per Antenna */
2698                         if (fat_tab->main_ant_cnt[i] != 0 || fat_tab->aux_ant_cnt[i] != 0) {
2699                                 mian_cnt = fat_tab->main_ant_cnt[i];
2700                                 aux_cnt = fat_tab->aux_ant_cnt[i];
2701                                 main_rssi = (mian_cnt != 0) ? (fat_tab->main_ant_sum[i] / mian_cnt) : 0;
2702                                 aux_rssi = (aux_cnt != 0) ? (fat_tab->aux_ant_sum[i] / aux_cnt) : 0;
2703                                 target_ant = (mian_cnt == aux_cnt) ? fat_tab->rx_idle_ant : ((mian_cnt >= aux_cnt) ? MAIN_ANT : AUX_ANT); /*Use counter number for OFDM*/
2704
2705                         } else { /*@CCK only case*/
2706                                 mian_cnt = fat_tab->main_ant_cnt_cck[i];
2707                                 aux_cnt = fat_tab->aux_ant_cnt_cck[i];
2708                                 main_rssi = (mian_cnt != 0) ? (fat_tab->main_ant_sum_cck[i] / mian_cnt) : 0;
2709                                 aux_rssi = (aux_cnt != 0) ? (fat_tab->aux_ant_sum_cck[i] / aux_cnt) : 0;
2710                                 target_ant = (main_rssi == aux_rssi) ? fat_tab->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/
2711                         }
2712
2713                         PHYDM_DBG(dm, DBG_ANT_DIV,
2714                                   "*** Client[ %d ] : Main_Cnt = (( %d ))  ,  CCK_Main_Cnt = (( %d )) ,  main_rssi= ((  %d ))\n",
2715                                   i, fat_tab->main_ant_cnt[i],
2716                                   fat_tab->main_ant_cnt_cck[i], main_rssi);
2717                         PHYDM_DBG(dm, DBG_ANT_DIV,
2718                                   "*** Client[ %d ] : Aux_Cnt   = (( %d ))  , CCK_Aux_Cnt   = (( %d )) ,  aux_rssi = ((  %d ))\n",
2719                                   i, fat_tab->aux_ant_cnt[i],
2720                                   fat_tab->aux_ant_cnt_cck[i], aux_rssi);
2721 #if 0
2722                         /* PHYDM_DBG(dm,DBG_ANT_DIV, "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i ,( target_ant ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"); */
2723 #endif
2724
2725                         local_max_rssi = (main_rssi > aux_rssi) ? main_rssi : aux_rssi;
2726                         /* @2 Select max_rssi for DIG */
2727                         if (local_max_rssi > ant_div_max_rssi && local_max_rssi < 40)
2728                                 ant_div_max_rssi = local_max_rssi;
2729                         if (local_max_rssi > max_rssi)
2730                                 max_rssi = local_max_rssi;
2731
2732                         /* @2 Select RX Idle Antenna */
2733                         if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
2734                                 rx_idle_ant = target_ant;
2735                                 min_max_rssi = local_max_rssi;
2736                         }
2737
2738 #ifdef ODM_EVM_ENHANCE_ANTDIV
2739                         if (dm->antdiv_evm_en == 1) {
2740                                 if (fat_tab->target_ant_enhance != 0xFF) {
2741                                         target_ant = fat_tab->target_ant_enhance;
2742                                         rx_idle_ant = fat_tab->target_ant_enhance;
2743                                 }
2744                         }
2745 #endif
2746
2747                         /* @2 Select TX Antenna */
2748                         if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
2749 #if (BEAMFORMING_SUPPORT == 1)
2750 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2751                                 if (dm_bdc_table->w_bfee_client[i] == 0)
2752 #endif
2753 #endif
2754                                 {
2755                                         odm_update_tx_ant(dm, target_ant, i);
2756                                 }
2757                         }
2758
2759 /* @------------------------------------------------------------ */
2760
2761 #if (BEAMFORMING_SUPPORT == 1)
2762 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2763
2764                         dm_bdc_table->num_client++;
2765
2766                         if (dm_bdc_table->bdc_mode == BDC_MODE_2 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
2767                                 /* @2 Byte counter */
2768
2769                                 ma_rx_temp = sta->rx_moving_average_tp; /* RX  TP   ( bit /sec) */
2770
2771                                 if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
2772                                         dm_bdc_table->MA_rx_TP_DIV[i] = ma_rx_temp;
2773                                 else
2774                                         dm_bdc_table->MA_rx_TP[i] = ma_rx_temp;
2775
2776                                 if (ma_rx_temp < TH2 && ma_rx_temp > TH1 && local_max_rssi <= monitor_rssi_threshold) {
2777                                         if (dm_bdc_table->w_bfer_client[i] == 1) { /* @Bfer_Target */
2778                                                 dm_bdc_table->num_bf_tar++;
2779
2780                                                 if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
2781                                                         improve_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 9) >> 3; /* @* 1.125 */
2782                                                         dm_bdc_table->BF_pass = (dm_bdc_table->MA_rx_TP[i] > improve_TP_temp) ? true : false;
2783                                                         PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :  { MA_rx_TP,improve_TP_temp, MA_rx_TP_DIV,  BF_pass}={ %d,  %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], improve_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->BF_pass);
2784                                                 }
2785                                         } else { /* @DIV_Target */
2786                                                 dm_bdc_table->num_div_tar++;
2787
2788                                                 if (dm_bdc_table->BDC_state == BDC_DECISION_STATE && dm_bdc_table->bdc_try_flag == 0) {
2789                                                         degrade_TP_temp = (dm_bdc_table->MA_rx_TP_DIV[i] * 5) >> 3; /* @* 0.625 */
2790                                                         dm_bdc_table->DIV_pass = (dm_bdc_table->MA_rx_TP[i] > degrade_TP_temp) ? true : false;
2791                                                         PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :  { MA_rx_TP, degrade_TP_temp, MA_rx_TP_DIV,  DIV_pass}=\n{ %d,  %d, %d , %d }\n", i, dm_bdc_table->MA_rx_TP[i], degrade_TP_temp, dm_bdc_table->MA_rx_TP_DIV[i], dm_bdc_table->DIV_pass);
2792                                                 }
2793                                         }
2794                                 }
2795
2796                                 if (ma_rx_temp > TH1) {
2797                                         if (dm_bdc_table->w_bfer_client[i] == 1) /* @Bfer_Target */
2798                                                 dm_bdc_table->is_all_bf_sta_idle = false;
2799                                         else /* @DIV_Target */
2800                                                 dm_bdc_table->is_all_div_sta_idle = false;
2801                                 }
2802
2803                                 PHYDM_DBG(dm, DBG_ANT_DIV,
2804                                           "*** Client[ %d ] :  { BFmeeCap, BFmerCap}  = { %d , %d }\n",
2805                                           i, dm_bdc_table->w_bfee_client[i],
2806                                           dm_bdc_table->w_bfer_client[i]);
2807
2808                                 if (dm_bdc_table->BDC_state == bdc_bfer_train_state)
2809                                         PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :    MA_rx_TP_DIV = (( %d ))\n", i, dm_bdc_table->MA_rx_TP_DIV[i]);
2810
2811                                 else
2812                                         PHYDM_DBG(dm, DBG_ANT_DIV, "*** Client[ %d ] :    MA_rx_TP = (( %d ))\n", i, dm_bdc_table->MA_rx_TP[i]);
2813                         }
2814 #endif
2815 #endif
2816                 }
2817
2818 #if (BEAMFORMING_SUPPORT == 1)
2819 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2820                 if (dm_bdc_table->bdc_try_flag == 0)
2821 #endif
2822 #endif
2823                 {
2824                         phydm_antdiv_reset_statistic(dm, i);
2825                 }
2826         }
2827
2828 /* @2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) */
2829 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2830         PHYDM_DBG(dm, DBG_ANT_DIV, "*** rx_idle_ant = (( %s ))\n",
2831                   (rx_idle_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
2832
2833 #if (BEAMFORMING_SUPPORT == 1)
2834 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2835         if (dm_bdc_table->bdc_mode == BDC_MODE_1 || dm_bdc_table->bdc_mode == BDC_MODE_3) {
2836                 PHYDM_DBG(dm, DBG_ANT_DIV,
2837                           "*** bdc_rx_idle_update_counter = (( %d ))\n",
2838                           dm_bdc_table->bdc_rx_idle_update_counter);
2839
2840                 if (dm_bdc_table->bdc_rx_idle_update_counter == 1) {
2841                         PHYDM_DBG(dm, DBG_ANT_DIV,
2842                                   "***Update RxIdle Antenna!!!\n");
2843                         dm_bdc_table->bdc_rx_idle_update_counter = 30;
2844                         odm_update_rx_idle_ant(dm, rx_idle_ant);
2845                 } else {
2846                         dm_bdc_table->bdc_rx_idle_update_counter--;
2847                         PHYDM_DBG(dm, DBG_ANT_DIV,
2848                                   "***NOT update RxIdle Antenna because of BF  ( need to fix TX-ant)\n");
2849                 }
2850         } else
2851 #endif
2852 #endif
2853                 odm_update_rx_idle_ant(dm, rx_idle_ant);
2854 #else
2855
2856         odm_update_rx_idle_ant(dm, rx_idle_ant);
2857
2858 #endif /* @#if(DM_ODM_SUPPORT_TYPE  == ODM_AP) */
2859
2860 /* @2 BDC Main Algorithm */
2861 #if (BEAMFORMING_SUPPORT == 1)
2862 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
2863         if (dm->antdiv_evm_en == 0 || fat_tab->evm_method_enable == 0)
2864                 odm_bd_ccoex_bfee_rx_div_arbitration(dm);
2865
2866         dm_bdc_table->num_txbfee_client = 0;
2867         dm_bdc_table->num_txbfer_client = 0;
2868 #endif
2869 #endif
2870
2871         if (ant_div_max_rssi == 0)
2872                 dig_t->ant_div_rssi_max = dm->rssi_min;
2873         else
2874                 dig_t->ant_div_rssi_max = ant_div_max_rssi;
2875
2876         PHYDM_DBG(dm, DBG_ANT_DIV, "***AntDiv End***\n\n");
2877 }
2878
2879 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
2880
2881 void odm_s0s1_sw_ant_div_reset(
2882         void *dm_void)
2883 {
2884         struct dm_struct *dm = (struct dm_struct *)dm_void;
2885         struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
2886         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2887
2888         fat_tab->is_become_linked = false;
2889         dm_swat_table->try_flag = SWAW_STEP_INIT;
2890         dm_swat_table->double_chk_flag = 0;
2891
2892         PHYDM_DBG(dm, DBG_ANT_DIV, "%s: fat_tab->is_become_linked = %d\n",
2893                   __func__, fat_tab->is_become_linked);
2894 }
2895
2896 void odm_s0s1_sw_ant_div(
2897         void *dm_void,
2898         u8 step)
2899 {
2900         struct dm_struct *dm = (struct dm_struct *)dm_void;
2901         struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
2902         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
2903         u32 i, min_max_rssi = 0xFF, local_max_rssi, local_min_rssi;
2904         u32 main_rssi, aux_rssi;
2905         u8 high_traffic_train_time_u = 0x32, high_traffic_train_time_l = 0, train_time_temp;
2906         u8 low_traffic_train_time_u = 200, low_traffic_train_time_l = 0;
2907         u8 rx_idle_ant = dm_swat_table->pre_antenna, target_ant = dm_swat_table->pre_antenna, next_ant = 0;
2908         struct cmn_sta_info *entry = NULL;
2909         u32 value32;
2910         u32 main_ant_sum = 0;
2911         u32 aux_ant_sum = 0;
2912         u32 main_ant_cnt = 0;
2913         u32 aux_ant_cnt = 0;
2914
2915         if (!dm->is_linked) { /* @is_linked==False */
2916                 PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
2917                 if (fat_tab->is_become_linked == true) {
2918                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
2919                         if (dm->support_ic_type == ODM_RTL8723B) {
2920                                 PHYDM_DBG(dm, DBG_ANT_DIV,
2921                                           "Set REG 948[9:6]=0x0\n");
2922                                 odm_set_bb_reg(dm, R_0x948, (BIT(9) | BIT(8) | BIT(7) | BIT(6)), 0x0);
2923                         }
2924                         fat_tab->is_become_linked = dm->is_linked;
2925                 }
2926                 return;
2927         } else {
2928                 if (fat_tab->is_become_linked == false) {
2929                         PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked !!!]\n");
2930
2931                         if (dm->support_ic_type == ODM_RTL8723B) {
2932                                 value32 = odm_get_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3));
2933
2934 #if (RTL8723B_SUPPORT == 1)
2935                                 if (value32 == 0x0)
2936                                         odm_update_rx_idle_ant_8723b(dm, MAIN_ANT, ANT1_2G, ANT2_2G);
2937                                 else if (value32 == 0x1)
2938                                         odm_update_rx_idle_ant_8723b(dm, AUX_ANT, ANT2_2G, ANT1_2G);
2939 #endif
2940
2941                                 PHYDM_DBG(dm, DBG_ANT_DIV,
2942                                           "8723B: First link! Force antenna to  %s\n",
2943                                           (value32 == 0x0 ? "MAIN" : "AUX"));
2944                         }
2945
2946                         if (dm->support_ic_type == ODM_RTL8723D) {
2947                                 value32 = odm_get_bb_reg(dm, R_0x864, BIT(5) | BIT(4) | BIT(3));
2948 #if (RTL8723D_SUPPORT == 1)
2949                                 if (value32 == 0x0)
2950                                         odm_update_rx_idle_ant_8723d(dm, MAIN_ANT, ANT1_2G, ANT2_2G);
2951                                 else if (value32 == 0x1)
2952                                         odm_update_rx_idle_ant_8723d(dm, AUX_ANT, ANT2_2G, ANT1_2G);
2953                                 PHYDM_DBG(dm, DBG_ANT_DIV,
2954                                           "8723D: First link! Force antenna to  %s\n",
2955                                           (value32 == 0x0 ? "MAIN" : "AUX"));
2956 #endif
2957                         }
2958                         fat_tab->is_become_linked = dm->is_linked;
2959                 }
2960         }
2961
2962         if (*fat_tab->p_force_tx_ant_by_desc == false) {
2963                 if (dm->is_one_entry_only == true)
2964                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
2965                 else
2966                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
2967         }
2968
2969         PHYDM_DBG(dm, DBG_ANT_DIV,
2970                   "[%d] { try_flag=(( %d )), step=(( %d )), double_chk_flag = (( %d )) }\n",
2971                   __LINE__, dm_swat_table->try_flag, step,
2972                   dm_swat_table->double_chk_flag);
2973
2974         /* @Handling step mismatch condition. */
2975         /* Peak step is not finished at last time. Recover the variable and check again. */
2976         if (step != dm_swat_table->try_flag) {
2977                 PHYDM_DBG(dm, DBG_ANT_DIV,
2978                           "[step != try_flag]    Need to Reset After Link\n");
2979                 odm_sw_ant_div_rest_after_link(dm);
2980         }
2981
2982         if (dm_swat_table->try_flag == SWAW_STEP_INIT) {
2983                 dm_swat_table->try_flag = SWAW_STEP_PEEK;
2984                 dm_swat_table->train_time_flag = 0;
2985                 PHYDM_DBG(dm, DBG_ANT_DIV,
2986                           "[set try_flag = 0]  Prepare for peek!\n\n");
2987                 return;
2988
2989         } else {
2990                 /* @1 Normal state (Begin Trying) */
2991                 if (dm_swat_table->try_flag == SWAW_STEP_PEEK) {
2992                         PHYDM_DBG(dm, DBG_ANT_DIV,
2993                                   "TxOkCnt=(( %llu )), RxOkCnt=(( %llu )), traffic_load = (%d))\n",
2994                                   dm->cur_tx_ok_cnt, dm->cur_rx_ok_cnt,
2995                                   dm->traffic_load);
2996
2997                         if (dm->traffic_load == TRAFFIC_HIGH) {
2998                                 train_time_temp = dm_swat_table->train_time;
2999
3000                                 if (dm_swat_table->train_time_flag == 3) {
3001                                         high_traffic_train_time_l = 0xa;
3002
3003                                         if (train_time_temp <= 16)
3004                                                 train_time_temp = high_traffic_train_time_l;
3005                                         else
3006                                                 train_time_temp -= 16;
3007
3008                                 } else if (dm_swat_table->train_time_flag == 2) {
3009                                         train_time_temp -= 8;
3010                                         high_traffic_train_time_l = 0xf;
3011                                 } else if (dm_swat_table->train_time_flag == 1) {
3012                                         train_time_temp -= 4;
3013                                         high_traffic_train_time_l = 0x1e;
3014                                 } else if (dm_swat_table->train_time_flag == 0) {
3015                                         train_time_temp += 8;
3016                                         high_traffic_train_time_l = 0x28;
3017                                 }
3018
3019                                 if (dm->support_ic_type == ODM_RTL8188F) {
3020                                         if (dm->support_interface == ODM_ITRF_SDIO)
3021                                                 high_traffic_train_time_l += 0xa;
3022                                 }
3023
3024 #if 0
3025                                 /* PHYDM_DBG(dm,DBG_ANT_DIV, "*** train_time_temp = ((%d))\n",train_time_temp); */
3026 #endif
3027
3028                                 /* @-- */
3029                                 if (train_time_temp > high_traffic_train_time_u)
3030                                         train_time_temp = high_traffic_train_time_u;
3031
3032                                 else if (train_time_temp < high_traffic_train_time_l)
3033                                         train_time_temp = high_traffic_train_time_l;
3034
3035                                 dm_swat_table->train_time = train_time_temp; /*@10ms~200ms*/
3036
3037                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3038                                           "train_time_flag=((%d)), train_time=((%d))\n",
3039                                           dm_swat_table->train_time_flag,
3040                                           dm_swat_table->train_time);
3041
3042                         } else if ((dm->traffic_load == TRAFFIC_MID) || (dm->traffic_load == TRAFFIC_LOW)) {
3043                                 train_time_temp = dm_swat_table->train_time;
3044
3045                                 if (dm_swat_table->train_time_flag == 3) {
3046                                         low_traffic_train_time_l = 10;
3047                                         if (train_time_temp < 50)
3048                                                 train_time_temp = low_traffic_train_time_l;
3049                                         else
3050                                                 train_time_temp -= 50;
3051                                 } else if (dm_swat_table->train_time_flag == 2) {
3052                                         train_time_temp -= 30;
3053                                         low_traffic_train_time_l = 36;
3054                                 } else if (dm_swat_table->train_time_flag == 1) {
3055                                         train_time_temp -= 10;
3056                                         low_traffic_train_time_l = 40;
3057                                 } else {
3058                                         train_time_temp += 10;
3059                                         low_traffic_train_time_l = 50;
3060                                 }
3061
3062                                 if (dm->support_ic_type == ODM_RTL8188F) {
3063                                         if (dm->support_interface == ODM_ITRF_SDIO)
3064                                                 low_traffic_train_time_l += 10;
3065                                 }
3066
3067                                 /* @-- */
3068                                 if (train_time_temp >= low_traffic_train_time_u)
3069                                         train_time_temp = low_traffic_train_time_u;
3070
3071                                 else if (train_time_temp <= low_traffic_train_time_l)
3072                                         train_time_temp = low_traffic_train_time_l;
3073
3074                                 dm_swat_table->train_time = train_time_temp; /*@10ms~200ms*/
3075
3076                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3077                                           "train_time_flag=((%d)) , train_time=((%d))\n",
3078                                           dm_swat_table->train_time_flag,
3079                                           dm_swat_table->train_time);
3080
3081                         } else {
3082                                 dm_swat_table->train_time = 0xc8; /*@200ms*/
3083                         }
3084
3085                         /* @----------------- */
3086
3087                         PHYDM_DBG(dm, DBG_ANT_DIV,
3088                                   "Current min_max_rssi is ((%d))\n",
3089                                   fat_tab->min_max_rssi);
3090
3091                         /* @---reset index--- */
3092                         if (dm_swat_table->reset_idx >= RSSI_CHECK_RESET_PERIOD) {
3093                                 fat_tab->min_max_rssi = 0;
3094                                 dm_swat_table->reset_idx = 0;
3095                         }
3096                         PHYDM_DBG(dm, DBG_ANT_DIV, "reset_idx = (( %d ))\n",
3097                                   dm_swat_table->reset_idx);
3098
3099                         dm_swat_table->reset_idx++;
3100
3101                         /* @---double check flag--- */
3102                         if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD && dm_swat_table->double_chk_flag == 0) {
3103                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3104                                           " min_max_rssi is ((%d)), and > %d\n",
3105                                           fat_tab->min_max_rssi,
3106                                           RSSI_CHECK_THRESHOLD);
3107
3108                                 dm_swat_table->double_chk_flag = 1;
3109                                 dm_swat_table->try_flag = SWAW_STEP_DETERMINE;
3110                                 dm_swat_table->rssi_trying = 0;
3111
3112                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3113                                           "Test the current ant for (( %d )) ms again\n",
3114                                           dm_swat_table->train_time);
3115                                 odm_update_rx_idle_ant(dm, fat_tab->rx_idle_ant);
3116                         odm_set_timer(dm, &dm_swat_table->phydm_sw_antenna_switch_timer, dm_swat_table->train_time); /*@ms*/
3117                         return;
3118                         }
3119
3120                         next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
3121
3122                         dm_swat_table->try_flag = SWAW_STEP_DETERMINE;
3123
3124                         if (dm_swat_table->reset_idx <= 1)
3125                                 dm_swat_table->rssi_trying = 2;
3126                         else
3127                                 dm_swat_table->rssi_trying = 1;
3128
3129                         odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_PEEK);
3130                         PHYDM_DBG(dm, DBG_ANT_DIV,
3131                                   "[set try_flag=1]  Normal state:  Begin Trying!!\n");
3132
3133                 } else if ((dm_swat_table->try_flag == SWAW_STEP_DETERMINE) && (dm_swat_table->double_chk_flag == 0)) {
3134                         next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
3135                         dm_swat_table->rssi_trying--;
3136                 }
3137
3138                 /* @1 Decision state */
3139                 if (dm_swat_table->try_flag == SWAW_STEP_DETERMINE && dm_swat_table->rssi_trying == 0) {
3140                         boolean is_by_ctrl_frame = false;
3141                         u64 pkt_cnt_total = 0;
3142
3143                         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
3144                                 entry = dm->phydm_sta_info[i];
3145                                 if (is_sta_active(entry)) {
3146 /* @2 Caculate RSSI per Antenna */
3147                                         #if 0
3148                                         main_ant_sum = (u32)fat_tab->main_ant_sum[i] + (u32)fat_tab->main_ant_sum_cck[i];
3149                                         aux_ant_sum = (u32)fat_tab->aux_ant_sum[i] + (u32)fat_tab->aux_ant_sum_cck[i];
3150                                         main_ant_cnt = (u32)fat_tab->main_ant_cnt[i] + (u32)fat_tab->main_ant_cnt_cck[i];
3151                                         aux_ant_cnt = (u32)fat_tab->aux_ant_cnt[i] + (u32)fat_tab->aux_ant_cnt_cck[i];
3152
3153                                         main_rssi = (main_ant_cnt != 0) ? (main_ant_sum / main_ant_cnt) : 0;
3154                                         aux_rssi = (aux_ant_cnt != 0) ? (aux_ant_sum / aux_ant_cnt) : 0;
3155
3156                                         if (fat_tab->main_ant_cnt[i] <= 1 && fat_tab->main_ant_cnt_cck[i] >= 1)
3157                                                 main_rssi = 0;
3158
3159                                         if (fat_tab->aux_ant_cnt[i] <= 1 && fat_tab->aux_ant_cnt_cck[i] >= 1)
3160                                                 aux_rssi = 0;
3161                                         #endif
3162                                         if (fat_tab->main_ant_cnt[i] != 0 || fat_tab->aux_ant_cnt[i] != 0) {
3163                                                 main_ant_cnt = (u32)fat_tab->main_ant_cnt[i];
3164                                                 aux_ant_cnt = (u32)fat_tab->aux_ant_cnt[i];
3165                                                 main_rssi = (main_ant_cnt != 0) ? (fat_tab->main_ant_sum[i] / main_ant_cnt) : 0;
3166                                                 aux_rssi = (aux_ant_cnt != 0) ? (fat_tab->aux_ant_sum[i] / aux_ant_cnt) : 0;
3167                                                 if (dm->support_ic_type == ODM_RTL8723D) {
3168                                                         if (dm_swat_table->pre_antenna == MAIN_ANT) {
3169                                                                 if (main_ant_cnt == 0)
3170                                                                         target_ant = (aux_ant_cnt != 0) ? AUX_ANT : dm_swat_table->pre_antenna;
3171                                                                 else
3172                                                                         target_ant = ((aux_ant_cnt > main_ant_cnt) && ((main_rssi - aux_rssi < 5) || (aux_rssi > main_rssi))) ? AUX_ANT : dm_swat_table->pre_antenna;
3173                                                         } else {
3174                                                                 if (aux_ant_cnt == 0)
3175                                                                         target_ant = (main_ant_cnt != 0) ? MAIN_ANT : dm_swat_table->pre_antenna;
3176                                                                 else
3177                                                                         target_ant = ((main_ant_cnt > aux_ant_cnt) && ((aux_rssi - main_rssi < 5) || (main_rssi > aux_rssi))) ? MAIN_ANT : dm_swat_table->pre_antenna;
3178                                                         }
3179                                                 } else {
3180                                                         if (dm_swat_table->pre_antenna == MAIN_ANT) {
3181                                                                 target_ant = ((aux_ant_cnt > 20) && (aux_rssi >= main_rssi)) ? AUX_ANT : dm_swat_table->pre_antenna;
3182                                                         } else if (dm_swat_table->pre_antenna == AUX_ANT) {
3183                                                                 target_ant = ((main_ant_cnt > 20) && (main_rssi >= aux_rssi)) ? MAIN_ANT : dm_swat_table->pre_antenna;
3184                                                         }
3185                                                 }
3186                                         } else { /*@CCK only case*/
3187                                                 main_ant_cnt = fat_tab->main_ant_cnt_cck[i];
3188                                                 aux_ant_cnt = fat_tab->aux_ant_cnt_cck[i];
3189                                                 main_rssi = (main_ant_cnt != 0) ? (fat_tab->main_ant_sum_cck[i] / main_ant_cnt) : 0;
3190                                                 aux_rssi = (aux_ant_cnt != 0) ? (fat_tab->aux_ant_sum_cck[i] / aux_ant_cnt) : 0;
3191                                                 target_ant = (main_rssi == aux_rssi) ? fat_tab->rx_idle_ant : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT); /*Use RSSI for CCK only case*/
3192                                         }
3193                                         #if 0
3194                                         target_ant = (main_rssi == aux_rssi) ? dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT);
3195                                         #endif
3196                                         local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi;
3197                                         local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi;
3198
3199                                         PHYDM_DBG(dm, DBG_ANT_DIV, "***  CCK_counter_main = (( %d ))  , CCK_counter_aux= ((  %d ))\n", fat_tab->main_ant_cnt_cck[i], fat_tab->aux_ant_cnt_cck[i]);
3200                                         PHYDM_DBG(dm, DBG_ANT_DIV, "***  OFDM_counter_main = (( %d ))  , OFDM_counter_aux= ((  %d ))\n", fat_tab->main_ant_cnt[i], fat_tab->aux_ant_cnt[i]);
3201                                         PHYDM_DBG(dm, DBG_ANT_DIV, "***  main_Cnt = (( %d ))  , aux_Cnt   = (( %d ))\n", main_ant_cnt, aux_ant_cnt);
3202                                         PHYDM_DBG(dm, DBG_ANT_DIV, "***  main_rssi= ((  %d )) , aux_rssi = ((  %d ))\n", main_rssi, aux_rssi);
3203                                         PHYDM_DBG(dm, DBG_ANT_DIV, "*** MAC ID:[ %d ] , target_ant = (( %s ))\n", i, (target_ant == MAIN_ANT) ? "MAIN_ANT" : "AUX_ANT");
3204
3205                                         /* @2 Select RX Idle Antenna */
3206
3207                                         if (local_max_rssi != 0 && local_max_rssi < min_max_rssi) {
3208                                                 rx_idle_ant = target_ant;
3209                                                 min_max_rssi = local_max_rssi;
3210                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "*** local_max_rssi-local_min_rssi = ((%d))\n", (local_max_rssi - local_min_rssi));
3211
3212                                                 if ((local_max_rssi - local_min_rssi) > 8) {
3213                                                         if (local_min_rssi != 0)
3214                                                                 dm_swat_table->train_time_flag = 3;
3215                                                         else {
3216                                                                 if (min_max_rssi > RSSI_CHECK_THRESHOLD)
3217                                                                         dm_swat_table->train_time_flag = 0;
3218                                                                 else
3219                                                                         dm_swat_table->train_time_flag = 3;
3220                                                         }
3221                                                 } else if ((local_max_rssi - local_min_rssi) > 5)
3222                                                         dm_swat_table->train_time_flag = 2;
3223                                                 else if ((local_max_rssi - local_min_rssi) > 2)
3224                                                         dm_swat_table->train_time_flag = 1;
3225                                                 else
3226                                                         dm_swat_table->train_time_flag = 0;
3227                                         }
3228
3229                                         /* @2 Select TX Antenna */
3230                                         if (target_ant == MAIN_ANT)
3231                                                 fat_tab->antsel_a[i] = ANT1_2G;
3232                                         else
3233                                                 fat_tab->antsel_a[i] = ANT2_2G;
3234                                 }
3235                                 phydm_antdiv_reset_statistic(dm, i);
3236                                 pkt_cnt_total += (main_ant_cnt + aux_ant_cnt);
3237                         }
3238
3239                         if (dm_swat_table->is_sw_ant_div_by_ctrl_frame) {
3240                                 odm_s0s1_sw_ant_div_by_ctrl_frame(dm, SWAW_STEP_DETERMINE);
3241                                 is_by_ctrl_frame = true;
3242                         }
3243
3244                         PHYDM_DBG(dm, DBG_ANT_DIV,
3245                                   "Control frame packet counter = %d, data frame packet counter = %llu\n",
3246                                   dm_swat_table->
3247                                   pkt_cnt_sw_ant_div_by_ctrl_frame,
3248                                   pkt_cnt_total);
3249
3250                         if (min_max_rssi == 0xff || ((pkt_cnt_total < (dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame >> 1)) && dm->phy_dbg_info.num_qry_beacon_pkt < 2)) {
3251                                 min_max_rssi = 0;
3252                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3253                                           "Check RSSI of control frame because min_max_rssi == 0xff\n");
3254                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3255                                           "is_by_ctrl_frame = %d\n",
3256                                           is_by_ctrl_frame);
3257
3258                                 if (is_by_ctrl_frame) {
3259                                         main_rssi = (fat_tab->main_ant_ctrl_frame_cnt != 0) ? (fat_tab->main_ant_ctrl_frame_sum / fat_tab->main_ant_ctrl_frame_cnt) : 0;
3260                                         aux_rssi = (fat_tab->aux_ant_ctrl_frame_cnt != 0) ? (fat_tab->aux_ant_ctrl_frame_sum / fat_tab->aux_ant_ctrl_frame_cnt) : 0;
3261
3262                                         if (fat_tab->main_ant_ctrl_frame_cnt <= 1 && fat_tab->cck_ctrl_frame_cnt_main >= 1)
3263                                                 main_rssi = 0;
3264
3265                                         if (fat_tab->aux_ant_ctrl_frame_cnt <= 1 && fat_tab->cck_ctrl_frame_cnt_aux >= 1)
3266                                                 aux_rssi = 0;
3267
3268                                         if (main_rssi != 0 || aux_rssi != 0) {
3269                                                 rx_idle_ant = (main_rssi == aux_rssi) ? dm_swat_table->pre_antenna : ((main_rssi >= aux_rssi) ? MAIN_ANT : AUX_ANT);
3270                                                 local_max_rssi = (main_rssi >= aux_rssi) ? main_rssi : aux_rssi;
3271                                                 local_min_rssi = (main_rssi >= aux_rssi) ? aux_rssi : main_rssi;
3272
3273                                                 if ((local_max_rssi - local_min_rssi) > 8)
3274                                                         dm_swat_table->train_time_flag = 3;
3275                                                 else if ((local_max_rssi - local_min_rssi) > 5)
3276                                                         dm_swat_table->train_time_flag = 2;
3277                                                 else if ((local_max_rssi - local_min_rssi) > 2)
3278                                                         dm_swat_table->train_time_flag = 1;
3279                                                 else
3280                                                         dm_swat_table->train_time_flag = 0;
3281
3282                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "Control frame: main_rssi = %d, aux_rssi = %d\n", main_rssi, aux_rssi);
3283                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "rx_idle_ant decided by control frame = %s\n", (rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"));
3284                                         }
3285                                 }
3286                         }
3287
3288                         fat_tab->min_max_rssi = min_max_rssi;
3289                         dm_swat_table->try_flag = SWAW_STEP_PEEK;
3290
3291                         if (dm_swat_table->double_chk_flag == 1) {
3292                                 dm_swat_table->double_chk_flag = 0;
3293
3294                                 if (fat_tab->min_max_rssi > RSSI_CHECK_THRESHOLD) {
3295                                         PHYDM_DBG(dm, DBG_ANT_DIV, " [Double check] min_max_rssi ((%d)) > %d again!!\n",
3296                                                   fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
3297
3298                                         odm_update_rx_idle_ant(dm, rx_idle_ant);
3299
3300                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
3301                                         return;
3302                                 } else {
3303                                         PHYDM_DBG(dm, DBG_ANT_DIV, " [Double check] min_max_rssi ((%d)) <= %d !!\n",
3304                                                   fat_tab->min_max_rssi, RSSI_CHECK_THRESHOLD);
3305
3306                                         next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
3307                                         dm_swat_table->try_flag = SWAW_STEP_PEEK;
3308                                         dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD;
3309                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[set try_flag=0]  Normal state:  Need to tryg again!!\n\n\n");
3310                                         return;
3311                                 }
3312                         } else {
3313                                 if (fat_tab->min_max_rssi < RSSI_CHECK_THRESHOLD)
3314                                         dm_swat_table->reset_idx = RSSI_CHECK_RESET_PERIOD;
3315
3316                                 dm_swat_table->pre_antenna = rx_idle_ant;
3317                                 odm_update_rx_idle_ant(dm, rx_idle_ant);
3318                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3319                                           "[reset try_flag = 0] Training accomplished !!!]\n\n\n");
3320                                 return;
3321                         }
3322                 }
3323         }
3324
3325         /* @1 4.Change TRX antenna */
3326
3327         PHYDM_DBG(dm, DBG_ANT_DIV,
3328                   "rssi_trying = (( %d )),    ant: (( %s )) >>> (( %s ))\n",
3329                   dm_swat_table->rssi_trying,
3330                   (fat_tab->rx_idle_ant == MAIN_ANT ? "MAIN" : "AUX"),
3331                   (next_ant == MAIN_ANT ? "MAIN" : "AUX"));
3332
3333         odm_update_rx_idle_ant(dm, next_ant);
3334
3335         /* @1 5.Reset Statistics */
3336
3337         fat_tab->rx_idle_ant = next_ant;
3338
3339         if (dm->support_ic_type == ODM_RTL8723D) {
3340                 if (fat_tab->rx_idle_ant == MAIN_ANT) {
3341                         fat_tab->main_ant_sum[0] = 0;
3342                         fat_tab->main_ant_cnt[0] = 0;
3343                         fat_tab->main_ant_sum_cck[0] = 0;
3344                         fat_tab->main_ant_cnt_cck[0] = 0;
3345                 } else {
3346                         fat_tab->aux_ant_sum[0] = 0;
3347                         fat_tab->aux_ant_cnt[0] = 0;
3348                         fat_tab->aux_ant_sum_cck[0] = 0;
3349                         fat_tab->aux_ant_cnt_cck[0] = 0;
3350                 }
3351         }
3352
3353         if (dm->support_ic_type == ODM_RTL8188F) {
3354                 if (dm->support_interface == ODM_ITRF_SDIO) {
3355                         ODM_delay_us(200);
3356
3357                         if (fat_tab->rx_idle_ant == MAIN_ANT) {
3358                                 fat_tab->main_ant_sum[0] = 0;
3359                                 fat_tab->main_ant_cnt[0] = 0;
3360                                 fat_tab->main_ant_sum_cck[0] = 0;
3361                                 fat_tab->main_ant_cnt_cck[0] = 0;
3362                         } else {
3363                                 fat_tab->aux_ant_sum[0] = 0;
3364                                 fat_tab->aux_ant_cnt[0] = 0;
3365                                 fat_tab->aux_ant_sum_cck[0] = 0;
3366                                 fat_tab->aux_ant_cnt_cck[0] = 0;
3367                         }
3368                 }
3369         }
3370         /* @1 6.Set next timer   (Trying state) */
3371         PHYDM_DBG(dm, DBG_ANT_DIV, " Test ((%s)) ant for (( %d )) ms\n",
3372                   (next_ant == MAIN_ANT ? "MAIN" : "AUX"),
3373                   dm_swat_table->train_time);
3374         odm_set_timer(dm, &dm_swat_table->phydm_sw_antenna_switch_timer,
3375                       dm_swat_table->train_time); /*@ms*/
3376 }
3377
3378 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3379 void odm_sw_antdiv_callback(
3380         struct phydm_timer_list *timer)
3381 {
3382         void *adapter = (void *)timer->Adapter;
3383         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3384         struct sw_antenna_switch *dm_swat_table = &hal_data->DM_OutSrc.dm_swat_table;
3385
3386 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
3387 #if USE_WORKITEM
3388         odm_schedule_work_item(&dm_swat_table->phydm_sw_antenna_switch_workitem);
3389 #else
3390         {
3391 #if 0
3392                 /* @dbg_print("SW_antdiv_Callback"); */
3393 #endif
3394                 odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
3395         }
3396 #endif
3397 #else
3398         odm_schedule_work_item(&dm_swat_table->phydm_sw_antenna_switch_workitem);
3399 #endif
3400 }
3401 void odm_sw_antdiv_workitem_callback(
3402         void *context)
3403 {
3404         void *adapter = (void *)context;
3405         HAL_DATA_TYPE *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3406
3407 #if 0
3408         /* @dbg_print("SW_antdiv_Workitem_Callback"); */
3409 #endif
3410         odm_s0s1_sw_ant_div(&hal_data->DM_OutSrc, SWAW_STEP_DETERMINE);
3411 }
3412
3413 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
3414
3415 void odm_sw_antdiv_workitem_callback(
3416         void *context)
3417 {
3418         void *
3419                 adapter = (void *)context;
3420         HAL_DATA_TYPE
3421         *hal_data = GET_HAL_DATA(((PADAPTER)adapter));
3422
3423 #if 0
3424         /*@dbg_print("SW_antdiv_Workitem_Callback");*/
3425 #endif
3426         odm_s0s1_sw_ant_div(&hal_data->odmpriv, SWAW_STEP_DETERMINE);
3427 }
3428
3429 void odm_sw_antdiv_callback(void *function_context)
3430 {
3431         struct dm_struct *dm = (struct dm_struct *)function_context;
3432         void *padapter = dm->adapter;
3433         if (*dm->is_net_closed == true)
3434                 return;
3435
3436 #if 0 /* @Can't do I/O in timer callback*/
3437         odm_s0s1_sw_ant_div(dm, SWAW_STEP_DETERMINE);
3438 #else
3439         rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter);
3440 #endif
3441 }
3442
3443 #endif
3444
3445 void odm_s0s1_sw_ant_div_by_ctrl_frame(
3446         void *dm_void,
3447         u8 step)
3448 {
3449         struct dm_struct *dm = (struct dm_struct *)dm_void;
3450         struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
3451         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3452
3453         switch (step) {
3454         case SWAW_STEP_PEEK:
3455                 dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame = 0;
3456                 dm_swat_table->is_sw_ant_div_by_ctrl_frame = true;
3457                 fat_tab->main_ant_ctrl_frame_cnt = 0;
3458                 fat_tab->aux_ant_ctrl_frame_cnt = 0;
3459                 fat_tab->main_ant_ctrl_frame_sum = 0;
3460                 fat_tab->aux_ant_ctrl_frame_sum = 0;
3461                 fat_tab->cck_ctrl_frame_cnt_main = 0;
3462                 fat_tab->cck_ctrl_frame_cnt_aux = 0;
3463                 fat_tab->ofdm_ctrl_frame_cnt_main = 0;
3464                 fat_tab->ofdm_ctrl_frame_cnt_aux = 0;
3465                 PHYDM_DBG(dm, DBG_ANT_DIV,
3466                           "odm_S0S1_SwAntDivForAPMode(): Start peek and reset counter\n");
3467                 break;
3468         case SWAW_STEP_DETERMINE:
3469                 dm_swat_table->is_sw_ant_div_by_ctrl_frame = false;
3470                 PHYDM_DBG(dm, DBG_ANT_DIV,
3471                           "odm_S0S1_SwAntDivForAPMode(): Stop peek\n");
3472                 break;
3473         default:
3474                 dm_swat_table->is_sw_ant_div_by_ctrl_frame = false;
3475                 break;
3476         }
3477 }
3478
3479 void odm_antsel_statistics_of_ctrl_frame(
3480         void *dm_void,
3481         u8 antsel_tr_mux,
3482         u32 rx_pwdb_all
3483
3484         )
3485 {
3486         struct dm_struct *dm = (struct dm_struct *)dm_void;
3487         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3488
3489         if (antsel_tr_mux == ANT1_2G) {
3490                 fat_tab->main_ant_ctrl_frame_sum += rx_pwdb_all;
3491                 fat_tab->main_ant_ctrl_frame_cnt++;
3492         } else {
3493                 fat_tab->aux_ant_ctrl_frame_sum += rx_pwdb_all;
3494                 fat_tab->aux_ant_ctrl_frame_cnt++;
3495         }
3496 }
3497
3498 void odm_s0s1_sw_ant_div_by_ctrl_frame_process_rssi(
3499         void *dm_void,
3500         void *phy_info_void,
3501         void *pkt_info_void
3502         /*      struct phydm_phyinfo_struct*            phy_info, */
3503         /*      struct phydm_perpkt_info_struct*                pktinfo */
3504         )
3505 {
3506         struct dm_struct *dm = (struct dm_struct *)dm_void;
3507         struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
3508         struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
3509         struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
3510         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3511
3512         if (!(dm->support_ability & ODM_BB_ANT_DIV))
3513                 return;
3514
3515         if (dm->ant_div_type != S0S1_SW_ANTDIV)
3516                 return;
3517
3518         /* @In try state */
3519         if (!dm_swat_table->is_sw_ant_div_by_ctrl_frame)
3520                 return;
3521
3522         /* No HW error and match receiver address */
3523         if (!pktinfo->is_to_self)
3524                 return;
3525
3526         dm_swat_table->pkt_cnt_sw_ant_div_by_ctrl_frame++;
3527
3528         if (pktinfo->is_cck_rate) {
3529                 fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G;
3530
3531                 if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
3532                         fat_tab->cck_ctrl_frame_cnt_main++;
3533                 else
3534                         fat_tab->cck_ctrl_frame_cnt_aux++;
3535
3536                 odm_antsel_statistics_of_ctrl_frame(dm, fat_tab->antsel_rx_keep_0, phy_info->rx_mimo_signal_strength[RF_PATH_A]);
3537         } else {
3538                 fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G;
3539
3540                 if (fat_tab->antsel_rx_keep_0 == ANT1_2G)
3541                         fat_tab->ofdm_ctrl_frame_cnt_main++;
3542                 else
3543                         fat_tab->ofdm_ctrl_frame_cnt_aux++;
3544
3545                 odm_antsel_statistics_of_ctrl_frame(dm, fat_tab->antsel_rx_keep_0, phy_info->rx_pwdb_all);
3546         }
3547 }
3548
3549 #endif /* @#if (RTL8723B_SUPPORT == 1) || (RTL8821A_SUPPORT == 1) */
3550
3551 void odm_set_next_mac_addr_target(
3552         void *dm_void)
3553 {
3554         struct dm_struct *dm = (struct dm_struct *)dm_void;
3555         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3556         struct cmn_sta_info *entry;
3557         u32 value32, i;
3558
3559         PHYDM_DBG(dm, DBG_ANT_DIV, "%s ==>\n", __func__);
3560
3561         if (dm->is_linked) {
3562                 for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
3563                         if ((fat_tab->train_idx + 1) == ODM_ASSOCIATE_ENTRY_NUM)
3564                                 fat_tab->train_idx = 0;
3565                         else
3566                                 fat_tab->train_idx++;
3567
3568                         entry = dm->phydm_sta_info[fat_tab->train_idx];
3569
3570                         if (is_sta_active(entry)) {
3571                                 /*@Match MAC ADDR*/
3572                                 value32 = (entry->mac_addr[5] << 8) | entry->mac_addr[4];
3573
3574                                 odm_set_mac_reg(dm, R_0x7b4, 0xFFFF, value32); /*@0x7b4~0x7b5*/
3575
3576                                 value32 = (entry->mac_addr[3] << 24) | (entry->mac_addr[2] << 16) | (entry->mac_addr[1] << 8) | entry->mac_addr[0];
3577
3578                                 odm_set_mac_reg(dm, R_0x7b0, MASKDWORD, value32); /*@0x7b0~0x7b3*/
3579
3580                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3581                                           "fat_tab->train_idx=%d\n",
3582                                           fat_tab->train_idx);
3583
3584                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3585                                           "Training MAC addr = %x:%x:%x:%x:%x:%x\n",
3586                                           entry->mac_addr[5],
3587                                           entry->mac_addr[4],
3588                                           entry->mac_addr[3],
3589                                           entry->mac_addr[2],
3590                                           entry->mac_addr[1],
3591                                           entry->mac_addr[0]);
3592
3593                                 break;
3594                         }
3595                 }
3596         }
3597 }
3598
3599 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3600
3601 void odm_fast_ant_training(
3602         void *dm_void)
3603 {
3604         struct dm_struct *dm = (struct dm_struct *)dm_void;
3605         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3606
3607         u32 max_rssi_path_a = 0, pckcnt_path_a = 0;
3608         u8 i, target_ant_path_a = 0;
3609         boolean is_pkt_filter_macth_path_a = false;
3610 #if (RTL8192E_SUPPORT == 1)
3611         u32 max_rssi_path_b = 0, pckcnt_path_b = 0;
3612         u8 target_ant_path_b = 0;
3613         boolean is_pkt_filter_macth_path_b = false;
3614 #endif
3615
3616         if (!dm->is_linked) { /* @is_linked==False */
3617                 PHYDM_DBG(dm, DBG_ANT_DIV, "[No Link!!!]\n");
3618
3619                 if (fat_tab->is_become_linked == true) {
3620                         odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
3621                         phydm_fast_training_enable(dm, FAT_OFF);
3622                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
3623                         fat_tab->is_become_linked = dm->is_linked;
3624                 }
3625                 return;
3626         } else {
3627                 if (fat_tab->is_become_linked == false) {
3628                         PHYDM_DBG(dm, DBG_ANT_DIV, "[Linked!!!]\n");
3629                         fat_tab->is_become_linked = dm->is_linked;
3630                 }
3631         }
3632
3633         if (*fat_tab->p_force_tx_ant_by_desc == false) {
3634                 if (dm->is_one_entry_only == true)
3635                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
3636                 else
3637                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
3638         }
3639
3640         if (dm->support_ic_type == ODM_RTL8188E)
3641                 odm_set_bb_reg(dm, R_0x864, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1));
3642 #if (RTL8192E_SUPPORT == 1)
3643         else if (dm->support_ic_type == ODM_RTL8192E) {
3644                 odm_set_bb_reg(dm, R_0xb38, BIT(2) | BIT(1) | BIT(0), ((dm->fat_comb_a) - 1)); /* path-A  */ /* ant combination=regB38[2:0]+1 */
3645                 odm_set_bb_reg(dm, R_0xb38, BIT(18) | BIT(17) | BIT(16), ((dm->fat_comb_b) - 1)); /* path-B  */ /* ant combination=regB38[18:16]+1 */
3646         }
3647 #endif
3648
3649         PHYDM_DBG(dm, DBG_ANT_DIV, "==>%s\n", __func__);
3650
3651         /* @1 TRAINING STATE */
3652         if (fat_tab->fat_state == FAT_TRAINING_STATE) {
3653                 /* @2 Caculate RSSI per Antenna */
3654
3655                 /* @3 [path-A]--------------------------- */
3656                 for (i = 0; i < (dm->fat_comb_a); i++) { /* @i : antenna index */
3657                         if (fat_tab->ant_rssi_cnt[i] == 0)
3658                                 fat_tab->ant_ave_rssi[i] = 0;
3659                         else {
3660                                 fat_tab->ant_ave_rssi[i] = fat_tab->ant_sum_rssi[i] / fat_tab->ant_rssi_cnt[i];
3661                                 is_pkt_filter_macth_path_a = true;
3662                         }
3663
3664                         if (fat_tab->ant_ave_rssi[i] > max_rssi_path_a) {
3665                                 max_rssi_path_a = fat_tab->ant_ave_rssi[i];
3666                                 pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
3667                                 target_ant_path_a = i;
3668                         } else if (fat_tab->ant_ave_rssi[i] == max_rssi_path_a) {
3669                                 if (fat_tab->ant_rssi_cnt[i] > pckcnt_path_a) {
3670                                         max_rssi_path_a = fat_tab->ant_ave_rssi[i];
3671                                         pckcnt_path_a = fat_tab->ant_rssi_cnt[i];
3672                                         target_ant_path_a = i;
3673                                 }
3674                         }
3675
3676                         PHYDM_DBG(
3677                                   "*** ant-index : [ %d ],      counter = (( %d )),     Avg RSSI = (( %d ))\n",
3678                                   i, fat_tab->ant_rssi_cnt[i],
3679                                   fat_tab->ant_ave_rssi[i]);
3680                 }
3681
3682 #if 0
3683 #if (RTL8192E_SUPPORT == 1)
3684                 /* @3 [path-B]--------------------------- */
3685                 for (i = 0; i < (dm->fat_comb_b); i++) {
3686                         if (fat_tab->antRSSIcnt_pathB[i] == 0)
3687                                 fat_tab->antAveRSSI_pathB[i] = 0;
3688                         else { /*  @(ant_rssi_cnt[i] != 0) */
3689                                 fat_tab->antAveRSSI_pathB[i] = fat_tab->antSumRSSI_pathB[i] / fat_tab->antRSSIcnt_pathB[i];
3690                                 is_pkt_filter_macth_path_b = true;
3691                         }
3692                         if (fat_tab->antAveRSSI_pathB[i] > max_rssi_path_b) {
3693                                 max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
3694                                 pckcnt_path_b = fat_tab->antRSSIcnt_pathB[i];
3695                                 target_ant_path_b = (u8)i;
3696                         }
3697                         if (fat_tab->antAveRSSI_pathB[i] == max_rssi_path_b) {
3698                                 if (fat_tab->antRSSIcnt_pathB > pckcnt_path_b) {
3699                                         max_rssi_path_b = fat_tab->antAveRSSI_pathB[i];
3700                                         target_ant_path_b = (u8)i;
3701                                 }
3702                         }
3703                         if (dm->fat_print_rssi == 1) {
3704                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3705                                           "***{path-B}: Sum RSSI[%d] = (( %d )),      cnt RSSI [%d] = (( %d )),     Avg RSSI[%d] = (( %d ))\n",
3706                                           i, fat_tab->antSumRSSI_pathB[i], i,
3707                                           fat_tab->antRSSIcnt_pathB[i], i,
3708                                           fat_tab->antAveRSSI_pathB[i]);
3709                         }
3710                 }
3711 #endif
3712 #endif
3713
3714                 /* @1 DECISION STATE */
3715
3716                 /* @2 Select TRX Antenna */
3717
3718                 phydm_fast_training_enable(dm, FAT_OFF);
3719
3720                 /* @3 [path-A]--------------------------- */
3721                 if (is_pkt_filter_macth_path_a == false) {
3722 #if 0
3723                         /* PHYDM_DBG(dm,DBG_ANT_DIV, "{path-A}: None Packet is matched\n"); */
3724 #endif
3725                         PHYDM_DBG(dm, DBG_ANT_DIV,
3726                                   "{path-A}: None Packet is matched\n");
3727                         odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
3728                 } else {
3729                         PHYDM_DBG(
3730                                   "target_ant_path_a = (( %d )) , max_rssi_path_a = (( %d ))\n",
3731                                   target_ant_path_a, max_rssi_path_a);
3732
3733                         /* @3 [ update RX-optional ant ]        Default RX is Omni, Optional RX is the best decision by FAT */
3734                         if (dm->support_ic_type == ODM_RTL8188E)
3735                                 odm_set_bb_reg(dm, R_0x864, BIT(8) | BIT(7) | BIT(6), target_ant_path_a);
3736                         else if (dm->support_ic_type == ODM_RTL8192E)
3737                                 odm_set_bb_reg(dm, R_0xb38, BIT(8) | BIT(7) | BIT(6), target_ant_path_a); /* Optional RX [pth-A] */
3738
3739                         /* @3 [ update TX ant ] */
3740                         odm_update_tx_ant(dm, target_ant_path_a, (fat_tab->train_idx));
3741
3742                         if (target_ant_path_a == 0)
3743                                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
3744                 }
3745 #if 0
3746 #if (RTL8192E_SUPPORT == 1)
3747                 /* @3 [path-B]--------------------------- */
3748                 if (is_pkt_filter_macth_path_b == false) {
3749                         if (dm->fat_print_rssi == 1)
3750                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3751                                           "***[%d]{path-B}: None Packet is matched\n\n\n",
3752                                           __LINE__);
3753                 } else {
3754                         if (dm->fat_print_rssi == 1) {
3755                                 PHYDM_DBG(dm, DBG_ANT_DIV,
3756                                           " ***target_ant_path_b = (( %d )) *** max_rssi = (( %d ))***\n\n\n",
3757                                           target_ant_path_b, max_rssi_path_b);
3758                         }
3759                         odm_set_bb_reg(dm, R_0xb38, BIT(21) | BIT20 | BIT19, target_ant_path_b);        /* @Default RX is Omni, Optional RX is the best decision by FAT */
3760                         odm_set_bb_reg(dm, R_0x80c, BIT(21), 1); /* Reg80c[21]=1'b1             //from TX Info */
3761
3762                         fat_tab->antsel_pathB[fat_tab->train_idx] = target_ant_path_b;
3763                 }
3764 #endif
3765 #endif
3766
3767                 /* @2 Reset counter */
3768                 for (i = 0; i < (dm->fat_comb_a); i++) {
3769                         fat_tab->ant_sum_rssi[i] = 0;
3770                         fat_tab->ant_rssi_cnt[i] = 0;
3771                 }
3772                 /*@
3773                 #if (RTL8192E_SUPPORT == 1)
3774                 for(i=0; i<=(dm->fat_comb_b); i++)
3775                 {
3776                         fat_tab->antSumRSSI_pathB[i] = 0;
3777                         fat_tab->antRSSIcnt_pathB[i] = 0;
3778                 }
3779                 #endif
3780                 */
3781
3782                 fat_tab->fat_state = FAT_PREPARE_STATE;
3783                 return;
3784         }
3785
3786         /* @1 NORMAL STATE */
3787         if (fat_tab->fat_state == FAT_PREPARE_STATE) {
3788                 PHYDM_DBG(dm, DBG_ANT_DIV, "[ Start Prepare state ]\n");
3789
3790                 odm_set_next_mac_addr_target(dm);
3791
3792                 /* @2 Prepare Training */
3793                 fat_tab->fat_state = FAT_TRAINING_STATE;
3794                 phydm_fast_training_enable(dm, FAT_ON);
3795                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
3796                 /* @enable HW AntDiv */
3797                 PHYDM_DBG(dm, DBG_ANT_DIV, "[Start Training state]\n");
3798
3799                 odm_set_timer(dm, &dm->fast_ant_training_timer, dm->antdiv_intvl); /* @ms */
3800         }
3801 }
3802
3803 void odm_fast_ant_training_callback(
3804         void *dm_void)
3805 {
3806         struct dm_struct *dm = (struct dm_struct *)dm_void;
3807
3808 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3809         if (*(dm->is_net_closed) == true)
3810                 return;
3811 #endif
3812
3813 #if USE_WORKITEM
3814         odm_schedule_work_item(&dm->fast_ant_training_workitem);
3815 #else
3816         PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
3817         odm_fast_ant_training(dm);
3818 #endif
3819 }
3820
3821 void odm_fast_ant_training_work_item_callback(
3822         void *dm_void)
3823 {
3824         struct dm_struct *dm = (struct dm_struct *)dm_void;
3825
3826         PHYDM_DBG(dm, DBG_ANT_DIV, "******%s******\n", __func__);
3827         odm_fast_ant_training(dm);
3828 }
3829
3830 #endif
3831
3832 void odm_ant_div_init(
3833         void *dm_void)
3834 {
3835         struct dm_struct *dm = (struct dm_struct *)dm_void;
3836         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
3837         struct sw_antenna_switch *dm_swat_table = &dm->dm_swat_table;
3838
3839         if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
3840                 PHYDM_DBG(dm, DBG_ANT_DIV,
3841                           "[Return!!!]   Not Support Antenna Diversity Function\n");
3842                 return;
3843         }
3844 /* @--- */
3845 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3846         if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
3847                 PHYDM_DBG(dm, DBG_ANT_DIV,
3848                           "[2G AntDiv Init]: Only Support 2G Antenna Diversity Function\n");
3849                 if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
3850                         return;
3851         } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
3852                 PHYDM_DBG(dm, DBG_ANT_DIV,
3853                           "[5G AntDiv Init]: Only Support 5G Antenna Diversity Function\n");
3854                 if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
3855                         return;
3856         } else if (fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G | ODM_ANTDIV_5G))
3857                 PHYDM_DBG(dm, DBG_ANT_DIV,
3858                           "[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n");
3859
3860 #endif
3861         /* @--- */
3862
3863         /* @2 [--General---] */
3864         dm->antdiv_period = 0;
3865
3866         fat_tab->is_become_linked = false;
3867         fat_tab->ant_div_on_off = 0xff;
3868
3869 /* @3       -   AP   - */
3870 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3871
3872 #if (BEAMFORMING_SUPPORT == 1)
3873 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3874         odm_bdc_init(dm);
3875 #endif
3876 #endif
3877
3878 /* @3     -   WIN   - */
3879 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3880         dm_swat_table->ant_5g = MAIN_ANT;
3881         dm_swat_table->ant_2g = MAIN_ANT;
3882 #endif
3883
3884         /* @2 [---Set MAIN_ANT as default antenna if Auto-ant enable---] */
3885         if (fat_tab->div_path_type == ANT_PATH_A)
3886                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
3887         else if (fat_tab->div_path_type == ANT_PATH_B)
3888                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
3889         else if (fat_tab->div_path_type == ANT_PATH_AB)
3890                 odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_AB);
3891
3892         dm->ant_type = ODM_AUTO_ANT;
3893
3894         fat_tab->rx_idle_ant = 0xff; /*to make RX-idle-antenna will be updated absolutly*/
3895         odm_update_rx_idle_ant(dm, MAIN_ANT);
3896         phydm_keep_rx_ack_ant_by_tx_ant_time(dm, 0); /* Timming issue: keep Rx ant after tx for ACK ( 5 x 3.2 mu = 16mu sec)*/
3897
3898         /* @2 [---Set TX Antenna---] */
3899         if (fat_tab->p_force_tx_ant_by_desc == NULL) {
3900                 fat_tab->force_tx_ant_by_desc = 0;
3901                 fat_tab->p_force_tx_ant_by_desc = &fat_tab->force_tx_ant_by_desc;
3902         }
3903         PHYDM_DBG(dm, DBG_ANT_DIV, "p_force_tx_ant_by_desc = %d\n",
3904                   *fat_tab->p_force_tx_ant_by_desc);
3905
3906         if (*fat_tab->p_force_tx_ant_by_desc == true)
3907                 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
3908         else
3909                 odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
3910
3911         /* @2 [--88E---] */
3912         if (dm->support_ic_type == ODM_RTL8188E) {
3913 #if (RTL8188E_SUPPORT == 1)
3914                 /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
3915                 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
3916                 /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
3917
3918                 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV && dm->ant_div_type != CG_TRX_HW_ANTDIV && dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
3919                         PHYDM_DBG(dm, DBG_ANT_DIV,
3920                                   "[Return!!!]  88E Not Supprrt This AntDiv type\n");
3921                         dm->support_ability &= ~(ODM_BB_ANT_DIV);
3922                         return;
3923                 }
3924
3925                 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
3926                         odm_rx_hw_ant_div_init_88e(dm);
3927                 else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
3928                         odm_trx_hw_ant_div_init_88e(dm);
3929 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3930                 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
3931                         odm_smart_hw_ant_div_init_88e(dm);
3932 #endif
3933 #endif
3934         }
3935
3936 /* @2 [--92E---] */
3937 #if (RTL8192E_SUPPORT == 1)
3938         else if (dm->support_ic_type == ODM_RTL8192E) {
3939                 /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
3940                 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
3941                 /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
3942
3943                 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV && dm->ant_div_type != CG_TRX_HW_ANTDIV && dm->ant_div_type != CG_TRX_SMART_ANTDIV) {
3944                         PHYDM_DBG(dm, DBG_ANT_DIV,
3945                                   "[Return!!!]  8192E Not Supprrt This AntDiv type\n");
3946                         dm->support_ability &= ~(ODM_BB_ANT_DIV);
3947                         return;
3948                 }
3949
3950                 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
3951                         odm_rx_hw_ant_div_init_92e(dm);
3952                 else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
3953                         odm_trx_hw_ant_div_init_92e(dm);
3954 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
3955                 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
3956                         odm_smart_hw_ant_div_init_92e(dm);
3957 #endif
3958         }
3959 #endif
3960
3961         /* @2 [--92F---] */
3962 #if (RTL8192F_SUPPORT == 1)
3963         else if (dm->support_ic_type == ODM_RTL8192F) {
3964         /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
3965         /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
3966         /* @dm->ant_div_type = CG_TRX_SMART_ANTDIV; */
3967
3968         if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
3969                 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
3970                         PHYDM_DBG(dm, DBG_ANT_DIV,
3971                                   "[Return!!!]  8192F Not Supprrt This AntDiv type\n");
3972                         dm->support_ability &= ~(ODM_BB_ANT_DIV);
3973                         return;
3974                 }
3975         }
3976         if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
3977                 odm_rx_hw_ant_div_init_92f(dm);
3978         else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
3979         odm_trx_hw_ant_div_init_92f(dm);
3980         }
3981 #endif
3982
3983 #if (RTL8197F_SUPPORT == 1)
3984         else if (dm->support_ic_type == ODM_RTL8197F) {
3985                 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
3986
3987                 if (dm->ant_div_type != CGCS_RX_HW_ANTDIV) {
3988                         PHYDM_DBG(dm, DBG_ANT_DIV,
3989                                   "[Return!!!]  8197F Not Supprrt This AntDiv type\n");
3990                         dm->support_ability &= ~(ODM_BB_ANT_DIV);
3991                         return;
3992                 }
3993                 phydm_rx_hw_ant_div_init_97f(dm);
3994         }
3995 #endif
3996 /* @2 [--8723B---] */
3997 #if (RTL8723B_SUPPORT == 1)
3998         else if (dm->support_ic_type == ODM_RTL8723B) {
3999                 dm->ant_div_type = S0S1_SW_ANTDIV;
4000                 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4001
4002                 if (dm->ant_div_type != S0S1_SW_ANTDIV && dm->ant_div_type != CG_TRX_HW_ANTDIV) {
4003                         PHYDM_DBG(dm, DBG_ANT_DIV,
4004                                   "[Return!!!] 8723B  Not Supprrt This AntDiv type\n");
4005                         dm->support_ability &= ~(ODM_BB_ANT_DIV);
4006                         return;
4007                 }
4008
4009                 if (dm->ant_div_type == S0S1_SW_ANTDIV)
4010                         odm_s0s1_sw_ant_div_init_8723b(dm);
4011                 else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4012                         odm_trx_hw_ant_div_init_8723b(dm);
4013         }
4014 #endif
4015 /*@2 [--8723D---]*/
4016 #if (RTL8723D_SUPPORT == 1)
4017         else if (dm->support_ic_type == ODM_RTL8723D) {
4018                 if (fat_tab->p_default_s0_s1 == NULL) {
4019                         fat_tab->default_s0_s1 = 1;
4020                         fat_tab->p_default_s0_s1 = &fat_tab->default_s0_s1;
4021                 }
4022                 PHYDM_DBG(dm, DBG_ANT_DIV, "default_s0_s1 = %d\n",
4023                           *fat_tab->p_default_s0_s1);
4024
4025                 if (*fat_tab->p_default_s0_s1 == true)
4026                         odm_update_rx_idle_ant(dm, MAIN_ANT);
4027                 else
4028                         odm_update_rx_idle_ant(dm, AUX_ANT);
4029
4030                 if (dm->ant_div_type == S0S1_TRX_HW_ANTDIV)
4031                         odm_trx_hw_ant_div_init_8723d(dm);
4032                 else if (dm->ant_div_type == S0S1_SW_ANTDIV)
4033                         odm_s0s1_sw_ant_div_init_8723d(dm);
4034                 else {
4035                         PHYDM_DBG(dm, DBG_ANT_DIV,
4036                                   "[Return!!!] 8723D  Not Supprrt This AntDiv type\n");
4037                         dm->support_ability &= ~(ODM_BB_ANT_DIV);
4038                         return;
4039                 }
4040         }
4041 #endif
4042 /* @2 [--8811A 8821A---] */
4043 #if (RTL8821A_SUPPORT == 1)
4044         else if (dm->support_ic_type == ODM_RTL8821) {
4045 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
4046                 dm->ant_div_type = HL_SW_SMART_ANT_TYPE1;
4047
4048                 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
4049                         odm_trx_hw_ant_div_init_8821a(dm);
4050                         phydm_hl_smart_ant_type1_init_8821a(dm);
4051                 } else
4052 #endif
4053                 {
4054 #ifdef ODM_CONFIG_BT_COEXIST
4055                         dm->ant_div_type = S0S1_SW_ANTDIV;
4056 #else
4057                         dm->ant_div_type = CG_TRX_HW_ANTDIV;
4058 #endif
4059
4060                         if (dm->ant_div_type != CG_TRX_HW_ANTDIV && dm->ant_div_type != S0S1_SW_ANTDIV) {
4061                                 PHYDM_DBG(dm, DBG_ANT_DIV,
4062                                           "[Return!!!] 8821A & 8811A  Not Supprrt This AntDiv type\n");
4063                                 dm->support_ability &= ~(ODM_BB_ANT_DIV);
4064                                 return;
4065                         }
4066                         if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4067                                 odm_trx_hw_ant_div_init_8821a(dm);
4068                         else if (dm->ant_div_type == S0S1_SW_ANTDIV)
4069                                 odm_s0s1_sw_ant_div_init_8821a(dm);
4070                 }
4071         }
4072 #endif
4073
4074 /* @2 [--8821C---] */
4075 #if (RTL8821C_SUPPORT == 1)
4076         else if (dm->support_ic_type == ODM_RTL8821C) {
4077                 dm->ant_div_type = S0S1_SW_ANTDIV;
4078                 if (dm->ant_div_type != S0S1_SW_ANTDIV) {
4079                         PHYDM_DBG(dm, DBG_ANT_DIV,
4080                                   "[Return!!!] 8821C  Not Supprrt This AntDiv type\n");
4081                         dm->support_ability &= ~(ODM_BB_ANT_DIV);
4082                         return;
4083                 }
4084                 phydm_s0s1_sw_ant_div_init_8821c(dm);
4085                 odm_trx_hw_ant_div_init_8821c(dm);
4086         }
4087 #endif
4088
4089 /* @2 [--8881A---] */
4090 #if (RTL8881A_SUPPORT == 1)
4091         else if (dm->support_ic_type == ODM_RTL8881A) {
4092                 /* @dm->ant_div_type = CGCS_RX_HW_ANTDIV; */
4093                 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4094
4095                 if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
4096                         odm_trx_hw_ant_div_init_8881a(dm);
4097                 } else {
4098                         PHYDM_DBG(dm, DBG_ANT_DIV,
4099                                   "[Return!!!] 8881A  Not Supprrt This AntDiv type\n");
4100                         dm->support_ability &= ~(ODM_BB_ANT_DIV);
4101                         return;
4102                 }
4103
4104                 odm_trx_hw_ant_div_init_8881a(dm);
4105         }
4106 #endif
4107
4108 /* @2 [--8812---] */
4109 #if (RTL8812A_SUPPORT == 1)
4110         else if (dm->support_ic_type == ODM_RTL8812) {
4111                 /* @dm->ant_div_type = CG_TRX_HW_ANTDIV; */
4112
4113                 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
4114                         PHYDM_DBG(dm, DBG_ANT_DIV,
4115                                   "[Return!!!] 8812A  Not Supprrt This AntDiv type\n");
4116                         dm->support_ability &= ~(ODM_BB_ANT_DIV);
4117                         return;
4118                 }
4119                 odm_trx_hw_ant_div_init_8812a(dm);
4120         }
4121 #endif
4122
4123 /*@[--8188F---]*/
4124 #if (RTL8188F_SUPPORT == 1)
4125         else if (dm->support_ic_type == ODM_RTL8188F) {
4126                 dm->ant_div_type = S0S1_SW_ANTDIV;
4127                 odm_s0s1_sw_ant_div_init_8188f(dm);
4128         }
4129 #endif
4130
4131 /*@[--8822B---]*/
4132 #if (RTL8822B_SUPPORT == 1)
4133         else if (dm->support_ic_type == ODM_RTL8822B) {
4134                 dm->ant_div_type = CG_TRX_HW_ANTDIV;
4135
4136                 if (dm->ant_div_type != CG_TRX_HW_ANTDIV) {
4137                         PHYDM_DBG(dm, DBG_ANT_DIV,
4138                                   "[Return!!!]  8822B Not Supprrt This AntDiv type\n");
4139                         dm->support_ability &= ~(ODM_BB_ANT_DIV);
4140                         return;
4141                 }
4142                 phydm_trx_hw_ant_div_init_22b(dm);
4143 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
4144                 dm->ant_div_type = HL_SW_SMART_ANT_TYPE2;
4145
4146                 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2)
4147                         phydm_hl_smart_ant_type2_init_8822b(dm);
4148 #endif
4149         }
4150 #endif
4151
4152         /*@
4153         PHYDM_DBG(dm, DBG_ANT_DIV, "*** support_ic_type=[%lu]\n",dm->support_ic_type);
4154         PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv support_ability=[%lu]\n",(dm->support_ability & ODM_BB_ANT_DIV)>>6);
4155         PHYDM_DBG(dm, DBG_ANT_DIV, "*** AntDiv type=[%d]\n",dm->ant_div_type);
4156         */
4157 }
4158
4159 void odm_ant_div(
4160         void *dm_void)
4161 {
4162         struct dm_struct *dm = (struct dm_struct *)dm_void;
4163         void *adapter = dm->adapter;
4164         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4165 #if (defined(CONFIG_HL_SMART_ANTENNA))
4166         struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
4167 #endif
4168
4169 #ifdef ODM_EVM_ENHANCE_ANTDIV
4170
4171         if (dm->is_linked) {
4172                 PHYDM_DBG(dm, DBG_ANT_DIV,
4173                           "tp_active_occur=((%d)), evm_method_enable=((%d))\n",
4174                           dm->tp_active_occur, fat_tab->evm_method_enable);
4175
4176                 if (dm->tp_active_occur == 1 && fat_tab->evm_method_enable == 1) {
4177                         fat_tab->idx_ant_div_counter_5g = dm->antdiv_period;
4178                         fat_tab->idx_ant_div_counter_2g = dm->antdiv_period;
4179                 }
4180         }
4181 #endif
4182
4183         if (*dm->band_type == ODM_BAND_5G) {
4184                 if (fat_tab->idx_ant_div_counter_5g < dm->antdiv_period) {
4185                         fat_tab->idx_ant_div_counter_5g++;
4186                         return;
4187                 } else
4188                         fat_tab->idx_ant_div_counter_5g = 0;
4189         } else if (*dm->band_type == ODM_BAND_2_4G) {
4190                 if (fat_tab->idx_ant_div_counter_2g < dm->antdiv_period) {
4191                         fat_tab->idx_ant_div_counter_2g++;
4192                         return;
4193                 } else
4194                         fat_tab->idx_ant_div_counter_2g = 0;
4195         }
4196
4197 /* @---------- */
4198
4199 /* @---------- */
4200 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN || DM_ODM_SUPPORT_TYPE == ODM_CE)
4201
4202         if (fat_tab->enable_ctrl_frame_antdiv) {
4203                 if (dm->data_frame_num <= 10 && dm->is_linked)
4204                         fat_tab->use_ctrl_frame_antdiv = 1;
4205                 else
4206                         fat_tab->use_ctrl_frame_antdiv = 0;
4207
4208                 PHYDM_DBG(dm, DBG_ANT_DIV,
4209                           "use_ctrl_frame_antdiv = (( %d )), data_frame_num = (( %d ))\n",
4210                           fat_tab->use_ctrl_frame_antdiv, dm->data_frame_num);
4211                 dm->data_frame_num = 0;
4212         }
4213
4214         {
4215 #if (BEAMFORMING_SUPPORT == 1)
4216
4217                 enum beamforming_cap beamform_cap = phydm_get_beamform_cap(dm);
4218                 PHYDM_DBG(dm, DBG_ANT_DIV, "is_bt_continuous_turn = ((%d))\n",
4219                           dm->is_bt_continuous_turn);
4220                 PHYDM_DBG(dm, DBG_ANT_DIV,
4221                           "[ AntDiv Beam Cap ]   cap= ((%d))\n", beamform_cap);
4222                 if (!dm->is_bt_continuous_turn) {
4223                         if ((beamform_cap & BEAMFORMEE_CAP) && (!(*fat_tab->is_no_csi_feedback))) { /* @BFmee On  &&   Div On->Div Off */
4224                                 PHYDM_DBG(dm, DBG_ANT_DIV,
4225                                           "[ AntDiv : OFF ]   BFmee ==1; cap= ((%d))\n",
4226                                           beamform_cap);
4227                                 PHYDM_DBG(dm, DBG_ANT_DIV,
4228                                           "[ AntDiv BF]   is_no_csi_feedback= ((%d))\n",
4229                                           *(fat_tab->is_no_csi_feedback));
4230                                 if (fat_tab->fix_ant_bfee == 0) {
4231                                         odm_ant_div_on_off(dm, ANTDIV_OFF,
4232                                                            ANT_PATH_A);
4233                                         fat_tab->fix_ant_bfee = 1;
4234                                 }
4235                                 return;
4236                         } else { /* @BFmee Off   &&   Div Off->Div On */
4237                                 if (fat_tab->fix_ant_bfee == 1 && dm->is_linked) {
4238                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[ AntDiv : ON ]   BFmee ==0; cap=((%d))\n", beamform_cap);
4239                                         PHYDM_DBG(dm, DBG_ANT_DIV, "[ AntDiv BF]   is_no_csi_feedback= ((%d))\n", *(fat_tab->is_no_csi_feedback));
4240                                         if (dm->ant_div_type != S0S1_SW_ANTDIV)
4241                                                 odm_ant_div_on_off(dm, ANTDIV_ON
4242                                                                    , ANT_PATH_A)
4243                                                                    ;
4244                                         fat_tab->fix_ant_bfee = 0;
4245                                 }
4246                         }
4247                 } else {
4248                         if (fat_tab->div_path_type == ANT_PATH_A)
4249                                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
4250                         else if (fat_tab->div_path_type == ANT_PATH_B)
4251                                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
4252                         else if (fat_tab->div_path_type == ANT_PATH_AB)
4253                                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_AB);
4254                 }
4255 #endif
4256         }
4257 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
4258         /* @----------just for fool proof */
4259
4260         if (dm->antdiv_rssi)
4261                 dm->debug_components |= DBG_ANT_DIV;
4262         else
4263                 dm->debug_components &= ~DBG_ANT_DIV;
4264
4265         if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_2G) {
4266 #if 0
4267                 /* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 2G AntDiv Running ]\n"); */
4268 #endif
4269                 if (!(dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC))
4270                         return;
4271         } else if (fat_tab->ant_div_2g_5g == ODM_ANTDIV_5G) {
4272 #if 0
4273                 /* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 5G AntDiv Running ]\n"); */
4274 #endif
4275                 if (!(dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC))
4276                         return;
4277         }
4278 #if 0
4279 /* @else        if(fat_tab->ant_div_2g_5g == (ODM_ANTDIV_2G|ODM_ANTDIV_5G)) */
4280 /* @{ */
4281 /* PHYDM_DBG(dm, DBG_ANT_DIV,"[ 2G & 5G AntDiv Running ]\n"); */
4282 /* @} */
4283 #endif
4284 #endif
4285
4286         /* @---------- */
4287
4288         if (dm->antdiv_select == 1)
4289                 dm->ant_type = ODM_FIX_MAIN_ANT;
4290         else if (dm->antdiv_select == 2)
4291                 dm->ant_type = ODM_FIX_AUX_ANT;
4292         else { /* @if (dm->antdiv_select==0) */
4293                 dm->ant_type = ODM_AUTO_ANT;
4294
4295 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4296                 /*Stop Antenna diversity for CMW500 testing case*/
4297                 if (dm->consecutive_idlel_time >= 10) {
4298                         dm->ant_type = ODM_FIX_MAIN_ANT;
4299                         PHYDM_DBG(dm, DBG_ANT_DIV,
4300                                   "[AntDiv: OFF] No TP case, consecutive_idlel_time=((%d))\n",
4301                                   dm->consecutive_idlel_time);
4302                 }
4303 #endif
4304         }
4305
4306 #if 0
4307         /* PHYDM_DBG(dm, DBG_ANT_DIV,"ant_type= (( %d )) , pre_ant_type= (( %d ))\n",dm->ant_type,dm->pre_ant_type); */
4308 #endif
4309
4310         if (dm->ant_type != ODM_AUTO_ANT) {
4311                 PHYDM_DBG(dm, DBG_ANT_DIV, "Fix Antenna at (( %s ))\n",
4312                           (dm->ant_type == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
4313
4314                 if (dm->ant_type != dm->pre_ant_type) {
4315                         odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
4316                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4317
4318                         if (dm->ant_type == ODM_FIX_MAIN_ANT)
4319                                 odm_update_rx_idle_ant(dm, MAIN_ANT);
4320                         else if (dm->ant_type == ODM_FIX_AUX_ANT)
4321                                 odm_update_rx_idle_ant(dm, AUX_ANT);
4322                 }
4323                 dm->pre_ant_type = dm->ant_type;
4324                 return;
4325         } else {
4326                 if (dm->ant_type != dm->pre_ant_type) {
4327                         odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
4328                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
4329                 }
4330                 dm->pre_ant_type = dm->ant_type;
4331         }
4332 #if (defined(CONFIG_2T4R_ANTENNA))
4333         if (dm->ant_type2 != ODM_AUTO_ANT) {
4334                 PHYDM_DBG(dm, DBG_ANT_DIV, "PathB Fix Ant at (( %s ))\n",
4335                           (dm->ant_type2 == ODM_FIX_MAIN_ANT) ? "MAIN" : "AUX");
4336
4337                 if (dm->ant_type2 != dm->pre_ant_type2) {
4338                         odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_B);
4339                         odm_tx_by_tx_desc_or_reg(dm, TX_BY_REG);
4340
4341                         if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
4342                                 phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
4343                         else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
4344                                 phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
4345                 }
4346                 dm->pre_ant_type2 = dm->ant_type2;
4347                 return;
4348         }
4349         if (dm->ant_type2 != dm->pre_ant_type2) {
4350                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_B);
4351                 odm_tx_by_tx_desc_or_reg(dm, TX_BY_DESC);
4352         }
4353         dm->pre_ant_type2 = dm->ant_type2;
4354
4355 #endif
4356
4357         /* @3 ----------------------------------------------------------------------------------------------------------- */
4358         /* @2 [--88E---] */
4359         if (dm->support_ic_type == ODM_RTL8188E) {
4360 #if (RTL8188E_SUPPORT == 1)
4361                 if (dm->ant_div_type == CG_TRX_HW_ANTDIV || dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4362                         odm_hw_ant_div(dm);
4363
4364 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4365                 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
4366                         odm_fast_ant_training(dm);
4367 #endif
4368
4369 #endif
4370         }
4371 /* @2 [--92E---] */
4372 #if (RTL8192E_SUPPORT == 1)
4373         else if (dm->support_ic_type == ODM_RTL8192E) {
4374                 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV || dm->ant_div_type == CG_TRX_HW_ANTDIV)
4375                         odm_hw_ant_div(dm);
4376
4377 #if (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
4378                 else if (dm->ant_div_type == CG_TRX_SMART_ANTDIV)
4379                         odm_fast_ant_training(dm);
4380 #endif
4381         }
4382 #endif
4383 /* @2 [--97F---] */
4384 #if (RTL8197F_SUPPORT == 1)
4385         else if (dm->support_ic_type == ODM_RTL8197F) {
4386                 if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4387                         odm_hw_ant_div(dm);
4388         }
4389 #endif
4390
4391 #if (RTL8723B_SUPPORT == 1)
4392         /* @2 [--8723B---] */
4393         else if (dm->support_ic_type == ODM_RTL8723B) {
4394                 if (phydm_is_bt_enable_8723b(dm)) {
4395                         PHYDM_DBG(dm, DBG_ANT_DIV, "[BT is enable!!!]\n");
4396                         if (fat_tab->is_become_linked == true) {
4397                                 PHYDM_DBG(dm, DBG_ANT_DIV,
4398                                           "Set REG 948[9:6]=0x0\n");
4399                                 if (dm->support_ic_type == ODM_RTL8723B)
4400                                         odm_set_bb_reg(dm, R_0x948, BIT(9) | BIT(8) | BIT(7) | BIT(6), 0x0);
4401
4402                                 fat_tab->is_become_linked = false;
4403                         }
4404                 } else {
4405                         if (dm->ant_div_type == S0S1_SW_ANTDIV) {
4406 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
4407                                 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
4408 #endif
4409                         } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4410                                 odm_hw_ant_div(dm);
4411                 }
4412         }
4413 #endif
4414 /*@8723D*/
4415 #if (RTL8723D_SUPPORT == 1)
4416         else if (dm->support_ic_type == ODM_RTL8723D) {
4417                 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
4418 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
4419                         if (dm->antdiv_counter ==
4420                                 CONFIG_ANTENNA_DIVERSITY_PERIOD) {
4421                                 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
4422                                 dm->antdiv_counter--;
4423                         } else {
4424                                 dm->antdiv_counter--;
4425                         }
4426                         if (dm->antdiv_counter == 0)
4427                                 dm->antdiv_counter = CONFIG_ANTENNA_DIVERSITY_PERIOD;
4428 #endif
4429                 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
4430                         odm_hw_ant_div(dm);
4431                 }
4432         }
4433 #endif
4434
4435 /* @2 [--8821A---] */
4436 #if (RTL8821A_SUPPORT == 1)
4437         else if (dm->support_ic_type == ODM_RTL8821) {
4438 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
4439                 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
4440                         if (sat_tab->fix_beam_pattern_en != 0) {
4441                                 PHYDM_DBG(dm, DBG_ANT_DIV,
4442                                           " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
4443                                           sat_tab->fix_beam_pattern_codeword);
4444                                 /*return;*/
4445                         } else {
4446 #if 0
4447                                 /*PHYDM_DBG(dm, DBG_ANT_DIV, "[ SmartAnt ] ant_div_type = HL_SW_SMART_ANT_TYPE1\n");*/
4448 #endif
4449                                 odm_fast_ant_training_hl_smart_antenna_type1(dm);
4450                         }
4451
4452                 } else
4453 #endif
4454                 {
4455 #ifdef ODM_CONFIG_BT_COEXIST
4456                         if (!dm->bt_info_table.is_bt_enabled) { /*@BT disabled*/
4457                                 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
4458                                         dm->ant_div_type = CG_TRX_HW_ANTDIV;
4459                                         PHYDM_DBG(dm, DBG_ANT_DIV, " [S0S1_SW_ANTDIV]  ->  [CG_TRX_HW_ANTDIV]\n");
4460 #if 0
4461                                         /*odm_set_bb_reg(dm, R_0x8d4, BIT24, 1); */
4462 #endif
4463                                         if (fat_tab->is_become_linked == true)
4464                                                 odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
4465                                 }
4466
4467                         } else { /*@BT enabled*/
4468
4469                                 if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
4470                                         dm->ant_div_type = S0S1_SW_ANTDIV;
4471                                         PHYDM_DBG(dm, DBG_ANT_DIV, " [CG_TRX_HW_ANTDIV]  ->  [S0S1_SW_ANTDIV]\n");
4472 #if 0
4473                                         /*odm_set_bb_reg(dm, R_0x8d4, BIT24, 0);*/
4474 #endif
4475                                         odm_ant_div_on_off(dm, ANTDIV_OFF, ANT_PATH_A);
4476                                 }
4477                         }
4478 #endif
4479
4480                         if (dm->ant_div_type == S0S1_SW_ANTDIV) {
4481 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
4482                                 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
4483 #endif
4484                         } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4485                                 odm_hw_ant_div(dm);
4486                 }
4487         }
4488 #endif
4489
4490 /* @2 [--8821C---] */
4491 #if (RTL8821C_SUPPORT == 1)
4492         else if (dm->support_ic_type == ODM_RTL8821C) {
4493                 if (!dm->is_bt_continuous_turn) {
4494                         dm->ant_div_type = S0S1_SW_ANTDIV;
4495                         PHYDM_DBG(dm, DBG_ANT_DIV,
4496                                   "is_bt_continuous_turn = ((%d))   ==> SW AntDiv\n",
4497                                   dm->is_bt_continuous_turn);
4498
4499                 } else {
4500                         dm->ant_div_type = CG_TRX_HW_ANTDIV;
4501                         PHYDM_DBG(dm, DBG_ANT_DIV,
4502                                   "is_bt_continuous_turn = ((%d))   ==> HW AntDiv\n",
4503                                   dm->is_bt_continuous_turn);
4504                         odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
4505                 }
4506
4507                 if (fat_tab->force_antdiv_type)
4508                         dm->ant_div_type = fat_tab->antdiv_type_dbg;
4509
4510                 if (dm->ant_div_type == S0S1_SW_ANTDIV) {
4511 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
4512                         odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
4513 #endif
4514                 } else if (dm->ant_div_type == CG_TRX_HW_ANTDIV) {
4515                         odm_ant_div_on_off(dm, ANTDIV_ON, ANT_PATH_A);
4516                         odm_hw_ant_div(dm);
4517                 }
4518         }
4519 #endif
4520
4521 /* @2 [--8881A---] */
4522 #if (RTL8881A_SUPPORT == 1)
4523         else if (dm->support_ic_type == ODM_RTL8881A)
4524                 odm_hw_ant_div(dm);
4525 #endif
4526
4527 /* @2 [--8812A---] */
4528 #if (RTL8812A_SUPPORT == 1)
4529         else if (dm->support_ic_type == ODM_RTL8812)
4530                 odm_hw_ant_div(dm);
4531 #endif
4532
4533 #if (RTL8188F_SUPPORT == 1)
4534         /* @[--8188F---]*/
4535         else if (dm->support_ic_type == ODM_RTL8188F) {
4536 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
4537                 odm_s0s1_sw_ant_div(dm, SWAW_STEP_PEEK);
4538 #endif
4539         }
4540 #endif
4541
4542 /* @[--8822B---]*/
4543 #if (RTL8822B_SUPPORT == 1)
4544         else if (dm->support_ic_type == ODM_RTL8822B) {
4545                 if (dm->ant_div_type == CG_TRX_HW_ANTDIV)
4546                         odm_hw_ant_div(dm);
4547 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
4548                 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) {
4549                         if (sat_tab->fix_beam_pattern_en != 0)
4550                                 PHYDM_DBG(dm, DBG_ANT_DIV,
4551                                           " [ SmartAnt ] Fix SmartAnt Pattern = 0x%x\n",
4552                                           sat_tab->fix_beam_pattern_codeword);
4553                         else
4554                                 phydm_fast_ant_training_hl_smart_antenna_type2(dm);
4555                 }
4556 #endif
4557         }
4558 #endif
4559 }
4560
4561 void odm_antsel_statistics(
4562         void *dm_void,
4563         void *phy_info_void,
4564         u8 antsel_tr_mux,
4565         u32 mac_id,
4566         u32 utility,
4567         u8 method,
4568         u8 is_cck_rate
4569
4570         )
4571 {
4572         struct dm_struct *dm = (struct dm_struct *)dm_void;
4573         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4574         struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
4575
4576         if (method == RSSI_METHOD) {
4577                 if (is_cck_rate) {
4578                         if (antsel_tr_mux == ANT1_2G) {
4579                                 if (fat_tab->main_ant_sum_cck[mac_id] > 65435) /*to prevent u16 overflow, max(RSSI)=100, 65435+100 = 65535 (u16)*/
4580                                         return;
4581
4582                                 fat_tab->main_ant_sum_cck[mac_id] += (u16)utility;
4583                                 fat_tab->main_ant_cnt_cck[mac_id]++;
4584                         } else {
4585                                 if (fat_tab->aux_ant_sum_cck[mac_id] > 65435)
4586                                         return;
4587
4588                                 fat_tab->aux_ant_sum_cck[mac_id] += (u16)utility;
4589                                 fat_tab->aux_ant_cnt_cck[mac_id]++;
4590                         }
4591
4592                 } else { /*ofdm rate*/
4593
4594                         if (antsel_tr_mux == ANT1_2G) {
4595                                 if (fat_tab->main_ant_sum[mac_id] > 65435)
4596                                         return;
4597
4598                                 fat_tab->main_ant_sum[mac_id] += (u16)utility;
4599                                 fat_tab->main_ant_cnt[mac_id]++;
4600                         } else {
4601                                 if (fat_tab->aux_ant_sum[mac_id] > 65435)
4602                                         return;
4603
4604                                 fat_tab->aux_ant_sum[mac_id] += (u16)utility;
4605                                 fat_tab->aux_ant_cnt[mac_id]++;
4606                         }
4607                 }
4608         }
4609 #ifdef ODM_EVM_ENHANCE_ANTDIV
4610         else if (method == EVM_METHOD) {
4611                 if (dm->rate_ss == 1) {
4612                         if (antsel_tr_mux == ANT1_2G) {
4613                                 fat_tab->main_ant_evm_sum[mac_id] += ((phy_info->rx_mimo_evm_dbm[0]) << 5);
4614                                 fat_tab->main_ant_evm_cnt[mac_id]++;
4615                         } else {
4616                                 fat_tab->aux_ant_evm_sum[mac_id] += ((phy_info->rx_mimo_evm_dbm[0]) << 5);
4617                                 fat_tab->aux_ant_evm_cnt[mac_id]++;
4618                         }
4619
4620                 } else { /*@>= 2SS*/
4621
4622                         if (antsel_tr_mux == ANT1_2G) {
4623                                 fat_tab->main_ant_evm_2ss_sum[mac_id][0] += (phy_info->rx_mimo_evm_dbm[0] << 5);
4624                                 fat_tab->main_ant_evm_2ss_sum[mac_id][1] += (phy_info->rx_mimo_evm_dbm[1] << 5);
4625                                 fat_tab->main_ant_evm_2ss_cnt[mac_id]++;
4626
4627                         } else {
4628                                 fat_tab->aux_ant_evm_2ss_sum[mac_id][0] += (phy_info->rx_mimo_evm_dbm[0] << 5);
4629                                 fat_tab->aux_ant_evm_2ss_sum[mac_id][1] += (phy_info->rx_mimo_evm_dbm[1] << 5);
4630                                 fat_tab->aux_ant_evm_2ss_cnt[mac_id]++;
4631                         }
4632                 }
4633
4634         } else if (method == CRC32_METHOD) {
4635                 if (antsel_tr_mux == ANT1_2G) {
4636                         fat_tab->main_crc32_ok_cnt += utility;
4637                         fat_tab->main_crc32_fail_cnt++;
4638                 } else {
4639                         fat_tab->aux_crc32_ok_cnt += utility;
4640                         fat_tab->aux_crc32_fail_cnt++;
4641                 }
4642
4643         } else if (method == TP_METHOD) {
4644                 if ((utility <= ODM_RATEMCS15 && utility >= ODM_RATEMCS0) &&
4645                     fat_tab->fat_state_cnt <= dm->antdiv_tp_period) {
4646                         if (antsel_tr_mux == ANT1_2G) {
4647                                 fat_tab->antdiv_tp_main += (phy_rate_table[utility]) << 5;
4648                                 fat_tab->antdiv_tp_main_cnt++;
4649                         } else {
4650                                 fat_tab->antdiv_tp_aux += (phy_rate_table[utility]) << 5;
4651                                 fat_tab->antdiv_tp_aux_cnt++;
4652                         }
4653                 }
4654         }
4655 #endif
4656 }
4657
4658 void odm_process_rssi_for_ant_div(
4659         void *dm_void,
4660         void *phy_info_void,
4661         void *pkt_info_void)
4662 {
4663         struct dm_struct *dm = (struct dm_struct *)dm_void;
4664         struct phydm_phyinfo_struct *phy_info = (struct phydm_phyinfo_struct *)phy_info_void;
4665         struct phydm_perpkt_info_struct *pktinfo = (struct phydm_perpkt_info_struct *)pkt_info_void;
4666         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4667 #if (defined(CONFIG_HL_SMART_ANTENNA))
4668         struct smt_ant_honbo *sat_tab = &dm->dm_sat_table;
4669         u32 beam_tmp;
4670         u8 next_ant;
4671         u8 train_pkt_number;
4672 #endif
4673         u8 rx_power_ant0 = phy_info->rx_mimo_signal_strength[0];
4674         u8 rx_power_ant1 = phy_info->rx_mimo_signal_strength[1];
4675         u8 rx_evm_ant0 = phy_info->rx_mimo_signal_quality[0];
4676         u8 rx_evm_ant1 = phy_info->rx_mimo_signal_quality[1];
4677         u8 rssi_avg;
4678
4679         if ((dm->support_ic_type & ODM_IC_2SS) && !pktinfo->is_cck_rate) {
4680                 if (rx_power_ant1 < 100)
4681                         rssi_avg = (u8)odm_convert_to_db((phydm_db_2_linear(rx_power_ant0) + phydm_db_2_linear(rx_power_ant1)) >> 1); /*@averaged PWDB*/
4682
4683         } else {
4684                 rx_power_ant0 = (u8)phy_info->rx_pwdb_all;
4685                 rssi_avg = rx_power_ant0;
4686         }
4687
4688 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE2
4689         if ((dm->ant_div_type == HL_SW_SMART_ANT_TYPE2) && (fat_tab->fat_state == FAT_TRAINING_STATE))
4690                 phydm_process_rssi_for_hb_smtant_type2(dm, phy_info, pktinfo, rssi_avg); /*@for 8822B*/
4691         else
4692 #endif
4693
4694 #ifdef CONFIG_HL_SMART_ANTENNA_TYPE1
4695 #ifdef CONFIG_FAT_PATCH
4696                 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1 && fat_tab->fat_state == FAT_TRAINING_STATE) {
4697                 /*@[Beacon]*/
4698                 if (pktinfo->is_packet_beacon) {
4699                         sat_tab->beacon_counter++;
4700                         PHYDM_DBG(dm, DBG_ANT_DIV,
4701                                   "MatchBSSID_beacon_counter = ((%d))\n",
4702                                   sat_tab->beacon_counter);
4703
4704                         if (sat_tab->beacon_counter >= sat_tab->pre_beacon_counter + 2) {
4705                                 if (sat_tab->ant_num > 1) {
4706                                         next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
4707                                         odm_update_rx_idle_ant(dm, next_ant);
4708                                 }
4709
4710                                 sat_tab->update_beam_idx++;
4711
4712                                 PHYDM_DBG(dm, DBG_ANT_DIV,
4713                                           "pre_beacon_counter = ((%d)), pkt_counter = ((%d)), update_beam_idx = ((%d))\n",
4714                                           sat_tab->pre_beacon_counter,
4715                                           sat_tab->pkt_counter,
4716                                           sat_tab->update_beam_idx);
4717
4718                                 sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
4719                                 sat_tab->pkt_counter = 0;
4720                         }
4721                 }
4722                 /*@[data]*/
4723                 else if (pktinfo->is_packet_to_self) {
4724                         if (sat_tab->pkt_skip_statistic_en == 0) {
4725                                 /*@
4726                                 PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]:  antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
4727                                         pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
4728                                 */
4729                                 PHYDM_DBG(dm, DBG_ANT_DIV,
4730                                           "ID[%d][pkt_cnt = %d]: {ANT, Beam} = {%d, %d}, RSSI = ((%d))\n",
4731                                           pktinfo->station_id,
4732                                           sat_tab->pkt_counter,
4733                                           fat_tab->antsel_rx_keep_0,
4734                                           sat_tab->fast_training_beam_num,
4735                                           rx_power_ant0);
4736
4737                                 sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
4738                                 sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
4739                                 sat_tab->pkt_counter++;
4740
4741 #if 1
4742                                 train_pkt_number = sat_tab->beam_train_cnt[fat_tab->rx_idle_ant - 1][sat_tab->fast_training_beam_num];
4743 #else
4744                                 train_pkt_number = sat_tab->per_beam_training_pkt_num;
4745 #endif
4746
4747                                 /*Swich Antenna erery N pkts*/
4748                                 if (sat_tab->pkt_counter == train_pkt_number) {
4749                                         if (sat_tab->ant_num > 1) {
4750                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "packet enugh ((%d ))pkts ---> Switch antenna\n", train_pkt_number);
4751                                                 next_ant = (fat_tab->rx_idle_ant == MAIN_ANT) ? AUX_ANT : MAIN_ANT;
4752                                                 odm_update_rx_idle_ant(dm, next_ant);
4753                                         }
4754
4755                                         sat_tab->update_beam_idx++;
4756                                         PHYDM_DBG(dm, DBG_ANT_DIV, "pre_beacon_counter = ((%d)), update_beam_idx_counter = ((%d))\n",
4757                                                   sat_tab->pre_beacon_counter, sat_tab->update_beam_idx);
4758
4759                                         sat_tab->pre_beacon_counter = sat_tab->beacon_counter;
4760                                         sat_tab->pkt_counter = 0;
4761                                 }
4762                         }
4763                 }
4764
4765                 /*Swich Beam after switch "sat_tab->ant_num" antennas*/
4766                 if (sat_tab->update_beam_idx == sat_tab->ant_num) {
4767                         sat_tab->update_beam_idx = 0;
4768                         sat_tab->pkt_counter = 0;
4769                         beam_tmp = sat_tab->fast_training_beam_num;
4770
4771                         if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
4772                                 fat_tab->fat_state = FAT_DECISION_STATE;
4773
4774 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
4775                                 odm_fast_ant_training_hl_smart_antenna_type1(dm);
4776 #else
4777                                 odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
4778 #endif
4779
4780                         } else {
4781                                 sat_tab->fast_training_beam_num++;
4782                                 PHYDM_DBG(dm, DBG_ANT_DIV,
4783                                           "Update Beam_num (( %d )) -> (( %d ))\n",
4784                                           beam_tmp,
4785                                           sat_tab->fast_training_beam_num);
4786                                 phydm_set_all_ant_same_beam_num(dm);
4787
4788                                 fat_tab->fat_state = FAT_TRAINING_STATE;
4789                         }
4790                 }
4791         }
4792 #else
4793
4794                 if (dm->ant_div_type == HL_SW_SMART_ANT_TYPE1) {
4795                 if ((dm->support_ic_type & ODM_HL_SMART_ANT_TYPE1_SUPPORT) &&
4796                     pktinfo->is_packet_to_self &&
4797                     fat_tab->fat_state == FAT_TRAINING_STATE) {
4798                         if (sat_tab->pkt_skip_statistic_en == 0) {
4799                                 /*@
4800                                 PHYDM_DBG(dm, DBG_ANT_DIV, "StaID[%d]:  antsel_pathA = ((%d)), hw_antsw_occur = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
4801                                         pktinfo->station_id, fat_tab->antsel_rx_keep_0, fat_tab->hw_antsw_occur, sat_tab->fast_training_beam_num, rx_power_ant0);
4802                                 */
4803                                 PHYDM_DBG(dm, DBG_ANT_DIV,
4804                                           "StaID[%d]:  antsel_pathA = ((%d)), is_packet_to_self = ((%d)), Beam_num = ((%d)), RSSI = ((%d))\n",
4805                                           pktinfo->station_id,
4806                                           fat_tab->antsel_rx_keep_0,
4807                                           pktinfo->is_packet_to_self,
4808                                           sat_tab->fast_training_beam_num,
4809                                           rx_power_ant0);
4810
4811                                 sat_tab->pkt_rssi_sum[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num] += rx_power_ant0;
4812                                 sat_tab->pkt_rssi_cnt[fat_tab->antsel_rx_keep_0][sat_tab->fast_training_beam_num]++;
4813                                 sat_tab->pkt_counter++;
4814
4815                                 /*swich beam every N pkt*/
4816                                 if (sat_tab->pkt_counter >= sat_tab->per_beam_training_pkt_num) {
4817                                         sat_tab->pkt_counter = 0;
4818                                         beam_tmp = sat_tab->fast_training_beam_num;
4819
4820                                         if (sat_tab->fast_training_beam_num >= (sat_tab->beam_patten_num_each_ant - 1)) {
4821                                                 fat_tab->fat_state = FAT_DECISION_STATE;
4822
4823 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
4824                                                 odm_fast_ant_training_hl_smart_antenna_type1(dm);
4825 #else
4826                                                 odm_schedule_work_item(&sat_tab->hl_smart_antenna_decision_workitem);
4827 #endif
4828
4829                                         } else {
4830                                                 sat_tab->fast_training_beam_num++;
4831                                                 phydm_set_all_ant_same_beam_num(dm);
4832
4833                                                 fat_tab->fat_state = FAT_TRAINING_STATE;
4834                                                 PHYDM_DBG(dm, DBG_ANT_DIV, "Update  Beam_num (( %d )) -> (( %d ))\n", beam_tmp, sat_tab->fast_training_beam_num);
4835                                         }
4836                                 }
4837                         }
4838                 }
4839         }
4840 #endif
4841         else
4842 #endif
4843                 if (dm->ant_div_type == CG_TRX_SMART_ANTDIV) {
4844                 if ((dm->support_ic_type & ODM_SMART_ANT_SUPPORT) && pktinfo->is_packet_to_self && fat_tab->fat_state == FAT_TRAINING_STATE) { /* @(pktinfo->is_packet_match_bssid && (!pktinfo->is_packet_beacon)) */
4845                         u8 antsel_tr_mux;
4846                         antsel_tr_mux = (fat_tab->antsel_rx_keep_2 << 2) | (fat_tab->antsel_rx_keep_1 << 1) | fat_tab->antsel_rx_keep_0;
4847                         fat_tab->ant_sum_rssi[antsel_tr_mux] += rx_power_ant0;
4848                         fat_tab->ant_rssi_cnt[antsel_tr_mux]++;
4849                 }
4850         } else { /* @ant_div_type != CG_TRX_SMART_ANTDIV */
4851                 if ((dm->support_ic_type & ODM_ANTDIV_SUPPORT) && (pktinfo->is_packet_to_self || fat_tab->use_ctrl_frame_antdiv)) {
4852                         if (dm->ant_div_type == S0S1_SW_ANTDIV) {
4853                                 if (pktinfo->is_cck_rate || dm->support_ic_type == ODM_RTL8188F)
4854                                         fat_tab->antsel_rx_keep_0 = (fat_tab->rx_idle_ant == MAIN_ANT) ? ANT1_2G : ANT2_2G;
4855
4856                                 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_power_ant0, RSSI_METHOD, pktinfo->is_cck_rate);
4857
4858                         } else {
4859                                 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_power_ant0, RSSI_METHOD, pktinfo->is_cck_rate);
4860
4861                                 #ifdef ODM_EVM_ENHANCE_ANTDIV
4862                                 if (dm->support_ic_type & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC) {
4863                                         if (!pktinfo->is_cck_rate) {
4864                                                 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_evm_ant0, EVM_METHOD, pktinfo->is_cck_rate);
4865                                                 odm_antsel_statistics(dm, phy_info, fat_tab->antsel_rx_keep_0, pktinfo->station_id, rx_evm_ant0, TP_METHOD, pktinfo->is_cck_rate);
4866                                         }
4867                                 }
4868                                 #endif
4869                         }
4870                 }
4871         }
4872 #if 0
4873         /* PHYDM_DBG(dm,DBG_ANT_DIV,"is_cck_rate=%d, pwdb_all=%d\n",pktinfo->is_cck_rate, phy_info->rx_pwdb_all); */
4874         /* PHYDM_DBG(dm,DBG_ANT_DIV,"antsel_tr_mux=3'b%d%d%d\n",fat_tab->antsel_rx_keep_2, fat_tab->antsel_rx_keep_1, fat_tab->antsel_rx_keep_0); */
4875 #endif
4876 }
4877
4878 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
4879 void odm_set_tx_ant_by_tx_info(
4880         void *dm_void,
4881         u8 *desc,
4882         u8 mac_id
4883
4884         )
4885 {
4886         struct dm_struct *dm = (struct dm_struct *)dm_void;
4887         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4888
4889         if (!(dm->support_ability & ODM_BB_ANT_DIV))
4890                 return;
4891
4892         if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4893                 return;
4894
4895         if (dm->support_ic_type == ODM_RTL8723B) {
4896 #if (RTL8723B_SUPPORT == 1)
4897                 SET_TX_DESC_ANTSEL_A_8723B(desc, fat_tab->antsel_a[mac_id]);
4898                 /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8723B] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
4899                         mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/
4900 #endif
4901         } else if (dm->support_ic_type == ODM_RTL8821) {
4902 #if (RTL8821A_SUPPORT == 1)
4903                 SET_TX_DESC_ANTSEL_A_8812(desc, fat_tab->antsel_a[mac_id]);
4904                 /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8821A] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
4905                         mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/
4906 #endif
4907         } else if (dm->support_ic_type == ODM_RTL8188E) {
4908 #if (RTL8188E_SUPPORT == 1)
4909                 SET_TX_DESC_ANTSEL_A_88E(desc, fat_tab->antsel_a[mac_id]);
4910                 SET_TX_DESC_ANTSEL_B_88E(desc, fat_tab->antsel_b[mac_id]);
4911                 SET_TX_DESC_ANTSEL_C_88E(desc, fat_tab->antsel_c[mac_id]);
4912                 /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8188E] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
4913                         mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/
4914 #endif
4915         } else if (dm->support_ic_type == ODM_RTL8821C) {
4916 #if (RTL8821C_SUPPORT == 1)
4917                 SET_TX_DESC_ANTSEL_A_8821C(desc, fat_tab->antsel_a[mac_id]);
4918                 /*PHYDM_DBG(dm,DBG_ANT_DIV, "[8821C] SetTxAntByTxInfo_WIN: mac_id=%d, antsel_tr_mux=3'b%d%d%d\n",
4919                         mac_id, fat_tab->antsel_c[mac_id], fat_tab->antsel_b[mac_id], fat_tab->antsel_a[mac_id]);*/
4920 #endif
4921         } else if (dm->support_ic_type == ODM_RTL8822B) {
4922 #if (RTL8822B_SUPPORT == 1)
4923                 SET_TX_DESC_ANTSEL_A_8822B(desc, fat_tab->antsel_a[mac_id]);
4924 #endif
4925
4926         }
4927 }
4928 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
4929
4930 void odm_set_tx_ant_by_tx_info(
4931         struct rtl8192cd_priv *priv,
4932         struct tx_desc *pdesc,
4933         unsigned short aid)
4934 {
4935         struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
4936         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
4937
4938         if (!(dm->support_ability & ODM_BB_ANT_DIV))
4939                 return;
4940
4941         if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
4942                 return;
4943
4944         if (dm->support_ic_type == ODM_RTL8881A) {
4945 #if 0
4946                 /*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);   */
4947 #endif
4948                 pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
4949                 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
4950         } else if (dm->support_ic_type == ODM_RTL8192E) {
4951 #if 0
4952                 /*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__);   */
4953 #endif
4954                 pdesc->Dword6 &= set_desc(~(BIT(18) | BIT(17) | BIT(16)));
4955                 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
4956         } else if (dm->support_ic_type == ODM_RTL8197F) {
4957 #if 0
4958                 /*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__);   */
4959 #endif
4960                 pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
4961                 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
4962         } else if (dm->support_ic_type == ODM_RTL8822B) {
4963                 pdesc->Dword6 &= set_desc(~(BIT(17) | BIT(16)));
4964                 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
4965         } else if (dm->support_ic_type == ODM_RTL8188E) {
4966 #if 0
4967                 /*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/
4968 #endif
4969                 pdesc->Dword2 &= set_desc(~BIT(24));
4970                 pdesc->Dword2 &= set_desc(~BIT(25));
4971                 pdesc->Dword7 &= set_desc(~BIT(29));
4972
4973                 pdesc->Dword2 |= set_desc(fat_tab->antsel_a[aid] << 24);
4974                 pdesc->Dword2 |= set_desc(fat_tab->antsel_b[aid] << 25);
4975                 pdesc->Dword7 |= set_desc(fat_tab->antsel_c[aid] << 29);
4976
4977         } else if (dm->support_ic_type == ODM_RTL8812) {
4978                 /*@[path-A]*/
4979 #if 0
4980                 /*panic_printk("[%s] [%d]   ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/
4981 #endif
4982
4983                 pdesc->Dword6 &= set_desc(~BIT(16));
4984                 pdesc->Dword6 &= set_desc(~BIT(17));
4985                 pdesc->Dword6 &= set_desc(~BIT(18));
4986
4987                 pdesc->Dword6 |= set_desc(fat_tab->antsel_a[aid] << 16);
4988                 pdesc->Dword6 |= set_desc(fat_tab->antsel_b[aid] << 17);
4989                 pdesc->Dword6 |= set_desc(fat_tab->antsel_c[aid] << 18);
4990         }
4991 }
4992
4993 #if 1 /*@def CONFIG_WLAN_HAL*/
4994 void odm_set_tx_ant_by_tx_info_hal(
4995         struct rtl8192cd_priv *priv,
4996         void *pdesc_data,
4997         u16 aid)
4998 {
4999         struct dm_struct *dm = GET_PDM_ODM(priv); /*@&(priv->pshare->_dmODM);*/
5000         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5001         PTX_DESC_DATA_88XX pdescdata = (PTX_DESC_DATA_88XX)pdesc_data;
5002
5003         if (!(dm->support_ability & ODM_BB_ANT_DIV))
5004                 return;
5005
5006         if (dm->ant_div_type == CGCS_RX_HW_ANTDIV)
5007                 return;
5008
5009         if (dm->support_ic_type & (ODM_RTL8881A | ODM_RTL8192E | ODM_RTL8814A | ODM_RTL8197F | ODM_RTL8822B)) {
5010 #if 0
5011                 /*panic_printk("[%s] [%d] ******odm_set_tx_ant_by_tx_info_hal******\n",__FUNCTION__,__LINE__);*/
5012 #endif
5013                 pdescdata->ant_sel = 1;
5014                 pdescdata->ant_sel_a = fat_tab->antsel_a[aid];
5015         }
5016 }
5017 #endif /*@#ifdef CONFIG_WLAN_HAL*/
5018
5019 #endif
5020
5021 void odm_ant_div_config(
5022         void *dm_void)
5023 {
5024         struct dm_struct *dm = (struct dm_struct *)dm_void;
5025         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5026 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
5027         PHYDM_DBG(dm, DBG_ANT_DIV, "WIN Config Antenna Diversity\n");
5028         /*@
5029         if(dm->support_ic_type==ODM_RTL8723B)
5030         {
5031                 if((!dm->dm_swat_table.ANTA_ON || !dm->dm_swat_table.ANTB_ON))
5032                         dm->support_ability &= ~(ODM_BB_ANT_DIV);
5033         }
5034         */
5035         #if (defined(CONFIG_2T3R_ANTENNA))
5036         #if (RTL8822B_SUPPORT == 1)
5037                 dm->rfe_type = ANT_2T3R_RFE_TYPE;
5038         #endif
5039         #endif
5040
5041         #if (defined(CONFIG_2T4R_ANTENNA))
5042         #if (RTL8822B_SUPPORT == 1)
5043                 dm->rfe_type = ANT_2T4R_RFE_TYPE;
5044         #endif
5045         #endif
5046
5047         if (dm->support_ic_type == ODM_RTL8723D)
5048                 dm->ant_div_type = S0S1_TRX_HW_ANTDIV;
5049 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
5050
5051         PHYDM_DBG(dm, DBG_ANT_DIV, "CE Config Antenna Diversity\n");
5052
5053         if (dm->support_ic_type == ODM_RTL8723B)
5054                 dm->ant_div_type = S0S1_SW_ANTDIV;
5055
5056         if (dm->support_ic_type == ODM_RTL8723D)
5057                 dm->ant_div_type = S0S1_SW_ANTDIV;
5058
5059 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
5060
5061         PHYDM_DBG(dm, DBG_ANT_DIV, "AP Config Antenna Diversity\n");
5062
5063         /* @2 [ NOT_SUPPORT_ANTDIV ] */
5064 #if (defined(CONFIG_NOT_SUPPORT_ANTDIV))
5065         dm->support_ability &= ~(ODM_BB_ANT_DIV);
5066         PHYDM_DBG(dm, DBG_ANT_DIV,
5067                   "[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n");
5068
5069         /* @2 [ 2G&5G_SUPPORT_ANTDIV ] */
5070 #elif (defined(CONFIG_2G5G_SUPPORT_ANTDIV))
5071         PHYDM_DBG(dm, DBG_ANT_DIV,
5072                   "[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously\n");
5073         fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G | ODM_ANTDIV_5G);
5074
5075         if (dm->support_ic_type & ODM_ANTDIV_SUPPORT)
5076                 dm->support_ability |= ODM_BB_ANT_DIV;
5077         if (*dm->band_type == ODM_BAND_5G) {
5078 #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
5079                 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
5080                 PHYDM_DBG(dm, DBG_ANT_DIV,
5081                           "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5082                 panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5083 #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
5084                 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5085                 PHYDM_DBG(dm, DBG_ANT_DIV,
5086                           "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5087                 panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5088 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
5089                 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
5090                 PHYDM_DBG(dm, DBG_ANT_DIV,
5091                           "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
5092 #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
5093                 dm->ant_div_type = S0S1_SW_ANTDIV;
5094                 PHYDM_DBG(dm, DBG_ANT_DIV,
5095                           "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
5096 #endif
5097         } else if (*dm->band_type == ODM_BAND_2_4G) {
5098 #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
5099                 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
5100                 PHYDM_DBG(dm, DBG_ANT_DIV,
5101                           "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5102 #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))
5103                 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5104                 PHYDM_DBG(dm, DBG_ANT_DIV,
5105                           "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5106 #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5107                 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
5108                 PHYDM_DBG(dm, DBG_ANT_DIV,
5109                           "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
5110 #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
5111                 dm->ant_div_type = S0S1_SW_ANTDIV;
5112                 PHYDM_DBG(dm, DBG_ANT_DIV,
5113                           "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
5114 #endif
5115         }
5116
5117         /* @2 [ 5G_SUPPORT_ANTDIV ] */
5118 #elif (defined(CONFIG_5G_SUPPORT_ANTDIV))
5119         PHYDM_DBG(dm, DBG_ANT_DIV,
5120                   "[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
5121         panic_printk("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n");
5122         fat_tab->ant_div_2g_5g = (ODM_ANTDIV_5G);
5123         if (*dm->band_type == ODM_BAND_5G) {
5124                 if (dm->support_ic_type & ODM_ANTDIV_5G_SUPPORT_IC)
5125                         dm->support_ability |= ODM_BB_ANT_DIV;
5126 #if (defined(CONFIG_5G_CGCS_RX_DIVERSITY))
5127                 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
5128                 PHYDM_DBG(dm, DBG_ANT_DIV,
5129                           "[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5130                 panic_printk("[ 5G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5131 #elif (defined(CONFIG_5G_CG_TRX_DIVERSITY))
5132                 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5133                 panic_printk("[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5134                 PHYDM_DBG(dm, DBG_ANT_DIV,
5135                           "[ 5G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5136 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY))
5137                 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
5138                 PHYDM_DBG(dm, DBG_ANT_DIV,
5139                           "[ 5G] : AntDiv type = CG_SMART_ANTDIV\n");
5140 #elif (defined(CONFIG_5G_S0S1_SW_ANT_DIVERSITY))
5141                 dm->ant_div_type = S0S1_SW_ANTDIV;
5142                 PHYDM_DBG(dm, DBG_ANT_DIV,
5143                           "[ 5G] : AntDiv type = S0S1_SW_ANTDIV\n");
5144 #endif
5145         } else if (*dm->band_type == ODM_BAND_2_4G) {
5146                 PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 2G ant_div_type\n");
5147                 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5148         }
5149
5150         /* @2 [ 2G_SUPPORT_ANTDIV ] */
5151 #elif (defined(CONFIG_2G_SUPPORT_ANTDIV))
5152         PHYDM_DBG(dm, DBG_ANT_DIV,
5153                   "[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n");
5154         fat_tab->ant_div_2g_5g = (ODM_ANTDIV_2G);
5155         if (*dm->band_type == ODM_BAND_2_4G) {
5156                 if (dm->support_ic_type & ODM_ANTDIV_2G_SUPPORT_IC)
5157                         dm->support_ability |= ODM_BB_ANT_DIV;
5158 #if (defined(CONFIG_2G_CGCS_RX_DIVERSITY))
5159                 dm->ant_div_type = CGCS_RX_HW_ANTDIV;
5160                 PHYDM_DBG(dm, DBG_ANT_DIV,
5161                           "[ 2.4G] : AntDiv type = CGCS_RX_HW_ANTDIV\n");
5162 #elif (defined(CONFIG_2G_CG_TRX_DIVERSITY))
5163                 dm->ant_div_type = CG_TRX_HW_ANTDIV;
5164                 PHYDM_DBG(dm, DBG_ANT_DIV,
5165                           "[ 2.4G] : AntDiv type = CG_TRX_HW_ANTDIV\n");
5166 #elif (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5167                 dm->ant_div_type = CG_TRX_SMART_ANTDIV;
5168                 PHYDM_DBG(dm, DBG_ANT_DIV,
5169                           "[ 2.4G] : AntDiv type = CG_SMART_ANTDIV\n");
5170 #elif (defined(CONFIG_2G_S0S1_SW_ANT_DIVERSITY))
5171                 dm->ant_div_type = S0S1_SW_ANTDIV;
5172                 PHYDM_DBG(dm, DBG_ANT_DIV,
5173                           "[ 2.4G] : AntDiv type = S0S1_SW_ANTDIV\n");
5174 #endif
5175         } else if (*dm->band_type == ODM_BAND_5G) {
5176                 PHYDM_DBG(dm, DBG_ANT_DIV, "Not Support 5G ant_div_type\n");
5177                 dm->support_ability &= ~(ODM_BB_ANT_DIV);
5178         }
5179 #endif
5180 #endif
5181
5182         PHYDM_DBG(dm, DBG_ANT_DIV,
5183                   "[AntDiv Config Info] AntDiv_SupportAbility = (( %x ))\n",
5184                   ((dm->support_ability & ODM_BB_ANT_DIV) ? 1 : 0));
5185         PHYDM_DBG(dm, DBG_ANT_DIV,
5186                   "[AntDiv Config Info] be_fix_tx_ant = ((%d))\n",
5187                   dm->dm_fat_table.b_fix_tx_ant);
5188 }
5189
5190 void odm_ant_div_timers(
5191         void *dm_void,
5192         u8 state)
5193 {
5194         struct dm_struct *dm = (struct dm_struct *)dm_void;
5195         if (state == INIT_ANTDIV_TIMMER) {
5196 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5197                 odm_initialize_timer(dm,
5198                                      &dm->dm_swat_table.phydm_sw_antenna_switch_timer,
5199                                      (void *)odm_sw_antdiv_callback, NULL,
5200                                      "phydm_sw_antenna_switch_timer");
5201 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5202                 odm_initialize_timer(dm, &dm->fast_ant_training_timer,
5203                                      (void *)odm_fast_ant_training_callback, NULL, "fast_ant_training_timer");
5204 #endif
5205
5206 #ifdef ODM_EVM_ENHANCE_ANTDIV
5207                 odm_initialize_timer(dm, &dm->evm_fast_ant_training_timer,
5208                                      (void *)phydm_evm_antdiv_callback, NULL,
5209                                      "evm_fast_ant_training_timer");
5210 #endif
5211         } else if (state == CANCEL_ANTDIV_TIMMER) {
5212 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5213                 odm_cancel_timer(dm,
5214                                  &dm->dm_swat_table.phydm_sw_antenna_switch_timer);
5215 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5216                 odm_cancel_timer(dm, &dm->fast_ant_training_timer);
5217 #endif
5218
5219 #ifdef ODM_EVM_ENHANCE_ANTDIV
5220                 odm_cancel_timer(dm, &dm->evm_fast_ant_training_timer);
5221 #endif
5222         } else if (state == RELEASE_ANTDIV_TIMMER) {
5223 #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5224                 odm_release_timer(dm,
5225                                   &dm->dm_swat_table.phydm_sw_antenna_switch_timer);
5226 #elif (defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY)) || (defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY))
5227                 odm_release_timer(dm, &dm->fast_ant_training_timer);
5228 #endif
5229
5230 #ifdef ODM_EVM_ENHANCE_ANTDIV
5231                 odm_release_timer(dm, &dm->evm_fast_ant_training_timer);
5232 #endif
5233         }
5234 }
5235
5236 void phydm_antdiv_debug(void *dm_void, char input[][16], u32 *_used,
5237                         char *output, u32 *_out_len)
5238 {
5239         struct dm_struct *dm = (struct dm_struct *)dm_void;
5240         struct phydm_fat_struct *fat_tab = &dm->dm_fat_table;
5241         u32 used = *_used;
5242         u32 out_len = *_out_len;
5243         u32 dm_value[10] = {0};
5244         char help[] = "-h";
5245         u8 i, input_idx = 0;
5246
5247         for (i = 0; i < 5; i++) {
5248                 if (input[i + 1]) {
5249                         PHYDM_SSCANF(input[i + 1], DCMD_HEX, &dm_value[i]);
5250                         input_idx++;
5251                 }
5252         }
5253
5254         if (input_idx == 0)
5255                 return;
5256
5257         if ((strcmp(input[1], help) == 0)) {
5258                 PDM_SNPF(out_len, used, output + used, out_len - used,
5259                          "{1} {0:auto, 1:fix main, 2:fix auto}\n");
5260                 PDM_SNPF(out_len, used, output + used, out_len - used,
5261                          "{2} {antdiv_period}\n");
5262                 #if (RTL8821C_SUPPORT == 1)
5263                 PDM_SNPF(out_len, used, output + used, out_len - used,
5264                          "{3} {en} {0:Default, 1:HW_Div, 2:SW_Div}\n");
5265                 #endif
5266
5267         } else if (dm_value[0] == 1) {
5268         /*@fixed or auto antenna*/
5269                 if (dm_value[1] == 0) {
5270                         dm->ant_type = ODM_AUTO_ANT;
5271                         PDM_SNPF(out_len, used, output + used, out_len - used,
5272                                  "AntDiv: Auto\n");
5273                 } else if (dm_value[1] == 1) {
5274                         dm->ant_type = ODM_FIX_MAIN_ANT;
5275                         PDM_SNPF(out_len, used, output + used, out_len - used,
5276                                  "AntDiv: Fix Main\n");
5277                 } else if (dm_value[1] == 2) {
5278                         dm->ant_type = ODM_FIX_AUX_ANT;
5279                         PDM_SNPF(out_len, used, output + used, out_len - used,
5280                                  "AntDiv: Fix Aux\n");
5281                 }
5282
5283                 if (dm->ant_type != ODM_AUTO_ANT) {
5284                         odm_stop_antenna_switch_dm(dm);
5285                         if (dm->ant_type == ODM_FIX_MAIN_ANT)
5286                                 odm_update_rx_idle_ant(dm, MAIN_ANT);
5287                         else if (dm->ant_type == ODM_FIX_AUX_ANT)
5288                                 odm_update_rx_idle_ant(dm, AUX_ANT);
5289                 } else {
5290                         phydm_enable_antenna_diversity(dm);
5291                 }
5292                 dm->pre_ant_type = dm->ant_type;
5293         } else if (dm_value[0] == 2) {
5294         /*@dynamic period for AntDiv*/
5295                 dm->antdiv_period = (u8)dm_value[1];
5296                 PDM_SNPF(out_len, used, output + used, out_len - used,
5297                          "AntDiv_period=((%d))\n", dm->antdiv_period);
5298         }
5299         #if (RTL8821C_SUPPORT == 1)
5300         else if (dm_value[0] == 3 &&
5301                  dm->support_ic_type == ODM_RTL8821C) {
5302                 /*Only for 8821C*/
5303                 if (dm_value[1] == 0) {
5304                         fat_tab->force_antdiv_type = false;
5305                         PDM_SNPF(out_len, used, output + used, out_len - used,
5306                                  "[8821C] AntDiv: Default\n");
5307                 } else if (dm_value[1] == 1) {
5308                         fat_tab->force_antdiv_type = true;
5309                         fat_tab->antdiv_type_dbg = CG_TRX_HW_ANTDIV;
5310                         PDM_SNPF(out_len, used, output + used, out_len - used,
5311                                  "[8821C] AntDiv: HW diversity\n");
5312                 } else if (dm_value[1] == 2) {
5313                         fat_tab->force_antdiv_type = true;
5314                         fat_tab->antdiv_type_dbg = S0S1_SW_ANTDIV;
5315                         PDM_SNPF(out_len, used, output + used, out_len - used,
5316                                  "[8821C] AntDiv: SW diversity\n");
5317                 }
5318         }
5319         #endif
5320         #ifdef ODM_EVM_ENHANCE_ANTDIV
5321         else if (dm_value[0] == 4) {
5322                 if (dm_value[1] == 0) {
5323                         /*@init parameters for EVM AntDiv*/
5324                         phydm_evm_sw_antdiv_init(dm);
5325                         PDM_SNPF(out_len, used, output + used, out_len - used,
5326                                  "init evm antdiv parameters\n");
5327                 } else if (dm_value[1] == 1) {
5328                         /*training number for EVM AntDiv*/
5329                         dm->antdiv_train_num = (u8)dm_value[2];
5330                         PDM_SNPF(out_len, used, output + used, out_len - used,
5331                                  "antdiv_train_num = ((%d))\n",
5332                                  dm->antdiv_train_num);
5333                 } else if (dm_value[1] == 2) {
5334                         /*training interval for EVM AntDiv*/
5335                         dm->antdiv_intvl = (u8)dm_value[2];
5336                         PDM_SNPF(out_len, used, output + used, out_len - used,
5337                                  "antdiv_intvl = ((%d))\n",
5338                                  dm->antdiv_intvl);
5339                 } else if (dm_value[1] == 3) {
5340                         /*@function period for EVM AntDiv*/
5341                         dm->evm_antdiv_period = (u8)dm_value[2];
5342                         PDM_SNPF(out_len, used, output + used, out_len - used,
5343                                  "evm_antdiv_period = ((%d))\n",
5344                                  dm->evm_antdiv_period);
5345                 } else if (dm_value[1] == 100) {/*show parameters*/
5346                         PDM_SNPF(out_len, used, output + used, out_len - used,
5347                                  "ant_type = ((%d))\n", dm->ant_type);
5348                         PDM_SNPF(out_len, used, output + used, out_len - used,
5349                                  "antdiv_train_num = ((%d))\n",
5350                                  dm->antdiv_train_num);
5351                         PDM_SNPF(out_len, used, output + used, out_len - used,
5352                                  "antdiv_intvl = ((%d))\n",
5353                                  dm->antdiv_intvl);
5354                         PDM_SNPF(out_len, used, output + used, out_len - used,
5355                                  "evm_antdiv_period = ((%d))\n",
5356                                  dm->evm_antdiv_period);
5357                 }
5358         }
5359         #ifdef CONFIG_2T4R_ANTENNA
5360         else if (dm_value[0] == 5) { /*Only for 8822B 2T4R case*/
5361
5362                 if (dm_value[1] == 0) {
5363                         dm->ant_type2 = ODM_AUTO_ANT;
5364                         PDM_SNPF(out_len, used, output + used, out_len - used,
5365                                  "AntDiv: PathB Auto\n");
5366                 } else if (dm_value[1] == 1) {
5367                         dm->ant_type2 = ODM_FIX_MAIN_ANT;
5368                         PDM_SNPF(out_len, used, output + used, out_len - used,
5369                                  "AntDiv: PathB Fix Main\n");
5370                 } else if (dm_value[1] == 2) {
5371                         dm->ant_type2 = ODM_FIX_AUX_ANT;
5372                         PDM_SNPF(out_len, used, output + used, out_len - used,
5373                                  "AntDiv: PathB Fix Aux\n");
5374                 }
5375
5376                 if (dm->ant_type2 != ODM_AUTO_ANT) {
5377                         odm_stop_antenna_switch_dm(dm);
5378                         if (dm->ant_type2 == ODM_FIX_MAIN_ANT)
5379                                 phydm_update_rx_idle_ant_pathb(dm, MAIN_ANT);
5380                         else if (dm->ant_type2 == ODM_FIX_AUX_ANT)
5381                                 phydm_update_rx_idle_ant_pathb(dm, AUX_ANT);
5382                 } else {
5383                         phydm_enable_antenna_diversity(dm);
5384                 }
5385                 dm->pre_ant_type2 = dm->ant_type2;
5386         }
5387         #endif
5388         #endif
5389         *_used = used;
5390         *_out_len = out_len;
5391 }
5392
5393 void odm_ant_div_reset(void *dm_void)
5394 {
5395         struct dm_struct *dm = (struct dm_struct *)dm_void;
5396
5397         #ifdef CONFIG_S0S1_SW_ANTENNA_DIVERSITY
5398         if (dm->ant_div_type == S0S1_SW_ANTDIV)
5399                 odm_s0s1_sw_ant_div_reset(dm);
5400         #endif
5401 }
5402
5403 void odm_antenna_diversity_init(void *dm_void)
5404 {
5405         struct dm_struct *dm = (struct dm_struct *)dm_void;
5406
5407         odm_ant_div_config(dm);
5408         odm_ant_div_init(dm);
5409 }
5410
5411 void odm_antenna_diversity(void *dm_void)
5412 {
5413         struct dm_struct *dm = (struct dm_struct *)dm_void;
5414
5415         if (*dm->mp_mode)
5416                 return;
5417
5418         if (!(dm->support_ability & ODM_BB_ANT_DIV)) {
5419                 PHYDM_DBG(dm, DBG_ANT_DIV,
5420                           "[Return!!!]   Not Support Antenna Diversity Function\n");
5421                 return;
5422         }
5423
5424         if (dm->pause_ability & ODM_BB_ANT_DIV) {
5425                 PHYDM_DBG(dm, DBG_ANT_DIV, "Return: Pause AntDIv in LV=%d\n",
5426                           dm->pause_lv_table.lv_antdiv);
5427                 return;
5428         }
5429
5430         odm_ant_div(dm);
5431 }
5432 #endif /*@#ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY*/