1 /******************************************************************************
3 * Copyright(c) 2007 - 2017 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __INC_PHYDM_BEAMFORMING_H
27 #define __INC_PHYDM_BEAMFORMING_H
29 #ifndef BEAMFORMING_SUPPORT
30 #define BEAMFORMING_SUPPORT 0
33 /*@Beamforming Related*/
34 #include "txbf/halcomtxbf.h"
35 #include "txbf/haltxbfjaguar.h"
36 #include "txbf/haltxbf8192e.h"
37 #include "txbf/haltxbf8814a.h"
38 #include "txbf/haltxbf8822b.h"
39 #include "txbf/haltxbfinterface.h"
41 #if (BEAMFORMING_SUPPORT == 1)
43 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
45 #define eq_mac_addr(a, b) (((a)[0] == (b)[0] && (a)[1] == (b)[1] && (a)[2] == (b)[2] && (a)[3] == (b)[3] && (a)[4] == (b)[4] && (a)[5] == (b)[5]) ? 1 : 0)
46 #define cp_mac_addr(des, src) ((des)[0] = (src)[0], (des)[1] = (src)[1], (des)[2] = (src)[2], (des)[3] = (src)[3], (des)[4] = (src)[4], (des)[5] = (src)[5])
50 #define MAX_BEAMFORMEE_SU 2
51 #define MAX_BEAMFORMER_SU 2
52 #if (RTL8822B_SUPPORT == 1)
53 #define MAX_BEAMFORMEE_MU 6
54 #define MAX_BEAMFORMER_MU 1
56 #define MAX_BEAMFORMEE_MU 0
57 #define MAX_BEAMFORMER_MU 0
60 #define BEAMFORMEE_ENTRY_NUM (MAX_BEAMFORMEE_SU + MAX_BEAMFORMEE_MU)
61 #define BEAMFORMER_ENTRY_NUM (MAX_BEAMFORMER_SU + MAX_BEAMFORMER_MU)
63 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
64 /*@for different naming between WIN and CE*/
65 #define BEACON_QUEUE BCN_QUEUE_INX
66 #define NORMAL_QUEUE MGT_QUEUE_INX
67 #define RT_DISABLE_FUNC RTW_DISABLE_FUNC
68 #define RT_ENABLE_FUNC RTW_ENABLE_FUNC
71 enum beamforming_entry_state {
72 BEAMFORMING_ENTRY_STATE_UNINITIALIZE,
73 BEAMFORMING_ENTRY_STATE_INITIALIZEING,
74 BEAMFORMING_ENTRY_STATE_INITIALIZED,
75 BEAMFORMING_ENTRY_STATE_PROGRESSING,
76 BEAMFORMING_ENTRY_STATE_PROGRESSED
79 enum beamforming_notify_state {
80 BEAMFORMING_NOTIFY_NONE,
81 BEAMFORMING_NOTIFY_ADD,
82 BEAMFORMING_NOTIFY_DELETE,
83 BEAMFORMEE_NOTIFY_ADD_SU,
84 BEAMFORMEE_NOTIFY_DELETE_SU,
85 BEAMFORMEE_NOTIFY_ADD_MU,
86 BEAMFORMEE_NOTIFY_DELETE_MU,
87 BEAMFORMING_NOTIFY_RESET
90 enum beamforming_cap {
91 BEAMFORMING_CAP_NONE = 0x0,
92 BEAMFORMER_CAP_HT_EXPLICIT = BIT(1),
93 BEAMFORMEE_CAP_HT_EXPLICIT = BIT(2),
94 BEAMFORMER_CAP_VHT_SU = BIT(5), /* @Self has er Cap, because Reg er & peer ee */
95 BEAMFORMEE_CAP_VHT_SU = BIT(6), /* @Self has ee Cap, because Reg ee & peer er */
96 BEAMFORMER_CAP_VHT_MU = BIT(7), /* @Self has er Cap, because Reg er & peer ee */
97 BEAMFORMEE_CAP_VHT_MU = BIT(8), /* @Self has ee Cap, because Reg ee & peer er */
98 BEAMFORMER_CAP = BIT(9),
99 BEAMFORMEE_CAP = BIT(10),
103 SOUNDING_SW_VHT_TIMER = 0x0,
104 SOUNDING_SW_HT_TIMER = 0x1,
105 sounding_stop_all_timer = 0x2,
106 SOUNDING_HW_VHT_TIMER = 0x3,
107 SOUNDING_HW_HT_TIMER = 0x4,
108 SOUNDING_STOP_OID_TIMER = 0x5,
109 SOUNDING_AUTO_VHT_TIMER = 0x6,
110 SOUNDING_AUTO_HT_TIMER = 0x7,
111 SOUNDING_FW_VHT_TIMER = 0x8,
112 SOUNDING_FW_HT_TIMER = 0x9,
115 struct _RT_BEAMFORM_STAINFO {
120 /*WIRELESS_MODE wireless_mode;*/
121 enum channel_width bw;
122 enum beamforming_cap beamform_cap;
124 u16 vht_beamform_cap;
126 u16 cur_beamform_vht;
129 struct _RT_BEAMFORMEE_ENTRY {
133 u16 aid; /*Used to construct AID field of NDPA packet.*/
134 u16 mac_id; /*Used to Set Reg42C in IBSS mode. */
135 u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
136 u8 g_id; /*Used to fill Tx DESC*/
138 u8 mac_addr[6]; /*@Used to fill Reg6E4 to fill Mac address of CSI report frame.*/
139 enum channel_width sound_bw; /*Sounding band_width*/
141 enum beamforming_cap beamform_entry_cap;
142 enum beamforming_entry_state beamform_entry_state;
143 boolean is_beamforming_in_progress;
144 /*@u8 log_seq; // Move to _RT_BEAMFORMER_ENTRY*/
145 /*@u16 log_retry_cnt:3; // 0~4 // Move to _RT_BEAMFORMER_ENTRY*/
146 /*@u16 LogSuccessCnt:2; // 0~2 // Move to _RT_BEAMFORMER_ENTRY*/
147 u16 log_status_fail_cnt : 5; /* @0~21 */
148 u16 default_csi_cnt : 5; /* @0~21 */
151 u8 num_of_sounding_dim;
152 u8 comp_steering_num_of_bfer;
158 u8 user_position[16];
161 struct _RT_BEAMFORMER_ENTRY {
163 /*P_AID of BFer entry is probably not used*/
164 u16 p_aid; /*@Used to fill Reg42C & Reg714 to compare with P_AID of Tx DESC. */
168 enum beamforming_cap beamform_entry_cap;
169 u8 num_of_sounding_dim;
170 u8 clock_reset_times; /*@Modified by Jeffery @2015-04-10*/
171 u8 pre_log_seq; /*@Modified by Jeffery @2015-03-30*/
172 u8 log_seq; /*@Modified by Jeffery @2014-10-29*/
173 u16 log_retry_cnt : 3; /*@Modified by Jeffery @2014-10-29*/
174 u16 log_success : 2; /*@Modified by Jeffery @2014-10-29*/
179 u8 user_position[16];
183 struct _RT_SOUNDING_INFO {
185 enum channel_width sound_bw;
186 enum sounding_mode sound_mode;
190 struct _RT_BEAMFORMING_OID_INFO {
192 enum channel_width sound_oid_bw;
193 enum sounding_mode sound_oid_mode;
194 u16 sound_oid_period;
197 struct _RT_BEAMFORMING_INFO {
198 enum beamforming_cap beamform_cap;
199 struct _RT_BEAMFORMEE_ENTRY beamformee_entry[BEAMFORMEE_ENTRY_NUM];
200 struct _RT_BEAMFORMER_ENTRY beamformer_entry[BEAMFORMER_ENTRY_NUM];
201 struct _RT_BEAMFORM_STAINFO beamform_sta_info;
202 u8 beamformee_cur_idx;
203 struct phydm_timer_list beamforming_timer;
204 struct phydm_timer_list mu_timer;
205 struct _RT_SOUNDING_INFO sounding_info;
206 struct _RT_BEAMFORMING_OID_INFO beamforming_oid_info;
207 struct _HAL_TXBF_INFO txbf_info;
208 u8 sounding_sequence;
209 u8 beamformee_su_cnt;
210 u8 beamformer_su_cnt;
211 u32 beamformee_su_reg_maping;
212 u32 beamformer_su_reg_maping;
214 u8 beamformee_mu_cnt;
215 u8 beamformer_mu_cnt;
216 u32 beamformee_mu_reg_maping;
218 boolean is_mu_sounding;
219 u8 first_mu_bfee_index;
220 boolean is_mu_sounding_in_progress;
221 boolean dbg_disable_mu_tx;
222 boolean apply_v_matrix;
224 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
225 void *source_adapter;
227 /* @Control register */
228 u32 reg_mu_tx_ctrl; /* @For USB/SDIO interfaces aync I/O */
233 void phydm_get_txbf_device_num(
237 struct _RT_NDPA_STA_INFO {
239 u16 feedback_type : 1;
243 enum phydm_acting_type {
244 phydm_acting_as_ibss = 0,
245 phydm_acting_as_ap = 1
249 phydm_beamforming_get_entry_beam_cap_by_mac_id(
253 struct _RT_BEAMFORMEE_ENTRY *
254 phydm_beamforming_get_bfee_entry_by_addr(
259 struct _RT_BEAMFORMER_ENTRY *
260 phydm_beamforming_get_bfer_entry_by_addr(
265 void phydm_beamforming_notify(
269 phydm_acting_determine(
271 enum phydm_acting_type type);
273 void beamforming_enter(
277 void beamforming_leave(
282 beamforming_start_fw(
286 void beamforming_check_sounding_success(
290 void phydm_beamforming_end_sw(
294 void beamforming_timer_callback(
297 void phydm_beamforming_init(
301 phydm_beamforming_get_beam_cap(
303 struct _RT_BEAMFORMING_INFO *beam_info);
306 phydm_get_beamform_cap(
310 beamforming_control_v1(
315 enum channel_width BW,
319 phydm_beamforming_control_v2(
323 enum channel_width BW,
326 void phydm_beamforming_watchdog(
329 void beamforming_sw_timer_callback(
330 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
331 struct phydm_timer_list *timer
332 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
333 void *function_context
338 beamforming_send_ht_ndpa_packet(
341 enum channel_width BW,
345 beamforming_send_vht_ndpa_packet(
349 enum channel_width BW,
353 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_AP))
354 #define beamforming_gid_paid(adapter, tcb)
355 #define phydm_acting_determine(dm, type) false
356 #define beamforming_enter(dm, sta_idx)
357 #define beamforming_leave(dm, RA)
358 #define beamforming_end_fw(dm)
359 #define beamforming_control_v1(dm, RA, AID, mode, BW, rate) true
360 #define beamforming_control_v2(dm, idx, mode, BW, period) true
361 #define phydm_beamforming_end_sw(dm, _status)
362 #define beamforming_timer_callback(dm)
363 #define phydm_beamforming_init(dm)
364 #define phydm_beamforming_control_v2(dm, _idx, _mode, _BW, _period) false
365 #define beamforming_watchdog(dm)
366 #define phydm_beamforming_watchdog(dm)
367 #endif /*@(DM_ODM_SUPPORT_TYPE & (ODM_CE | ODM_AP))*/
368 #endif /*@(BEAMFORMING_SUPPORT == 1)*/