rtl8821ce/hal/phydm/phydm_cck_pd.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2017  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 /*@************************************************************
  27  * include files
  28  ************************************************************/
  29
  30 #include "mp_precomp.h"
  31 #include "phydm_precomp.h"
  32
  33 #ifdef PHYDM_SUPPORT_CCKPD
  34 #ifdef PHYDM_COMPILE_CCKPD_TYPE1
  35 void phydm_write_cck_pd_type1(void *dm_void, u8 cca_th)
  36 {
  37         struct dm_struct *dm = (struct dm_struct *)dm_void;
  38         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
  39
  40         PHYDM_DBG(dm, DBG_CCKPD, "[%s] cck_cca_th=((0x%x))\n",
  41                   __func__, cca_th);
  42
  43         odm_write_1byte(dm, R_0xa0a, cca_th);
  44         cckpd_t->cur_cck_cca_thres = cca_th;
  45 }
  46
  47 void phydm_set_cckpd_lv_type1(void *dm_void, enum cckpd_lv lv)
  48 {
  49         struct dm_struct *dm = (struct dm_struct *)dm_void;
  50         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
  51         u8 pd_th = 0;
  52
  53         PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
  54         PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
  55
  56         if (cckpd_t->cck_pd_lv == lv) {
  57                 PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
  58                 return;
  59         }
  60
  61         cckpd_t->cck_pd_lv = lv;
  62         cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
  63
  64         if (lv == CCK_PD_LV_4)
  65                 pd_th = 0xed;
  66         else if (lv == CCK_PD_LV_3)
  67                 pd_th = 0xdd;
  68         else if (lv == CCK_PD_LV_2)
  69                 pd_th = 0xcd;
  70         else if (lv == CCK_PD_LV_1)
  71                 pd_th = 0x83;
  72         else if (lv == CCK_PD_LV_0)
  73                 pd_th = 0x40;
  74
  75         phydm_write_cck_pd_type1(dm, pd_th);
  76 }
  77
  78 void phydm_cckpd_type1(void *dm_void)
  79 {
  80         struct dm_struct *dm = (struct dm_struct *)dm_void;
  81         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
  82         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
  83         enum cckpd_lv lv = CCK_PD_LV_INIT;
  84         boolean is_update = true;
  85
  86         if (dm->is_linked) {
  87         #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
  88                 if (dm->rssi_min > 60) {
  89                         lv = CCK_PD_LV_3;
  90                 } else if (dm->rssi_min > 35) {
  91                         lv = CCK_PD_LV_2;
  92                 } else if (dm->rssi_min > 20) {
  93                         if (cckpd_t->cck_fa_ma > 500)
  94                                 lv = CCK_PD_LV_2;
  95                         else if (cckpd_t->cck_fa_ma < 250)
  96                                 lv = CCK_PD_LV_1;
  97                         else
  98                                 is_update = false;
  99                 } else { /*RSSI < 20*/
 100                         lv = CCK_PD_LV_1;
 101                 }
 102         #else /*ODM_AP*/
 103                 if (dig_t->cur_ig_value > 0x32)
 104                         lv = CCK_PD_LV_4;
 105                 else if (dig_t->cur_ig_value > 0x2a)
 106                         lv = CCK_PD_LV_3;
 107                 else if (dig_t->cur_ig_value > 0x24)
 108                         lv = CCK_PD_LV_2;
 109                 else
 110                         lv = CCK_PD_LV_1;
 111         #endif
 112         } else {
 113                 if (cckpd_t->cck_fa_ma > 1000)
 114                         lv = CCK_PD_LV_1;
 115                 else if (cckpd_t->cck_fa_ma < 500)
 116                         lv = CCK_PD_LV_0;
 117                 else
 118                         is_update = false;
 119         }
 120
 121         /*[Abnormal case] =================================================*/
 122         #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 123         /*@HP 22B LPS power consumption issue & [PCIE-1596]*/
 124         if (dm->hp_hw_id && dm->traffic_load == TRAFFIC_ULTRA_LOW) {
 125                 lv = CCK_PD_LV_0;
 126                 PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case1\n");
 127         } else if ((dm->p_advance_ota & PHYDM_ASUS_OTA_SETTING) &&
 128             cckpd_t->cck_fa_ma > 200 && dm->rssi_min <= 20) {
 129                 lv = CCK_PD_LV_1;
 130                 cckpd_t->cck_pd_lv = lv;
 131                 phydm_write_cck_pd_type1(dm, 0xc3); /*@for ASUS OTA test*/
 132                 is_update = false;
 133                 PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case2\n");
 134         }
 135         #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))
 136                 #ifdef MCR_WIRELESS_EXTEND
 137                 lv = CCK_PD_LV_2;
 138                 cckpd_t->cck_pd_lv = lv;
 139                 phydm_write_cck_pd_type1(dm, 0x43);
 140                 is_update = false;
 141                 PHYDM_DBG(dm, DBG_CCKPD, "CCKPD Abnormal case3\n");
 142                 #endif
 143         #endif
 144         /*=================================================================*/
 145
 146         if (is_update)
 147                 phydm_set_cckpd_lv_type1(dm, lv);
 148
 149         PHYDM_DBG(dm, DBG_CCKPD, "is_linked=%d, lv=%d, pd_th=0x%x\n\n",
 150                   dm->is_linked, cckpd_t->cck_pd_lv,
 151                   cckpd_t->cur_cck_cca_thres);
 152 }
 153 #endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE1*/
 154
 155 #ifdef PHYDM_COMPILE_CCKPD_TYPE2
 156 void phydm_write_cck_pd_type2(void *dm_void, u8 cca_th, u8 cca_th_aaa)
 157 {
 158         struct dm_struct *dm = (struct dm_struct *)dm_void;
 159         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 160
 161         PHYDM_DBG(dm, DBG_CCKPD, "[%s] pd_th=0x%x, cs_ratio=0x%x\n",
 162                   __func__, cca_th, cca_th_aaa);
 163
 164         odm_set_bb_reg(dm, R_0xa08, 0xf0000, cca_th);
 165         odm_set_bb_reg(dm, R_0xaa8, 0x1f0000, cca_th_aaa);
 166         cckpd_t->cur_cck_cca_thres = cca_th;
 167         cckpd_t->cck_cca_th_aaa = cca_th_aaa;
 168 }
 169
 170 void phydm_set_cckpd_lv_type2(void *dm_void, enum cckpd_lv lv)
 171 {
 172         struct dm_struct *dm = (struct dm_struct *)dm_void;
 173         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 174         u8 pd_th = 0, cs_ratio = 0, cs_2r_offset = 0;
 175         u8 cck_n_rx = 1;
 176
 177         PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
 178         PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
 179
 180         /*@r_mrx & r_cca_mrc*/
 181         cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(18)) &&
 182                     odm_get_bb_reg(dm, R_0xa2c, BIT(22))) ? 2 : 1;
 183
 184         if (cckpd_t->cck_pd_lv == lv && cckpd_t->cck_n_rx == cck_n_rx) {
 185                 PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
 186                 return;
 187         }
 188
 189         cckpd_t->cck_n_rx = cck_n_rx;
 190         cckpd_t->cck_pd_lv = lv;
 191         cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
 192
 193         if (lv == CCK_PD_LV_4) {
 194                 cs_ratio = cckpd_t->aaa_default + 8;
 195                 cs_2r_offset = 5;
 196                 pd_th = 0xd;
 197         } else if (lv == CCK_PD_LV_3) {
 198                 cs_ratio = cckpd_t->aaa_default + 6;
 199                 cs_2r_offset = 4;
 200                 pd_th = 0xd;
 201         } else if (lv == CCK_PD_LV_2) {
 202                 cs_ratio = cckpd_t->aaa_default + 4;
 203                 cs_2r_offset = 3;
 204                 pd_th = 0xd;
 205         } else if (lv == CCK_PD_LV_1) {
 206                 cs_ratio = cckpd_t->aaa_default + 2;
 207                 cs_2r_offset = 1;
 208                 pd_th = 0x7;
 209         } else if (lv == CCK_PD_LV_0) {
 210                 cs_ratio = cckpd_t->aaa_default;
 211                 cs_2r_offset = 0;
 212                 pd_th = 0x3;
 213         }
 214
 215         if (cckpd_t->cck_n_rx == 2) {
 216                 if (cs_ratio >= cs_2r_offset)
 217                         cs_ratio = cs_ratio - cs_2r_offset;
 218                 else
 219                         cs_ratio = 0;
 220         }
 221         phydm_write_cck_pd_type2(dm, pd_th, cs_ratio);
 222 }
 223
 224 void phydm_cckpd_type2(void *dm_void)
 225 {
 226         struct dm_struct *dm = (struct dm_struct *)dm_void;
 227         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 228         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 229         enum cckpd_lv lv = CCK_PD_LV_INIT;
 230         u8 igi = dig_t->cur_ig_value;
 231         u8 rssi_min = dm->rssi_min;
 232         boolean is_update = true;
 233
 234         PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
 235
 236         if (dm->is_linked) {
 237                 if (igi > 0x38 && rssi_min > 32) {
 238                         lv = CCK_PD_LV_4;
 239                 } else if (igi > 0x2a && rssi_min > 32) {
 240                         lv = CCK_PD_LV_3;
 241                 } else if (igi > 0x24 || (rssi_min > 24 && rssi_min <= 30)) {
 242                         lv = CCK_PD_LV_2;
 243                 } else if (igi <= 0x24 || rssi_min < 22) {
 244                         if (cckpd_t->cck_fa_ma > 1000) {
 245                                 lv = CCK_PD_LV_1;
 246                         } else if (cckpd_t->cck_fa_ma < 500) {
 247                                 lv = CCK_PD_LV_0;
 248                         } else {
 249                                 is_update = false;
 250                         }
 251                 } else {
 252                         is_update = false;
 253                 }
 254         } else {
 255                 if (cckpd_t->cck_fa_ma > 1000) {
 256                         lv = CCK_PD_LV_1;
 257                 } else if (cckpd_t->cck_fa_ma < 500) {
 258                         lv = CCK_PD_LV_0;
 259                 } else {
 260                         is_update = false;
 261                 }
 262         }
 263
 264         if (is_update) {
 265                 phydm_set_cckpd_lv_type2(dm, lv);
 266         }
 267
 268         PHYDM_DBG(dm, DBG_CCKPD,
 269                   "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x\n\n",
 270                   dm->is_linked, cckpd_t->cck_pd_lv, cckpd_t->cck_n_rx,
 271                   cckpd_t->cck_cca_th_aaa, cckpd_t->cur_cck_cca_thres);
 272 }
 273 #endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE2*/
 274
 275 #ifdef PHYDM_COMPILE_CCKPD_TYPE3
 276 void phydm_write_cck_pd_type3(void *dm_void, u8 pd_th, u8 cs_ratio,
 277                               enum cckpd_mode mode)
 278 {
 279         struct dm_struct *dm = (struct dm_struct *)dm_void;
 280         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 281
 282         PHYDM_DBG(dm, DBG_CCKPD,
 283                   "[%s] mode=%d, pd_th=0x%x, cs_ratio=0x%x\n", __func__,
 284                   mode, pd_th, cs_ratio);
 285
 286         switch (mode) {
 287         case CCK_BW20_1R: /*RFBW20_1R*/
 288         {
 289                 cckpd_t->cur_cck_pd_20m_1r = pd_th;
 290                 cckpd_t->cur_cck_cs_ratio_20m_1r = cs_ratio;
 291                 odm_set_bb_reg(dm, R_0xac8, 0xff, pd_th);
 292                 odm_set_bb_reg(dm, R_0xad0, 0x1f, cs_ratio);
 293         } break;
 294         case CCK_BW20_2R: /*RFBW20_2R*/
 295         {
 296                 cckpd_t->cur_cck_pd_20m_2r = pd_th;
 297                 cckpd_t->cur_cck_cs_ratio_20m_2r = cs_ratio;
 298                 odm_set_bb_reg(dm, R_0xac8, 0xff00, pd_th);
 299                 odm_set_bb_reg(dm, R_0xad0, 0x3e0, cs_ratio);
 300         } break;
 301         case CCK_BW40_1R: /*RFBW40_1R*/
 302         {
 303                 cckpd_t->cur_cck_pd_40m_1r = pd_th;
 304                 cckpd_t->cur_cck_cs_ratio_40m_1r = cs_ratio;
 305                 odm_set_bb_reg(dm, R_0xacc, 0xff, pd_th);
 306                 odm_set_bb_reg(dm, R_0xad0, 0x1f00000, cs_ratio);
 307         } break;
 308         case CCK_BW40_2R: /*RFBW40_2R*/
 309         {
 310                 cckpd_t->cur_cck_pd_40m_2r = pd_th;
 311                 cckpd_t->cur_cck_cs_ratio_40m_2r = cs_ratio;
 312                 odm_set_bb_reg(dm, R_0xacc, 0xff00, pd_th);
 313                 odm_set_bb_reg(dm, R_0xad0, 0x3e000000, cs_ratio);
 314         } break;
 315
 316         default:
 317                 /*@pr_debug("[%s] warning!\n", __func__);*/
 318                 break;
 319         }
 320 }
 321
 322 void phydm_set_cckpd_lv_type3(void *dm_void, enum cckpd_lv lv)
 323 {
 324         struct dm_struct *dm = (struct dm_struct *)dm_void;
 325         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 326         enum cckpd_mode cck_mode = CCK_BW20_2R;
 327         enum channel_width cck_bw = CHANNEL_WIDTH_20;
 328         u8 cck_n_rx = 1;
 329         u8 pd_th;
 330         u8 cs_ratio;
 331
 332         PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
 333         PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
 334
 335         /*[Check Nrx]*/
 336         cck_n_rx = (odm_get_bb_reg(dm, R_0xa2c, BIT(17))) ? 2 : 1;
 337
 338         /*[Check BW]*/
 339         if (odm_get_bb_reg(dm, R_0x800, BIT(0)))
 340                 cck_bw = CHANNEL_WIDTH_40;
 341         else
 342                 cck_bw = CHANNEL_WIDTH_20;
 343
 344         /*[Check LV]*/
 345         if (cckpd_t->cck_pd_lv == lv &&
 346             cckpd_t->cck_n_rx == cck_n_rx &&
 347             cckpd_t->cck_bw == cck_bw) {
 348                 PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
 349                 return;
 350         }
 351
 352         cckpd_t->cck_bw = cck_bw;
 353         cckpd_t->cck_n_rx = cck_n_rx;
 354         cckpd_t->cck_pd_lv = lv;
 355         cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
 356
 357         if (cck_n_rx == 2) {
 358                 if (cck_bw == CHANNEL_WIDTH_20) {
 359                         pd_th = cckpd_t->cck_pd_20m_2r;
 360                         cs_ratio = cckpd_t->cck_cs_ratio_20m_2r;
 361                         cck_mode = CCK_BW20_2R;
 362                 } else {
 363                         pd_th = cckpd_t->cck_pd_40m_2r;
 364                         cs_ratio = cckpd_t->cck_cs_ratio_40m_2r;
 365                         cck_mode = CCK_BW40_2R;
 366                 }
 367         } else {
 368                 if (cck_bw == CHANNEL_WIDTH_20) {
 369                         pd_th = cckpd_t->cck_pd_20m_1r;
 370                         cs_ratio = cckpd_t->cck_cs_ratio_20m_1r;
 371                         cck_mode = CCK_BW20_1R;
 372                 } else {
 373                         pd_th = cckpd_t->cck_pd_40m_1r;
 374                         cs_ratio = cckpd_t->cck_cs_ratio_40m_1r;
 375                         cck_mode = CCK_BW40_1R;
 376                 }
 377         }
 378
 379         if (lv == CCK_PD_LV_4) {
 380                 if (cck_n_rx == 2) {
 381                         pd_th += 4;
 382                         cs_ratio += 2;
 383                 } else {
 384                         pd_th += 4;
 385                         cs_ratio += 3;
 386                 }
 387         } else if (lv == CCK_PD_LV_3) {
 388                 if (cck_n_rx == 2) {
 389                         pd_th += 3;
 390                         cs_ratio += 1;
 391                 } else {
 392                         pd_th += 3;
 393                         cs_ratio += 2;
 394                 }
 395         } else if (lv == CCK_PD_LV_2) {
 396                 pd_th += 2;
 397                 cs_ratio += 1;
 398         } else if (lv == CCK_PD_LV_1) {
 399                 pd_th += 1;
 400                 cs_ratio += 1;
 401         }
 402         #if 0
 403         else if (lv == CCK_PD_LV_0) {
 404                 pd_th += 0;
 405                 cs_ratio += 0;
 406         }
 407         #endif
 408
 409         phydm_write_cck_pd_type3(dm, pd_th, cs_ratio, cck_mode);
 410 }
 411
 412 void phydm_cckpd_type3(void *dm_void)
 413 {
 414         struct dm_struct *dm = (struct dm_struct *)dm_void;
 415         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 416         enum cckpd_lv lv = CCK_PD_LV_INIT;
 417         u8 igi = dm->dm_dig_table.cur_ig_value;
 418         boolean is_update = true;
 419         u8 pd_th = 0;
 420         u8 cs_ratio = 0;
 421
 422         PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
 423
 424         if (dm->is_linked) {
 425                 if (igi > 0x38 && dm->rssi_min > 32) {
 426                         lv = CCK_PD_LV_4;
 427                 } else if ((igi > 0x2a) && (dm->rssi_min > 32)) {
 428                         lv = CCK_PD_LV_3;
 429                 } else if ((igi > 0x24) ||
 430                            (dm->rssi_min > 24 && dm->rssi_min <= 30)) {
 431                         lv = CCK_PD_LV_2;
 432                 } else if ((igi <= 0x24) || (dm->rssi_min < 22)) {
 433                         if (cckpd_t->cck_fa_ma > 1000)
 434                                 lv = CCK_PD_LV_1;
 435                         else if (cckpd_t->cck_fa_ma < 500)
 436                                 lv = CCK_PD_LV_0;
 437                         else
 438                                 is_update = false;
 439                 }
 440         } else {
 441                 if (cckpd_t->cck_fa_ma > 1000)
 442                         lv = CCK_PD_LV_1;
 443                 else if (cckpd_t->cck_fa_ma < 500)
 444                         lv = CCK_PD_LV_0;
 445                 else
 446                         is_update = false;
 447         }
 448
 449         if (is_update)
 450                 phydm_set_cckpd_lv_type3(dm, lv);
 451
 452         if (cckpd_t->cck_n_rx == 2) {
 453                 if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {
 454                         pd_th = cckpd_t->cur_cck_pd_20m_2r;
 455                         cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_2r;
 456                 } else {
 457                         pd_th = cckpd_t->cur_cck_pd_40m_2r;
 458                         cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_2r;
 459                 }
 460         } else {
 461                 if (cckpd_t->cck_bw == CHANNEL_WIDTH_20) {
 462                         pd_th = cckpd_t->cur_cck_pd_20m_1r;
 463                         cs_ratio = cckpd_t->cur_cck_cs_ratio_20m_1r;
 464                 } else {
 465                         pd_th = cckpd_t->cur_cck_pd_40m_1r;
 466                         cs_ratio = cckpd_t->cur_cck_cs_ratio_40m_1r;
 467                 }
 468         }
 469         PHYDM_DBG(dm, DBG_CCKPD,
 470                   "[%dR][%dM] is_linked=%d, lv=%d, cs_ratio=0x%x, pd_th=0x%x\n\n",
 471                   cckpd_t->cck_n_rx, 20 << cckpd_t->cck_bw, dm->is_linked,
 472                   cckpd_t->cck_pd_lv, cs_ratio, pd_th);
 473 }
 474
 475 void phydm_cck_pd_init_type3(void *dm_void)
 476 {
 477         struct dm_struct *dm = (struct dm_struct *)dm_void;
 478         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 479         u32 reg_tmp = 0;
 480
 481         /*Get Default value*/
 482         cckpd_t->cck_pd_20m_1r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff);
 483         cckpd_t->cck_pd_20m_2r = (u8)odm_get_bb_reg(dm, R_0xac8, 0xff00);
 484         cckpd_t->cck_pd_40m_1r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff);
 485         cckpd_t->cck_pd_40m_2r = (u8)odm_get_bb_reg(dm, R_0xacc, 0xff00);
 486
 487         reg_tmp = odm_get_bb_reg(dm, R_0xad0, MASKDWORD);
 488         cckpd_t->cck_cs_ratio_20m_1r = (u8)(reg_tmp & 0x1f);
 489         cckpd_t->cck_cs_ratio_20m_2r = (u8)((reg_tmp & 0x3e0) >> 5);
 490         cckpd_t->cck_cs_ratio_40m_1r = (u8)((reg_tmp & 0x1f00000) >> 20);
 491         cckpd_t->cck_cs_ratio_40m_2r = (u8)((reg_tmp & 0x3e000000) >> 25);
 492
 493         phydm_set_cckpd_lv_type3(dm, CCK_PD_LV_0);
 494 }
 495 #endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE3*/
 496
 497 #ifdef PHYDM_COMPILE_CCKPD_TYPE4
 498 void phydm_write_cck_pd_type4(void *dm_void, enum cckpd_lv lv,
 499                               enum cckpd_mode mode)
 500 {
 501         struct dm_struct *dm = (struct dm_struct *)dm_void;
 502         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 503         u32 val = 0;
 504
 505         PHYDM_DBG(dm, DBG_CCKPD, "write CCK CCA parameters(CS_ratio & PD)\n");
 506         switch (mode) {
 507         case CCK_BW20_1R: /*RFBW20_1R*/
 508         {
 509                 val = cckpd_t->cck_pd_table_jgr3[0][0][0][lv];
 510                 odm_set_bb_reg(dm, R_0x1ac8, 0xff, val);
 511                 val = cckpd_t->cck_pd_table_jgr3[0][0][1][lv];
 512                 odm_set_bb_reg(dm, R_0x1ad0, 0x1f, val);
 513         } break;
 514         case CCK_BW40_1R: /*RFBW40_1R*/
 515         {
 516                 val = cckpd_t->cck_pd_table_jgr3[1][0][0][lv];
 517                 odm_set_bb_reg(dm, R_0x1acc, 0xff, val);
 518                 val = cckpd_t->cck_pd_table_jgr3[1][0][1][lv];
 519                 odm_set_bb_reg(dm, R_0x1ad0, 0x01F00000, val);
 520         } break;
 521         #if (defined(PHYDM_COMPILE_ABOVE_2SS))
 522         case CCK_BW20_2R: /*RFBW20_2R*/
 523         {
 524                 val = cckpd_t->cck_pd_table_jgr3[0][1][0][lv];
 525                 odm_set_bb_reg(dm, R_0x1ac8, 0xff00, val);
 526                 val = cckpd_t->cck_pd_table_jgr3[0][1][1][lv];
 527                 odm_set_bb_reg(dm, R_0x1ad0, 0x3e0, val);
 528         } break;
 529         case CCK_BW40_2R: /*RFBW40_2R*/
 530         {
 531                 val = cckpd_t->cck_pd_table_jgr3[1][1][0][lv];
 532                 odm_set_bb_reg(dm, R_0x1acc, 0xff00, val);
 533                 val = cckpd_t->cck_pd_table_jgr3[1][1][1][lv];
 534                 odm_set_bb_reg(dm, R_0x1ad0, 0x3E000000, val);
 535         } break;
 536         #endif
 537         #if (defined(PHYDM_COMPILE_ABOVE_3SS))
 538         case CCK_BW20_3R: /*RFBW20_3R*/
 539         {
 540                 val = cckpd_t->cck_pd_table_jgr3[0][2][0][lv];
 541                 odm_set_bb_reg(dm, R_0x1ac8, 0xff0000, val);
 542                 val = cckpd_t->cck_pd_table_jgr3[0][2][1][lv];
 543                 odm_set_bb_reg(dm, R_0x1ad0, 0x7c00, val);
 544         } break;
 545         case CCK_BW40_3R: /*RFBW40_3R*/
 546         {
 547                 val = cckpd_t->cck_pd_table_jgr3[1][2][0][lv];
 548                 odm_set_bb_reg(dm, R_0x1acc, 0xff0000, val);
 549                 val = cckpd_t->cck_pd_table_jgr3[1][2][1][lv] & 0x3;
 550                 odm_set_bb_reg(dm, R_0x1ad0, 0xC0000000, val);
 551                 val = (cckpd_t->cck_pd_table_jgr3[1][2][1][lv] & 0x1c) >> 2;
 552                 odm_set_bb_reg(dm, R_0x1ad4, 0x7, val);
 553         } break;
 554         #endif
 555         #if (defined(PHYDM_COMPILE_ABOVE_4SS))
 556         case CCK_BW20_4R: /*RFBW20_4R*/
 557         {
 558                 val = cckpd_t->cck_pd_table_jgr3[0][3][0][lv];
 559                 odm_set_bb_reg(dm, R_0x1ac8, 0xff000000, val);
 560                 val = cckpd_t->cck_pd_table_jgr3[0][3][1][lv];
 561                 odm_set_bb_reg(dm, R_0x1ad0, 0xF8000, val);
 562         } break;
 563         case CCK_BW40_4R: /*RFBW40_4R*/
 564         {
 565                 val = cckpd_t->cck_pd_table_jgr3[1][3][0][lv];
 566                 odm_set_bb_reg(dm, R_0x1acc, 0xff000000, val);
 567                 val = cckpd_t->cck_pd_table_jgr3[1][3][1][lv];
 568                 odm_set_bb_reg(dm, R_0x1ad4, 0xf8, val);
 569         } break;
 570         #endif
 571         default:
 572                 /*@pr_debug("[%s] warning!\n", __func__);*/
 573                 break;
 574         }
 575 }
 576
 577 void phydm_set_cck_pd_lv_type4(void *dm_void, enum cckpd_lv lv)
 578 {
 579         struct dm_struct *dm = (struct dm_struct *)dm_void;
 580         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 581         enum cckpd_mode cck_mode = CCK_BW20_2R;
 582         enum channel_width cck_bw = CHANNEL_WIDTH_20;
 583         u8 cck_n_rx;
 584         u32 val;
 585         /*u32 val_dbg = 0;*/
 586
 587         PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
 588         PHYDM_DBG(dm, DBG_CCKPD, "lv: (%d) -> (%d)\n", cckpd_t->cck_pd_lv, lv);
 589
 590         /*[Check Nrx]*/
 591         cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
 592
 593         /*[Check BW]*/
 594         val = odm_get_bb_reg(dm, R_0x9b0, 0xc);
 595         if (val == 0)
 596                 cck_bw = CHANNEL_WIDTH_20;
 597         else if (val == 1)
 598                 cck_bw = CHANNEL_WIDTH_40;
 599         else
 600                 cck_bw = CHANNEL_WIDTH_80;
 601
 602         /*[Check LV]*/
 603         if (cckpd_t->cck_pd_lv == lv &&
 604             cckpd_t->cck_n_rx == cck_n_rx &&
 605             cckpd_t->cck_bw == cck_bw) {
 606                 PHYDM_DBG(dm, DBG_CCKPD, "stay in lv=%d\n", lv);
 607                 return;
 608         }
 609
 610         cckpd_t->cck_bw = cck_bw;
 611         cckpd_t->cck_n_rx = cck_n_rx;
 612         cckpd_t->cck_pd_lv = lv;
 613         cckpd_t->cck_fa_ma = CCK_FA_MA_RESET;
 614
 615         switch (cck_n_rx) {
 616         case 1: /*1R*/
 617         {
 618                 if (cck_bw == CHANNEL_WIDTH_20)
 619                         cck_mode = CCK_BW20_1R;
 620                 else if (cck_bw == CHANNEL_WIDTH_40)
 621                         cck_mode = CCK_BW40_1R;
 622         } break;
 623         #if (defined(PHYDM_COMPILE_ABOVE_2SS))
 624         case 2: /*2R*/
 625         {
 626                 if (cck_bw == CHANNEL_WIDTH_20)
 627                         cck_mode = CCK_BW20_2R;
 628                 else if (cck_bw == CHANNEL_WIDTH_40)
 629                         cck_mode = CCK_BW40_2R;
 630         } break;
 631         #endif
 632         #if (defined(PHYDM_COMPILE_ABOVE_3SS))
 633         case 3: /*3R*/
 634         {
 635                 if (cck_bw == CHANNEL_WIDTH_20)
 636                         cck_mode = CCK_BW20_3R;
 637                 else if (cck_bw == CHANNEL_WIDTH_40)
 638                         cck_mode = CCK_BW40_3R;
 639         } break;
 640         #endif
 641         #if (defined(PHYDM_COMPILE_ABOVE_4SS))
 642         case 4: /*4R*/
 643         {
 644                 if (cck_bw == CHANNEL_WIDTH_20)
 645                         cck_mode = CCK_BW20_4R;
 646                 else if (cck_bw == CHANNEL_WIDTH_40)
 647                         cck_mode = CCK_BW40_4R;
 648         } break;
 649         #endif
 650         default:
 651                 /*@pr_debug("[%s] warning!\n", __func__);*/
 652                 break;
 653         }
 654 phydm_write_cck_pd_type4(dm, lv, cck_mode);
 655 }
 656
 657 void phydm_read_cckpd_para_type4(void *dm_void)
 658 {
 659         struct dm_struct *dm = (struct dm_struct *)dm_void;
 660         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 661         u8 bw = 0; /*r_RX_RF_BW*/
 662         u8 n_rx = 0;
 663         u8 curr_cck_pd_t[2][4][2];
 664         u32 reg0 = 0;
 665         u32 reg1 = 0;
 666         u32 reg2 = 0;
 667         u32 reg3 = 0;
 668
 669         bw = (u8)odm_get_bb_reg(dm, R_0x9b0, 0xc);
 670         n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
 671
 672         reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);
 673         reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);
 674         reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);
 675         reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);
 676         curr_cck_pd_t[0][0][0] = (u8)(reg0 & 0x000000ff);
 677         curr_cck_pd_t[1][0][0] = (u8)(reg1 & 0x000000ff);
 678         curr_cck_pd_t[0][0][1] = (u8)(reg2 & 0x0000001f);
 679         curr_cck_pd_t[1][0][1] = (u8)((reg2 & 0x01f00000) >> 20);
 680         #if (defined(PHYDM_COMPILE_ABOVE_2SS))
 681         if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
 682                 curr_cck_pd_t[0][1][0] = (u8)((reg0 & 0x0000ff00) >> 8);
 683                 curr_cck_pd_t[1][1][0] = (u8)((reg1 & 0x0000ff00) >> 8);
 684                 curr_cck_pd_t[0][1][1] = (u8)((reg2 & 0x000003E0) >> 5);
 685                 curr_cck_pd_t[1][1][1] = (u8)((reg2 & 0x3E000000) >> 25);
 686         }
 687         #endif
 688         #if (defined(PHYDM_COMPILE_ABOVE_3SS))
 689         if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
 690                 curr_cck_pd_t[0][2][0] = (u8)((reg0 & 0x00ff0000) >> 16);
 691                 curr_cck_pd_t[1][2][0] = (u8)((reg1 & 0x00ff0000) >> 16);
 692                 curr_cck_pd_t[0][2][1] = (u8)((reg2 & 0x00007C00) >> 10);
 693                 curr_cck_pd_t[1][2][1] = (u8)((reg2 & 0xC0000000) >> 30) |
 694                                           ((reg3 & 0x7) << 3);
 695         }
 696         #endif
 697         #if (defined(PHYDM_COMPILE_ABOVE_4SS))
 698         if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
 699                 curr_cck_pd_t[0][3][0] = (u8)((reg0 & 0xff000000) >> 24);
 700                 curr_cck_pd_t[1][3][0] = (u8)((reg1 & 0xff000000) >> 24);
 701                 curr_cck_pd_t[0][3][1] = (u8)((reg2 & 0x000F8000) >> 15);
 702                 curr_cck_pd_t[1][3][1] = (u8)((reg3 & 0x000000F8) >> 3);
 703         }
 704         #endif
 705
 706         PHYDM_DBG(dm, DBG_CCKPD, "bw=%dM, Nrx=%d\n", 20 << bw, n_rx);
 707         PHYDM_DBG(dm, DBG_CCKPD, "lv=%d, readback CS_th=%x, PD th=%x\n",
 708                   cckpd_t->cck_pd_lv,
 709                   curr_cck_pd_t[bw][n_rx - 1][1],
 710                   curr_cck_pd_t[bw][n_rx - 1][0]);
 711 }
 712
 713 void phydm_cckpd_type4(void *dm_void)
 714 {
 715         struct dm_struct *dm = (struct dm_struct *)dm_void;
 716         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 717         u8 igi = dm->dm_dig_table.cur_ig_value;
 718         enum cckpd_lv lv = 0;
 719         boolean is_update = true;
 720
 721         PHYDM_DBG(dm, DBG_CCKPD, "%s ======>\n", __func__);
 722
 723         if (dm->is_linked) {
 724                 PHYDM_DBG(dm, DBG_CCKPD, "Linked!!!\n");
 725                 if (igi > 0x38 && dm->rssi_min > 32) {
 726                         lv = CCK_PD_LV_4;
 727                         PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
 728                 } else if ((igi > 0x2a) && (dm->rssi_min > 32)) {
 729                         lv = CCK_PD_LV_3;
 730                         PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
 731                 } else if ((igi > 0x24) ||
 732                            (dm->rssi_min > 24 && dm->rssi_min <= 30)) {
 733                         lv = CCK_PD_LV_2;
 734                         PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
 735                 } else if ((igi <= 0x24) || (dm->rssi_min < 22)) {
 736                         if (cckpd_t->cck_fa_ma > 1000) {
 737                                 lv = CCK_PD_LV_1;
 738                                 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-1\n");
 739                         } else if (cckpd_t->cck_fa_ma < 500) {
 740                                 lv = CCK_PD_LV_0;
 741                                 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-2\n");
 742                         } else {
 743                                 is_update = false;
 744                                 PHYDM_DBG(dm, DBG_CCKPD, "Order 4-3\n");
 745                         }
 746                 } else {
 747                         is_update = false;
 748                 }
 749         } else {
 750                 PHYDM_DBG(dm, DBG_CCKPD, "UnLinked!!!\n");
 751                 if (cckpd_t->cck_fa_ma > 1000) {
 752                         lv = CCK_PD_LV_1;
 753                         PHYDM_DBG(dm, DBG_CCKPD, "Order 1\n");
 754                 } else if (cckpd_t->cck_fa_ma < 500) {
 755                         lv = CCK_PD_LV_0;
 756                         PHYDM_DBG(dm, DBG_CCKPD, "Order 2\n");
 757                 } else {
 758                         is_update = false;
 759                         PHYDM_DBG(dm, DBG_CCKPD, "Order 3\n");
 760                 }
 761         }
 762
 763         if (is_update)
 764                 phydm_set_cck_pd_lv_type4(dm, lv);
 765
 766
 767         PHYDM_DBG(dm, DBG_CCKPD, "setting CS_th = 0x%x, PD th = 0x%x\n",
 768                   cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw]
 769                   [cckpd_t->cck_n_rx - 1][1][lv],
 770                   cckpd_t->cck_pd_table_jgr3[cckpd_t->cck_bw]
 771                   [cckpd_t->cck_n_rx - 1][0][lv]);
 772
 773         phydm_read_cckpd_para_type4(dm);
 774 }
 775
 776 void phydm_cck_pd_init_type4(void *dm_void)
 777 {
 778         struct dm_struct *dm = (struct dm_struct *)dm_void;
 779         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 780         u32 reg0 = 0;
 781         u32 reg1 = 0;
 782         u32 reg2 = 0;
 783         u32 reg3 = 0;
 784         u8 pd_step = 0;
 785         u8 cck_bw = 0; /*r_RX_RF_BW*/
 786         u8 cck_n_rx = 0;
 787         u8 val = 0;
 788         u8 i = 0;
 789
 790         PHYDM_DBG(dm, DBG_CCKPD, "[%s]======>\n", __func__);
 791
 792         #if 0
 793         /*@
 794          *cckpd_t[0][0][0][0] =  1ac8[7:0]      r_PD_lim_RFBW20_1R
 795          *cckpd_t[0][1][0][0] =  1ac8[15:8]     r_PD_lim_RFBW20_2R
 796          *cckpd_t[0][2][0][0] =  1ac8[23:16]    r_PD_lim_RFBW20_3R
 797          *cckpd_t[0][3][0][0] =  1ac8[31:24]    r_PD_lim_RFBW20_4R
 798          *cckpd_t[1][0][0][0] =  1acc[7:0]      r_PD_lim_RFBW40_1R
 799          *cckpd_t[1][1][0][0] =  1acc[15:8]     r_PD_lim_RFBW40_2R
 800          *cckpd_t[1][2][0][0] =  1acc[23:16]    r_PD_lim_RFBW40_3R
 801          *cckpd_t[1][3][0][0] =  1acc[31:24]    r_PD_lim_RFBW40_4R
 802          *
 803          *
 804          *cckpd_t[0][0][1][0] =  1ad0[4:0]      r_CS_ratio_RFBW20_1R[4:0]
 805          *cckpd_t[0][1][1][0] =  1ad0[9:5]      r_CS_ratio_RFBW20_2R[4:0]
 806          *cckpd_t[0][2][1][0] =  1ad0[14:10]    r_CS_ratio_RFBW20_3R[4:0]
 807          *cckpd_t[0][3][1][0] =  1ad0[19:15]    r_CS_ratio_RFBW20_4R[4:0]
 808          *cckpd_t[1][0][1][0] =  1ad0[24:20]    r_CS_ratio_RFBW40_1R[4:0]
 809          *cckpd_t[1][1][1][0] =  1ad0[29:25]    r_CS_ratio_RFBW40_2R[4:0]
 810          *cckpd_t[1][2][1][0] =  1ad0[31:30]    r_CS_ratio_RFBW40_3R[1:0]
 811          *                        1ad4[2:0]     r_CS_ratio_RFBW40_3R[4:2]
 812          *cckpd_t[1][3][1][0] =  1ad4[7:3]      r_CS_ratio_RFBW40_4R[4:0]
 813          */
 814         #endif
 815         /*[Check Nrx]*/
 816         cck_n_rx = (u8)odm_get_bb_reg(dm, R_0x1a2c, 0x60000) + 1;
 817
 818         /*[Check BW]*/
 819         val = odm_get_bb_reg(dm, R_0x9b0, 0xc);
 820         if (val == 0)
 821                 cck_bw = CHANNEL_WIDTH_20;
 822         else if (val == 1)
 823                 cck_bw = CHANNEL_WIDTH_40;
 824         else
 825                 cck_bw = CHANNEL_WIDTH_80;
 826
 827         cckpd_t->cck_bw = cck_bw;
 828         cckpd_t->cck_n_rx = cck_n_rx;
 829         reg0 = odm_get_bb_reg(dm, R_0x1ac8, MASKDWORD);
 830         reg1 = odm_get_bb_reg(dm, R_0x1acc, MASKDWORD);
 831         reg2 = odm_get_bb_reg(dm, R_0x1ad0, MASKDWORD);
 832         reg3 = odm_get_bb_reg(dm, R_0x1ad4, MASKDWORD);
 833
 834         for (i = 0 ; i < CCK_PD_LV_MAX ; i++) {
 835                 pd_step = i * 2;
 836
 837                 val = (u8)(reg0 & 0x000000ff) + pd_step;
 838                 PHYDM_DBG(dm, DBG_CCKPD, "lvl %d val = %x\n\n", i, val);
 839                 cckpd_t->cck_pd_table_jgr3[0][0][0][i] = val;
 840
 841                 val = (u8)(reg1 & 0x000000ff) + pd_step;
 842                 cckpd_t->cck_pd_table_jgr3[1][0][0][i] = val;
 843
 844                 val = (u8)(reg2 & 0x0000001F) + pd_step;
 845                 cckpd_t->cck_pd_table_jgr3[0][0][1][i] = val;
 846
 847                 val = (u8)((reg2 & 0x01F00000) >> 20) + pd_step;
 848                 cckpd_t->cck_pd_table_jgr3[1][0][1][i] = val;
 849
 850                 #ifdef PHYDM_COMPILE_ABOVE_2SS
 851                 if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS) {
 852                         val = (u8)((reg0 & 0x0000ff00) >> 8) + pd_step;
 853                         cckpd_t->cck_pd_table_jgr3[0][1][0][i] = val;
 854
 855                         val = (u8)((reg1 & 0x0000ff00) >> 8) + pd_step;
 856                         cckpd_t->cck_pd_table_jgr3[1][1][0][i] = val;
 857
 858                         val = (u8)((reg2 & 0x000003E0) >> 5) + pd_step;
 859                         cckpd_t->cck_pd_table_jgr3[0][1][1][i] = val;
 860
 861                         val = (u8)((reg2 & 0x3E000000) >> 25) + pd_step;
 862                         cckpd_t->cck_pd_table_jgr3[1][1][1][i] = val;
 863                 }
 864                 #endif
 865
 866                 #ifdef PHYDM_COMPILE_ABOVE_3SS
 867                 if (dm->support_ic_type & PHYDM_IC_ABOVE_3SS) {
 868                         val = (u8)((reg0 & 0x00ff0000) >> 16) + pd_step;
 869                         cckpd_t->cck_pd_table_jgr3[0][2][0][i] = val;
 870
 871                         val = (u8)((reg1 & 0x00ff0000) >> 16) + pd_step;
 872                         cckpd_t->cck_pd_table_jgr3[1][2][0][i] = val;
 873                         val = (u8)((reg2 & 0x00007C00) >> 10) + pd_step;
 874                         cckpd_t->cck_pd_table_jgr3[0][2][1][i] = val;
 875                         val = (u8)(((reg2 & 0xC0000000) >> 30) |
 876                               ((reg3 & 0x7) << 3)) + pd_step;
 877                         cckpd_t->cck_pd_table_jgr3[1][2][1][i] = val;
 878                 }
 879                 #endif
 880
 881                 #ifdef PHYDM_COMPILE_ABOVE_4SS
 882                 if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
 883                         val = (u8)((reg0 & 0xff000000) >> 24) + pd_step;
 884                         cckpd_t->cck_pd_table_jgr3[0][3][0][i] = val;
 885
 886                         val = (u8)((reg1 & 0xff000000) >> 24) + pd_step;
 887                         cckpd_t->cck_pd_table_jgr3[1][3][0][i] = val;
 888
 889                         val = (u8)((reg2 & 0x000F8000) >> 15) + pd_step;
 890                         cckpd_t->cck_pd_table_jgr3[0][3][1][i] = val;
 891
 892                         val = (u8)((reg3 & 0x000000F8) >> 3) + pd_step;
 893                         cckpd_t->cck_pd_table_jgr3[1][3][1][i] = val;
 894                 }
 895                 #endif
 896         }
 897 }
 898 #endif /*#ifdef PHYDM_COMPILE_CCKPD_TYPE4*/
 899
 900 void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len)
 901 {
 902         struct dm_struct *dm = (struct dm_struct *)dm_void;
 903         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 904         enum cckpd_lv lv;
 905
 906         if (val_len != 1) {
 907                 PHYDM_DBG(dm, ODM_COMP_API, "[Error][CCKPD]Need val_len=1\n");
 908                 return;
 909         }
 910
 911         lv = (enum cckpd_lv)val_buf[0];
 912
 913         if (lv > CCK_PD_LV_4) {
 914                 pr_debug("[%s] warning! lv=%d\n", __func__, lv);
 915                 return;
 916         }
 917
 918         switch (cckpd_t->cckpd_hw_type) {
 919         #ifdef PHYDM_COMPILE_CCKPD_TYPE1
 920         case 1:
 921                 phydm_set_cckpd_lv_type1(dm, lv);
 922                 break;
 923         #endif
 924         #ifdef PHYDM_COMPILE_CCKPD_TYPE2
 925         case 2:
 926                 phydm_set_cckpd_lv_type2(dm, lv);
 927                 break;
 928         #endif
 929         #ifdef PHYDM_COMPILE_CCKPD_TYPE3
 930         case 3:
 931                 phydm_set_cckpd_lv_type3(dm, lv);
 932                 break;
 933         #endif
 934         #ifdef PHYDM_COMPILE_CCKPD_TYPE4
 935         case 4:
 936                 phydm_set_cck_pd_lv_type4(dm, lv);
 937                 break;
 938         #endif
 939         default:
 940                 pr_debug("[%s]warning\n", __func__);
 941                 break;
 942         }
 943 }
 944
 945 boolean
 946 phydm_stop_cck_pd_th(void *dm_void)
 947 {
 948         struct dm_struct *dm = (struct dm_struct *)dm_void;
 949
 950         if (!(dm->support_ability & (ODM_BB_CCK_PD | ODM_BB_FA_CNT))) {
 951                 PHYDM_DBG(dm, DBG_CCKPD, "Not Support\n");
 952                 return true;
 953         }
 954
 955         if (dm->pause_ability & ODM_BB_CCK_PD) {
 956                 PHYDM_DBG(dm, DBG_CCKPD, "Return: Pause CCKPD in LV=%d\n",
 957                           dm->pause_lv_table.lv_cckpd);
 958                 return true;
 959         }
 960
 961         if (dm->is_linked && (*dm->channel > 36)) {
 962                 PHYDM_DBG(dm, DBG_CCKPD, "Return: 5G CH=%d\n", *dm->channel);
 963                 return true;
 964         }
 965         return false;
 966 }
 967
 968 void phydm_cck_pd_th(void *dm_void)
 969 {
 970         struct dm_struct *dm = (struct dm_struct *)dm_void;
 971         struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
 972         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
 973         u32 cck_fa = fa_t->cnt_cck_fail;
 974         #ifdef PHYDM_TDMA_DIG_SUPPORT
 975         struct phydm_fa_acc_struct *fa_acc_t = &dm->false_alm_cnt_acc;
 976         #endif
 977
 978         PHYDM_DBG(dm, DBG_CCKPD, "[%s] ======>\n", __func__);
 979
 980         if (phydm_stop_cck_pd_th(dm))
 981                 return;
 982
 983         #ifdef PHYDM_TDMA_DIG_SUPPORT
 984         if (dm->original_dig_restore)
 985                 cck_fa = fa_t->cnt_cck_fail;
 986         else
 987                 cck_fa = fa_acc_t->cnt_cck_fail_1sec;
 988         #endif
 989
 990         if (cckpd_t->cck_fa_ma == CCK_FA_MA_RESET)
 991                 cckpd_t->cck_fa_ma = cck_fa;
 992         else
 993                 cckpd_t->cck_fa_ma = (cckpd_t->cck_fa_ma * 3 + cck_fa) >> 2;
 994
 995         PHYDM_DBG(dm, DBG_CCKPD,
 996                   "IGI=0x%x, rssi_min=%d, cck_fa=%d, cck_fa_ma=%d\n",
 997                   dm->dm_dig_table.cur_ig_value, dm->rssi_min,
 998                   cck_fa, cckpd_t->cck_fa_ma);
 999
1000         switch (cckpd_t->cckpd_hw_type) {
1001         #ifdef PHYDM_COMPILE_CCKPD_TYPE1
1002         case 1:
1003                 phydm_cckpd_type1(dm);
1004                 break;
1005         #endif
1006         #ifdef PHYDM_COMPILE_CCKPD_TYPE2
1007         case 2:
1008                 phydm_cckpd_type2(dm);
1009                 break;
1010         #endif
1011         #ifdef PHYDM_COMPILE_CCKPD_TYPE3
1012         case 3:
1013                 phydm_cckpd_type3(dm);
1014                 break;
1015         #endif
1016         #ifdef PHYDM_COMPILE_CCKPD_TYPE4
1017         case 4:
1018                 phydm_cckpd_type4(dm);
1019                 break;
1020         #endif
1021         default:
1022                 pr_debug("[%s]warning\n", __func__);
1023                 break;
1024         }
1025 }
1026
1027 void phydm_cck_pd_init(void *dm_void)
1028 {
1029         struct dm_struct *dm = (struct dm_struct *)dm_void;
1030         struct phydm_cckpd_struct *cckpd_t = &dm->dm_cckpd_table;
1031
1032         if (dm->support_ic_type & CCK_PD_IC_TYPE1)
1033                 cckpd_t->cckpd_hw_type = 1;
1034         else if (dm->support_ic_type & CCK_PD_IC_TYPE2)
1035                 cckpd_t->cckpd_hw_type = 2;
1036         else if (dm->support_ic_type & CCK_PD_IC_TYPE3)
1037                 cckpd_t->cckpd_hw_type = 3;
1038         else if (dm->support_ic_type & CCK_PD_IC_TYPE4)
1039                 cckpd_t->cckpd_hw_type = 4;
1040
1041         PHYDM_DBG(dm, DBG_CCKPD, "[%s] cckpd_hw_type=%d\n",
1042                   __func__, cckpd_t->cckpd_hw_type);
1043
1044         cckpd_t->cck_pd_lv = CCK_PD_LV_INIT;
1045         cckpd_t->cck_n_rx = 0xff;
1046         cckpd_t->cck_bw = CHANNEL_WIDTH_MAX;
1047
1048         switch (cckpd_t->cckpd_hw_type) {
1049         #ifdef PHYDM_COMPILE_CCKPD_TYPE1
1050         case 1:
1051                 phydm_set_cckpd_lv_type1(dm, CCK_PD_LV_0);
1052                 break;
1053         #endif
1054         #ifdef PHYDM_COMPILE_CCKPD_TYPE2
1055         case 2:
1056                 cckpd_t->aaa_default = odm_read_1byte(dm, 0xaaa) & 0x1f;
1057                 phydm_set_cckpd_lv_type2(dm, CCK_PD_LV_0);
1058                 break;
1059         #endif
1060         #ifdef PHYDM_COMPILE_CCKPD_TYPE3
1061         case 3:
1062                 phydm_cck_pd_init_type3(dm);
1063                 break;
1064         #endif
1065         #ifdef PHYDM_COMPILE_CCKPD_TYPE4
1066         case 4:
1067                 phydm_cck_pd_init_type4(dm);
1068                 break;
1069         #endif
1070         default:
1071                 pr_debug("[%s]warning\n", __func__);
1072                 break;
1073         }
1074 }
1075 #endif /*#ifdef PHYDM_SUPPORT_CCKPD*/