rtl8821ce/hal/phydm/phydm_cck_pd.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2017  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __PHYDM_CCK_PD_H__
  27 #define __PHYDM_CCK_PD_H__
  28
  29 #define CCK_PD_VERSION "3.0"
  30
  31 /*@
  32  * 1 ============================================================
  33  * 1  Definition
  34  * 1 ============================================================
  35  */
  36 #define CCK_FA_MA_RESET 0xffffffff
  37
  38 /*@Run time flag of CCK_PD HW type*/
  39 #define CCK_PD_IC_TYPE1 (ODM_RTL8188E | ODM_RTL8812 | ODM_RTL8821 |\
  40                         ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8814A |\
  41                         ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8703B |\
  42                         ODM_RTL8195A | ODM_RTL8188F)
  43
  44 #define CCK_PD_IC_TYPE2 (ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8723D |\
  45                         ODM_RTL8710B | ODM_RTL8195B) /*extend 0xaaa*/
  46
  47 #define CCK_PD_IC_TYPE3 ODM_RTL8192F /*@extend for different bw & path*/
  48
  49 #define CCK_PD_IC_TYPE4 ODM_IC_JGR3_SERIES /*@extend for different bw & path*/
  50
  51 /*@Compile time flag of CCK_PD HW type*/
  52 #if (RTL8188E_SUPPORT || RTL8812A_SUPPORT || RTL8821A_SUPPORT ||\
  53         RTL8192E_SUPPORT || RTL8723B_SUPPORT || RTL8814A_SUPPORT ||\
  54         RTL8881A_SUPPORT || RTL8822B_SUPPORT || RTL8703B_SUPPORT ||\
  55         RTL8195A_SUPPORT || RTL8188F_SUPPORT)
  56         #define PHYDM_COMPILE_CCKPD_TYPE1 /*@only 0xa0a*/
  57 #endif
  58
  59 #if (RTL8197F_SUPPORT || RTL8821C_SUPPORT || RTL8723D_SUPPORT ||\
  60         RTL8710B_SUPPORT || RTL8195B_SUPPORT)
  61         #define PHYDM_COMPILE_CCKPD_TYPE2 /*@extend 0xaaa*/
  62 #endif
  63
  64 #if (RTL8192F_SUPPORT)
  65         #define PHYDM_COMPILE_CCKPD_TYPE3 /*@extend for different & path*/
  66 #endif
  67
  68 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
  69         #define PHYDM_COMPILE_CCKPD_TYPE4 /*@extend for different bw & path*/
  70 #endif
  71 /*@
  72  * 1 ============================================================
  73  * 1  enumeration
  74  * 1 ============================================================
  75  */
  76 enum cckpd_lv {
  77         CCK_PD_LV_INIT = 0xff,
  78         CCK_PD_LV_0 = 0,
  79         CCK_PD_LV_1 = 1,
  80         CCK_PD_LV_2 = 2,
  81         CCK_PD_LV_3 = 3,
  82         CCK_PD_LV_4 = 4,
  83         CCK_PD_LV_MAX = 5
  84 };
  85
  86 enum cckpd_mode {
  87         CCK_BW20_1R = 0,
  88         CCK_BW20_2R = 1,
  89         CCK_BW20_3R = 2,
  90         CCK_BW20_4R = 3,
  91         CCK_BW40_1R = 4,
  92         CCK_BW40_2R = 5,
  93         CCK_BW40_3R = 6,
  94         CCK_BW40_4R = 7
  95 };
  96
  97 /*@
  98  * 1 ============================================================
  99  * 1  structure
 100  * 1 ============================================================
 101  */
 102
 103 #ifdef PHYDM_SUPPORT_CCKPD
 104 struct phydm_cckpd_struct {
 105         u8              cckpd_hw_type;
 106         u8              cur_cck_cca_thres; /*@current cck_pd value 0xa0a*/
 107         u32             cck_fa_ma;
 108         u8              rvrt_val;
 109         u8              pause_lv;
 110         u8              cck_n_rx;
 111         enum channel_width cck_bw;
 112         enum cckpd_lv   cck_pd_lv;
 113         #ifdef PHYDM_COMPILE_CCKPD_TYPE2
 114         u8              cck_cca_th_aaa; /*@current cs_ratio value 0xaaa*/
 115         u8              aaa_default;    /*@Init cs_ratio value - 0xaaa*/
 116         #endif
 117         #ifdef PHYDM_COMPILE_CCKPD_TYPE3
 118         /*Default value*/
 119         u8              cck_pd_20m_1r;
 120         u8              cck_pd_20m_2r;
 121         u8              cck_pd_40m_1r;
 122         u8              cck_pd_40m_2r;
 123         u8              cck_cs_ratio_20m_1r;
 124         u8              cck_cs_ratio_20m_2r;
 125         u8              cck_cs_ratio_40m_1r;
 126         u8              cck_cs_ratio_40m_2r;
 127         /*Current value*/
 128         u8              cur_cck_pd_20m_1r;
 129         u8              cur_cck_pd_20m_2r;
 130         u8              cur_cck_pd_40m_1r;
 131         u8              cur_cck_pd_40m_2r;
 132         u8              cur_cck_cs_ratio_20m_1r;
 133         u8              cur_cck_cs_ratio_20m_2r;
 134         u8              cur_cck_cs_ratio_40m_1r;
 135         u8              cur_cck_cs_ratio_40m_2r;
 136         #endif
 137         #ifdef PHYDM_COMPILE_CCKPD_TYPE4
 138         /*@[bw][nrx][0:PD/1:CS][lv]*/
 139         u8              cck_pd_table_jgr3[2][4][2][CCK_PD_LV_MAX];
 140         #endif
 141 };
 142 #endif
 143
 144 /*@
 145  * 1 ============================================================
 146  * 1  function prototype
 147  * 1 ============================================================
 148  */
 149 void phydm_set_cckpd_val(void *dm_void, u32 *val_buf, u8 val_len);
 150
 151 void phydm_cck_pd_th(void *dm_void);
 152
 153 void phydm_cck_pd_init(void *dm_void);
 154 #endif