rtl8821ce/hal/phydm/phydm_dig.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2017  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 /*@************************************************************
  27  * include files
  28  * ************************************************************
  29  */
  30 #include "mp_precomp.h"
  31 #include "phydm_precomp.h"
  32
  33 #ifdef CFG_DIG_DAMPING_CHK
  34 void phydm_dig_recorder_reset(void *dm_void)
  35 {
  36         struct dm_struct *dm = (struct dm_struct *)dm_void;
  37         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
  38         struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
  39
  40         PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
  41
  42         odm_memory_set(dm, &dig_rc->igi_bitmap, 0,
  43                        sizeof(struct phydm_dig_recorder_strcut));
  44 }
  45
  46 void phydm_dig_recorder(void *dm_void, boolean first_connect, u8 igi_curr,
  47                         u32 fa_cnt)
  48 {
  49         struct dm_struct *dm = (struct dm_struct *)dm_void;
  50         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
  51         struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
  52         u8 igi_pre = dig_rc->igi_history[0];
  53         u8 igi_up = 0;
  54
  55         if (!dm->is_linked)
  56                 return;
  57
  58         PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
  59
  60         if (first_connect) {
  61                 phydm_dig_recorder_reset(dm);
  62                 dig_rc->igi_history[0] = igi_curr;
  63                 dig_rc->fa_history[0] = fa_cnt;
  64                 return;
  65         }
  66
  67         igi_pre = dig_rc->igi_history[0];
  68         igi_up = (igi_curr > igi_pre) ? 1 : 0;
  69         dig_rc->igi_bitmap = ((dig_rc->igi_bitmap << 1) & 0xfe) | igi_up;
  70
  71         dig_rc->igi_history[3] = dig_rc->igi_history[2];
  72         dig_rc->igi_history[2] = dig_rc->igi_history[1];
  73         dig_rc->igi_history[1] = dig_rc->igi_history[0];
  74         dig_rc->igi_history[0] = igi_curr;
  75
  76         dig_rc->fa_history[3] = dig_rc->fa_history[2];
  77         dig_rc->fa_history[2] = dig_rc->fa_history[1];
  78         dig_rc->fa_history[1] = dig_rc->fa_history[0];
  79         dig_rc->fa_history[0] = fa_cnt;
  80
  81         PHYDM_DBG(dm, DBG_DIG, "igi_history[3:0] = {0x%x, 0x%x, 0x%x, 0x%x}\n",
  82                   dig_rc->igi_history[3], dig_rc->igi_history[2],
  83                   dig_rc->igi_history[1], dig_rc->igi_history[0]);
  84         PHYDM_DBG(dm, DBG_DIG, "fa_history[3:0] = {%d, %d, %d, %d}\n",
  85                   dig_rc->fa_history[3], dig_rc->fa_history[2],
  86                   dig_rc->fa_history[1], dig_rc->fa_history[0]);
  87         PHYDM_DBG(dm, DBG_DIG, "igi_bitmap = {%d, %d, %d, %d} = 0x%x\n",
  88                   (u8)((dig_rc->igi_bitmap & BIT(3)) >> 3),
  89                   (u8)((dig_rc->igi_bitmap & BIT(2)) >> 2),
  90                   (u8)((dig_rc->igi_bitmap & BIT(1)) >> 1),
  91                   (u8)(dig_rc->igi_bitmap & BIT(0)),
  92                   dig_rc->igi_bitmap);
  93 }
  94
  95 void phydm_dig_damping_chk(void *dm_void)
  96 {
  97         struct dm_struct *dm = (struct dm_struct *)dm_void;
  98         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
  99         struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
 100         u8 igi_bitmap_4bit = dig_rc->igi_bitmap & 0xf;
 101         u8 diff1 = 0, diff2 = 0;
 102         u32 fa_low_th = dig_t->fa_th[0];
 103         u32 fa_high_th = dig_t->fa_th[1];
 104         u8 fa_pattern_match = 0;
 105         u32 time_tmp;
 106
 107         if (!dm->is_linked)
 108                 return;
 109
 110         PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
 111
 112         /*@== Release Damping ================================================*/
 113         if (dig_rc->damping_limit_en) {
 114                 PHYDM_DBG(dm, DBG_DIG,
 115                           "[Damping Limit!] limit_time=%d, phydm_sys_up_time=%d\n",
 116                           dig_rc->limit_time, dm->phydm_sys_up_time);
 117
 118                 time_tmp = dig_rc->limit_time + DIG_LIMIT_PERIOD;
 119
 120                 if (DIFF_2(dm->rssi_min, dig_rc->limit_rssi) > 3 ||
 121                     time_tmp < dm->phydm_sys_up_time) {
 122                         dig_rc->damping_limit_en = 0;
 123                         PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, limit_rssi=%d\n",
 124                                   dm->rssi_min, dig_rc->limit_rssi);
 125                 }
 126                 return;
 127         }
 128
 129         /*@== Damping Pattern Check===========================================*/
 130         PHYDM_DBG(dm, DBG_DIG, "fa_th{H, L}= {%d,%d}\n", fa_high_th, fa_low_th);
 131
 132         switch (igi_bitmap_4bit) {
 133         case 0x5: /*@4b'0101 ex:down(0x24)->up(0x28)->down(0x24)->up(0x28)*/
 134                 if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
 135                         diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
 136
 137                 if (dig_rc->igi_history[2] > dig_rc->igi_history[3])
 138                         diff2 = dig_rc->igi_history[2] - dig_rc->igi_history[3];
 139
 140                 if (dig_rc->fa_history[0] < fa_low_th &&
 141                     dig_rc->fa_history[1] > fa_high_th &&
 142                     dig_rc->fa_history[2] < fa_low_th &&
 143                     dig_rc->fa_history[3] > fa_high_th) {
 144                     /*@Check each fa element*/
 145                         fa_pattern_match = 1;
 146                 }
 147                 break;
 148         case 0x9: /*@4b'1001 ex:up(0x28)->down(0x26)->down(0x24)->up(0x28)*/
 149                 if (dig_rc->igi_history[0] > dig_rc->igi_history[1])
 150                         diff1 = dig_rc->igi_history[0] - dig_rc->igi_history[1];
 151
 152                 if (dig_rc->igi_history[2] < dig_rc->igi_history[3])
 153                         diff2 = dig_rc->igi_history[3] - dig_rc->igi_history[2];
 154
 155                 if (dig_rc->fa_history[0] < fa_low_th &&
 156                     dig_rc->fa_history[1] > fa_high_th &&
 157                     dig_rc->fa_history[2] > fa_low_th &&
 158                     dig_rc->fa_history[3] < fa_high_th) {
 159                     /*@Check each fa element*/
 160                         fa_pattern_match = 1;
 161                 }
 162                 break;
 163         default:
 164                 break;
 165         }
 166
 167         if (diff1 >= 2 && diff2 >= 2 && fa_pattern_match) {
 168                 dig_rc->damping_limit_en = 1;
 169                 dig_rc->damping_limit_val = dig_rc->igi_history[0];
 170                 dig_rc->limit_time = dm->phydm_sys_up_time;
 171                 dig_rc->limit_rssi = dm->rssi_min;
 172
 173                 PHYDM_DBG(dm, DBG_DIG,
 174                           "[Start damping_limit!] IGI_dyn_min=0x%x, limit_time=%d, limit_rssi=%d\n",
 175                           dig_rc->damping_limit_val,
 176                           dig_rc->limit_time, dig_rc->limit_rssi);
 177         }
 178
 179         PHYDM_DBG(dm, DBG_DIG, "damping_limit=%d\n", dig_rc->damping_limit_en);
 180 }
 181 #endif
 182
 183 boolean
 184 phydm_dig_go_up_check(void *dm_void)
 185 {
 186         struct dm_struct *dm = (struct dm_struct *)dm_void;
 187         struct ccx_info *ccx_info = &dm->dm_ccx_info;
 188         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 189         u8 cur_ig_value = dig_t->cur_ig_value;
 190         u8 max_cover_bond = 0;
 191         u8 rx_gain_range_max = dig_t->rx_gain_range_max;
 192         u8 i = 0, j = 0;
 193         u8 total_nhm_cnt = ccx_info->nhm_rpt_sum;
 194         u32 dig_cnt = 0;
 195         u32 over_dig_cnt = 0;
 196         boolean ret = true;
 197
 198         if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE)
 199                 return ret;
 200
 201         max_cover_bond = DIG_MAX_BALANCE_MODE - dig_t->upcheck_init_val;
 202
 203         if (cur_ig_value < max_cover_bond - 6)
 204                 dig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_0;
 205         else if (cur_ig_value <= DIG_MAX_BALANCE_MODE)
 206                 dig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_1;
 207         else /* @cur_ig_value > DM_DIG_MAX_AP, foolproof */
 208                 dig_t->go_up_chk_lv = DIG_GOUPCHECK_LEVEL_2;
 209
 210         PHYDM_DBG(dm, DBG_DIG, "check_lv = %d, max_cover_bond = 0x%x\n",
 211                   dig_t->go_up_chk_lv, max_cover_bond);
 212
 213         if (total_nhm_cnt == 0)
 214                 return true;
 215
 216         if (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_0) {
 217                 for (i = 3; i <= 11; i++)
 218                         dig_cnt += ccx_info->nhm_result[i];
 219
 220                 if ((dig_t->lv0_ratio_reciprocal * dig_cnt) >= total_nhm_cnt)
 221                         ret = true;
 222                 else
 223                         ret = false;
 224
 225         } else if (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_1) {
 226                 /* search index */
 227                 for (i = 0; i <= 10; i++) {
 228                         if ((max_cover_bond * 2) == ccx_info->nhm_th[i]) {
 229                                 for (j = (i + 1); j <= 11; j++)
 230                                         over_dig_cnt += ccx_info->nhm_result[j];
 231                                 break;
 232                         }
 233                 }
 234
 235                 if (dig_t->lv1_ratio_reciprocal * over_dig_cnt < total_nhm_cnt)
 236                         ret = true;
 237                 else
 238                         ret = false;
 239
 240                 if (!ret) {
 241                         /* update dig_t->rx_gain_range_max */
 242                         if (rx_gain_range_max + 6 >= max_cover_bond)
 243                                 dig_t->rx_gain_range_max =  max_cover_bond - 6;
 244                         else
 245                                 dig_t->rx_gain_range_max =  rx_gain_range_max;
 246
 247                         PHYDM_DBG(dm, DBG_DIG,
 248                                   "Noise pwr over DIG can filter, lock rx_gain_range_max to 0x%x\n",
 249                                   dig_t->rx_gain_range_max);
 250                 }
 251         } else if (dig_t->go_up_chk_lv == DIG_GOUPCHECK_LEVEL_2) {
 252                 /* @cur_ig_value > DM_DIG_MAX_AP, foolproof */
 253                 ret = true;
 254         }
 255
 256         return ret;
 257 }
 258
 259 void phydm_fa_threshold_check(void *dm_void, boolean is_dfs_band)
 260 {
 261         struct dm_struct *dm = (struct dm_struct *)dm_void;
 262         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 263
 264         if (dig_t->is_dbg_fa_th) {
 265                 PHYDM_DBG(dm, DBG_DIG, "Manual Fix FA_th\n");
 266         } else if (dm->is_linked) {
 267                 if (dm->rssi_min < 20) { /*@[PHYDM-252]*/
 268                         dig_t->fa_th[0] = 500;
 269                         dig_t->fa_th[1] = 750;
 270                         dig_t->fa_th[2] = 1000;
 271                 } else if (((dm->rx_tp >> 2) > dm->tx_tp) && /*Test RX TP*/
 272                            (dm->rx_tp < 10) && (dm->rx_tp > 1)) { /*TP=1~10Mb*/
 273                         dig_t->fa_th[0] = 125;
 274                         dig_t->fa_th[1] = 250;
 275                         dig_t->fa_th[2] = 500;
 276                 } else {
 277                         dig_t->fa_th[0] = 250;
 278                         dig_t->fa_th[1] = 500;
 279                         dig_t->fa_th[2] = 750;
 280                 }
 281         } else {
 282                 if (is_dfs_band) { /* @For DFS band and no link */
 283
 284                         dig_t->fa_th[0] = 250;
 285                         dig_t->fa_th[1] = 1000;
 286                         dig_t->fa_th[2] = 2000;
 287                 } else {
 288                         dig_t->fa_th[0] = 2000;
 289                         dig_t->fa_th[1] = 4000;
 290                         dig_t->fa_th[2] = 5000;
 291                 }
 292         }
 293
 294         PHYDM_DBG(dm, DBG_DIG, "FA_th={%d,%d,%d}\n", dig_t->fa_th[0],
 295                   dig_t->fa_th[1], dig_t->fa_th[2]);
 296 }
 297
 298 void phydm_set_big_jump_step(void *dm_void, u8 curr_igi)
 299 {
 300 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
 301         struct dm_struct *dm = (struct dm_struct *)dm_void;
 302         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 303         u8 step1[8] = {24, 30, 40, 50, 60, 70, 80, 90};
 304         u8 big_jump_lmt = dig_t->big_jump_lmt[dig_t->agc_table_idx];
 305         u8 i;
 306
 307         if (dig_t->enable_adjust_big_jump == 0)
 308                 return;
 309
 310         for (i = 0; i <= dig_t->big_jump_step1; i++) {
 311                 if ((curr_igi + step1[i]) > big_jump_lmt) {
 312                         if (i != 0)
 313                                 i = i - 1;
 314                         break;
 315                 } else if (i == dig_t->big_jump_step1) {
 316                         break;
 317                 }
 318         }
 319         if (dm->support_ic_type & ODM_RTL8822B)
 320                 odm_set_bb_reg(dm, R_0x8c8, 0xe, i);
 321         else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
 322                 odm_set_bb_reg(dm, ODM_REG_BB_AGC_SET_2_11N, 0xe, i);
 323
 324         PHYDM_DBG(dm, DBG_DIG, "Bigjump = %d (ori = 0x%x), LMT=0x%x\n", i,
 325                   dig_t->big_jump_step1, big_jump_lmt);
 326 #endif
 327 }
 328
 329 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
 330 void phydm_write_dig_reg_jgr3(void *dm_void, u8 igi)
 331 {
 332         struct dm_struct *dm = (struct dm_struct *)dm_void;
 333         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 334
 335         PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
 336
 337         /* Set IGI value */
 338         if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
 339                 return;
 340
 341         odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC, igi);
 342
 343         #if (defined(PHYDM_COMPILE_ABOVE_2SS))
 344         if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
 345                 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3, igi);
 346         #endif
 347
 348         #if (defined(PHYDM_COMPILE_ABOVE_4SS))
 349         if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
 350                 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3, igi);
 351                 odm_set_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3, igi);
 352         }
 353         #endif
 354 }
 355
 356 u8 phydm_get_igi_reg_val_jgr3(void *dm_void, enum bb_path path)
 357 {
 358         struct dm_struct *dm = (struct dm_struct *)dm_void;
 359         u32 val = 0;
 360
 361         PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
 362
 363         /* Set IGI value */
 364         if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
 365                 return (u8)val;
 366
 367         if (path == BB_PATH_A)
 368                 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_11AC);
 369         else if (path == BB_PATH_B)
 370                 #if (defined(PHYDM_COMPILE_ABOVE_2SS))
 371                 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_B_11AC3);
 372                 #else
 373                 ;
 374                 #endif
 375         else if (path == BB_PATH_C)
 376                 #if (defined(PHYDM_COMPILE_ABOVE_3SS))
 377                 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_C_11AC3);
 378                 #else
 379                 ;
 380                 #endif
 381         else if (path == BB_PATH_D)
 382                 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
 383                 val = odm_get_bb_reg(dm, R_0x1d70, ODM_BIT_IGI_D_11AC3);
 384                 #else
 385                 ;
 386                 #endif
 387
 388         return (u8)val;
 389 }
 390
 391 void phydm_fa_cnt_statistics_jgr3(void *dm_void)
 392 {
 393         struct dm_struct *dm = (struct dm_struct *)dm_void;
 394         struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
 395         u32 ret_value = 0;
 396         u32 cck_enable = 0;
 397         u16 ofdm_tx_counter = 0;
 398         u16 cck_tx_counter = 0;
 399
 400         if (!(dm->support_ic_type & ODM_IC_JGR3_SERIES))
 401                 return;
 402
 403         ofdm_tx_counter = (u16)odm_get_bb_reg(dm, R_0x2de0, MASKLWORD);
 404         cck_tx_counter = (u16)odm_get_bb_reg(dm, R_0x2de4, MASKLWORD);
 405
 406         ret_value = odm_get_bb_reg(dm, R_0x2d20, MASKDWORD);
 407         fa_t->cnt_fast_fsync = (ret_value & 0xffff);
 408         fa_t->cnt_sb_search_fail = ((ret_value & 0xffff0000) >> 16);
 409
 410         ret_value = odm_get_bb_reg(dm, R_0x2d04, MASKDWORD);
 411         fa_t->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
 412
 413         ret_value = odm_get_bb_reg(dm, R_0x2d08, MASKDWORD);
 414         fa_t->cnt_rate_illegal = (ret_value & 0xffff);
 415         fa_t->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
 416
 417         ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
 418         fa_t->cnt_mcs_fail = (ret_value & 0xffff);
 419
 420         /* read OFDM FA counter */
 421         fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0x2d00, MASKLWORD);
 422
 423         /* Read CCK FA counter */
 424         fa_t->cnt_cck_fail = odm_get_bb_reg(dm, R_0x1a5c, MASKLWORD);
 425
 426         /* read CCK/OFDM CCA counter */
 427         ret_value = odm_get_bb_reg(dm, R_0x2c08, MASKDWORD);
 428         fa_t->cnt_ofdm_cca = ((ret_value & 0xffff0000) >> 16);
 429         fa_t->cnt_cck_cca = ret_value & 0xffff;
 430
 431         /* read CCK CRC32 counter */
 432         ret_value = odm_get_bb_reg(dm, R_0x2c04, MASKDWORD);
 433         fa_t->cnt_cck_crc32_error = ((ret_value & 0xffff0000) >> 16);
 434         fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
 435
 436         /* read OFDM CRC32 counter */
 437         ret_value = odm_get_bb_reg(dm, R_0x2c14, MASKDWORD);
 438         fa_t->cnt_ofdm_crc32_error = ((ret_value & 0xffff0000) >> 16);
 439         fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
 440
 441         /* read HT CRC32 counter */
 442         ret_value = odm_get_bb_reg(dm, R_0x2c10, MASKDWORD);
 443         fa_t->cnt_ht_crc32_error = ((ret_value & 0xffff0000) >> 16);
 444         fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
 445
 446         /* @for VHT part */
 447         if (dm->support_ic_type & ODM_RTL8822C) {
 448                 /* read VHT CRC32 counter */
 449                 ret_value = odm_get_bb_reg(dm, R_0x2c0c, MASKDWORD);
 450                 fa_t->cnt_vht_crc32_error = ((ret_value & 0xffff0000) >> 16);
 451                 fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
 452
 453                 ret_value = odm_get_bb_reg(dm, R_0x2d10, MASKDWORD);
 454                 fa_t->cnt_mcs_fail_vht = ((ret_value & 0xffff0000) >> 16);
 455
 456                 ret_value = odm_get_bb_reg(dm, R_0x2d0c, MASKDWORD);
 457                 fa_t->cnt_crc8_fail_vht = ret_value & 0xffff +
 458                                           ((ret_value & 0xffff0000) >> 16);
 459         } else {
 460                 fa_t->cnt_vht_crc32_error = 0;
 461                 fa_t->cnt_vht_crc32_ok = 0;
 462                 fa_t->cnt_mcs_fail_vht = 0;
 463                 fa_t->cnt_crc8_fail_vht = 0;
 464         }
 465
 466         cck_enable = odm_get_bb_reg(dm, R_0x1c3c, BIT(1)); /* @98f 1C3c[1] */
 467         if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
 468                 fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail
 469                                 - ofdm_tx_counter;
 470                 fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
 471                 PHYDM_DBG(dm, DBG_FA_CNT, "ac3 OFDM FA = %d, CCK FA = %d\n",
 472                           fa_t->cnt_ofdm_fail - ofdm_tx_counter,
 473                           fa_t->cnt_cck_fail);
 474         } else {
 475                 fa_t->cnt_all = fa_t->cnt_ofdm_fail - ofdm_tx_counter;
 476                 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
 477                 PHYDM_DBG(dm, DBG_FA_CNT, "ac3 CCK disable OFDM FA = %d\n",
 478                           fa_t->cnt_ofdm_fail - ofdm_tx_counter);
 479         }
 480
 481         PHYDM_DBG(dm, DBG_FA_CNT,
 482                   "ac3 [OFDM FA Detail] Parity_fail=((%d)), Rate_Illegal=((%d)), CRC8_fail=((%d)), Mcs_fail=((%d)), Fast_Fsync=((%d)), SBD_fail=((%d))\n",
 483                   fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
 484                   fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail, fa_t->cnt_fast_fsync,
 485                   fa_t->cnt_sb_search_fail);
 486 }
 487
 488 #endif
 489
 490 void phydm_write_dig_reg(void *dm_void, u8 igi)
 491 {
 492         struct dm_struct *dm = (struct dm_struct *)dm_void;
 493
 494         PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
 495
 496         odm_set_bb_reg(dm, ODM_REG(IGI_A, dm), ODM_BIT(IGI, dm), igi);
 497
 498         #if (defined(PHYDM_COMPILE_ABOVE_2SS))
 499         if (dm->support_ic_type & PHYDM_IC_ABOVE_2SS)
 500                 odm_set_bb_reg(dm, ODM_REG(IGI_B, dm), ODM_BIT(IGI, dm), igi);
 501         #endif
 502
 503         #if (defined(PHYDM_COMPILE_ABOVE_4SS))
 504         if (dm->support_ic_type & PHYDM_IC_ABOVE_4SS) {
 505                 odm_set_bb_reg(dm, ODM_REG(IGI_C, dm), ODM_BIT(IGI, dm), igi);
 506                 odm_set_bb_reg(dm, ODM_REG(IGI_D, dm), ODM_BIT(IGI, dm), igi);
 507         }
 508         #endif
 509 }
 510
 511 void odm_write_dig(void *dm_void, u8 new_igi)
 512 {
 513         struct dm_struct *dm = (struct dm_struct *)dm_void;
 514         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 515         struct phydm_adaptivity_struct *adaptivity = &dm->adaptivity;
 516
 517         PHYDM_DBG(dm, DBG_DIG, "%s===>\n", __func__);
 518
 519         /* @1 Check IGI by upper bound */
 520         if (adaptivity->igi_lmt_en &&
 521             new_igi > adaptivity->adapt_igi_up && dm->is_linked) {
 522                 new_igi = adaptivity->adapt_igi_up;
 523
 524                 PHYDM_DBG(dm, DBG_DIG, "Force Adaptivity Up-bound=((0x%x))\n",
 525                           new_igi);
 526         }
 527
 528         #if (RTL8192F_SUPPORT)
 529         if ((dm->support_ic_type & ODM_RTL8192F) &&
 530             dm->cut_version == ODM_CUT_A &&
 531             new_igi > 0x38) {
 532                 new_igi = 0x38;
 533                 PHYDM_DBG(dm, DBG_DIG,
 534                           "Force 92F Adaptivity Up-bound=((0x%x))\n", new_igi);
 535         }
 536         #endif
 537
 538         if (dig_t->cur_ig_value != new_igi) {
 539                 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
 540                 /* @Modify big jump step for 8822B and 8197F */
 541                 if (dm->support_ic_type &
 542                     (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F))
 543                         phydm_set_big_jump_step(dm, new_igi);
 544                 #endif
 545
 546                 #if (ODM_PHY_STATUS_NEW_TYPE_SUPPORT)
 547                 /* Set IGI value of CCK for new CCK AGC */
 548                 if (dm->cck_new_agc &&
 549                     (dm->support_ic_type & PHYSTS_2ND_TYPE_IC))
 550                         odm_set_bb_reg(dm, R_0xa0c, 0x3f00, (new_igi >> 1));
 551                 #endif
 552
 553                 /*@Add by YuChen for USB IO too slow issue*/
 554                 if (!(dm->support_ic_type & ODM_IC_PWDB_EDCCA)) {
 555                         if (dm->support_ability & ODM_BB_ADAPTIVITY &&
 556                             new_igi < dig_t->cur_ig_value) {
 557                                 dig_t->cur_ig_value = new_igi;
 558                                 phydm_adaptivity(dm);
 559                         }
 560                 } else {
 561                         if (dm->support_ability & ODM_BB_ADAPTIVITY &&
 562                             new_igi > dig_t->cur_ig_value) {
 563                                 dig_t->cur_ig_value = new_igi;
 564                                 phydm_adaptivity(dm);
 565                         }
 566                 }
 567
 568                 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
 569                 if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
 570                         phydm_write_dig_reg_jgr3(dm, new_igi);
 571                 else
 572                 #endif
 573                         phydm_write_dig_reg(dm, new_igi);
 574
 575                 dig_t->cur_ig_value = new_igi;
 576         }
 577
 578         PHYDM_DBG(dm, DBG_DIG, "New_igi=((0x%x))\n\n", new_igi);
 579 }
 580
 581 u8 phydm_get_igi_reg_val(void *dm_void, enum bb_path path)
 582 {
 583         struct dm_struct *dm = (struct dm_struct *)dm_void;
 584         u32 val = 0;
 585         u32 bit_map = ODM_BIT(IGI, dm);
 586
 587         switch (path) {
 588         case BB_PATH_A:
 589                 val = odm_get_bb_reg(dm, ODM_REG(IGI_A, dm), bit_map);
 590                 break;
 591         #if (defined(PHYDM_COMPILE_ABOVE_2SS))
 592         case BB_PATH_B:
 593                 val = odm_get_bb_reg(dm, ODM_REG(IGI_B, dm), bit_map);
 594                 break;
 595         #endif
 596
 597         #if (defined(PHYDM_COMPILE_ABOVE_3SS))
 598         case BB_PATH_C:
 599                 val = odm_get_bb_reg(dm, ODM_REG(IGI_C, dm), bit_map);
 600                 break;
 601         #endif
 602
 603         #if (defined(PHYDM_COMPILE_ABOVE_4SS))
 604         case BB_PATH_D:
 605                 val = odm_get_bb_reg(dm, ODM_REG(IGI_D, dm), bit_map);
 606                 break;
 607         #endif
 608
 609         default:
 610                 break;
 611         }
 612
 613         return (u8)val;
 614 }
 615
 616 u8 phydm_get_igi(void *dm_void, enum bb_path path)
 617 {
 618         struct dm_struct *dm = (struct dm_struct *)dm_void;
 619         u8 val;
 620
 621         #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
 622         if (dm->support_ic_type & ODM_IC_JGR3_SERIES)
 623                 val = phydm_get_igi_reg_val_jgr3(dm, path);
 624         else
 625         #endif
 626                 val = phydm_get_igi_reg_val(dm, path);
 627
 628         return val;
 629 }
 630
 631 void phydm_set_dig_val(void *dm_void, u32 *val_buf, u8 val_len)
 632 {
 633         struct dm_struct *dm = (struct dm_struct *)dm_void;
 634
 635         if (val_len != 1) {
 636                 PHYDM_DBG(dm, ODM_COMP_API, "[Error][DIG]Need val_len=1\n");
 637                 return;
 638         }
 639
 640         odm_write_dig(dm, (u8)(*val_buf));
 641 }
 642
 643 void odm_pause_dig(void *dm_void, enum phydm_pause_type type,
 644                    enum phydm_pause_level lv, u8 igi_input)
 645 {
 646         struct dm_struct *dm = (struct dm_struct *)dm_void;
 647         u8 rpt = false;
 648         u32 igi = (u32)igi_input;
 649
 650         PHYDM_DBG(dm, DBG_DIG, "[%s]type=%d, LV=%d, igi=0x%x\n", __func__, type,
 651                   lv, igi);
 652
 653         switch (type) {
 654         case PHYDM_PAUSE:
 655         case PHYDM_PAUSE_NO_SET: {
 656                 rpt = phydm_pause_func(dm, F00_DIG, PHYDM_PAUSE, lv, 1, &igi);
 657                 break;
 658         }
 659
 660         case PHYDM_RESUME: {
 661                 rpt = phydm_pause_func(dm, F00_DIG, PHYDM_RESUME, lv, 1, &igi);
 662                 break;
 663         }
 664         default:
 665                 PHYDM_DBG(dm, DBG_DIG, "Wrong type\n");
 666                 break;
 667         }
 668
 669         PHYDM_DBG(dm, DBG_DIG, "pause_result=%d\n", rpt);
 670 }
 671
 672 boolean
 673 phydm_dig_abort(void *dm_void)
 674 {
 675         struct dm_struct *dm = (struct dm_struct *)dm_void;
 676 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
 677         void *adapter = dm->adapter;
 678 #endif
 679
 680         /* support_ability */
 681         if ((!(dm->support_ability & ODM_BB_FA_CNT)) ||
 682             (!(dm->support_ability & ODM_BB_DIG)) ||
 683             *dm->is_scan_in_process) {
 684                 PHYDM_DBG(dm, DBG_DIG, "Not Support\n");
 685                 return true;
 686         }
 687
 688         if (dm->pause_ability & ODM_BB_DIG) {
 689                 PHYDM_DBG(dm, DBG_DIG, "Return: Pause DIG in LV=%d\n",
 690                           dm->pause_lv_table.lv_dig);
 691                 return true;
 692         }
 693
 694 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 695 #if OS_WIN_FROM_WIN7(OS_VERSION)
 696         if (IsAPModeExist(adapter) && ((PADAPTER)(adapter))->bInHctTest) {
 697                 PHYDM_DBG(dm, DBG_DIG, " Return: Is AP mode or In HCT Test\n");
 698                 return true;
 699         }
 700 #endif
 701 #endif
 702
 703         return false;
 704 }
 705
 706 void phydm_dig_init(void *dm_void)
 707 {
 708         struct dm_struct *dm = (struct dm_struct *)dm_void;
 709         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 710 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
 711         struct phydm_fa_struct *false_alm_cnt = &dm->false_alm_cnt;
 712 #endif
 713         u32 ret_value = 0;
 714         u8 i;
 715
 716         dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
 717         dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
 718         dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
 719
 720         dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
 721
 722         dig_t->is_media_connect = false;
 723
 724         dig_t->fa_th[0] = 250;
 725         dig_t->fa_th[1] = 500;
 726         dig_t->fa_th[2] = 750;
 727         dig_t->is_dbg_fa_th = false;
 728 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
 729         /* @For RTL8881A */
 730         false_alm_cnt->cnt_ofdm_fail_pre = 0;
 731 #endif
 732
 733         dig_t->rx_gain_range_max = DIG_MAX_BALANCE_MODE;
 734         dig_t->rx_gain_range_min = dig_t->cur_ig_value;
 735
 736 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
 737         dig_t->enable_adjust_big_jump = 1;
 738         if (dm->support_ic_type & ODM_RTL8822B)
 739                 ret_value = odm_get_bb_reg(dm, R_0x8c8, MASKLWORD);
 740         else if (dm->support_ic_type & (ODM_RTL8197F | ODM_RTL8192F))
 741                 ret_value = odm_get_bb_reg(dm, R_0xc74, MASKLWORD);
 742
 743         dig_t->big_jump_step1 = (u8)(ret_value & 0xe) >> 1;
 744         dig_t->big_jump_step2 = (u8)(ret_value & 0x30) >> 4;
 745         dig_t->big_jump_step3 = (u8)(ret_value & 0xc0) >> 6;
 746
 747         if (dm->support_ic_type &
 748             (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F)) {
 749                 for (i = 0; i < sizeof(dig_t->big_jump_lmt); i++) {
 750                         if (dig_t->big_jump_lmt[i] == 0)
 751                                 dig_t->big_jump_lmt[i] = 0x64;
 752                                 /* Set -10dBm as default value */
 753                 }
 754         }
 755 #endif
 756
 757 #ifdef PHYDM_TDMA_DIG_SUPPORT
 758         dm->original_dig_restore = true;
 759 #endif
 760 #ifdef CFG_DIG_DAMPING_CHK
 761         phydm_dig_recorder_reset(dm);
 762         dig_t->dig_dl_en = 1;
 763 #endif
 764 }
 765
 766 void phydm_dig_abs_boundary_decision(struct dm_struct *dm, boolean is_dfs_band)
 767 {
 768         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 769
 770         if (!dm->is_linked) {
 771                 dig_t->dm_dig_max = DIG_MAX_COVERAGR;
 772                 dig_t->dm_dig_min = DIG_MIN_COVERAGE;
 773         } else if (is_dfs_band) {
 774                 if (*dm->band_width == CHANNEL_WIDTH_20)
 775                         dig_t->dm_dig_min = DIG_MIN_DFS + 2;
 776                 else
 777                         dig_t->dm_dig_min = DIG_MIN_DFS;
 778
 779                 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
 780                 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
 781         } else {
 782                 if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
 783                 /*service > 2 devices*/
 784                         dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
 785                         #if (DIG_HW == 1)
 786                         dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
 787                         #else
 788                         dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
 789                         #endif
 790                 } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
 791                 /*service 1 devices*/
 792                         dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
 793                         dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
 794                 }
 795
 796                 if (dm->support_ic_type &
 797                     (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
 798                         dig_t->dm_dig_min = 0x1c;
 799                 else if (dm->support_ic_type & ODM_RTL8197F)
 800                         dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
 801                 else
 802                         dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
 803         }
 804
 805         PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
 806                   dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
 807 }
 808
 809 void phydm_dig_dym_boundary_decision(struct dm_struct *dm)
 810 {
 811         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 812 #ifdef CFG_DIG_DAMPING_CHK
 813         struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
 814 #endif
 815         u8 offset = 15, tmp_max = 0;
 816         u8 max_of_rssi_min = 0;
 817
 818         PHYDM_DBG(dm, DBG_DIG, "%s ======>\n", __func__);
 819
 820         if (!dm->is_linked) {
 821                 /*@if no link, always stay at lower bound*/
 822                 dig_t->rx_gain_range_max = dig_t->dig_max_of_min;
 823                 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
 824
 825                 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
 826                           dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
 827                 return;
 828         }
 829
 830         PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n", dm->rssi_min, offset);
 831
 832         /* @DIG lower bound */
 833         if (dm->rssi_min > dig_t->dig_max_of_min)
 834                 dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
 835         else if (dm->rssi_min < dig_t->dm_dig_min)
 836                 dig_t->rx_gain_range_min = dig_t->dm_dig_min;
 837         else
 838                 dig_t->rx_gain_range_min = dm->rssi_min;
 839
 840 #ifdef CFG_DIG_DAMPING_CHK
 841         /*@Limit Dyn min by damping*/
 842         if (dig_t->dig_dl_en &&
 843             dig_rc->damping_limit_en &&
 844             dig_t->rx_gain_range_min < dig_rc->damping_limit_val) {
 845                 PHYDM_DBG(dm, DBG_DIG,
 846                           "[Limit by Damping] Dig_dyn_min=0x%x -> 0x%x\n",
 847                           dig_t->rx_gain_range_min, dig_rc->damping_limit_val);
 848
 849                 dig_t->rx_gain_range_min = dig_rc->damping_limit_val;
 850         }
 851 #endif
 852
 853         /* @DIG upper bound */
 854         tmp_max = dig_t->rx_gain_range_min + offset;
 855         if (dig_t->rx_gain_range_min != dm->rssi_min) {
 856                 max_of_rssi_min = dm->rssi_min + offset;
 857                 if (tmp_max > max_of_rssi_min)
 858                         tmp_max = max_of_rssi_min;
 859         }
 860
 861         if (tmp_max > dig_t->dm_dig_max)
 862                 dig_t->rx_gain_range_max = dig_t->dm_dig_max;
 863         else if (tmp_max < dig_t->dm_dig_min)
 864                 dig_t->rx_gain_range_max = dig_t->dm_dig_min;
 865         else
 866                 dig_t->rx_gain_range_max = tmp_max;
 867
 868         #ifdef CONFIG_PHYDM_ANTENNA_DIVERSITY
 869         /* @1 Force Lower Bound for AntDiv */
 870         if (!dm->is_one_entry_only &&
 871             (dm->support_ability & ODM_BB_ANT_DIV) &&
 872             (dm->ant_div_type == CG_TRX_HW_ANTDIV ||
 873              dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
 874                 if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
 875                         dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
 876                 else
 877                         dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
 878
 879                 PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
 880                           dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
 881         }
 882         #endif
 883
 884         PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
 885                   dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
 886 }
 887
 888 void phydm_dig_abnormal_case(struct dm_struct *dm)
 889 {
 890         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 891
 892         /* @Abnormal lower bound case */
 893         if (dig_t->rx_gain_range_min > dig_t->rx_gain_range_max)
 894                 dig_t->rx_gain_range_min = dig_t->rx_gain_range_max;
 895
 896         PHYDM_DBG(dm, DBG_DIG, "Abnoraml checked {Max, Min}={0x%x, 0x%x}\n",
 897                   dig_t->rx_gain_range_max, dig_t->rx_gain_range_min);
 898 }
 899
 900 u8 phydm_new_igi_by_fa(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *step_size)
 901 {
 902         boolean dig_go_up_check = true;
 903         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 904
 905 #if 0
 906         /*@dig_go_up_check = phydm_dig_go_up_check(dm);*/
 907 #endif
 908
 909         if (fa_cnt > dig_t->fa_th[2] && dig_go_up_check)
 910                 igi = igi + step_size[0];
 911         else if ((fa_cnt > dig_t->fa_th[1]) && dig_go_up_check)
 912                 igi = igi + step_size[1];
 913         else if (fa_cnt < dig_t->fa_th[0])
 914                 igi = igi - step_size[2];
 915
 916         return igi;
 917 }
 918
 919 u8 phydm_get_new_igi(struct dm_struct *dm, u8 igi, u32 fa_cnt,
 920                      boolean is_dfs_band)
 921 {
 922         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
 923         u8 step[3] = {0};
 924         boolean first_connect = false, first_dis_connect = false;
 925
 926         first_connect = (dm->is_linked) && !dig_t->is_media_connect;
 927         first_dis_connect = (!dm->is_linked) && dig_t->is_media_connect;
 928
 929         if (dm->is_linked) {
 930                 if (dm->pre_rssi_min <= dm->rssi_min) {
 931                         PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
 932                         step[0] = 2;
 933                         step[1] = 1;
 934                         step[2] = 2;
 935                 } else {
 936                         step[0] = 4;
 937                         step[1] = 2;
 938                         step[2] = 2;
 939                 }
 940         } else {
 941                 step[0] = 2;
 942                 step[1] = 1;
 943                 step[2] = 2;
 944         }
 945
 946         PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
 947                   step[0]);
 948
 949         if (first_connect) {
 950                 if (is_dfs_band) {
 951                         if (dm->rssi_min > DIG_MAX_DFS)
 952                                 igi = DIG_MAX_DFS;
 953                         else
 954                                 igi = dm->rssi_min;
 955                         PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
 956                                   dig_t->rx_gain_range_max);
 957                 } else {
 958                         igi = dig_t->rx_gain_range_min;
 959                 }
 960
 961                 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 962                 #if (RTL8812A_SUPPORT)
 963                 if (dm->support_ic_type == ODM_RTL8812)
 964                         odm_config_bb_with_header_file(dm,
 965                                                        CONFIG_BB_AGC_TAB_DIFF);
 966                 #endif
 967                 #endif
 968                 PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
 969         } else if (dm->is_linked) {
 970                 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n");
 971                 /* @4 Abnormal # beacon case */
 972                 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
 973                 if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
 974                     fa_cnt < DM_DIG_FA_TH1 && dm->bsta_state &&
 975                     dm->support_ic_type != ODM_RTL8723D) {
 976                         dig_t->rx_gain_range_min = 0x1c;
 977                         igi = dig_t->rx_gain_range_min;
 978                         PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n",
 979                                   dm->phy_dbg_info.num_qry_beacon_pkt, igi);
 980                 } else {
 981                         igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
 982                 }
 983                 #else
 984                 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
 985                 #endif
 986         } else {
 987                 /* @2 Before link */
 988                 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
 989
 990                 if (first_dis_connect) {
 991                         igi = dig_t->dm_dig_min;
 992                         PHYDM_DBG(dm, DBG_DIG,
 993                                   "First disconnect:foce IGI to lower bound\n");
 994                 } else {
 995                         PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
 996                                   igi, fa_cnt);
 997
 998                         igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
 999                 }
1000         }
1001
1002         /*@Check IGI by dyn-upper/lower bound */
1003         if (igi < dig_t->rx_gain_range_min)
1004                 igi = dig_t->rx_gain_range_min;
1005
1006         if (igi > dig_t->rx_gain_range_max)
1007                 igi = dig_t->rx_gain_range_max;
1008
1009         PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
1010                   fa_cnt, dig_t->cur_ig_value, igi);
1011
1012         return igi;
1013 }
1014
1015 boolean phydm_dig_dfs_mode_en(void *dm_void)
1016 {
1017         struct dm_struct *dm = (struct dm_struct *)dm_void;
1018         boolean dfs_mode_en = false;
1019
1020         /* @Modify lower bound for DFS band */
1021         if (dm->is_dfs_band) {
1022                 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
1023                 dfs_mode_en = true;
1024                 #else
1025                 if (phydm_dfs_master_enabled(dm))
1026                         dfs_mode_en = true;
1027                 #endif
1028                 PHYDM_DBG(dm, DBG_DIG, "In DFS band\n");
1029         }
1030         return dfs_mode_en;
1031 }
1032
1033 void phydm_dig(void *dm_void)
1034 {
1035         struct dm_struct *dm = (struct dm_struct *)dm_void;
1036         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1037         struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
1038 #ifdef PHYDM_TDMA_DIG_SUPPORT
1039         struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
1040 #endif
1041         boolean first_connect, first_disconnect;
1042         u8 igi = dig_t->cur_ig_value;
1043         u8 new_igi = 0x20;
1044         u32 fa_cnt = falm_cnt->cnt_all;
1045         boolean dfs_mode_en = false;
1046
1047 #ifdef PHYDM_TDMA_DIG_SUPPORT
1048         if (!(dm->original_dig_restore)) {
1049                 if (dig_t->cur_ig_value_tdma == 0)
1050                         dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
1051
1052                 igi = dig_t->cur_ig_value_tdma;
1053                 fa_cnt = falm_cnt_acc->cnt_all_1sec;
1054         }
1055 #endif
1056
1057         if (phydm_dig_abort(dm)) {
1058                 dig_t->cur_ig_value = phydm_get_igi(dm, BB_PATH_A);
1059                 return;
1060         }
1061
1062         PHYDM_DBG(dm, DBG_DIG, "%s Start===>\n", __func__);
1063
1064         /* @1 Update status */
1065         first_connect = (dm->is_linked) && !dig_t->is_media_connect;
1066         first_disconnect = (!dm->is_linked) && dig_t->is_media_connect;
1067
1068         PHYDM_DBG(dm, DBG_DIG,
1069                   "is_linked=%d, RSSI=%d, 1stConnect=%d, 1stDisconnect=%d\n",
1070                   dm->is_linked, dm->rssi_min, first_connect, first_disconnect);
1071
1072         PHYDM_DBG(dm, DBG_DIG, "DIG ((%s)) mode\n",
1073                   (*dm->bb_op_mode ? "Balance" : "Performance"));
1074
1075         /*@DFS mode enable check*/
1076         dfs_mode_en = phydm_dig_dfs_mode_en(dm);
1077
1078 #ifdef CFG_DIG_DAMPING_CHK
1079         /*Record IGI History*/
1080         phydm_dig_recorder(dm, first_connect, igi, fa_cnt);
1081
1082         /*@DIG Damping Check*/
1083         phydm_dig_damping_chk(dm);
1084 #endif
1085
1086         /*@Absolute Boundary Decision */
1087         phydm_dig_abs_boundary_decision(dm, dfs_mode_en);
1088
1089         /*@Dynamic Boundary Decision*/
1090         phydm_dig_dym_boundary_decision(dm);
1091
1092         /*@Abnormal case check*/
1093         phydm_dig_abnormal_case(dm);
1094
1095         /*@FA threshold decision */
1096         phydm_fa_threshold_check(dm, dfs_mode_en);
1097
1098         /*Select new IGI by FA */
1099         new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
1100
1101         /* @1 Update status */
1102         #ifdef PHYDM_TDMA_DIG_SUPPORT
1103         if (!(dm->original_dig_restore)) {
1104                 dig_t->cur_ig_value_tdma = new_igi;
1105                 /*@It is possible fa_acc_1sec_tsf >= */
1106                 /*@1sec while tdma_dig_state == 0*/
1107                 if (dig_t->tdma_dig_state != 0)
1108                         odm_write_dig(dm, dig_t->cur_ig_value_tdma);
1109         } else
1110         #endif
1111                 odm_write_dig(dm, new_igi);
1112
1113         dig_t->is_media_connect = dm->is_linked;
1114 }
1115
1116 void phydm_dig_lps_32k(void *dm_void)
1117 {
1118         struct dm_struct *dm = (struct dm_struct *)dm_void;
1119         u8 current_igi = dm->rssi_min;
1120
1121         odm_write_dig(dm, current_igi);
1122 }
1123
1124 void phydm_dig_by_rssi_lps(void *dm_void)
1125 {
1126 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1127         struct dm_struct *dm = (struct dm_struct *)dm_void;
1128         struct phydm_fa_struct *falm_cnt;
1129
1130         u8 rssi_lower = DIG_MIN_LPS; /* @0x1E or 0x1C */
1131         u8 current_igi = dm->rssi_min;
1132
1133         falm_cnt = &dm->false_alm_cnt;
1134         if (phydm_dig_abort(dm))
1135                 return;
1136
1137         current_igi = current_igi + RSSI_OFFSET_DIG_LPS;
1138         PHYDM_DBG(dm, DBG_DIG, "%s==>\n", __func__);
1139
1140         /* Using FW PS mode to make IGI */
1141         /* @Adjust by  FA in LPS MODE */
1142         if (falm_cnt->cnt_all > DM_DIG_FA_TH2_LPS)
1143                 current_igi = current_igi + 4;
1144         else if (falm_cnt->cnt_all > DM_DIG_FA_TH1_LPS)
1145                 current_igi = current_igi + 2;
1146         else if (falm_cnt->cnt_all < DM_DIG_FA_TH0_LPS)
1147                 current_igi = current_igi - 2;
1148
1149         /* @Lower bound checking */
1150
1151         /* RSSI Lower bound check */
1152         if ((dm->rssi_min - 10) > DIG_MIN_LPS)
1153                 rssi_lower = (dm->rssi_min - 10);
1154         else
1155                 rssi_lower = DIG_MIN_LPS;
1156
1157         /* Upper and Lower Bound checking */
1158         if (current_igi > DIG_MAX_LPS)
1159                 current_igi = DIG_MAX_LPS;
1160         else if (current_igi < rssi_lower)
1161                 current_igi = rssi_lower;
1162
1163         PHYDM_DBG(dm, DBG_DIG, "fa_cnt_all=%d, rssi_min=%d, curr_igi=0x%x\n",
1164                   falm_cnt->cnt_all, dm->rssi_min, current_igi);
1165         odm_write_dig(dm, current_igi);
1166 #endif
1167 }
1168
1169 /* @3============================================================
1170  * 3 FASLE ALARM CHECK
1171  * 3============================================================
1172  */
1173 void phydm_false_alarm_counter_reg_reset(void *dm_void)
1174 {
1175         struct dm_struct *dm = (struct dm_struct *)dm_void;
1176         struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
1177 #ifdef PHYDM_TDMA_DIG_SUPPORT
1178         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1179         struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
1180 #endif
1181         u32 false_alm_cnt;
1182
1183 #ifdef PHYDM_TDMA_DIG_SUPPORT
1184         if (!(dm->original_dig_restore)) {
1185                 if (dig_t->cur_ig_value_tdma == 0)
1186                         dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
1187
1188                 false_alm_cnt = falm_cnt_acc->cnt_all_1sec;
1189         } else
1190 #endif
1191         {
1192                 false_alm_cnt = falm_cnt->cnt_all;
1193         }
1194
1195 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1196         if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1197                 /* reset CCK FA counter */
1198                 odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 0);
1199                 odm_set_bb_reg(dm, R_0x1a2c, BIT(15) | BIT(14), 2);
1200
1201                 /* reset CCK CCA counter */
1202                 odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 0);
1203                 odm_set_bb_reg(dm, R_0x1a2c, BIT(13) | BIT(12), 2);
1204
1205                 /* reset OFDM CCA counter, OFDM FA counter*/
1206                 odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 1);
1207                 odm_set_bb_reg(dm, R_0x1eb4, BIT(25), 0);
1208         }
1209 #endif
1210 #if (ODM_IC_11N_SERIES_SUPPORT)
1211         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1212                 /*reset false alarm counter registers*/
1213                 odm_set_bb_reg(dm, R_0xc0c, BIT(31), 1);
1214                 odm_set_bb_reg(dm, R_0xc0c, BIT(31), 0);
1215                 odm_set_bb_reg(dm, R_0xd00, BIT(27), 1);
1216                 odm_set_bb_reg(dm, R_0xd00, BIT(27), 0);
1217
1218                 /*update ofdm counter*/
1219                 /*update page C counter*/
1220                 odm_set_bb_reg(dm, R_0xc00, BIT(31), 0);
1221                 /*update page D counter*/
1222                 odm_set_bb_reg(dm, R_0xd00, BIT(31), 0);
1223
1224                 /*reset CCK CCA counter*/
1225                 odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 0);
1226                 odm_set_bb_reg(dm, R_0xa2c, BIT(13) | BIT(12), 2);
1227
1228                 /*reset CCK FA counter*/
1229                 odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 0);
1230                 odm_set_bb_reg(dm, R_0xa2c, BIT(15) | BIT(14), 2);
1231
1232                 /*reset CRC32 counter*/
1233                 odm_set_bb_reg(dm, R_0xf14, BIT(16), 1);
1234                 odm_set_bb_reg(dm, R_0xf14, BIT(16), 0);
1235         }
1236 #endif /* @#if (ODM_IC_11N_SERIES_SUPPORT) */
1237
1238 #if (ODM_IC_11AC_SERIES_SUPPORT)
1239         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1240                 #if (RTL8881A_SUPPORT)
1241                 /* Reset FA counter by enable/disable OFDM */
1242                 if ((dm->support_ic_type == ODM_RTL8881A) &&
1243                     false_alm_cnt->cnt_ofdm_fail_pre >= 0x7fff) {
1244                         /* reset OFDM */
1245                         odm_set_bb_reg(dm, R_0x808, BIT(29), 0);
1246                         odm_set_bb_reg(dm, R_0x808, BIT(29), 1);
1247                         false_alm_cnt->cnt_ofdm_fail_pre = 0;
1248                         PHYDM_DBG(dm, DBG_FA_CNT, "Reset FA_cnt\n");
1249                 }
1250                 #endif /* @#if (RTL8881A_SUPPORT) */
1251
1252                 /* reset OFDM FA countner */
1253                 odm_set_bb_reg(dm, R_0x9a4, BIT(17), 1);
1254                 odm_set_bb_reg(dm, R_0x9a4, BIT(17), 0);
1255
1256                 /* reset CCK FA counter */
1257                 odm_set_bb_reg(dm, R_0xa2c, BIT(15), 0);
1258                 odm_set_bb_reg(dm, R_0xa2c, BIT(15), 1);
1259
1260                 /* reset CCA counter */
1261                 phydm_reset_bb_hw_cnt_ac(dm);
1262         }
1263 #endif /* @#if (ODM_IC_11AC_SERIES_SUPPORT) */
1264 }
1265
1266 void phydm_false_alarm_counter_reg_hold(void *dm_void)
1267 {
1268         struct dm_struct *dm = (struct dm_struct *)dm_void;
1269
1270         if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1271                 /* @hold cck counter */
1272                 odm_set_bb_reg(dm, R_0x1a2c, BIT(12), 1);
1273                 odm_set_bb_reg(dm, R_0x1a2c, BIT(14), 1);
1274         } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1275                 /*@hold ofdm counter*/
1276                 /*@hold page C counter*/
1277                 odm_set_bb_reg(dm, R_0xc00, BIT(31), 1);
1278                 /*@hold page D counter*/
1279                 odm_set_bb_reg(dm, R_0xd00, BIT(31), 1);
1280
1281                 /*@hold cck counter*/
1282                 odm_set_bb_reg(dm, R_0xa2c, BIT(12), 1);
1283                 odm_set_bb_reg(dm, R_0xa2c, BIT(14), 1);
1284         }
1285 }
1286
1287 #if (ODM_IC_11N_SERIES_SUPPORT)
1288 void phydm_fa_cnt_statistics_n(void *dm_void)
1289 {
1290         struct dm_struct *dm = (struct dm_struct *)dm_void;
1291         struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1292         u32 reg = 0;
1293
1294         if (!(dm->support_ic_type & ODM_IC_11N_SERIES))
1295                 return;
1296
1297         /* @hold ofdm & cck counter */
1298         phydm_false_alarm_counter_reg_hold(dm);
1299
1300         reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11N, MASKDWORD);
1301         fa_t->cnt_fast_fsync = (reg & 0xffff);
1302         fa_t->cnt_sb_search_fail = ((reg & 0xffff0000) >> 16);
1303
1304         reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11N, MASKDWORD);
1305         fa_t->cnt_ofdm_cca = (reg & 0xffff);
1306         fa_t->cnt_parity_fail = ((reg & 0xffff0000) >> 16);
1307
1308         reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11N, MASKDWORD);
1309         fa_t->cnt_rate_illegal = (reg & 0xffff);
1310         fa_t->cnt_crc8_fail = ((reg & 0xffff0000) >> 16);
1311
1312         reg = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11N, MASKDWORD);
1313         fa_t->cnt_mcs_fail = (reg & 0xffff);
1314
1315         fa_t->cnt_ofdm_fail =
1316                 fa_t->cnt_parity_fail + fa_t->cnt_rate_illegal +
1317                 fa_t->cnt_crc8_fail + fa_t->cnt_mcs_fail +
1318                 fa_t->cnt_fast_fsync + fa_t->cnt_sb_search_fail;
1319
1320         /* read CCK CRC32 counter */
1321         fa_t->cnt_cck_crc32_error = odm_get_bb_reg(dm, R_0xf84, MASKDWORD);
1322         fa_t->cnt_cck_crc32_ok = odm_get_bb_reg(dm, R_0xf88, MASKDWORD);
1323
1324         /* read OFDM CRC32 counter */
1325         reg = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11N, MASKDWORD);
1326         fa_t->cnt_ofdm_crc32_error = (reg & 0xffff0000) >> 16;
1327         fa_t->cnt_ofdm_crc32_ok = reg & 0xffff;
1328
1329         /* read HT CRC32 counter */
1330         reg = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11N, MASKDWORD);
1331         fa_t->cnt_ht_crc32_error = (reg & 0xffff0000) >> 16;
1332         fa_t->cnt_ht_crc32_ok = reg & 0xffff;
1333
1334         /* read VHT CRC32 counter */
1335         fa_t->cnt_vht_crc32_error = 0;
1336         fa_t->cnt_vht_crc32_ok = 0;
1337
1338         #if (RTL8723D_SUPPORT)
1339         if (dm->support_ic_type == ODM_RTL8723D) {
1340                 /* read HT CRC32 agg counter */
1341                 reg = odm_get_bb_reg(dm, R_0xfb8, MASKDWORD);
1342                 fa_t->cnt_ht_crc32_error_agg = (reg & 0xffff0000) >> 16;
1343                 fa_t->cnt_ht_crc32_ok_agg = reg & 0xffff;
1344         }
1345         #endif
1346
1347         #if (RTL8188E_SUPPORT)
1348         if (dm->support_ic_type == ODM_RTL8188E) {
1349                 reg = odm_get_bb_reg(dm, ODM_REG_SC_CNT_11N, MASKDWORD);
1350                 fa_t->cnt_bw_lsc = (reg & 0xffff);
1351                 fa_t->cnt_bw_usc = ((reg & 0xffff0000) >> 16);
1352         }
1353         #endif
1354
1355         reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_LSB_11N, MASKBYTE0);
1356         fa_t->cnt_cck_fail = reg;
1357
1358         reg = odm_get_bb_reg(dm, ODM_REG_CCK_FA_MSB_11N, MASKBYTE3);
1359         fa_t->cnt_cck_fail += (reg & 0xff) << 8;
1360
1361         reg = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11N, MASKDWORD);
1362         fa_t->cnt_cck_cca = ((reg & 0xFF) << 8) | ((reg & 0xFF00) >> 8);
1363
1364         fa_t->cnt_all_pre = fa_t->cnt_all;
1365
1366         fa_t->cnt_all = fa_t->cnt_fast_fsync +
1367                         fa_t->cnt_sb_search_fail +
1368                         fa_t->cnt_parity_fail +
1369                         fa_t->cnt_rate_illegal +
1370                         fa_t->cnt_crc8_fail +
1371                         fa_t->cnt_mcs_fail +
1372                         fa_t->cnt_cck_fail;
1373
1374         fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca + fa_t->cnt_cck_cca;
1375
1376         PHYDM_DBG(dm, DBG_FA_CNT,
1377                   "[OFDM FA Detail] Parity_Fail=((%d)), Rate_Illegal=((%d)), CRC8_fail=((%d)), Mcs_fail=((%d)), Fast_Fsync=(( %d )), SBD_fail=((%d))\n",
1378                   fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
1379                   fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail, fa_t->cnt_fast_fsync,
1380                   fa_t->cnt_sb_search_fail);
1381 }
1382 #endif
1383
1384 #if (ODM_IC_11AC_SERIES_SUPPORT == 1)
1385 void phydm_fa_cnt_statistics_ac(void *dm_void)
1386 {
1387         struct dm_struct *dm = (struct dm_struct *)dm_void;
1388         struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1389         u32 ret_value = 0;
1390         u32 cck_enable;
1391
1392         if (!(dm->support_ic_type & ODM_IC_11AC_SERIES))
1393                 return;
1394
1395         ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE1_11AC, MASKDWORD);
1396         fa_t->cnt_fast_fsync = ((ret_value & 0xffff0000) >> 16);
1397
1398         ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE2_11AC, MASKDWORD);
1399         fa_t->cnt_sb_search_fail = (ret_value & 0xffff);
1400
1401         ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE3_11AC, MASKDWORD);
1402         fa_t->cnt_parity_fail = (ret_value & 0xffff);
1403         fa_t->cnt_rate_illegal = ((ret_value & 0xffff0000) >> 16);
1404
1405         ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE4_11AC, MASKDWORD);
1406         fa_t->cnt_crc8_fail = (ret_value & 0xffff);
1407         fa_t->cnt_mcs_fail = ((ret_value & 0xffff0000) >> 16);
1408
1409         ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE5_11AC, MASKDWORD);
1410         fa_t->cnt_crc8_fail_vht = (ret_value & 0xffff) +
1411                                   (ret_value & 0xffff0000 >> 16);
1412
1413         ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_FA_TYPE6_11AC, MASKDWORD);
1414         fa_t->cnt_mcs_fail_vht = (ret_value & 0xffff);
1415
1416         /* read OFDM FA counter */
1417         fa_t->cnt_ofdm_fail = odm_get_bb_reg(dm, R_0xf48, MASKLWORD);
1418
1419         /* Read CCK FA counter */
1420         fa_t->cnt_cck_fail = odm_get_bb_reg(dm, ODM_REG_CCK_FA_11AC, MASKLWORD);
1421
1422         /* read CCK/OFDM CCA counter */
1423         ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CCA_CNT_11AC, MASKDWORD);
1424         fa_t->cnt_ofdm_cca = (ret_value & 0xffff0000) >> 16;
1425         fa_t->cnt_cck_cca = ret_value & 0xffff;
1426
1427         /* read CCK CRC32 counter */
1428         ret_value = odm_get_bb_reg(dm, ODM_REG_CCK_CRC32_CNT_11AC, MASKDWORD);
1429         fa_t->cnt_cck_crc32_error = (ret_value & 0xffff0000) >> 16;
1430         fa_t->cnt_cck_crc32_ok = ret_value & 0xffff;
1431
1432         /* read OFDM CRC32 counter */
1433         ret_value = odm_get_bb_reg(dm, ODM_REG_OFDM_CRC32_CNT_11AC, MASKDWORD);
1434         fa_t->cnt_ofdm_crc32_error = (ret_value & 0xffff0000) >> 16;
1435         fa_t->cnt_ofdm_crc32_ok = ret_value & 0xffff;
1436
1437         /* read HT CRC32 counter */
1438         ret_value = odm_get_bb_reg(dm, ODM_REG_HT_CRC32_CNT_11AC, MASKDWORD);
1439         fa_t->cnt_ht_crc32_error = (ret_value & 0xffff0000) >> 16;
1440         fa_t->cnt_ht_crc32_ok = ret_value & 0xffff;
1441
1442         /* read VHT CRC32 counter */
1443         ret_value = odm_get_bb_reg(dm, ODM_REG_VHT_CRC32_CNT_11AC, MASKDWORD);
1444         fa_t->cnt_vht_crc32_error = (ret_value & 0xffff0000) >> 16;
1445         fa_t->cnt_vht_crc32_ok = ret_value & 0xffff;
1446
1447         #if (RTL8881A_SUPPORT)
1448         if (dm->support_ic_type == ODM_RTL8881A) {
1449                 u32 tmp = 0;
1450
1451                 if (fa_t->cnt_ofdm_fail >= fa_t->cnt_ofdm_fail_pre) {
1452                         tmp = fa_t->cnt_ofdm_fail_pre;
1453                         fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
1454                         fa_t->cnt_ofdm_fail = fa_t->cnt_ofdm_fail - tmp;
1455                 } else {
1456                         fa_t->cnt_ofdm_fail_pre = fa_t->cnt_ofdm_fail;
1457                 }
1458
1459                 PHYDM_DBG(dm, DBG_FA_CNT,
1460                           "[8881]cnt_ofdm_fail{curr,pre}={%d,%d}\n",
1461                           fa_t->cnt_ofdm_fail_pre, tmp);
1462         }
1463         #endif
1464
1465         cck_enable = odm_get_bb_reg(dm, ODM_REG_BB_RX_PATH_11AC, BIT(28));
1466
1467         if (cck_enable) { /* @if(*dm->band_type == ODM_BAND_2_4G) */
1468                 fa_t->cnt_all = fa_t->cnt_ofdm_fail + fa_t->cnt_cck_fail;
1469                 fa_t->cnt_cca_all = fa_t->cnt_cck_cca + fa_t->cnt_ofdm_cca;
1470         } else {
1471                 fa_t->cnt_all = fa_t->cnt_ofdm_fail;
1472                 fa_t->cnt_cca_all = fa_t->cnt_ofdm_cca;
1473         }
1474 }
1475 #endif
1476
1477 void phydm_get_dbg_port_info(void *dm_void)
1478 {
1479         struct dm_struct *dm = (struct dm_struct *)dm_void;
1480         struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1481         u32 dbg_port = dm->adaptivity.adaptivity_dbg_port;
1482         u32 val = 0;
1483
1484         /*set debug port to 0x0*/
1485         if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, 0x0)) {
1486                 fa_t->dbg_port0 = phydm_get_bb_dbg_port_val(dm);
1487                 phydm_release_bb_dbg_port(dm);
1488         }
1489
1490         if (dm->support_ic_type & ODM_RTL8723D) {
1491                 val = odm_get_bb_reg(dm, R_0x9a0, BIT(29));
1492         } else if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1493                 val = odm_get_bb_reg(dm, R_0x2d38, BIT(24));
1494         } else if (phydm_set_bb_dbg_port(dm, DBGPORT_PRI_1, dbg_port)) {
1495                 if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E))
1496                         val = (phydm_get_bb_dbg_port_val(dm) & BIT(30)) >> 30;
1497                 else
1498                         val = (phydm_get_bb_dbg_port_val(dm) & BIT(29)) >> 29;
1499                 phydm_release_bb_dbg_port(dm);
1500         }
1501
1502         fa_t->edcca_flag = (boolean)val;
1503
1504         PHYDM_DBG(dm, DBG_FA_CNT, "FA_Cnt: Dbg port 0x0 = 0x%x, EDCCA = %d\n\n",
1505                   fa_t->dbg_port0, fa_t->edcca_flag);
1506 }
1507
1508 void phydm_false_alarm_counter_statistics(void *dm_void)
1509 {
1510         struct dm_struct *dm = (struct dm_struct *)dm_void;
1511         struct phydm_fa_struct *fa_t = &dm->false_alm_cnt;
1512
1513         if (!(dm->support_ability & ODM_BB_FA_CNT))
1514                 return;
1515
1516         PHYDM_DBG(dm, DBG_FA_CNT, "%s======>\n", __func__);
1517
1518         if (dm->support_ic_type & ODM_IC_JGR3_SERIES) {
1519                 #ifdef PHYDM_IC_JGR3_SERIES_SUPPORT
1520                 phydm_fa_cnt_statistics_jgr3(dm);
1521                 #endif
1522         } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1523                 #if (ODM_IC_11N_SERIES_SUPPORT)
1524                 phydm_fa_cnt_statistics_n(dm);
1525                 #endif
1526         } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1527                 #if (ODM_IC_11AC_SERIES_SUPPORT)
1528                 phydm_fa_cnt_statistics_ac(dm);
1529                 #endif
1530         }
1531
1532         phydm_get_dbg_port_info(dm);
1533         phydm_false_alarm_counter_reg_reset(dm_void);
1534
1535         fa_t->time_fa_all = fa_t->cnt_fast_fsync * 12 +
1536                             fa_t->cnt_sb_search_fail * 12 +
1537                             fa_t->cnt_parity_fail * 28 +
1538                             fa_t->cnt_rate_illegal * 28 +
1539                             fa_t->cnt_crc8_fail * 36 +
1540                             fa_t->cnt_crc8_fail_vht * 36 +
1541                             fa_t->cnt_mcs_fail_vht * 36 +
1542                             fa_t->cnt_mcs_fail * 32 +
1543                             fa_t->cnt_cck_fail * 80;
1544
1545         fa_t->cnt_crc32_error_all = fa_t->cnt_vht_crc32_error +
1546                                     fa_t->cnt_ht_crc32_error +
1547                                     fa_t->cnt_ofdm_crc32_error +
1548                                     fa_t->cnt_cck_crc32_error;
1549
1550         fa_t->cnt_crc32_ok_all = fa_t->cnt_vht_crc32_ok +
1551                                  fa_t->cnt_ht_crc32_ok +
1552                                  fa_t->cnt_ofdm_crc32_ok +
1553                                  fa_t->cnt_cck_crc32_ok;
1554
1555         PHYDM_DBG(dm, DBG_FA_CNT,
1556                   "[OFDM FA Detail-1] Parity=((%d)), Rate_Illegal=((%d)), HT_CRC8=((%d)), HT_MCS=((%d))\n",
1557                   fa_t->cnt_parity_fail, fa_t->cnt_rate_illegal,
1558                   fa_t->cnt_crc8_fail, fa_t->cnt_mcs_fail);
1559         PHYDM_DBG(dm, DBG_FA_CNT,
1560                   "[OFDM FA Detail-2] Fast_Fsync=((%d)), SBD=((%d)), VHT_CRC8=((%d)), VHT_MCS=((%d))\n",
1561                   fa_t->cnt_fast_fsync, fa_t->cnt_sb_search_fail,
1562                   fa_t->cnt_crc8_fail_vht, fa_t->cnt_mcs_fail_vht);
1563         PHYDM_DBG(dm, DBG_FA_CNT,
1564                   "[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1565                   fa_t->cnt_cck_cca, fa_t->cnt_ofdm_cca, fa_t->cnt_cca_all);
1566         PHYDM_DBG(dm, DBG_FA_CNT,
1567                   "[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
1568                   fa_t->cnt_cck_fail, fa_t->cnt_ofdm_fail, fa_t->cnt_all);
1569         PHYDM_DBG(dm, DBG_FA_CNT, "[CCK]  CRC32 {error, ok}= {%d, %d}\n",
1570                   fa_t->cnt_cck_crc32_error, fa_t->cnt_cck_crc32_ok);
1571         PHYDM_DBG(dm, DBG_FA_CNT, "[OFDM]CRC32 {error, ok}= {%d, %d}\n",
1572                   fa_t->cnt_ofdm_crc32_error, fa_t->cnt_ofdm_crc32_ok);
1573         PHYDM_DBG(dm, DBG_FA_CNT, "[ HT ]  CRC32 {error, ok}= {%d, %d}\n",
1574                   fa_t->cnt_ht_crc32_error, fa_t->cnt_ht_crc32_ok);
1575         PHYDM_DBG(dm, DBG_FA_CNT, "[VHT]  CRC32 {error, ok}= {%d, %d}\n",
1576                   fa_t->cnt_vht_crc32_error, fa_t->cnt_vht_crc32_ok);
1577         PHYDM_DBG(dm, DBG_FA_CNT, "[TOTAL]  CRC32 {error, ok}= {%d, %d}\n",
1578                   fa_t->cnt_crc32_error_all, fa_t->cnt_crc32_ok_all);
1579 }
1580
1581 #ifdef PHYDM_TDMA_DIG_SUPPORT
1582 void phydm_set_tdma_dig_timer(void *dm_void)
1583 {
1584         struct dm_struct *dm = (struct dm_struct *)dm_void;
1585         u32 delta_time_us = dm->tdma_dig_timer_ms * 1000;
1586         struct phydm_dig_struct *dig_t;
1587         u32 timeout;
1588         u32 current_time_stamp, diff_time_stamp, regb0;
1589
1590         dig_t = &dm->dm_dig_table;
1591         /*some IC has no FREERUN_CUNT register, like 92E*/
1592         if (dm->support_ic_type & ODM_RTL8197F)
1593                 current_time_stamp = odm_get_bb_reg(dm, R_0x568, 0xffffffff);
1594         else
1595                 return;
1596
1597         timeout = current_time_stamp + delta_time_us;
1598
1599         diff_time_stamp = current_time_stamp - dig_t->cur_timestamp;
1600         dig_t->pre_timestamp = dig_t->cur_timestamp;
1601         dig_t->cur_timestamp = current_time_stamp;
1602
1603         /*@HIMR0, it shows HW interrupt mask*/
1604         regb0 = odm_get_bb_reg(dm, R_0xb0, 0xffffffff);
1605
1606         PHYDM_DBG(dm, DBG_DIG, "Set next timer\n");
1607         PHYDM_DBG(dm, DBG_DIG,
1608                   "curr_time_stamp=%d, delta_time_us=%d\n",
1609                   current_time_stamp, delta_time_us);
1610         PHYDM_DBG(dm, DBG_DIG,
1611                   "timeout=%d, diff_time_stamp=%d, Reg0xb0 = 0x%x\n",
1612                   timeout, diff_time_stamp, regb0);
1613
1614         if (dm->support_ic_type & ODM_RTL8197F) /*REG_PS_TIMER2*/
1615                 odm_set_bb_reg(dm, R_0x588, 0xffffffff, timeout);
1616         else {
1617                 PHYDM_DBG(dm, DBG_DIG, "NOT 97F, NOT start\n");
1618                 return;
1619         }
1620 }
1621
1622 void phydm_tdma_dig_timer_check(void *dm_void)
1623 {
1624         struct dm_struct *dm = (struct dm_struct *)dm_void;
1625         struct phydm_dig_struct *dig_t;
1626
1627         dig_t = &dm->dm_dig_table;
1628
1629         PHYDM_DBG(dm, DBG_DIG, "tdma_dig_cnt=%d, pre_tdma_dig_cnt=%d\n",
1630                   dig_t->tdma_dig_cnt, dig_t->pre_tdma_dig_cnt);
1631
1632         if (dig_t->tdma_dig_cnt == 0 ||
1633             dig_t->tdma_dig_cnt == dig_t->pre_tdma_dig_cnt) {
1634                 if (dm->support_ability & ODM_BB_DIG) {
1635 #ifdef IS_USE_NEW_TDMA
1636                         if (dm->support_ic_type &
1637                             (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B)) {
1638                                 PHYDM_DBG(dm, DBG_DIG,
1639                                           "Check fail, Restart timer\n\n");
1640                                 phydm_false_alarm_counter_reset(dm);
1641                                 odm_set_timer(dm, &dm->tdma_dig_timer,
1642                                               dm->tdma_dig_timer_ms);
1643                         } else {
1644                                 PHYDM_DBG(dm, DBG_DIG,
1645                                           "Not 98F/22C/14B no SW timer\n");
1646                         }
1647 #else
1648                         /*@if interrupt mask info is got.*/
1649                         /*Reg0xb0 is no longer needed*/
1650 #if 0
1651                         /*regb0 = odm_get_bb_reg(dm, R_0xb0, bMaskDWord);*/
1652 #endif
1653                         PHYDM_DBG(dm, DBG_DIG,
1654                                   "Check fail, Mask[0]=0x%x, restart timer\n",
1655                                   *dm->interrupt_mask);
1656
1657                         phydm_tdma_dig_add_interrupt_mask_handler(dm);
1658                         phydm_enable_rx_related_interrupt_handler(dm);
1659                         phydm_set_tdma_dig_timer(dm);
1660 #endif
1661                 }
1662         } else {
1663                 PHYDM_DBG(dm, DBG_DIG, "Check pass, update pre_tdma_dig_cnt\n");
1664         }
1665
1666         dig_t->pre_tdma_dig_cnt = dig_t->tdma_dig_cnt;
1667 }
1668
1669 /*@different IC/team may use different timer for tdma-dig*/
1670 void phydm_tdma_dig_add_interrupt_mask_handler(void *dm_void)
1671 {
1672         struct dm_struct *dm = (struct dm_struct *)dm_void;
1673
1674 #if (DM_ODM_SUPPORT_TYPE == (ODM_AP))
1675         if (dm->support_ic_type & ODM_RTL8197F) {
1676                 /*@HAL_INT_TYPE_PSTIMEOUT2*/
1677                 phydm_add_interrupt_mask_handler(dm, HAL_INT_TYPE_PSTIMEOUT2);
1678         }
1679 #elif (DM_ODM_SUPPORT_TYPE == (ODM_WIN))
1680 #elif (DM_ODM_SUPPORT_TYPE == (ODM_CE))
1681 #endif
1682 }
1683
1684 /* will be triggered by HW timer*/
1685 void phydm_tdma_dig(void *dm_void)
1686 {
1687         struct dm_struct *dm;
1688         struct phydm_dig_struct *dig_t;
1689         struct phydm_fa_struct *falm_cnt;
1690         u32 reg_c50;
1691
1692 #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
1693 #ifdef IS_USE_NEW_TDMA
1694         if (dm->support_ic_type &
1695             (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B)) {
1696                 PHYDM_DBG(dm, DBG_DIG, "98F/22C/14B, new tdma\n");
1697                 return;
1698         }
1699 #endif
1700 #endif
1701
1702         dm = (struct dm_struct *)dm_void;
1703         dig_t = &dm->dm_dig_table;
1704         falm_cnt = &dm->false_alm_cnt;
1705         reg_c50 = odm_get_bb_reg(dm, R_0xc50, MASKBYTE0);
1706
1707         dig_t->tdma_dig_state =
1708                 dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
1709
1710         PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, regc50=0x%x\n",
1711                   dig_t->tdma_dig_state, reg_c50);
1712
1713         dig_t->tdma_dig_cnt++;
1714
1715         if (dig_t->tdma_dig_state == 1) {
1716                 /* update IGI from tdma_dig_state == 0*/
1717                 if (dig_t->cur_ig_value_tdma == 0)
1718                         dig_t->cur_ig_value_tdma = dig_t->cur_ig_value;
1719
1720                 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
1721                 phydm_tdma_false_alarm_counter_check(dm);
1722                 PHYDM_DBG(dm, DBG_DIG, "tdma_dig_state=%d, reset FA counter\n",
1723                           dig_t->tdma_dig_state);
1724
1725         } else if (dig_t->tdma_dig_state == 0) {
1726                 /* update dig_t->CurIGValue,*/
1727                 /* @it may different from dig_t->cur_ig_value_tdma */
1728                 /* TDMA IGI upperbond @ L-state = */
1729                 /* rf_ft_var.tdma_dig_low_upper_bond = 0x26 */
1730
1731                 if (dig_t->cur_ig_value >= dm->tdma_dig_low_upper_bond)
1732                         dig_t->low_ig_value = dm->tdma_dig_low_upper_bond;
1733                 else
1734                         dig_t->low_ig_value = dig_t->cur_ig_value;
1735
1736                 odm_write_dig(dm, dig_t->low_ig_value);
1737                 phydm_tdma_false_alarm_counter_check(dm);
1738         } else {
1739                 phydm_tdma_false_alarm_counter_check(dm);
1740         }
1741 }
1742
1743 /*@============================================================*/
1744 /*@FASLE ALARM CHECK*/
1745 /*@============================================================*/
1746 void phydm_tdma_false_alarm_counter_check(void *dm_void)
1747 {
1748         struct dm_struct *dm;
1749         struct phydm_fa_struct *falm_cnt;
1750         struct phydm_fa_acc_struct *falm_cnt_acc;
1751         struct phydm_dig_struct *dig_t;
1752         boolean rssi_dump_en = 0;
1753         u32 timestamp;
1754         u8 tdma_dig_state_number;
1755         u32 start_th = 0;
1756
1757         dm = (struct dm_struct *)dm_void;
1758         falm_cnt = &dm->false_alm_cnt;
1759         falm_cnt_acc = &dm->false_alm_cnt_acc;
1760         dig_t = &dm->dm_dig_table;
1761
1762         if (dig_t->tdma_dig_state == 1)
1763                 phydm_false_alarm_counter_reset(dm);
1764         /* Reset FalseAlarmCounterStatistics */
1765         /* @fa_acc_1sec_tsf = fa_acc_1sec_tsf, keep */
1766         /* @fa_end_tsf = fa_start_tsf = TSF */
1767         else {
1768                 phydm_false_alarm_counter_statistics(dm);
1769                 if (dm->support_ic_type & ODM_RTL8197F) /*REG_FREERUN_CNT*/
1770                         timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
1771                 else {
1772                         PHYDM_DBG(dm, DBG_DIG, "NOT 97F! NOT start\n");
1773                         return;
1774                 }
1775                 dig_t->fa_end_timestamp = timestamp;
1776                 dig_t->fa_acc_1sec_timestamp +=
1777                         (dig_t->fa_end_timestamp - dig_t->fa_start_timestamp);
1778
1779                 /*prevent dumb*/
1780                 if (dm->tdma_dig_state_number == 1)
1781                         dm->tdma_dig_state_number = 2;
1782
1783                 tdma_dig_state_number = dm->tdma_dig_state_number;
1784                 dig_t->sec_factor =
1785                         tdma_dig_state_number / (tdma_dig_state_number - 1);
1786
1787                 /*@1sec = 1000000us*/
1788                 if (dig_t->sec_factor)
1789                         start_th = (u32)(1000000 / dig_t->sec_factor);
1790
1791                 if (dig_t->fa_acc_1sec_timestamp >= start_th) {
1792                         rssi_dump_en = 1;
1793                         phydm_false_alarm_counter_acc(dm, rssi_dump_en);
1794                         PHYDM_DBG(dm, DBG_DIG,
1795                                   "sec_factor=%d, total FA=%d, is_linked=%d\n",
1796                                   dig_t->sec_factor, falm_cnt_acc->cnt_all,
1797                                   dm->is_linked);
1798
1799                         phydm_noisy_detection(dm);
1800                         #ifdef PHYDM_SUPPORT_CCKPD
1801                         phydm_cck_pd_th(dm);
1802                         #endif
1803                         phydm_dig(dm);
1804                         phydm_false_alarm_counter_acc_reset(dm);
1805
1806                         /* Reset FalseAlarmCounterStatistics */
1807                         /* @fa_end_tsf = fa_start_tsf = TSF, keep */
1808                         /* @fa_acc_1sec_tsf = 0 */
1809                         phydm_false_alarm_counter_reset(dm);
1810                 } else {
1811                         phydm_false_alarm_counter_acc(dm, rssi_dump_en);
1812                 }
1813         }
1814 }
1815
1816 void phydm_false_alarm_counter_acc(void *dm_void, boolean rssi_dump_en)
1817 {
1818         struct dm_struct *dm = (struct dm_struct *)dm_void;
1819         struct phydm_fa_struct *falm_cnt;
1820         struct phydm_fa_acc_struct *falm_cnt_acc;
1821         struct phydm_dig_struct *dig_t;
1822
1823         falm_cnt = &dm->false_alm_cnt;
1824         falm_cnt_acc = &dm->false_alm_cnt_acc;
1825         dig_t = &dm->dm_dig_table;
1826
1827         falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
1828         falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
1829         falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
1830         falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
1831         falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
1832         falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
1833         falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
1834         falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
1835         falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
1836         falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
1837         falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
1838         falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
1839         falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
1840         falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
1841         falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
1842         falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
1843         falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
1844         falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
1845         falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
1846         falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
1847         falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
1848         falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
1849
1850         if (rssi_dump_en == 1) {
1851                 falm_cnt_acc->cnt_all_1sec =
1852                         falm_cnt_acc->cnt_all * dig_t->sec_factor;
1853                 falm_cnt_acc->cnt_cca_all_1sec =
1854                         falm_cnt_acc->cnt_cca_all * dig_t->sec_factor;
1855                 falm_cnt_acc->cnt_cck_fail_1sec =
1856                         falm_cnt_acc->cnt_cck_fail * dig_t->sec_factor;
1857         }
1858 }
1859
1860 void phydm_false_alarm_counter_acc_reset(void *dm_void)
1861 {
1862         struct dm_struct *dm = (struct dm_struct *)dm_void;
1863         struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
1864
1865 #ifdef IS_USE_NEW_TDMA
1866         struct phydm_fa_acc_struct *falm_cnt_acc_low = NULL;
1867         u32 tmp_cca_1sec = 0;
1868         u32 tmp_fa_1sec = 0;
1869
1870         /*@clear L-fa_acc struct*/
1871         falm_cnt_acc_low = &dm->false_alm_cnt_acc_low;
1872         tmp_cca_1sec = falm_cnt_acc_low->cnt_cca_all_1sec;
1873         tmp_fa_1sec = falm_cnt_acc_low->cnt_all_1sec;
1874         odm_memory_set(dm, falm_cnt_acc_low, 0, sizeof(dm->false_alm_cnt_acc));
1875         falm_cnt_acc_low->cnt_cca_all_1sec = tmp_cca_1sec;
1876         falm_cnt_acc_low->cnt_all_1sec = tmp_fa_1sec;
1877
1878         /*@clear H-fa_acc struct*/
1879         falm_cnt_acc = &dm->false_alm_cnt_acc;
1880         tmp_cca_1sec = falm_cnt_acc->cnt_cca_all_1sec;
1881         tmp_fa_1sec = falm_cnt_acc->cnt_all_1sec;
1882         odm_memory_set(dm, falm_cnt_acc, 0, sizeof(dm->false_alm_cnt_acc));
1883         falm_cnt_acc->cnt_cca_all_1sec = tmp_cca_1sec;
1884         falm_cnt_acc->cnt_all_1sec = tmp_fa_1sec;
1885 #else
1886         falm_cnt_acc = &dm->false_alm_cnt_acc;
1887         /* @Cnt_all_for_rssi_dump & Cnt_CCA_all_for_rssi_dump */
1888         /* @do NOT need to be reset */
1889         odm_memory_set(dm, falm_cnt_acc, 0, sizeof(falm_cnt_acc));
1890 #endif
1891 }
1892
1893 void phydm_false_alarm_counter_reset(void *dm_void)
1894 {
1895         struct dm_struct *dm = (struct dm_struct *)dm_void;
1896         struct phydm_fa_struct *falm_cnt;
1897         struct phydm_dig_struct *dig_t;
1898         u32 timestamp;
1899
1900         falm_cnt = &dm->false_alm_cnt;
1901         dig_t = &dm->dm_dig_table;
1902
1903         memset(falm_cnt, 0, sizeof(dm->false_alm_cnt));
1904         phydm_false_alarm_counter_reg_reset(dm);
1905
1906 #ifdef IS_USE_NEW_TDMA
1907         return;
1908 #endif
1909         if (dig_t->tdma_dig_state != 1)
1910                 dig_t->fa_acc_1sec_timestamp = 0;
1911         else
1912                 dig_t->fa_acc_1sec_timestamp = dig_t->fa_acc_1sec_timestamp;
1913
1914         /*REG_FREERUN_CNT*/
1915         timestamp = odm_get_bb_reg(dm, R_0x568, bMaskDWord);
1916         dig_t->fa_start_timestamp = timestamp;
1917         dig_t->fa_end_timestamp = timestamp;
1918 }
1919
1920 #ifdef IS_USE_NEW_TDMA
1921 void phydm_tdma_dig_timers(void *dm_void, u8 state)
1922 {
1923 #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
1924         struct dm_struct *dm = (struct dm_struct *)dm_void;
1925         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1926
1927         if (dm->support_ic_type &
1928             (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B)) {
1929                 if (state == INIT_TDMA_DIG_TIMMER)
1930                         odm_initialize_timer(dm, &dm->tdma_dig_timer,
1931                                              (void *)phydm_tdma_dig_cbk,
1932                                              NULL, "phydm_tdma_dig_timer");
1933                 else if (state == CANCEL_TDMA_DIG_TIMMER)
1934                         odm_cancel_timer(dm, &dm->tdma_dig_timer);
1935                 else if (state == RELEASE_TDMA_DIG_TIMMER)
1936                         odm_release_timer(dm, &dm->tdma_dig_timer);
1937         }
1938 #endif
1939 }
1940
1941 u8 get_new_igi_bound(struct dm_struct *dm, u8 igi, u32 fa_cnt, u8 *rx_gain_max,
1942                      u8 *rx_gain_min, boolean is_dfs_band)
1943 {
1944         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
1945         u8 step[3] = {0};
1946         u8 cur_igi = igi;
1947         boolean first_connect = false, first_dis_connect = false;
1948
1949         first_connect = (dm->is_linked) && !dig_t->is_media_connect;
1950         first_dis_connect = (!dm->is_linked) && dig_t->is_media_connect;
1951
1952         if (dm->is_linked) {
1953                 if (dm->pre_rssi_min <= dm->rssi_min) {
1954                         PHYDM_DBG(dm, DBG_DIG, "pre_rssi_min <= rssi_min\n");
1955                         step[0] = 2;
1956                         step[1] = 1;
1957                         step[2] = 2;
1958                 } else {
1959                         step[0] = 4;
1960                         step[1] = 2;
1961                         step[2] = 2;
1962                 }
1963         } else {
1964                 step[0] = 2;
1965                 step[1] = 1;
1966                 step[2] = 2;
1967         }
1968
1969         PHYDM_DBG(dm, DBG_DIG, "step = {-%d, +%d, +%d}\n", step[2], step[1],
1970                   step[0]);
1971
1972         if (first_connect) {
1973                 if (is_dfs_band) {
1974                         if (dm->rssi_min > DIG_MAX_DFS)
1975                                 igi = DIG_MAX_DFS;
1976                         else
1977                                 igi = dm->rssi_min;
1978                         PHYDM_DBG(dm, DBG_DIG, "DFS band:IgiMax=0x%x\n",
1979                                   *rx_gain_max);
1980                 } else {
1981                         igi = *rx_gain_min;
1982                 }
1983
1984                 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1985                 #if (RTL8812A_SUPPORT)
1986                 if (dm->support_ic_type == ODM_RTL8812)
1987                         odm_config_bb_with_header_file(dm,
1988                                                        CONFIG_BB_AGC_TAB_DIFF);
1989                 #endif
1990                 #endif
1991                 PHYDM_DBG(dm, DBG_DIG, "First connect: foce IGI=0x%x\n", igi);
1992         } else if (dm->is_linked) {
1993                 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI @ linked\n");
1994                 /* @4 Abnormal # beacon case */
1995                 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN | ODM_CE))
1996                 if (dm->phy_dbg_info.num_qry_beacon_pkt < 5 &&
1997                     fa_cnt < DM_DIG_FA_TH1 && dm->bsta_state &&
1998                     dm->support_ic_type != ODM_RTL8723D) {
1999                         *rx_gain_min = 0x1c;
2000                         igi = *rx_gain_min;
2001                         PHYDM_DBG(dm, DBG_DIG, "Beacon_num=%d,force igi=0x%x\n",
2002                                   dm->phy_dbg_info.num_qry_beacon_pkt, igi);
2003                 } else {
2004                         igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
2005                 }
2006                 #else
2007                 igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
2008                 #endif
2009         } else {
2010                 /* @2 Before link */
2011                 PHYDM_DBG(dm, DBG_DIG, "Adjust IGI before link\n");
2012
2013                 if (first_dis_connect) {
2014                         igi = dig_t->dm_dig_min;
2015                         PHYDM_DBG(dm, DBG_DIG,
2016                                   "First disconnect:foce IGI to lower bound\n");
2017                 } else {
2018                         PHYDM_DBG(dm, DBG_DIG, "Pre_IGI=((0x%x)), FA=((%d))\n",
2019                                   igi, fa_cnt);
2020
2021                         igi = phydm_new_igi_by_fa(dm, igi, fa_cnt, step);
2022                 }
2023         }
2024         /*@Check IGI by dyn-upper/lower bound */
2025         if (igi < *rx_gain_min)
2026                 igi = *rx_gain_min;
2027
2028         if (igi > *rx_gain_max)
2029                 igi = *rx_gain_max;
2030
2031         PHYDM_DBG(dm, DBG_DIG, "fa_cnt = %d, IGI: 0x%x -> 0x%x\n",
2032                   fa_cnt, cur_igi, igi);
2033
2034         return igi;
2035 }
2036
2037 /*@callback function triggered by SW timer*/
2038 void phydm_tdma_dig_cbk(void *dm_void)
2039 {
2040 #if (RTL8198F_SUPPORT || RTL8822C_SUPPORT || RTL8814B_SUPPORT)
2041         struct dm_struct *dm = (struct dm_struct *)dm_void;
2042         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2043
2044         if (phydm_dig_abort(dm) || (dm->original_dig_restore))
2045                 return;
2046         /*@
2047          *PHYDM_DBG(dm, DBG_DIG, "timer callback =======> tdma_dig_state=%d\n");
2048          *        dig_t->tdma_dig_state);
2049          *PHYDM_DBG(dm, DBG_DIG, "tdma_h_igi=0x%x, tdma_l_igi=0x%x\n",
2050          *        dig_t->cur_ig_value_tdma,
2051          *        dig_t->low_ig_value);
2052          */
2053         phydm_tdma_fa_cnt_chk(dm);
2054
2055         /*@prevent dumb*/
2056         if (dm->tdma_dig_state_number < 2)
2057                 dm->tdma_dig_state_number = 2;
2058
2059         /*@update state*/
2060         dig_t->tdma_dig_cnt++;
2061         dig_t->tdma_dig_state = dig_t->tdma_dig_cnt % dm->tdma_dig_state_number;
2062
2063         /*@
2064          *PHYDM_DBG(dm, DBG_DIG, "enter state %d, dig count %d\n",
2065          *        dig_t->tdma_dig_state, dig_t->tdma_dig_cnt);
2066          */
2067
2068         if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2069                 odm_write_dig(dm, dig_t->low_ig_value);
2070         else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2071                 odm_write_dig(dm, dig_t->cur_ig_value_tdma);
2072
2073         odm_set_timer(dm, &dm->tdma_dig_timer, dm->tdma_dig_timer_ms);
2074 #endif
2075 }
2076
2077 /*@============================================================*/
2078 /*@FASLE ALARM CHECK*/
2079 /*@============================================================*/
2080 void phydm_tdma_fa_cnt_chk(void *dm_void)
2081 {
2082         struct dm_struct *dm = (struct dm_struct *)dm_void;
2083         struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2084         struct phydm_fa_acc_struct *fa_t_acc, *fa_t_acc_low;
2085         struct phydm_dig_struct *dig_t = NULL;
2086         boolean rssi_dump_en = false;
2087         u32 timestamp = 0;
2088         u8 states_per_block = 0;
2089         u8 cur_tdma_dig_state = 0;
2090         u32 start_th = 0;
2091         u8 state_diff = 0;
2092         u32 tdma_dig_block_period_ms = 0;
2093         u32 tdma_dig_block_cnt_thd = 0;
2094         u32 timestamp_diff = 0;
2095
2096         if (!(dm->support_ic_type &
2097             (ODM_RTL8198F | ODM_RTL8822C | ODM_RTL8814B))) {
2098                 PHYDM_DBG(dm, DBG_DIG, "Not 98F/22C/14B\n");
2099                 return;
2100         }
2101
2102         fa_t_acc = &dm->false_alm_cnt_acc;
2103         fa_t_acc_low = &dm->false_alm_cnt_acc_low;
2104         dig_t = &dm->dm_dig_table;
2105         states_per_block = dm->tdma_dig_state_number;
2106
2107         /*@calculate duration of a tdma block*/
2108         tdma_dig_block_period_ms = dm->tdma_dig_timer_ms * states_per_block;
2109
2110         /*@
2111          *caution!ONE_SEC_MS must be divisible by tdma_dig_block_period_ms,
2112          *or FA will be fewer.
2113          */
2114         tdma_dig_block_cnt_thd = ONE_SEC_MS / tdma_dig_block_period_ms;
2115
2116         /*@tdma_dig_state == 0, collect H-state FA, else, collect L-state FA*/
2117         if (dig_t->tdma_dig_state == TDMA_DIG_LOW_STATE)
2118                 cur_tdma_dig_state = TDMA_DIG_LOW_STATE;
2119         else if (dig_t->tdma_dig_state >= TDMA_DIG_HIGH_STATE)
2120                 cur_tdma_dig_state = TDMA_DIG_HIGH_STATE;
2121         /*@
2122          *PHYDM_DBG(dm, DBG_DIG, "in state %d, dig count %d\n",
2123          *        cur_tdma_dig_state, dig_t->tdma_dig_cnt);
2124          */
2125         if (cur_tdma_dig_state == 0) {
2126                 /*@L-state indicates next block*/
2127                 dig_t->tdma_dig_block_cnt++;
2128
2129                 /*@1sec dump check*/
2130                 if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
2131                         rssi_dump_en = true;
2132
2133                 /*@
2134                  *PHYDM_DBG(dm, DBG_DIG,"[L-state] tdma_dig_block_cnt=%d\n",
2135                  *        dig_t->tdma_dig_block_cnt);
2136                  */
2137
2138                 /*@collect FA till this block end*/
2139                 phydm_false_alarm_counter_statistics(dm);
2140                 phydm_fa_cnt_acc(dm, rssi_dump_en, cur_tdma_dig_state);
2141                 /*@1s L-FA collect end*/
2142
2143                 /*@1sec dump reached*/
2144                 if (rssi_dump_en) {
2145                         /*@L-DIG*/
2146                         phydm_noisy_detection(dm);
2147                         #ifdef PHYDM_SUPPORT_CCKPD
2148                         phydm_cck_pd_th(dm);
2149                         #endif
2150                         PHYDM_DBG(dm, DBG_DIG, "run tdma L-state dig ====>\n");
2151                         phydm_tdma_low_dig(dm);
2152                         PHYDM_DBG(dm, DBG_DIG, "\n\n");
2153                 }
2154         } else if (cur_tdma_dig_state == 1) {
2155                 /*@1sec dump check*/
2156                 if (dig_t->tdma_dig_block_cnt >= tdma_dig_block_cnt_thd)
2157                         rssi_dump_en = true;
2158
2159                 /*@
2160                  *PHYDM_DBG(dm, DBG_DIG,"[H-state] tdma_dig_block_cnt=%d\n",
2161                  *        dig_t->tdma_dig_block_cnt);
2162                  */
2163
2164                 /*@collect FA till this block end*/
2165                 phydm_false_alarm_counter_statistics(dm);
2166                 phydm_fa_cnt_acc(dm, rssi_dump_en, cur_tdma_dig_state);
2167                 /*@1s H-FA collect end*/
2168
2169                 /*@1sec dump reached*/
2170                 state_diff = dm->tdma_dig_state_number - dig_t->tdma_dig_state;
2171                 if (rssi_dump_en && (state_diff == 1)) {
2172                         /*@H-DIG*/
2173                         phydm_noisy_detection(dm);
2174                         #ifdef PHYDM_SUPPORT_CCKPD
2175                         phydm_cck_pd_th(dm);
2176                         #endif
2177                         PHYDM_DBG(dm, DBG_DIG, "run tdma H-state dig ====>\n");
2178                         phydm_tdma_high_dig(dm);
2179                         PHYDM_DBG(dm, DBG_DIG, "\n\n");
2180                         PHYDM_DBG(dm, DBG_DIG, "1 sec reached, is_linked=%d\n",
2181                                   dm->is_linked);
2182                         PHYDM_DBG(dm, DBG_DIG, "1 sec L-CCA=%d, L-FA=%d\n",
2183                                   fa_t_acc_low->cnt_cca_all_1sec,
2184                                   fa_t_acc_low->cnt_all_1sec);
2185                         PHYDM_DBG(dm, DBG_DIG, "1 sec H-CCA=%d, H-FA=%d\n",
2186                                   fa_t_acc->cnt_cca_all_1sec,
2187                                   fa_t_acc->cnt_all_1sec);
2188                         PHYDM_DBG(dm, DBG_DIG,
2189                                   "1 sec TOTAL-CCA=%d, TOTAL-FA=%d\n\n",
2190                                   fa_t_acc->cnt_cca_all +
2191                                   fa_t_acc_low->cnt_cca_all,
2192                                   fa_t_acc->cnt_all + fa_t_acc_low->cnt_all);
2193
2194                         /*@Reset AccFalseAlarmCounterStatistics */
2195                         phydm_false_alarm_counter_acc_reset(dm);
2196                         dig_t->tdma_dig_block_cnt = 0;
2197                 }
2198         }
2199         /*@Reset FalseAlarmCounterStatistics */
2200         phydm_false_alarm_counter_reset(dm);
2201 }
2202
2203 void phydm_tdma_low_dig(void *dm_void)
2204 {
2205         struct dm_struct *dm = (struct dm_struct *)dm_void;
2206         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2207         struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2208         struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc_low;
2209 #ifdef CFG_DIG_DAMPING_CHK
2210         struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
2211 #endif
2212         boolean first_connect, first_disconnect;
2213         u8 igi = dig_t->cur_ig_value;
2214         u8 new_igi = 0x20;
2215         u8 tdma_l_igi = dig_t->low_ig_value;
2216         u8 tdma_l_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE];
2217         u8 tdma_l_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE];
2218         u32 fa_cnt = falm_cnt->cnt_all;
2219         boolean dfs_mode_en = false, is_performance = true;
2220         u8 rssi_min = dm->rssi_min;
2221         u8 igi_upper_rssi_min = 0;
2222         u8 offset = 15;
2223
2224         if (!(dm->original_dig_restore)) {
2225                 if (tdma_l_igi == 0)
2226                         tdma_l_igi = igi;
2227
2228                 fa_cnt = falm_cnt_acc->cnt_all_1sec;
2229         }
2230
2231         if (phydm_dig_abort(dm)) {
2232                 dig_t->low_ig_value = phydm_get_igi(dm, BB_PATH_A);
2233                 return;
2234         }
2235
2236         /*@Mode Decision*/
2237         dfs_mode_en = false;
2238         is_performance = true;
2239
2240         /* @Abs Boundary Decision*/
2241         dig_t->dm_dig_max = DIG_MAX_COVERAGR; //0x26
2242         dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; //0x20
2243         dig_t->dig_max_of_min = DIG_MAX_OF_MIN_COVERAGE; //0x22
2244
2245         if (dfs_mode_en) {
2246                 if (*dm->band_width == CHANNEL_WIDTH_20)
2247                         dig_t->dm_dig_min = DIG_MIN_DFS + 2;
2248                 else
2249                         dig_t->dm_dig_min = DIG_MIN_DFS;
2250
2251         } else {
2252                 if (dm->support_ic_type &
2253                     (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
2254                         dig_t->dm_dig_min = 0x1c;
2255                 else if (dm->support_ic_type & ODM_RTL8197F)
2256                         dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
2257         }
2258
2259         PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
2260                   dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
2261
2262         /* @Dyn Boundary by RSSI*/
2263         if (!dm->is_linked) {
2264                 /*@if no link, always stay at lower bound*/
2265                 tdma_l_dym_max = 0x26;
2266                 tdma_l_dym_min = dig_t->dm_dig_min;
2267
2268                 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
2269                           tdma_l_dym_max, tdma_l_dym_min);
2270         } else {
2271                 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
2272                           dm->rssi_min, offset);
2273
2274                 /* @DIG lower bound in L-state*/
2275                 tdma_l_dym_min = dig_t->dm_dig_min;
2276
2277 #ifdef CFG_DIG_DAMPING_CHK
2278                 /*@Limit Dyn min by damping*/
2279                 if (dig_t->dig_dl_en &&
2280                     dig_rc->damping_limit_en &&
2281                     tdma_l_dym_min < dig_rc->damping_limit_val) {
2282                         PHYDM_DBG(dm, DBG_DIG,
2283                                   "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
2284                                   tdma_l_dym_min, dig_rc->damping_limit_val);
2285
2286                         tdma_l_dym_min = dig_rc->damping_limit_val;
2287                 }
2288 #endif
2289
2290                 /*@DIG upper bound in L-state*/
2291                 igi_upper_rssi_min = rssi_min + offset;
2292                 if (igi_upper_rssi_min > dig_t->dm_dig_max)
2293                         tdma_l_dym_max = dig_t->dm_dig_max;
2294                 else if (igi_upper_rssi_min < dig_t->dm_dig_min)
2295                         tdma_l_dym_max = dig_t->dm_dig_min;
2296                 else
2297                         tdma_l_dym_max = igi_upper_rssi_min;
2298
2299                 /* @1 Force Lower Bound for AntDiv */
2300                 /*@
2301                  *if (!dm->is_one_entry_only &&
2302                  *(dm->support_ability & ODM_BB_ANT_DIV) &&
2303                  *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
2304                  *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
2305                  *if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
2306                  *      dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
2307                  *else
2308                  *      dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
2309                  *
2310                  *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
2311                  *        dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
2312                  *}
2313                  */
2314
2315                 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
2316                           tdma_l_dym_max, tdma_l_dym_min);
2317         }
2318
2319         /*@Abnormal Case Check*/
2320         /*@Abnormal lower bound case*/
2321         if (tdma_l_dym_min > tdma_l_dym_max)
2322                 tdma_l_dym_min = tdma_l_dym_max;
2323
2324         PHYDM_DBG(dm, DBG_DIG,
2325                   "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
2326                   tdma_l_dym_max, tdma_l_dym_min);
2327
2328         /*@False Alarm Threshold Decision*/
2329         phydm_fa_threshold_check(dm, dfs_mode_en);
2330
2331         /*@Adjust Initial Gain by False Alarm*/
2332         /*Select new IGI by FA */
2333         if (!(dm->original_dig_restore)) {
2334                 tdma_l_igi = get_new_igi_bound(dm, tdma_l_igi, fa_cnt,
2335                                                &tdma_l_dym_max,
2336                                                &tdma_l_dym_min,
2337                                                dfs_mode_en);
2338         } else {
2339                 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
2340         }
2341
2342         /*Update status*/
2343         if (!(dm->original_dig_restore)) {
2344                 dig_t->low_ig_value = tdma_l_igi;
2345                 dig_t->tdma_rx_gain_min[TDMA_DIG_LOW_STATE] = tdma_l_dym_min;
2346                 dig_t->tdma_rx_gain_max[TDMA_DIG_LOW_STATE] = tdma_l_dym_max;
2347 #if 0
2348                 /*odm_write_dig(dm, tdma_l_igi);*/
2349 #endif
2350         } else {
2351                 odm_write_dig(dm, new_igi);
2352         }
2353
2354         dig_t->is_media_connect = dm->is_linked;
2355 }
2356
2357 void phydm_tdma_high_dig(void *dm_void)
2358 {
2359         struct dm_struct *dm = (struct dm_struct *)dm_void;
2360         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2361         struct phydm_fa_struct *falm_cnt = &dm->false_alm_cnt;
2362         struct phydm_fa_acc_struct *falm_cnt_acc = &dm->false_alm_cnt_acc;
2363 #ifdef CFG_DIG_DAMPING_CHK
2364         struct phydm_dig_recorder_strcut *dig_rc = &dig_t->dig_recorder_t;
2365 #endif
2366         boolean first_connect, first_disconnect;
2367         u8 igi = dig_t->cur_ig_value;
2368         u8 new_igi = 0x20;
2369         u8 tdma_h_igi = dig_t->cur_ig_value_tdma;
2370         u8 tdma_h_dym_min = dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE];
2371         u8 tdma_h_dym_max = dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE];
2372         u32 fa_cnt = falm_cnt->cnt_all;
2373         boolean dfs_mode_en = false, is_performance = true;
2374         u8 rssi_min = dm->rssi_min;
2375         u8 igi_upper_rssi_min = 0;
2376         u8 offset = 15;
2377
2378         if (!(dm->original_dig_restore)) {
2379                 if (tdma_h_igi == 0)
2380                         tdma_h_igi = igi;
2381
2382                 fa_cnt = falm_cnt_acc->cnt_all_1sec;
2383         }
2384
2385         if (phydm_dig_abort(dm)) {
2386                 dig_t->cur_ig_value_tdma = phydm_get_igi(dm, BB_PATH_A);
2387                 return;
2388         }
2389
2390         /*@Mode Decision*/
2391         dfs_mode_en = false;
2392         is_performance = true;
2393
2394         /*@Abs Boundary Decision*/
2395         dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE; // 0x2a
2396
2397         if (!dm->is_linked) {
2398                 dig_t->dm_dig_max = DIG_MAX_COVERAGR;
2399                 dig_t->dm_dig_min = DIG_MIN_PERFORMANCE; // 0x20
2400         } else if (dfs_mode_en) {
2401                 if (*dm->band_width == CHANNEL_WIDTH_20)
2402                         dig_t->dm_dig_min = DIG_MIN_DFS + 2;
2403                 else
2404                         dig_t->dm_dig_min = DIG_MIN_DFS;
2405
2406                 dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
2407                 dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
2408         } else {
2409                 if (*dm->bb_op_mode == PHYDM_BALANCE_MODE) {
2410                 /*service > 2 devices*/
2411                         dig_t->dm_dig_max = DIG_MAX_BALANCE_MODE;
2412                         #if (DIG_HW == 1)
2413                         dig_t->dig_max_of_min = DIG_MIN_COVERAGE;
2414                         #else
2415                         dig_t->dig_max_of_min = DIG_MAX_OF_MIN_BALANCE_MODE;
2416                         #endif
2417                 } else if (*dm->bb_op_mode == PHYDM_PERFORMANCE_MODE) {
2418                 /*service 1 devices*/
2419                         dig_t->dm_dig_max = DIG_MAX_PERFORMANCE_MODE;
2420                         dig_t->dig_max_of_min = DIG_MAX_OF_MIN_PERFORMANCE_MODE;
2421                 }
2422
2423                 if (dm->support_ic_type &
2424                     (ODM_RTL8814A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8822B))
2425                         dig_t->dm_dig_min = 0x1c;
2426                 else if (dm->support_ic_type & ODM_RTL8197F)
2427                         dig_t->dm_dig_min = 0x1e; /*@For HW setting*/
2428                 else
2429                         dig_t->dm_dig_min = DIG_MIN_PERFORMANCE;
2430         }
2431         PHYDM_DBG(dm, DBG_DIG, "Abs{Max, Min}={0x%x, 0x%x}, Max_of_min=0x%x\n",
2432                   dig_t->dm_dig_max, dig_t->dm_dig_min, dig_t->dig_max_of_min);
2433
2434         /*@Dyn Boundary by RSSI*/
2435         if (!dm->is_linked) {
2436                 /*@if no link, always stay at lower bound*/
2437                 tdma_h_dym_max = dig_t->dig_max_of_min;
2438                 tdma_h_dym_min = dig_t->dm_dig_min;
2439
2440                 PHYDM_DBG(dm, DBG_DIG, "No-Link, Dyn{Max, Min}={0x%x, 0x%x}\n",
2441                           tdma_h_dym_max, tdma_h_dym_min);
2442         } else {
2443                 PHYDM_DBG(dm, DBG_DIG, "rssi_min=%d, ofst=%d\n",
2444                           dm->rssi_min, offset);
2445
2446                 /* @DIG lower bound in H-state*/
2447                 if (rssi_min < dig_t->dm_dig_min)
2448                         tdma_h_dym_min = dig_t->dm_dig_min;
2449                 else
2450                         tdma_h_dym_min = rssi_min; // turbo not considered yet
2451
2452 #ifdef CFG_DIG_DAMPING_CHK
2453                 /*@Limit Dyn min by damping*/
2454                 if (dig_t->dig_dl_en &&
2455                     dig_rc->damping_limit_en &&
2456                     tdma_h_dym_min < dig_rc->damping_limit_val) {
2457                         PHYDM_DBG(dm, DBG_DIG,
2458                                   "[Limit by Damping] dyn_min=0x%x -> 0x%x\n",
2459                                   tdma_h_dym_min, dig_rc->damping_limit_val);
2460
2461                         tdma_h_dym_min = dig_rc->damping_limit_val;
2462                 }
2463 #endif
2464
2465                 /*@DIG upper bound in H-state*/
2466                 igi_upper_rssi_min = rssi_min + offset;
2467                 if (igi_upper_rssi_min > dig_t->dm_dig_max)
2468                         tdma_h_dym_max = dig_t->dm_dig_max;
2469                 else
2470                         tdma_h_dym_max = igi_upper_rssi_min;
2471
2472                 /* @1 Force Lower Bound for AntDiv */
2473                 /*@
2474                  *if (!dm->is_one_entry_only &&
2475                  *(dm->support_ability & ODM_BB_ANT_DIV) &&
2476                  *(dm->ant_div_type == CG_TRX_HW_ANTDIV ||
2477                  *dm->ant_div_type == CG_TRX_SMART_ANTDIV)) {
2478                  *      if (dig_t->ant_div_rssi_max > dig_t->dig_max_of_min)
2479                  *      dig_t->rx_gain_range_min = dig_t->dig_max_of_min;
2480                  *      else
2481                  *      dig_t->rx_gain_range_min = (u8)dig_t->ant_div_rssi_max;
2482                  */
2483                 /*@
2484                  *PHYDM_DBG(dm, DBG_DIG, "Force Dyn-Min=0x%x, RSSI_max=0x%x\n",
2485                  *        dig_t->rx_gain_range_min, dig_t->ant_div_rssi_max);
2486                  *}
2487                  */
2488                 PHYDM_DBG(dm, DBG_DIG, "Dyn{Max, Min}={0x%x, 0x%x}\n",
2489                           tdma_h_dym_max, tdma_h_dym_min);
2490         }
2491
2492         /*@Abnormal Case Check*/
2493         /*@Abnormal low higher bound case*/
2494         if (tdma_h_dym_max < dig_t->dm_dig_min)
2495                 tdma_h_dym_max = dig_t->dm_dig_min;
2496         /*@Abnormal lower bound case*/
2497         if (tdma_h_dym_min > tdma_h_dym_max)
2498                 tdma_h_dym_min = tdma_h_dym_max;
2499
2500         PHYDM_DBG(dm, DBG_DIG, "Abnoraml chk, force {Max, Min}={0x%x, 0x%x}\n",
2501                   tdma_h_dym_max, tdma_h_dym_min);
2502
2503         /*@False Alarm Threshold Decision*/
2504         phydm_fa_threshold_check(dm, dfs_mode_en);
2505
2506         /*@Adjust Initial Gain by False Alarm*/
2507         /*Select new IGI by FA */
2508         if (!(dm->original_dig_restore)) {
2509                 tdma_h_igi = get_new_igi_bound(dm, tdma_h_igi, fa_cnt,
2510                                                &tdma_h_dym_max,
2511                                                &tdma_h_dym_min,
2512                                                dfs_mode_en);
2513         } else {
2514                 new_igi = phydm_get_new_igi(dm, igi, fa_cnt, dfs_mode_en);
2515         }
2516
2517         /*Update status*/
2518         if (!(dm->original_dig_restore)) {
2519                 dig_t->cur_ig_value_tdma = tdma_h_igi;
2520                 dig_t->tdma_rx_gain_min[TDMA_DIG_HIGH_STATE] = tdma_h_dym_min;
2521                 dig_t->tdma_rx_gain_max[TDMA_DIG_HIGH_STATE] = tdma_h_dym_max;
2522 #if 0
2523                 /*odm_write_dig(dm, tdma_h_igi);*/
2524 #endif
2525         } else {
2526                 odm_write_dig(dm, new_igi);
2527         }
2528
2529         dig_t->is_media_connect = dm->is_linked;
2530 }
2531
2532 void phydm_fa_cnt_acc(void *dm_void, boolean rssi_dump_en,
2533                       u8 cur_tdma_dig_state)
2534 {
2535         struct dm_struct *dm = (struct dm_struct *)dm_void;
2536         struct phydm_fa_struct *falm_cnt = NULL;
2537         struct phydm_fa_acc_struct *falm_cnt_acc = NULL;
2538         struct phydm_dig_struct *dig_t = NULL;
2539         u8 factor_num = 0;
2540         u8 factor_denum = 1;
2541         u8 total_state_number;
2542
2543         dig_t = &dm->dm_dig_table;
2544         falm_cnt = &dm->false_alm_cnt;
2545 #ifdef IS_USE_NEW_TDMA
2546         if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE)
2547                 falm_cnt_acc = &dm->false_alm_cnt_acc_low;
2548         else if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE)
2549 #endif
2550                 falm_cnt_acc = &dm->false_alm_cnt_acc;
2551         /*@
2552          *PHYDM_DBG(dm, DBG_DIG,
2553          *        "[%s] ==> dig_state=%d, one_sec=%d\n", __func__,
2554          *        cur_tdma_dig_state, rssi_dump_en);
2555          */
2556         falm_cnt_acc->cnt_parity_fail += falm_cnt->cnt_parity_fail;
2557         falm_cnt_acc->cnt_rate_illegal += falm_cnt->cnt_rate_illegal;
2558         falm_cnt_acc->cnt_crc8_fail += falm_cnt->cnt_crc8_fail;
2559         falm_cnt_acc->cnt_mcs_fail += falm_cnt->cnt_mcs_fail;
2560         falm_cnt_acc->cnt_ofdm_fail += falm_cnt->cnt_ofdm_fail;
2561         falm_cnt_acc->cnt_cck_fail += falm_cnt->cnt_cck_fail;
2562         falm_cnt_acc->cnt_all += falm_cnt->cnt_all;
2563         falm_cnt_acc->cnt_fast_fsync += falm_cnt->cnt_fast_fsync;
2564         falm_cnt_acc->cnt_sb_search_fail += falm_cnt->cnt_sb_search_fail;
2565         falm_cnt_acc->cnt_ofdm_cca += falm_cnt->cnt_ofdm_cca;
2566         falm_cnt_acc->cnt_cck_cca += falm_cnt->cnt_cck_cca;
2567         falm_cnt_acc->cnt_cca_all += falm_cnt->cnt_cca_all;
2568         falm_cnt_acc->cnt_cck_crc32_error += falm_cnt->cnt_cck_crc32_error;
2569         falm_cnt_acc->cnt_cck_crc32_ok += falm_cnt->cnt_cck_crc32_ok;
2570         falm_cnt_acc->cnt_ofdm_crc32_error += falm_cnt->cnt_ofdm_crc32_error;
2571         falm_cnt_acc->cnt_ofdm_crc32_ok += falm_cnt->cnt_ofdm_crc32_ok;
2572         falm_cnt_acc->cnt_ht_crc32_error += falm_cnt->cnt_ht_crc32_error;
2573         falm_cnt_acc->cnt_ht_crc32_ok += falm_cnt->cnt_ht_crc32_ok;
2574         falm_cnt_acc->cnt_vht_crc32_error += falm_cnt->cnt_vht_crc32_error;
2575         falm_cnt_acc->cnt_vht_crc32_ok += falm_cnt->cnt_vht_crc32_ok;
2576         falm_cnt_acc->cnt_crc32_error_all += falm_cnt->cnt_crc32_error_all;
2577         falm_cnt_acc->cnt_crc32_ok_all += falm_cnt->cnt_crc32_ok_all;
2578
2579         /*@
2580          *PHYDM_DBG(dm, DBG_DIG,
2581          *      "[CCA Cnt]     {CCK, OFDM, Total} = {%d, %d, %d}\n",
2582          *      falm_cnt->cnt_cck_cca,
2583          *      falm_cnt->cnt_ofdm_cca,
2584          *      falm_cnt->cnt_cca_all);
2585          *PHYDM_DBG(dm, DBG_DIG,
2586          *      "[FA Cnt]      {CCK, OFDM, Total} = {%d, %d, %d}\n",
2587          *      falm_cnt->cnt_cck_fail,
2588          *      falm_cnt->cnt_ofdm_fail,
2589          *      falm_cnt->cnt_all);
2590          */
2591         if (rssi_dump_en == 1) {
2592                 total_state_number = dm->tdma_dig_state_number;
2593
2594                 if (cur_tdma_dig_state == TDMA_DIG_HIGH_STATE) {
2595                         factor_num = total_state_number;
2596                         factor_denum = total_state_number - 1;
2597                 } else if (cur_tdma_dig_state == TDMA_DIG_LOW_STATE) {
2598                         factor_num = total_state_number;
2599                         factor_denum = 1;
2600                 }
2601
2602                 falm_cnt_acc->cnt_all_1sec =
2603                         falm_cnt_acc->cnt_all * factor_num / factor_denum;
2604                 falm_cnt_acc->cnt_cca_all_1sec =
2605                         falm_cnt_acc->cnt_cca_all * factor_num / factor_denum;
2606                 falm_cnt_acc->cnt_cck_fail_1sec =
2607                         falm_cnt_acc->cnt_cck_fail * factor_num / factor_denum;
2608                 /*@
2609                  *PHYDM_DBG(dm, DBG_DIG,
2610                  *      "[ACC CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
2611                  *      falm_cnt_acc->cnt_cck_cca,
2612                  *      falm_cnt_acc->cnt_ofdm_cca,
2613                  *      falm_cnt_acc->cnt_cca_all);
2614                  *PHYDM_DBG(dm, DBG_DIG,
2615                  *      "[ACC FA Cnt]  {CCK, OFDM, Total} = {%d, %d, %d}\n\n",
2616                  *      falm_cnt_acc->cnt_cck_fail,
2617                  *      falm_cnt_acc->cnt_ofdm_fail,
2618                  *      falm_cnt_acc->cnt_all);
2619                  */
2620         }
2621 }
2622 #endif /*@#ifdef IS_USE_NEW_TDMA*/
2623 #endif /*@#ifdef PHYDM_TDMA_DIG_SUPPORT*/
2624
2625 void phydm_dig_debug(void *dm_void, char input[][16], u32 *_used, char *output,
2626                      u32 *_out_len)
2627 {
2628         struct dm_struct *dm = (struct dm_struct *)dm_void;
2629         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2630         char help[] = "-h";
2631         char monitor[] = "-m";
2632         u32 var1[10] = {0};
2633         u32 used = *_used;
2634         u32 out_len = *_out_len;
2635         u8 i;
2636
2637         if ((strcmp(input[1], help) == 0)) {
2638                 PDM_SNPF(out_len, used, output + used, out_len - used,
2639                          "{0} {en} fa_th[0] fa_th[1] fa_th[2]\n");
2640                 PDM_SNPF(out_len, used, output + used, out_len - used,
2641                          "{1} {Damping Limit en}\n");
2642         } else if ((strcmp(input[1], monitor) == 0)) {
2643                 PDM_SNPF(out_len, used, output + used, out_len - used,
2644                          "Read DIG fa_th[0:2]= {%d, %d, %d}\n", dig_t->fa_th[0],
2645                          dig_t->fa_th[1], dig_t->fa_th[2]);
2646
2647         } else {
2648                 PHYDM_SSCANF(input[1], DCMD_DECIMAL, &var1[0]);
2649
2650                 for (i = 1; i < 10; i++)
2651                         PHYDM_SSCANF(input[i + 1], DCMD_DECIMAL, &var1[i]);
2652
2653                 if (var1[0] == 0) {
2654                         if (var1[1] == 1) {
2655                                 dig_t->is_dbg_fa_th = true;
2656                                 dig_t->fa_th[0] = (u16)var1[2];
2657                                 dig_t->fa_th[1] = (u16)var1[3];
2658                                 dig_t->fa_th[2] = (u16)var1[4];
2659
2660                                 PDM_SNPF(out_len, used, output + used,
2661                                          out_len - used,
2662                                          "Set DIG fa_th[0:2]= {%d, %d, %d}\n",
2663                                          dig_t->fa_th[0], dig_t->fa_th[1],
2664                                          dig_t->fa_th[2]);
2665                         } else {
2666                                 dig_t->is_dbg_fa_th = false;
2667                         }
2668                 }
2669                 #ifdef CFG_DIG_DAMPING_CHK
2670                 else if (var1[0] == 1) {
2671                         dig_t->dig_dl_en = (u8)var1[1];
2672                         /*@*/
2673                 }
2674                 #endif
2675         }
2676         *_used = used;
2677         *_out_len = out_len;
2678 }
2679
2680 #ifdef CONFIG_MCC_DM
2681 #if (RTL8822B_SUPPORT)
2682 void phydm_mcc_igi_clr(void *dm_void, u8 clr_port)
2683 {
2684         struct dm_struct *dm = (struct dm_struct *)dm_void;
2685         struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
2686         mcc_dm->mcc_rssi[clr_port] = 0xff;
2687         mcc_dm->mcc_dm_val[0][clr_port] = 0xff; /* 0xc50 clr */
2688         mcc_dm->mcc_dm_val[1][clr_port] = 0xff; /* 0xe50 clr */
2689 }
2690
2691 void phydm_mcc_igi_chk(void *dm_void)
2692 {
2693         struct dm_struct *dm = (struct dm_struct *)dm_void;
2694         struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
2695
2696         if (mcc_dm->mcc_dm_val[0][0] == 0xff &&
2697             mcc_dm->mcc_dm_val[0][1] == 0xff) {
2698                 mcc_dm->mcc_dm_reg[0] = 0xffff;
2699                 mcc_dm->mcc_reg_id[0] = 0xff;
2700         }
2701         if (mcc_dm->mcc_dm_val[1][0] == 0xff &&
2702             mcc_dm->mcc_dm_val[1][1] == 0xff) {
2703                 mcc_dm->mcc_dm_reg[1] = 0xffff;
2704                 mcc_dm->mcc_reg_id[1] = 0xff;
2705         }
2706 }
2707
2708 void phydm_mcc_igi_cal(void *dm_void)
2709 {
2710         struct dm_struct *dm = (struct dm_struct *)dm_void;
2711         struct _phydm_mcc_dm_ *mcc_dm = &dm->mcc_dm;
2712         struct phydm_dig_struct *dig_t = &dm->dm_dig_table;
2713         u8      shift = 0;
2714         u8      igi_val0, igi_val1;
2715         if (mcc_dm->mcc_rssi[0] == 0xff)
2716                 phydm_mcc_igi_clr(dm, 0);
2717         if (mcc_dm->mcc_rssi[1] == 0xff)
2718                 phydm_mcc_igi_clr(dm, 1);
2719         phydm_mcc_igi_chk(dm);
2720         igi_val0 = mcc_dm->mcc_rssi[0] - shift;
2721         igi_val1 = mcc_dm->mcc_rssi[1] - shift;
2722         phydm_fill_mcccmd(dm, 0, 0xc50, igi_val0, igi_val1);
2723         phydm_fill_mcccmd(dm, 1, 0xe50, igi_val0, igi_val1);
2724         PHYDM_DBG(dm, DBG_COMP_MCC, "RSSI_min: %d %d, MCC_igi: %d %d\n",
2725                   mcc_dm->mcc_rssi[0], mcc_dm->mcc_rssi[1],
2726                   mcc_dm->mcc_dm_val[0][0], mcc_dm->mcc_dm_val[0][1]);
2727 }
2728 #endif /*#if (RTL8822B_SUPPORT)*/
2729 #endif /*#ifdef CONFIG_MCC_DM*/