1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
21 /* ************************************************************
23 * ************************************************************ */
24 #include "mp_precomp.h"
25 #include "phydm_precomp.h"
27 #if (CONFIG_DYNAMIC_RX_PATH == 1)
30 phydm_process_phy_status_for_dynamic_rx_path(
32 void *p_phy_info_void,
36 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
37 struct _odm_phy_status_info_ *p_phy_info = (struct _odm_phy_status_info_ *)p_phy_info_void;
38 struct _odm_per_pkt_info_ *p_pktinfo = (struct _odm_per_pkt_info_ *)p_pkt_info_void;
39 struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
47 phydm_drp_get_statistic(
51 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
52 struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
53 struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
55 odm_false_alarm_counter_statistics(p_dm_odm);
57 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[CCA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
58 false_alm_cnt->cnt_cck_cca, false_alm_cnt->cnt_ofdm_cca, false_alm_cnt->cnt_cca_all));
60 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[FA Cnt] {CCK, OFDM, Total} = {%d, %d, %d}\n",
61 false_alm_cnt->cnt_cck_fail, false_alm_cnt->cnt_ofdm_fail, false_alm_cnt->cnt_all));
65 phydm_dynamic_rx_path(
69 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
70 struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
71 u8 training_set_timmer_en;
75 struct _FALSE_ALARM_STATISTICS *false_alm_cnt = (struct _FALSE_ALARM_STATISTICS *)phydm_get_structure(p_dm_odm, PHYDM_FALSEALMCNT);
77 if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) {
78 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Return Init] Not Support Dynamic RX PAth\n"));
82 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("Current drp_state = ((%d))\n", p_dm_drp_table->drp_state));
84 curr_drp_state = p_dm_drp_table->drp_state;
86 if (p_dm_drp_table->drp_state == DRP_INIT_STATE) {
88 phydm_drp_get_statistic(p_dm_odm);
90 if (false_alm_cnt->cnt_crc32_ok_all > 20) {
91 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Stop DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all));
92 p_dm_drp_table->drp_state = DRP_INIT_STATE;
93 training_set_timmer_en = false;
95 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Start DRP Training] cnt_crc32_ok_all = ((%d))\n", false_alm_cnt->cnt_crc32_ok_all));
96 p_dm_drp_table->drp_state = DRP_TRAINING_STATE_0;
97 p_dm_drp_table->curr_rx_path = PHYDM_AB;
98 training_set_timmer_en = true;
101 } else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_0) {
103 phydm_drp_get_statistic(p_dm_odm);
105 p_dm_drp_table->curr_cca_all_cnt_0 = false_alm_cnt->cnt_cca_all;
106 p_dm_drp_table->curr_fa_all_cnt_0 = false_alm_cnt->cnt_all;
108 p_dm_drp_table->drp_state = DRP_TRAINING_STATE_1;
109 p_dm_drp_table->curr_rx_path = PHYDM_B;
110 training_set_timmer_en = true;
112 } else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_1) {
114 phydm_drp_get_statistic(p_dm_odm);
116 p_dm_drp_table->curr_cca_all_cnt_1 = false_alm_cnt->cnt_cca_all;
117 p_dm_drp_table->curr_fa_all_cnt_1 = false_alm_cnt->cnt_all;
120 p_dm_drp_table->drp_state = DRP_DECISION_STATE;
123 if (p_dm_odm->mp_mode) {
124 rx_ok_cal = p_dm_odm->phy_dbg_info.num_qry_phy_status_cck + p_dm_odm->phy_dbg_info.num_qry_phy_status_ofdm;
125 RSSI = (rx_ok_cal != 0) ? p_dm_odm->rx_pwdb_ave / rx_ok_cal : 0;
126 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("MP RSSI = ((%d))\n", RSSI));
129 if (RSSI > p_dm_drp_table->rssi_threshold)
131 p_dm_drp_table->drp_state = DRP_DECISION_STATE;
135 p_dm_drp_table->drp_state = DRP_TRAINING_STATE_2;
136 p_dm_drp_table->curr_rx_path = PHYDM_A;
137 training_set_timmer_en = true;
140 } else if (p_dm_drp_table->drp_state == DRP_TRAINING_STATE_2) {
142 phydm_drp_get_statistic(p_dm_odm);
144 p_dm_drp_table->curr_cca_all_cnt_2 = false_alm_cnt->cnt_cca_all;
145 p_dm_drp_table->curr_fa_all_cnt_2 = false_alm_cnt->cnt_all;
146 p_dm_drp_table->drp_state = DRP_DECISION_STATE;
149 if (p_dm_drp_table->drp_state == DRP_DECISION_STATE) {
151 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("Current drp_state = ((%d))\n", p_dm_drp_table->drp_state));
153 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[0] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_0, p_dm_drp_table->curr_fa_all_cnt_0));
154 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[1] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_1, p_dm_drp_table->curr_fa_all_cnt_1));
155 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[2] {CCA, FA} = {%d, %d}\n", p_dm_drp_table->curr_cca_all_cnt_2, p_dm_drp_table->curr_fa_all_cnt_2));
157 if (p_dm_drp_table->curr_fa_all_cnt_1 < p_dm_drp_table->curr_fa_all_cnt_0) {
159 if ((p_dm_drp_table->curr_fa_all_cnt_0 - p_dm_drp_table->curr_fa_all_cnt_1) > p_dm_drp_table->fa_diff_threshold)
160 p_dm_drp_table->curr_rx_path = PHYDM_B;
162 p_dm_drp_table->curr_rx_path = PHYDM_AB;
164 p_dm_drp_table->curr_rx_path = PHYDM_AB;
166 phydm_config_ofdm_rx_path(p_dm_odm, p_dm_drp_table->curr_rx_path);
167 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Training Result] curr_rx_path = ((%s%s)),\n",
168 ((p_dm_drp_table->curr_rx_path & PHYDM_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & PHYDM_B) ? "B" : " ")));
170 p_dm_drp_table->drp_state = DRP_INIT_STATE;
171 training_set_timmer_en = false;
174 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("DRP_state: ((%d)) -> ((%d))\n", curr_drp_state, p_dm_drp_table->drp_state));
176 if (training_set_timmer_en) {
178 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Training en] curr_rx_path = ((%s%s)), training_time = ((%d ms))\n",
179 ((p_dm_drp_table->curr_rx_path & PHYDM_A) ? "A" : " "), ((p_dm_drp_table->curr_rx_path & PHYDM_B) ? "B" : " "), p_dm_drp_table->training_time));
181 phydm_config_ofdm_rx_path(p_dm_odm, p_dm_drp_table->curr_rx_path);
182 odm_set_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer), p_dm_drp_table->training_time); /*ms*/
184 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("DRP period end\n\n", curr_drp_state, p_dm_drp_table->drp_state));
188 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
190 phydm_dynamic_rx_path_callback(
191 struct timer_list *p_timer
194 struct _ADAPTER *adapter = (struct _ADAPTER *)p_timer->adapter;
195 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(adapter);
196 struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->DM_OutSrc);
197 struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
199 #if DEV_BUS_TYPE == RT_PCI_INTERFACE
201 odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem));
204 /* dbg_print("phydm_dynamic_rx_path\n"); */
205 phydm_dynamic_rx_path(p_dm_odm);
209 odm_schedule_work_item(&(p_dm_drp_table->phydm_dynamic_rx_path_workitem));
214 phydm_dynamic_rx_path_workitem_callback(
218 struct _ADAPTER *p_adapter = (struct _ADAPTER *)p_context;
219 HAL_DATA_TYPE *p_hal_data = GET_HAL_DATA(p_adapter);
220 struct PHY_DM_STRUCT *p_dm_odm = &(p_hal_data->DM_OutSrc);
222 /* dbg_print("phydm_dynamic_rx_path\n"); */
223 phydm_dynamic_rx_path(p_dm_odm);
225 #else if (DM_ODM_SUPPORT_TYPE == ODM_CE)
228 phydm_dynamic_rx_path_callback(
229 void *function_context
232 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)function_context;
233 struct _ADAPTER *padapter = p_dm_odm->adapter;
235 if (padapter->net_closed == _TRUE)
238 #if 0 /* Can't do I/O in timer callback*/
239 odm_s0s1_sw_ant_div(p_dm_odm, SWAW_STEP_DETERMINE);
241 /*rtw_run_in_thread_cmd(padapter, odm_sw_antdiv_workitem_callback, padapter);*/
248 phydm_dynamic_rx_path_timers(
253 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
254 struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
256 if (state == INIT_DRP_TIMMER) {
258 odm_initialize_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer),
259 (void *)phydm_dynamic_rx_path_callback, NULL, "phydm_sw_antenna_switch_timer");
260 } else if (state == CANCEL_DRP_TIMMER)
262 odm_cancel_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer));
264 else if (state == RELEASE_DRP_TIMMER)
266 odm_release_timer(p_dm_odm, &(p_dm_drp_table->phydm_dynamic_rx_path_timer));
271 phydm_dynamic_rx_path_init(
275 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
276 struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
279 if (!(p_dm_odm->support_ability & ODM_BB_DYNAMIC_RX_PATH)) {
280 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("[Return] Not Support Dynamic RX PAth\n"));
283 ODM_RT_TRACE(p_dm_odm, ODM_COMP_DYNAMIC_RX_PATH, ODM_DBG_LOUD, ("phydm_dynamic_rx_path_init\n"));
285 p_dm_drp_table->drp_state = DRP_INIT_STATE;
286 p_dm_drp_table->rssi_threshold = DRP_RSSI_TH;
287 p_dm_drp_table->fa_count_thresold = 50;
288 p_dm_drp_table->fa_diff_threshold = 50;
289 p_dm_drp_table->training_time = 100; /*ms*/
290 p_dm_drp_table->drp_skip_counter = 0;
291 p_dm_drp_table->drp_period = 0;
292 p_dm_drp_table->drp_init_finished = true;
294 ret_value = phydm_api_trx_mode(p_dm_odm, (enum odm_rf_path_e)(ODM_RF_A | ODM_RF_B), (enum odm_rf_path_e)(ODM_RF_A | ODM_RF_B), true);
307 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
309 u32 out_len = *_out_len;
310 struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
312 switch (dm_value[0]) {
314 case DRP_TRAINING_TIME:
315 p_dm_drp_table->training_time = (u16)dm_value[1];
317 case DRP_TRAINING_PERIOD:
318 p_dm_drp_table->drp_period = (u8)dm_value[1];
320 case DRP_RSSI_THRESHOLD:
321 p_dm_drp_table->rssi_threshold = (u8)dm_value[1];
323 case DRP_FA_THRESHOLD:
324 p_dm_drp_table->fa_count_thresold = dm_value[1];
326 case DRP_FA_DIFF_THRESHOLD:
327 p_dm_drp_table->fa_diff_threshold = dm_value[1];
330 PHYDM_SNPRINTF((output + used, out_len - used, "[DRP] unknown command\n"));
336 phydm_dynamic_rx_path_caller(
340 struct PHY_DM_STRUCT *p_dm_odm = (struct PHY_DM_STRUCT *)p_dm_void;
341 struct _DYNAMIC_RX_PATH_ *p_dm_drp_table = &(p_dm_odm->dm_drp_table);
343 if (p_dm_drp_table->drp_skip_counter < p_dm_drp_table->drp_period)
344 p_dm_drp_table->drp_skip_counter++;
346 p_dm_drp_table->drp_skip_counter = 0;
348 if (p_dm_drp_table->drp_skip_counter != 0)
351 if (p_dm_drp_table->drp_init_finished != true)
354 phydm_dynamic_rx_path(p_dm_odm);