rtl8821ce/hal/phydm/phydm_pre_define.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2017  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __PHYDMPREDEFINE_H__
  27 #define __PHYDMPREDEFINE_H__
  28
  29 /****************************************************************
  30  * 1 ============================================================
  31  * 1  Definition
  32  * 1 ============================================================
  33  ***************************************************************/
  34
  35 #define PHYDM_CODE_BASE                 "PHYDM_V030"
  36 #define PHYDM_RELEASE_DATE              "20180605.0"
  37
  38 /*PHYDM API status*/
  39 #define PHYDM_SET_FAIL                  0
  40 #define PHYDM_SET_SUCCESS               1
  41 #define PHYDM_SET_NO_NEED               3
  42
  43 /*PHYDM Set/Revert*/
  44 #define PHYDM_SET                       1
  45 #define PHYDM_REVERT                    2
  46
  47 /* @Max path of IC */
  48 /*N-IC*/
  49 #define MAX_PATH_NUM_8188E              1
  50 #define MAX_PATH_NUM_8188F              1
  51 #define MAX_PATH_NUM_8710B              1
  52 #define MAX_PATH_NUM_8723B              1
  53 #define MAX_PATH_NUM_8723D              1
  54 #define MAX_PATH_NUM_8703B              1
  55 #define MAX_PATH_NUM_8192E              2
  56 #define MAX_PATH_NUM_8192F              2
  57 #define MAX_PATH_NUM_8197F              2
  58 #define MAX_PATH_NUM_8198F              4
  59 /*@AC-IC*/
  60 #define MAX_PATH_NUM_8821A              1
  61 #define MAX_PATH_NUM_8881A              1
  62 #define MAX_PATH_NUM_8821C              1
  63 #define MAX_PATH_NUM_8195B              1
  64 #define MAX_PATH_NUM_8812A              2
  65 #define MAX_PATH_NUM_8822B              2
  66 #define MAX_PATH_NUM_8822C              2
  67 #define MAX_PATH_NUM_8814A              4
  68 #define MAX_PATH_NUM_8814B              4
  69 #define MAX_PATH_NUM_8814C              4
  70 #define MAX_PATH_NUM_8195B              1
  71
  72 /* @Max RF path */
  73 #define PHYDM_MAX_RF_PATH_N             2       /*@For old N-series IC*/
  74 #define PHYDM_MAX_RF_PATH               4
  75
  76 /* number of entry */
  77 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
  78         #ifdef DM_ODM_CE_MAC80211
  79                 /* @defined in wifi.h (32+1) */
  80         #else
  81                 #define ASSOCIATE_ENTRY_NUM     MACID_NUM_SW_LIMIT  /* @Max size of asoc_entry[].*/
  82         #endif
  83         #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
  84 #elif(DM_ODM_SUPPORT_TYPE & (ODM_AP))
  85         #define ASSOCIATE_ENTRY_NUM     NUM_STAT
  86         #define ODM_ASSOCIATE_ENTRY_NUM (ASSOCIATE_ENTRY_NUM + 1)
  87 #elif(DM_ODM_SUPPORT_TYPE & (ODM_IOT))
  88         #ifdef CONFIG_CONCURRENT_MODE
  89                 #define ASSOCIATE_ENTRY_NUM     NUM_STA + 2 /*@2 is for station mod*/
  90         #else
  91                 #define ASSOCIATE_ENTRY_NUM     NUM_STA /*@8 is for max size of asoc_entry[].*/
  92         #endif
  93         #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
  94 #else
  95         #define ODM_ASSOCIATE_ENTRY_NUM (((ASSOCIATE_ENTRY_NUM + 1) * 3) + 1)
  96 #endif
  97
  98 /* @-----MGN rate--------------------------------- */
  99
 100 enum PDM_RATE_TYPE {
 101         PDM_1SS                 = 1,    /*VHT/HT 1SS*/
 102         PDM_2SS                 = 2,    /*VHT/HT 2SS*/
 103         PDM_3SS                 = 3,    /*VHT/HT 3SS*/
 104         PDM_4SS                 = 4,    /*VHT/HT 4SS*/
 105         PDM_CCK                 = 11,   /*@B*/
 106         PDM_OFDM                = 12    /*@G*/
 107 };
 108
 109 enum ODM_MGN_RATE {
 110         ODM_MGN_1M              = 0x02,
 111         ODM_MGN_2M              = 0x04,
 112         ODM_MGN_5_5M            = 0x0B,
 113         ODM_MGN_6M              = 0x0C,
 114         ODM_MGN_9M              = 0x12,
 115         ODM_MGN_11M             = 0x16,
 116         ODM_MGN_12M             = 0x18,
 117         ODM_MGN_18M             = 0x24,
 118         ODM_MGN_24M             = 0x30,
 119         ODM_MGN_36M             = 0x48,
 120         ODM_MGN_48M             = 0x60,
 121         ODM_MGN_54M             = 0x6C,
 122         ODM_MGN_MCS32           = 0x7F,
 123         ODM_MGN_MCS0            = 0x80,
 124         ODM_MGN_MCS1,
 125         ODM_MGN_MCS2,
 126         ODM_MGN_MCS3,
 127         ODM_MGN_MCS4,
 128         ODM_MGN_MCS5,
 129         ODM_MGN_MCS6,
 130         ODM_MGN_MCS7            = 0x87,
 131         ODM_MGN_MCS8,
 132         ODM_MGN_MCS9,
 133         ODM_MGN_MCS10,
 134         ODM_MGN_MCS11,
 135         ODM_MGN_MCS12,
 136         ODM_MGN_MCS13,
 137         ODM_MGN_MCS14,
 138         ODM_MGN_MCS15,
 139         ODM_MGN_MCS16           = 0x90,
 140         ODM_MGN_MCS17,
 141         ODM_MGN_MCS18,
 142         ODM_MGN_MCS19,
 143         ODM_MGN_MCS20,
 144         ODM_MGN_MCS21,
 145         ODM_MGN_MCS22,
 146         ODM_MGN_MCS23,
 147         ODM_MGN_MCS24           = 0x98,
 148         ODM_MGN_MCS25,
 149         ODM_MGN_MCS26,
 150         ODM_MGN_MCS27,
 151         ODM_MGN_MCS28,
 152         ODM_MGN_MCS29,
 153         ODM_MGN_MCS30,
 154         ODM_MGN_MCS31,
 155         ODM_MGN_VHT1SS_MCS0     = 0xa0,
 156         ODM_MGN_VHT1SS_MCS1,
 157         ODM_MGN_VHT1SS_MCS2,
 158         ODM_MGN_VHT1SS_MCS3,
 159         ODM_MGN_VHT1SS_MCS4,
 160         ODM_MGN_VHT1SS_MCS5,
 161         ODM_MGN_VHT1SS_MCS6,
 162         ODM_MGN_VHT1SS_MCS7,
 163         ODM_MGN_VHT1SS_MCS8,
 164         ODM_MGN_VHT1SS_MCS9,
 165         ODM_MGN_VHT2SS_MCS0     = 0xaa,
 166         ODM_MGN_VHT2SS_MCS1     = 0xab,
 167         ODM_MGN_VHT2SS_MCS2,
 168         ODM_MGN_VHT2SS_MCS3,
 169         ODM_MGN_VHT2SS_MCS4,
 170         ODM_MGN_VHT2SS_MCS5     = 0xaf,
 171         ODM_MGN_VHT2SS_MCS6     = 0xb0,
 172         ODM_MGN_VHT2SS_MCS7,
 173         ODM_MGN_VHT2SS_MCS8,
 174         ODM_MGN_VHT2SS_MCS9     = 0xb3,
 175         ODM_MGN_VHT3SS_MCS0     = 0xb4,
 176         ODM_MGN_VHT3SS_MCS1,
 177         ODM_MGN_VHT3SS_MCS2,
 178         ODM_MGN_VHT3SS_MCS3,
 179         ODM_MGN_VHT3SS_MCS4,
 180         ODM_MGN_VHT3SS_MCS5,
 181         ODM_MGN_VHT3SS_MCS6,
 182         ODM_MGN_VHT3SS_MCS7     = 0xbb,
 183         ODM_MGN_VHT3SS_MCS8     = 0xbc,
 184         ODM_MGN_VHT3SS_MCS9     = 0xbd,
 185         ODM_MGN_VHT4SS_MCS0     = 0xbe,
 186         ODM_MGN_VHT4SS_MCS1,
 187         ODM_MGN_VHT4SS_MCS2,
 188         ODM_MGN_VHT4SS_MCS3,
 189         ODM_MGN_VHT4SS_MCS4,
 190         ODM_MGN_VHT4SS_MCS5,
 191         ODM_MGN_VHT4SS_MCS6,
 192         ODM_MGN_VHT4SS_MCS7,
 193         ODM_MGN_VHT4SS_MCS8,
 194         ODM_MGN_VHT4SS_MCS9     = 0xc7,
 195         ODM_MGN_UNKNOWN
 196 };
 197
 198 #define ODM_MGN_MCS0_SG         0xc0
 199 #define ODM_MGN_MCS1_SG         0xc1
 200 #define ODM_MGN_MCS2_SG         0xc2
 201 #define ODM_MGN_MCS3_SG         0xc3
 202 #define ODM_MGN_MCS4_SG         0xc4
 203 #define ODM_MGN_MCS5_SG         0xc5
 204 #define ODM_MGN_MCS6_SG         0xc6
 205 #define ODM_MGN_MCS7_SG         0xc7
 206 #define ODM_MGN_MCS8_SG         0xc8
 207 #define ODM_MGN_MCS9_SG         0xc9
 208 #define ODM_MGN_MCS10_SG        0xca
 209 #define ODM_MGN_MCS11_SG        0xcb
 210 #define ODM_MGN_MCS12_SG        0xcc
 211 #define ODM_MGN_MCS13_SG        0xcd
 212 #define ODM_MGN_MCS14_SG        0xce
 213 #define ODM_MGN_MCS15_SG        0xcf
 214
 215 /* @-----DESC rate--------------------------------- */
 216
 217 #define ODM_RATEMCS15_SG        0x1c
 218 #define ODM_RATEMCS32           0x20
 219
 220 enum phydm_ctrl_info_rate {
 221         ODM_RATE1M              = 0x00,
 222         ODM_RATE2M              = 0x01,
 223         ODM_RATE5_5M            = 0x02,
 224         ODM_RATE11M             = 0x03,
 225 /* OFDM Rates, TxHT = 0 */
 226         ODM_RATE6M              = 0x04,
 227         ODM_RATE9M              = 0x05,
 228         ODM_RATE12M             = 0x06,
 229         ODM_RATE18M             = 0x07,
 230         ODM_RATE24M             = 0x08,
 231         ODM_RATE36M             = 0x09,
 232         ODM_RATE48M             = 0x0A,
 233         ODM_RATE54M             = 0x0B,
 234 /* @MCS Rates, TxHT = 1 */
 235         ODM_RATEMCS0            = 0x0C,
 236         ODM_RATEMCS1            = 0x0D,
 237         ODM_RATEMCS2            = 0x0E,
 238         ODM_RATEMCS3            = 0x0F,
 239         ODM_RATEMCS4            = 0x10,
 240         ODM_RATEMCS5            = 0x11,
 241         ODM_RATEMCS6            = 0x12,
 242         ODM_RATEMCS7            = 0x13,
 243         ODM_RATEMCS8            = 0x14,
 244         ODM_RATEMCS9            = 0x15,
 245         ODM_RATEMCS10           = 0x16,
 246         ODM_RATEMCS11           = 0x17,
 247         ODM_RATEMCS12           = 0x18,
 248         ODM_RATEMCS13           = 0x19,
 249         ODM_RATEMCS14           = 0x1A,
 250         ODM_RATEMCS15           = 0x1B,
 251         ODM_RATEMCS16           = 0x1C,
 252         ODM_RATEMCS17           = 0x1D,
 253         ODM_RATEMCS18           = 0x1E,
 254         ODM_RATEMCS19           = 0x1F,
 255         ODM_RATEMCS20           = 0x20,
 256         ODM_RATEMCS21           = 0x21,
 257         ODM_RATEMCS22           = 0x22,
 258         ODM_RATEMCS23           = 0x23,
 259         ODM_RATEMCS24           = 0x24,
 260         ODM_RATEMCS25           = 0x25,
 261         ODM_RATEMCS26           = 0x26,
 262         ODM_RATEMCS27           = 0x27,
 263         ODM_RATEMCS28           = 0x28,
 264         ODM_RATEMCS29           = 0x29,
 265         ODM_RATEMCS30           = 0x2A,
 266         ODM_RATEMCS31           = 0x2B,
 267         ODM_RATEVHTSS1MCS0      = 0x2C,
 268         ODM_RATEVHTSS1MCS1      = 0x2D,
 269         ODM_RATEVHTSS1MCS2      = 0x2E,
 270         ODM_RATEVHTSS1MCS3      = 0x2F,
 271         ODM_RATEVHTSS1MCS4      = 0x30,
 272         ODM_RATEVHTSS1MCS5      = 0x31,
 273         ODM_RATEVHTSS1MCS6      = 0x32,
 274         ODM_RATEVHTSS1MCS7      = 0x33,
 275         ODM_RATEVHTSS1MCS8      = 0x34,
 276         ODM_RATEVHTSS1MCS9      = 0x35,
 277         ODM_RATEVHTSS2MCS0      = 0x36,
 278         ODM_RATEVHTSS2MCS1      = 0x37,
 279         ODM_RATEVHTSS2MCS2      = 0x38,
 280         ODM_RATEVHTSS2MCS3      = 0x39,
 281         ODM_RATEVHTSS2MCS4      = 0x3A,
 282         ODM_RATEVHTSS2MCS5      = 0x3B,
 283         ODM_RATEVHTSS2MCS6      = 0x3C,
 284         ODM_RATEVHTSS2MCS7      = 0x3D,
 285         ODM_RATEVHTSS2MCS8      = 0x3E,
 286         ODM_RATEVHTSS2MCS9      = 0x3F,
 287         ODM_RATEVHTSS3MCS0      = 0x40,
 288         ODM_RATEVHTSS3MCS1      = 0x41,
 289         ODM_RATEVHTSS3MCS2      = 0x42,
 290         ODM_RATEVHTSS3MCS3      = 0x43,
 291         ODM_RATEVHTSS3MCS4      = 0x44,
 292         ODM_RATEVHTSS3MCS5      = 0x45,
 293         ODM_RATEVHTSS3MCS6      = 0x46,
 294         ODM_RATEVHTSS3MCS7      = 0x47,
 295         ODM_RATEVHTSS3MCS8      = 0x48,
 296         ODM_RATEVHTSS3MCS9      = 0x49,
 297         ODM_RATEVHTSS4MCS0      = 0x4A,
 298         ODM_RATEVHTSS4MCS1      = 0x4B,
 299         ODM_RATEVHTSS4MCS2      = 0x4C,
 300         ODM_RATEVHTSS4MCS3      = 0x4D,
 301         ODM_RATEVHTSS4MCS4      = 0x4E,
 302         ODM_RATEVHTSS4MCS5      = 0x4F,
 303         ODM_RATEVHTSS4MCS6      = 0x50,
 304         ODM_RATEVHTSS4MCS7      = 0x51,
 305         ODM_RATEVHTSS4MCS8      = 0x52,
 306         ODM_RATEVHTSS4MCS9      = 0x53,
 307 };
 308
 309 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 310         #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
 311 #else
 312         #if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8192F_SUPPORT)
 313                 #define ODM_NUM_RATE_IDX (ODM_RATEMCS15 + 1)
 314         #elif (RTL8723B_SUPPORT || RTL8188E_SUPPORT || RTL8188F_SUPPORT)
 315                 #define ODM_NUM_RATE_IDX (ODM_RATEMCS7 + 1)
 316         #elif (RTL8821A_SUPPORT || RTL8881A_SUPPORT)
 317                 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS1MCS9 + 1)
 318         #elif (RTL8812A_SUPPORT)
 319                 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS2MCS9 + 1)
 320         #elif (RTL8814A_SUPPORT)
 321                 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS3MCS9 + 1)
 322         #else
 323                 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
 324         #endif
 325 #endif
 326
 327 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 328         #define CONFIG_SFW_SUPPORTED
 329 #endif
 330
 331 /****************************************************************
 332  * 1 ============================================================
 333  * 1  enumeration
 334  * 1 ============================================================
 335  ***************************************************************/
 336
 337 /*      ODM_CMNINFO_INTERFACE */
 338 enum odm_interface {
 339         ODM_ITRF_PCIE   =       0x1,
 340         ODM_ITRF_USB    =       0x2,
 341         ODM_ITRF_SDIO   =       0x4,
 342         ODM_ITRF_ALL    =       0x7,
 343 };
 344
 345 /*@========[Run time IC flag] ===================================*/
 346
 347 enum phydm_ic {
 348         ODM_RTL8188E    =       BIT(0),
 349         ODM_RTL8812     =       BIT(1),
 350         ODM_RTL8821     =       BIT(2),
 351         ODM_RTL8192E    =       BIT(3),
 352         ODM_RTL8723B    =       BIT(4),
 353         ODM_RTL8814A    =       BIT(5),
 354         ODM_RTL8881A    =       BIT(6),
 355         ODM_RTL8822B    =       BIT(7),
 356         ODM_RTL8703B    =       BIT(8),
 357         ODM_RTL8195A    =       BIT(9),
 358         ODM_RTL8188F    =       BIT(10),
 359         ODM_RTL8723D    =       BIT(11),
 360         ODM_RTL8197F    =       BIT(12),
 361         ODM_RTL8821C    =       BIT(13),
 362         ODM_RTL8814B    =       BIT(14),
 363         ODM_RTL8198F    =       BIT(15),
 364         ODM_RTL8710B    =       BIT(16),
 365         ODM_RTL8192F    =       BIT(17),
 366         ODM_RTL8822C    =       BIT(18),
 367         ODM_RTL8195B    =       BIT(19)
 368 };
 369
 370 #define ODM_IC_N_1SS            (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B |\
 371                                  ODM_RTL8703B | ODM_RTL8723D | ODM_RTL8195A |\
 372                                  ODM_RTL8710B)
 373 #define ODM_IC_N_2SS            (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8192F)
 374 #define ODM_IC_N_3SS            0
 375 #define ODM_IC_N_4SS            0
 376
 377 #define ODM_IC_AC_1SS           (ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C |\
 378                                  ODM_RTL8195B)
 379 #define ODM_IC_AC_2SS           (ODM_RTL8812 | ODM_RTL8822B)
 380 #define ODM_IC_AC_3SS           0
 381 #define ODM_IC_AC_4SS           (ODM_RTL8814A)
 382
 383 #define ODM_IC_JGR3_1SS         0
 384 #define ODM_IC_JGR3_2SS         (ODM_RTL8822C)
 385 #define ODM_IC_JGR3_3SS         0
 386 #define ODM_IC_JGR3_4SS         (ODM_RTL8198F | ODM_RTL8814B)
 387
 388 /*@====the following macro DO NOT need to update when adding a new IC======= */
 389 #define ODM_IC_1SS              (ODM_IC_N_1SS | ODM_IC_AC_1SS | ODM_IC_JGR3_1SS)
 390 #define ODM_IC_2SS              (ODM_IC_N_2SS | ODM_IC_AC_2SS | ODM_IC_JGR3_2SS)
 391 #define ODM_IC_3SS              (ODM_IC_N_3SS | ODM_IC_AC_3SS | ODM_IC_JGR3_3SS)
 392 #define ODM_IC_4SS              (ODM_IC_N_4SS | ODM_IC_AC_4SS | ODM_IC_JGR3_4SS)
 393
 394 #define PHYDM_IC_ABOVE_1SS      (ODM_IC_1SS | ODM_IC_2SS | ODM_IC_3SS |\
 395                                  ODM_IC_4SS)
 396 #define PHYDM_IC_ABOVE_2SS      (ODM_IC_2SS | ODM_IC_3SS | ODM_IC_4SS)
 397 #define PHYDM_IC_ABOVE_3SS      (ODM_IC_3SS | ODM_IC_4SS)
 398 #define PHYDM_IC_ABOVE_4SS      ODM_IC_4SS
 399
 400 #define ODM_IC_11N_SERIES       (ODM_IC_N_1SS | ODM_IC_N_2SS | ODM_IC_N_3SS |\
 401                                  ODM_IC_N_4SS)
 402 #define ODM_IC_11AC_SERIES      (ODM_IC_AC_1SS | ODM_IC_AC_2SS |\
 403                                  ODM_IC_AC_3SS | ODM_IC_AC_4SS)
 404 #define ODM_IC_JGR3_SERIES      (ODM_IC_JGR3_1SS | ODM_IC_JGR3_2SS |\
 405                                  ODM_IC_JGR3_3SS | ODM_IC_JGR3_4SS)
 406 /*@====================================================*/
 407
 408 #define ODM_IC_11AC_1_SERIES    (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
 409 #define ODM_IC_11AC_2_SERIES    (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C |\
 410                                  ODM_RTL8195B)
 411
 412 /*@[Phy status type]*/
 413 #define PHYSTS_2ND_TYPE_IC      (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D |\
 414                                  ODM_RTL8821C | ODM_RTL8710B | ODM_RTL8195B |\
 415                                  ODM_RTL8192F)
 416 #define PHYSTS_3RD_TYPE_IC      (ODM_RTL8198F | ODM_RTL8814B | ODM_RTL8822C)
 417 /*@[FW Type]*/
 418 #define PHYDM_IC_8051_SERIES    (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 |\
 419                                  ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |\
 420                                  ODM_RTL8188F | ODM_RTL8192F)
 421 #define PHYDM_IC_3081_SERIES    (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\
 422                                  ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\
 423                                  ODM_RTL8822C)
 424 /*@[LA mode]*/
 425 #define PHYDM_IC_SUPPORT_LA_MODE (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F |\
 426                                   ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8198F |\
 427                                   ODM_RTL8192F | ODM_RTL8822C)
 428 /*@[BF]*/
 429 #define ODM_IC_TXBF_SUPPORT     (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 |\
 430                                  ODM_RTL8814A | ODM_RTL8881A | ODM_RTL8822B |\
 431                                  ODM_RTL8197F | ODM_RTL8821C | ODM_RTL8195B |\
 432                                  ODM_RTL8198F | ODM_RTL8822C)
 433 #define PHYDM_IC_SUPPORT_MU_BFEE (ODM_RTL8822B | ODM_RTL8821C | ODM_RTL8814B |\
 434                                   ODM_RTL8195B | ODM_RTL8198F | ODM_RTL8822C)
 435 #define PHYDM_IC_SUPPORT_MU_BFER (ODM_RTL8822B | ODM_RTL8814B | ODM_RTL8198F |\
 436                                   ODM_RTL8822C)
 437 /*@[PHYDM API]*/
 438 #define CMN_API_SUPPORT_IC (ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8192F |\
 439                             ODM_RTL8821C | ODM_RTL8195B | ODM_RTL8822C |\
 440                             ODM_RTL8198F)
 441
 442 /*@========[Compile time IC flag] ========================*/
 443 /*@========[AC-3/AC/N Support] ===========================*/
 444
 445 #if (RTL8814B_SUPPORT || RTL8198F_SUPPORT || RTL8822C_SUPPORT)
 446         #define PHYDM_IC_JGR3_SERIES_SUPPORT
 447         #if (RTL8814B_SUPPORT || RTL8822C_SUPPORT)
 448                 #define PHYDM_IC_JGR3_80M_SUPPORT
 449         #endif
 450 #endif
 451
 452 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
 453
 454         #ifdef RTK_AC_SUPPORT
 455         #define ODM_IC_11AC_SERIES_SUPPORT      1
 456         #else
 457         #define ODM_IC_11AC_SERIES_SUPPORT      0
 458         #endif
 459
 460         #define ODM_IC_11N_SERIES_SUPPORT       1
 461
 462 #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 463
 464         #define ODM_IC_11AC_SERIES_SUPPORT      1
 465         #define ODM_IC_11N_SERIES_SUPPORT       1
 466
 467 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211)
 468
 469         #define ODM_IC_11AC_SERIES_SUPPORT      1
 470         #define ODM_IC_11N_SERIES_SUPPORT       1
 471
 472 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE) && defined(DM_ODM_CE_MAC80211_V2)
 473
 474         #define ODM_IC_11AC_SERIES_SUPPORT              1
 475         #define ODM_IC_11N_SERIES_SUPPORT                       1
 476
 477 #else /*ODM_CE*/
 478
 479         #if (RTL8188E_SUPPORT || RTL8723B_SUPPORT || RTL8192E_SUPPORT ||\
 480              RTL8195A_SUPPORT || RTL8703B_SUPPORT || RTL8188F_SUPPORT ||\
 481              RTL8723D_SUPPORT || RTL8197F_SUPPORT || RTL8710B_SUPPORT ||\
 482              RTL8192F_SUPPORT)
 483                 #define ODM_IC_11N_SERIES_SUPPORT       1
 484                 #define ODM_IC_11AC_SERIES_SUPPORT      0
 485         #else
 486                 #define ODM_IC_11N_SERIES_SUPPORT       0
 487                 #define ODM_IC_11AC_SERIES_SUPPORT      1
 488         #endif
 489 #endif
 490
 491 /*@===IC SS Compile Flag, prepare for code size reduction==============*/
 492 #if (RTL8188E_SUPPORT || RTL8188F_SUPPORT || RTL8723B_SUPPORT ||\
 493         RTL8703B_SUPPORT || RTL8723D_SUPPORT || RTL8881A_SUPPORT ||\
 494         RTL8821A_SUPPORT || RTL8821C_SUPPORT || RTL8195A_SUPPORT ||\
 495         RTL8710B_SUPPORT || RTL8195B_SUPPORT)
 496
 497         #define PHYDM_COMPILE_IC_1SS
 498 #endif
 499
 500 #if (RTL8192E_SUPPORT || RTL8197F_SUPPORT || RTL8812A_SUPPORT ||\
 501         RTL8822B_SUPPORT || RTL8192F_SUPPORT || RTL8822C_SUPPORT)
 502         #define PHYDM_COMPILE_IC_2SS
 503 #endif
 504
 505 /*@#define PHYDM_COMPILE_IC_3SS*/
 506
 507 #if ((RTL8814B_SUPPORT) || (RTL8814A_SUPPORT) || (RTL8198F_SUPPORT))
 508         #define PHYDM_COMPILE_IC_4SS
 509 #endif
 510
 511 /*@==[ABOVE N-SS COMPILE FLAG]=================================================*/
 512 #if (defined(PHYDM_COMPILE_IC_1SS) || defined(PHYDM_COMPILE_IC_2SS) ||\
 513         defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))
 514         #define PHYDM_COMPILE_ABOVE_1SS
 515 #endif
 516
 517 #if (defined(PHYDM_COMPILE_IC_2SS) || defined(PHYDM_COMPILE_IC_3SS) ||\
 518         defined(PHYDM_COMPILE_IC_4SS))
 519         #define PHYDM_COMPILE_ABOVE_2SS
 520 #endif
 521
 522 #if (defined(PHYDM_COMPILE_IC_3SS) || defined(PHYDM_COMPILE_IC_4SS))
 523         #define PHYDM_COMPILE_ABOVE_3SS
 524 #endif
 525
 526 #if (defined(PHYDM_COMPILE_IC_4SS))
 527         #define PHYDM_COMPILE_ABOVE_4SS
 528 #endif
 529
 530 /*@========[New Phy-Status Support] ========================*/
 531 #if (RTL8197F_SUPPORT || RTL8723D_SUPPORT || RTL8822B_SUPPORT ||\
 532         RTL8821C_SUPPORT || RTL8710B_SUPPORT || RTL8195B_SUPPORT ||\
 533         RTL8192F_SUPPORT)
 534         #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT                 1
 535 #else
 536         #define ODM_PHY_STATUS_NEW_TYPE_SUPPORT                 0
 537 #endif
 538
 539 #if (RTL8198F_SUPPORT) || (RTL8814B_SUPPORT) || (RTL8822C_SUPPORT)
 540         #define PHYSTS_3RD_TYPE_SUPPORT
 541 #endif
 542
 543 #if (RTL8198F_SUPPORT || RTL8814B_SUPPORT || RTL8822C_SUPPORT)
 544         #define BB_RAM_SUPPORT
 545 #endif
 546
 547 /*@============================================================================*/
 548
 549 #if (RTL8822B_SUPPORT || RTL8197F_SUPPORT || RTL8821C_SUPPORT ||\
 550         RTL8192F_SUPPORT || RTL8195B_SUPPORT || RTL8822C_SUPPORT ||\
 551         RTL8198F_SUPPORT)
 552 #define PHYDM_COMMON_API_SUPPORT
 553 #endif
 554
 555
 556 #define CCK_RATE_NUM            4
 557 #define OFDM_RATE_NUM           8
 558
 559 #define LEGACY_RATE_NUM         12
 560
 561 #define HT_RATE_NUM_4SS         32
 562 #define VHT_RATE_NUM_4SS        40
 563
 564 #define HT_RATE_NUM_3SS         24
 565 #define VHT_RATE_NUM_3SS        30
 566
 567 #define HT_RATE_NUM_2SS         16
 568 #define VHT_RATE_NUM_2SS        20
 569
 570 #define HT_RATE_NUM_1SS         8
 571 #define VHT_RATE_NUM_1SS        10
 572 #if (defined(PHYDM_COMPILE_ABOVE_4SS))
 573         #define HT_RATE_NUM     HT_RATE_NUM_4SS
 574         #define VHT_RATE_NUM    VHT_RATE_NUM_4SS
 575 #elif (defined(PHYDM_COMPILE_ABOVE_3SS))
 576         #define HT_RATE_NUM     HT_RATE_NUM_3SS
 577         #define VHT_RATE_NUM    VHT_RATE_NUM_3SS
 578 #elif (defined(PHYDM_COMPILE_ABOVE_2SS))
 579         #define HT_RATE_NUM     HT_RATE_NUM_2SS
 580         #define VHT_RATE_NUM    VHT_RATE_NUM_2SS
 581 #else
 582         #define HT_RATE_NUM     HT_RATE_NUM_1SS
 583         #define VHT_RATE_NUM    VHT_RATE_NUM_1SS
 584 #endif
 585
 586 #define LOW_BW_RATE_NUM         VHT_RATE_NUM
 587
 588 enum phydm_ic_ip {
 589         PHYDM_IC_N              = 0,
 590         PHYDM_IC_AC             = 1,
 591         PHYDM_IC_JGR3           = 2
 592 };
 593
 594 /* ODM_CMNINFO_CUT_VER */
 595 enum odm_cut_version {
 596         ODM_CUT_A               = 0,
 597         ODM_CUT_B               = 1,
 598         ODM_CUT_C               = 2,
 599         ODM_CUT_D               = 3,
 600         ODM_CUT_E               = 4,
 601         ODM_CUT_F               = 5,
 602         ODM_CUT_G               = 6,
 603         ODM_CUT_H               = 7,
 604         ODM_CUT_I               = 8,
 605         ODM_CUT_J               = 9,
 606         ODM_CUT_K               = 10,
 607         ODM_CUT_TEST            = 15,
 608 };
 609
 610 /* ODM_CMNINFO_FAB_VER */
 611 enum odm_fab {
 612         ODM_TSMC                = 0,
 613         ODM_UMC                 = 1,
 614 };
 615
 616 /* ODM_CMNINFO_OP_MODE */
 617 enum odm_operation_mode {
 618         ODM_NO_LINK             = BIT(0),
 619         ODM_LINK                = BIT(1),
 620         ODM_SCAN                = BIT(2),
 621         ODM_POWERSAVE           = BIT(3),
 622         ODM_AP_MODE             = BIT(4),
 623         ODM_CLIENT_MODE         = BIT(5),
 624         ODM_AD_HOC              = BIT(6),
 625         ODM_WIFI_DIRECT         = BIT(7),
 626         ODM_WIFI_DISPLAY        = BIT(8),
 627 };
 628
 629 /* ODM_CMNINFO_WM_MODE */
 630 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE))
 631 enum odm_wireless_mode {
 632         ODM_WM_UNKNOW           = 0x0,
 633         ODM_WM_B                = BIT(0),
 634         ODM_WM_G                = BIT(1),
 635         ODM_WM_A                = BIT(2),
 636         ODM_WM_N24G             = BIT(3),
 637         ODM_WM_N5G              = BIT(4),
 638         ODM_WM_AUTO             = BIT(5),
 639         ODM_WM_AC               = BIT(6),
 640 };
 641 #else
 642 enum odm_wireless_mode {
 643         ODM_WM_UNKNOWN          = 0x00,/*@0x0*/
 644         ODM_WM_A                = BIT(0), /* @0x1*/
 645         ODM_WM_B                = BIT(1), /* @0x2*/
 646         ODM_WM_G                = BIT(2),/* @0x4*/
 647         ODM_WM_AUTO             = BIT(3),/* @0x8*/
 648         ODM_WM_N24G             = BIT(4),/* @0x10*/
 649         ODM_WM_N5G              = BIT(5),/* @0x20*/
 650         ODM_WM_AC_5G            = BIT(6),/* @0x40*/
 651         ODM_WM_AC_24G           = BIT(7),/* @0x80*/
 652         ODM_WM_AC_ONLY          = BIT(8),/* @0x100*/
 653         ODM_WM_MAX              = BIT(11)/* @0x800*/
 654
 655 };
 656 #endif
 657
 658 /* ODM_CMNINFO_BAND */
 659 enum odm_band_type {
 660 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP))
 661         ODM_BAND_2_4G           = BIT(0),
 662         ODM_BAND_5G             = BIT(1),
 663 #else
 664         ODM_BAND_2_4G           = 0,
 665         ODM_BAND_5G,
 666         ODM_BAND_ON_BOTH,
 667         ODM_BANDMAX
 668 #endif
 669 };
 670
 671 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
 672 enum phydm_sec_chnl_offset {
 673         PHYDM_DONT_CARE         = 0,
 674         PHYDM_BELOW             = 1,
 675         PHYDM_ABOVE             = 2
 676 };
 677
 678 /* ODM_CMNINFO_SEC_MODE */
 679 enum odm_security {
 680         ODM_SEC_OPEN            = 0,
 681         ODM_SEC_WEP40           = 1,
 682         ODM_SEC_TKIP            = 2,
 683         ODM_SEC_RESERVE         = 3,
 684         ODM_SEC_AESCCMP         = 4,
 685         ODM_SEC_WEP104          = 5,
 686         ODM_WEP_WPA_MIXED       = 6, /* WEP + WPA */
 687         ODM_SEC_SMS4            = 7,
 688 };
 689
 690 /* ODM_CMNINFO_CHNL */
 691
 692 /* ODM_CMNINFO_BOARD_TYPE */
 693 enum odm_board_type {
 694         ODM_BOARD_DEFAULT       = 0,      /* The DEFAULT case. */
 695         ODM_BOARD_MINICARD      = BIT(0), /* @0 = non-mini card, 1= mini card. */
 696         ODM_BOARD_SLIM          = BIT(1), /* @0 = non-slim card, 1 = slim card */
 697         ODM_BOARD_BT            = BIT(2), /* @0 = without BT card, 1 = with BT */
 698         ODM_BOARD_EXT_PA        = BIT(3), /* @0 = no 2G ext-PA, 1 = existing 2G ext-PA */
 699         ODM_BOARD_EXT_LNA       = BIT(4), /* @0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
 700         ODM_BOARD_EXT_TRSW      = BIT(5), /* @0 = no ext-TRSW, 1 = existing ext-TRSW */
 701         ODM_BOARD_EXT_PA_5G     = BIT(6), /* @0 = no 5G ext-PA, 1 = existing 5G ext-PA */
 702         ODM_BOARD_EXT_LNA_5G    = BIT(7), /* @0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
 703 };
 704
 705 enum odm_package_type {
 706         ODM_PACKAGE_DEFAULT     = 0,
 707         ODM_PACKAGE_QFN68       = BIT(0),
 708         ODM_PACKAGE_TFBGA90     = BIT(1),
 709         ODM_PACKAGE_TFBGA79     = BIT(2),
 710 };
 711
 712 enum odm_type_gpa {
 713         TYPE_GPA0               = 0x0000,
 714         TYPE_GPA1               = 0x0055,
 715         TYPE_GPA2               = 0x00AA,
 716         TYPE_GPA3               = 0x00FF,
 717         TYPE_GPA4               = 0x5500,
 718         TYPE_GPA5               = 0x5555,
 719         TYPE_GPA6               = 0x55AA,
 720         TYPE_GPA7               = 0x55FF,
 721         TYPE_GPA8               = 0xAA00,
 722         TYPE_GPA9               = 0xAA55,
 723         TYPE_GPA10              = 0xAAAA,
 724         TYPE_GPA11              = 0xAAFF,
 725         TYPE_GPA12              = 0xFF00,
 726         TYPE_GPA13              = 0xFF55,
 727         TYPE_GPA14              = 0xFFAA,
 728         TYPE_GPA15              = 0xFFFF,
 729 };
 730
 731 enum odm_type_apa {
 732         TYPE_APA0               = 0x0000,
 733         TYPE_APA1               = 0x0055,
 734         TYPE_APA2               = 0x00AA,
 735         TYPE_APA3               = 0x00FF,
 736         TYPE_APA4               = 0x5500,
 737         TYPE_APA5               = 0x5555,
 738         TYPE_APA6               = 0x55AA,
 739         TYPE_APA7               = 0x55FF,
 740         TYPE_APA8               = 0xAA00,
 741         TYPE_APA9               = 0xAA55,
 742         TYPE_APA10              = 0xAAAA,
 743         TYPE_APA11              = 0xAAFF,
 744         TYPE_APA12              = 0xFF00,
 745         TYPE_APA13              = 0xFF55,
 746         TYPE_APA14              = 0xFFAA,
 747         TYPE_APA15              = 0xFFFF,
 748 };
 749
 750 enum odm_type_glna {
 751         TYPE_GLNA0              = 0x0000,
 752         TYPE_GLNA1              = 0x0055,
 753         TYPE_GLNA2              = 0x00AA,
 754         TYPE_GLNA3              = 0x00FF,
 755         TYPE_GLNA4              = 0x5500,
 756         TYPE_GLNA5              = 0x5555,
 757         TYPE_GLNA6              = 0x55AA,
 758         TYPE_GLNA7              = 0x55FF,
 759         TYPE_GLNA8              = 0xAA00,
 760         TYPE_GLNA9              = 0xAA55,
 761         TYPE_GLNA10             = 0xAAAA,
 762         TYPE_GLNA11             = 0xAAFF,
 763         TYPE_GLNA12             = 0xFF00,
 764         TYPE_GLNA13             = 0xFF55,
 765         TYPE_GLNA14             = 0xFFAA,
 766         TYPE_GLNA15             = 0xFFFF,
 767 };
 768
 769 enum odm_type_alna {
 770         TYPE_ALNA0              = 0x0000,
 771         TYPE_ALNA1              = 0x0055,
 772         TYPE_ALNA2              = 0x00AA,
 773         TYPE_ALNA3              = 0x00FF,
 774         TYPE_ALNA4              = 0x5500,
 775         TYPE_ALNA5              = 0x5555,
 776         TYPE_ALNA6              = 0x55AA,
 777         TYPE_ALNA7              = 0x55FF,
 778         TYPE_ALNA8              = 0xAA00,
 779         TYPE_ALNA9              = 0xAA55,
 780         TYPE_ALNA10             = 0xAAAA,
 781         TYPE_ALNA11             = 0xAAFF,
 782         TYPE_ALNA12             = 0xFF00,
 783         TYPE_ALNA13             = 0xFF55,
 784         TYPE_ALNA14             = 0xFFAA,
 785         TYPE_ALNA15             = 0xFFFF,
 786 };
 787
 788 #define PAUSE_FAIL              0
 789 #define PAUSE_SUCCESS           1
 790
 791 enum odm_parameter_init {
 792         ODM_PRE_SETTING         = 0,
 793         ODM_POST_SETTING        = 1,
 794         ODM_INIT_FW_SETTING
 795 };
 796
 797 enum phydm_pause_type {
 798         PHYDM_PAUSE             = 1,    /*Pause & Set new value*/
 799         PHYDM_PAUSE_NO_SET      = 2,    /*Pause & Stay in current value*/
 800         PHYDM_RESUME            = 3
 801 };
 802
 803 enum phydm_pause_level {
 804         PHYDM_PAUSE_RELEASE     = -1,
 805         PHYDM_PAUSE_LEVEL_0     = 0,    /* @Low Priority function */
 806         PHYDM_PAUSE_LEVEL_1     = 1,    /* @Middle Priority function */
 807         PHYDM_PAUSE_LEVEL_2     = 2,    /* @High priority function (ex: Check hang function) */
 808         PHYDM_PAUSE_LEVEL_3     = 3,    /* @Debug function (the highest priority) */
 809         PHYDM_PAUSE_MAX_NUM     = 4
 810 };
 811
 812 enum phydm_dis_hw_fun {
 813         HW_FUN_DIS              = 0,    /*@Disable a cetain HW function & backup the original value*/
 814         HW_FUN_RESUME           = 1     /*Revert */
 815 };
 816
 817 #endif