rtl8821ce/hal/phydm/phydm_rainfo.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2017  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __PHYDMRAINFO_H__
  27 #define __PHYDMRAINFO_H__
  28
  29 #define RAINFO_VERSION "8.0"
  30
  31 #define FORCED_UPDATE_RAMASK_PERIOD     5
  32
  33 #define H2C_MAX_LENGTH          7
  34
  35 #define RA_FLOOR_UP_GAP         3
  36 #define RA_FLOOR_TABLE_SIZE     7
  37
  38 #define ACTIVE_TP_THRESHOLD     1
  39 #define RA_RETRY_DESCEND_NUM    2
  40 #define RA_RETRY_LIMIT_LOW      4
  41 #define RA_RETRY_LIMIT_HIGH     32
  42
  43 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
  44         #define FIRST_MACID     1
  45 #else
  46         #define FIRST_MACID     0
  47 #endif
  48
  49 /* @1 ============================================================
  50  * 1 enumrate
  51  * 1 ============================================================
  52  */
  53
  54 enum phydm_ra_dbg_para {
  55         RADBG_PCR_TH_OFFSET     = 0,
  56         RADBG_RTY_PENALTY       = 1,
  57         RADBG_N_HIGH            = 2,
  58         RADBG_N_LOW             = 3,
  59         RADBG_TRATE_UP_TABLE    = 4,
  60         RADBG_TRATE_DOWN_TABLE  = 5,
  61         RADBG_TRYING_NECESSARY  = 6,
  62         RADBG_TDROPING_NECESSARY = 7,
  63         RADBG_RATE_UP_RTY_RATIO = 8,
  64         RADBG_RATE_DOWN_RTY_RATIO = 9, /* u8 */
  65
  66         RADBG_DEBUG_MONITOR1    = 0xc,
  67         RADBG_DEBUG_MONITOR2    = 0xd,
  68         RADBG_DEBUG_MONITOR3    = 0xe,
  69         RADBG_DEBUG_MONITOR4    = 0xf,
  70         RADBG_DEBUG_MONITOR5    = 0x10,
  71         NUM_RA_PARA
  72 };
  73
  74 enum phydm_wireless_mode {
  75         PHYDM_WIRELESS_MODE_UNKNOWN     = 0x00,
  76         PHYDM_WIRELESS_MODE_A           = 0x01,
  77         PHYDM_WIRELESS_MODE_B           = 0x02,
  78         PHYDM_WIRELESS_MODE_G           = 0x04,
  79         PHYDM_WIRELESS_MODE_AUTO        = 0x08,
  80         PHYDM_WIRELESS_MODE_N_24G       = 0x10,
  81         PHYDM_WIRELESS_MODE_N_5G        = 0x20,
  82         PHYDM_WIRELESS_MODE_AC_5G       = 0x40,
  83         PHYDM_WIRELESS_MODE_AC_24G      = 0x80,
  84         PHYDM_WIRELESS_MODE_AC_ONLY     = 0x100,
  85         PHYDM_WIRELESS_MODE_MAX         = 0x800,
  86         PHYDM_WIRELESS_MODE_ALL         = 0xFFFF
  87 };
  88
  89 enum phydm_rateid_idx {
  90         PHYDM_BGN_40M_2SS       = 0,
  91         PHYDM_BGN_40M_1SS       = 1,
  92         PHYDM_BGN_20M_2SS       = 2,
  93         PHYDM_BGN_20M_1SS       = 3,
  94         PHYDM_GN_N2SS           = 4,
  95         PHYDM_GN_N1SS           = 5,
  96         PHYDM_BG                = 6,
  97         PHYDM_G                 = 7,
  98         PHYDM_B_20M             = 8,
  99         PHYDM_ARFR0_AC_2SS      = 9,
 100         PHYDM_ARFR1_AC_1SS      = 10,
 101         PHYDM_ARFR2_AC_2G_1SS   = 11,
 102         PHYDM_ARFR3_AC_2G_2SS   = 12,
 103         PHYDM_ARFR4_AC_3SS      = 13,
 104         PHYDM_ARFR5_N_3SS       = 14,
 105         PHYDM_ARFR7_N_4SS       = 15,
 106         PHYDM_ARFR6_AC_4SS      = 16
 107 };
 108
 109 #if (RATE_ADAPTIVE_SUPPORT == 1)/* @88E RA */
 110
 111 struct _phydm_txstatistic_ {
 112         u32     hw_total_tx;
 113         u32     hw_tx_success;
 114         u32     hw_tx_rty;
 115         u32     hw_tx_drop;
 116 };
 117
 118 /* @1 ============================================================
 119  * 1  structure
 120  * 1 ============================================================
 121  */
 122 struct _odm_ra_info_ {
 123         u8      rate_id;
 124         u32     rate_mask;
 125         u32     ra_use_rate;
 126         u8      rate_sgi;
 127         u8      rssi_sta_ra;
 128         u8      pre_rssi_sta_ra;
 129         u8      sgi_enable;
 130         u8      decision_rate;
 131         u8      pre_rate;
 132         u8      highest_rate;
 133         u8      lowest_rate;
 134         u32     nsc_up;
 135         u32     nsc_down;
 136         u16     RTY[5];
 137         u32     TOTAL;
 138         u16     DROP;
 139         u8      active;
 140         u16     rpt_time;
 141         u8      ra_waiting_counter;
 142         u8      ra_pending_counter;
 143         u8      ra_drop_after_down;
 144 #if 1 /* POWER_TRAINING_ACTIVE == 1 */ /* For compile  pass only~! */
 145         u8      pt_active;      /* on or off */
 146         u8      pt_try_state;   /* @0 trying state, 1 for decision state */
 147         u8      pt_stage;       /* @0~6 */
 148         u8      pt_stop_count;  /* Stop PT counter */
 149         u8      pt_pre_rate;    /* @if rate change do PT */
 150         u8      pt_pre_rssi;    /* @if RSSI change 5% do PT */
 151         u8      pt_mode_ss;     /* @decide whitch rate should do PT */
 152         u8      ra_stage;       /* @StageRA, decide how many times RA will be done between PT */
 153         u8      pt_smooth_factor;
 154 #endif
 155 #if (DM_ODM_SUPPORT_TYPE == ODM_AP) &&  ((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))
 156         u8      rate_down_counter;
 157         u8      rate_up_counter;
 158         u8      rate_direction;
 159         u8      bounding_type;
 160         u8      bounding_counter;
 161         u8      bounding_learning_time;
 162         u8      rate_down_start_time;
 163 #endif
 164 };
 165 #endif
 166
 167
 168 struct ra_table {
 169         u8      firstconnect;
 170         /*@u8   link_tx_rate[ODM_ASSOCIATE_ENTRY_NUM];*/
 171         u8      mu1_rate[30];
 172         u8      highest_client_tx_order;
 173         u16     highest_client_tx_rate_order;
 174         u8      power_tracking_flag;
 175         u8      ra_th_ofst; /*RA_threshold_offset*/
 176         u8      ra_ofst_direc; /*RA_offset_direction*/
 177         u8      up_ramask_cnt; /*@force update_ra_mask counter*/
 178         u8      up_ramask_cnt_tmp; /*@Just for debug, should be removed latter*/
 179 #if 0   /*@CONFIG_RA_DYNAMIC_RTY_LIMIT*/
 180         u8      per_rate_retrylimit_20M[ODM_NUM_RATE_IDX];
 181         u8      per_rate_retrylimit_40M[ODM_NUM_RATE_IDX];
 182         u8      retry_descend_num;
 183         u8      retrylimit_low;
 184         u8      retrylimit_high;
 185 #endif
 186         u8      ldpc_thres; /* @if RSSI > ldpc_th => switch from LPDC to BCC */
 187         void (*record_ra_info)(void *dm_void, u8 macid,
 188                                struct cmn_sta_info *sta, u64 ra_mask);
 189 };
 190
 191 /* @1 ============================================================
 192  * 1  Function Prototype
 193  * 1 ============================================================
 194  */
 195 boolean phydm_is_cck_rate(void *dm_void, u8 rate);
 196
 197 boolean phydm_is_ofdm_rate(void *dm_void, u8 rate);
 198
 199 boolean phydm_is_ht_rate(void *dm_void, u8 rate);
 200
 201 boolean phydm_is_vht_rate(void *dm_void, u8 rate);
 202
 203 u8 phydm_rate_type_2_num_ss(void *dm_void, enum PDM_RATE_TYPE type);
 204
 205 u8 phydm_rate_to_num_ss(void *dm_void, u8 data_rate);
 206
 207 void phydm_h2C_debug(void *dm_void, char input[][16], u32 *_used,
 208                      char *output, u32 *_out_len);
 209
 210 void phydm_ra_debug(void *dm_void, char input[][16], u32 *_used, char *output,
 211                     u32 *_out_len);
 212
 213 void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
 214
 215 void phydm_ra_dynamic_retry_count(void *dm_void);
 216
 217
 218 void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component);
 219
 220 void phydm_print_rate_2_buff(void *dm_void, u8 rate, char *buf, u16 buf_size);
 221
 222 void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len);
 223
 224 u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx);
 225
 226 void phydm_ra_info_watchdog(void *dm_void);
 227
 228 void phydm_ra_info_init(void *dm_void);
 229
 230 void phydm_modify_RA_PCR_threshold(void *dm_void, u8 ra_ofst_direc,
 231                                    u8 ra_th_ofst);
 232
 233 u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode);
 234
 235 u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw);
 236 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
 237 void phydm_update_hal_ra_mask(
 238         void *dm_void,
 239         u32 wireless_mode,
 240         u8 rf_type,
 241         u8 BW,
 242         u8 mimo_ps_enable,
 243         u8 disable_cck_rate,
 244         u32 *ratr_bitmap_msb_in,
 245         u32 *ratr_bitmap_in,
 246         u8 tx_rate_level);
 247 #endif
 248
 249 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
 250 u8 phydm_get_plcp(void *dm_void, u16 macid);
 251 #endif
 252
 253 void phydm_refresh_rate_adaptive_mask(void *dm_void);
 254
 255 u8 phydm_rssi_lv_dec(void *dm_void, u32 rssi, u8 ratr_state);
 256
 257 void odm_ra_post_action_on_assoc(void *dm);
 258
 259 u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, boolean is_erp_protect);
 260
 261 void phydm_show_sta_info(void *dm_void, char input[][16], u32 *_used,
 262                          char *output, u32 *_out_len);
 263
 264 u8 phydm_get_rate_from_rssi_lv(void *dm_void, u8 sta_idx);
 265
 266 void phydm_ra_registed(void *dm_void, u8 macid, u8 rssi_from_assoc);
 267
 268 void phydm_ra_offline(void *dm_void, u8 macid);
 269
 270 void phydm_ra_mask_watchdog(void *dm_void);
 271
 272 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 273 void odm_refresh_basic_rate_mask(
 274         void *dm_void);
 275 #endif
 276 #endif /*@#ifndef __PHYDMRAINFO_H__*/